JP3821143B2 - Method and apparatus for detecting signal level having filter function - Google Patents

Description

  The present invention relates to a signal level detection method and apparatus for detecting a signal level of an analog input signal, and more particularly to a signal level detection method and apparatus having a filter function for removing a high frequency noise component superimposed on an analog input signal.

  Conventionally, for example, when a signal level of an analog input signal (in other words, a detection result by a sensor) input from various sensors that detect an operation state or the like of a control target is captured in a control device, it is superimposed on the analog input signal. In order to remove the generated high frequency noise, a noise removing filter (low pass filter) is used. As this type of filter, for example, two types of filters, an analog filter as shown in FIG. 6A and a digital filter as shown in FIG. 7A, are known.

  Here, in the analog filter shown in FIG. 6A, the non-inverting input terminal (+) of the operational amplifier OP1 is grounded, and a capacitor C1 and a resistor are provided between the inverting input terminal (−) and the output terminal of the operational amplifier OP1. R1 is connected in parallel, and an input signal (analog) is input to the inverting input terminal (−) of the operational amplifier OP1 via the resistor R2.

  In this analog filter, as the charge corresponding to the input signal is charged and discharged to the capacitor C via the resistors R1 and R2, the output signal obtained by removing the noise component from the input signal as shown in FIG. The charge / discharge time generated and determined by the resistance values of the resistors R1 and R2 and the capacitance of the capacitor C becomes the filter delay time.

  On the other hand, the digital filter shown in FIG. 6B sequentially latches input data obtained by A / D converting an input signal (analog) by a plurality of stages of latch circuits LT that operate in synchronization with a clock CK having a fixed period. Output data is generated by adding outputs from the latch circuits LT by an adder circuit ADD.

  That is, in this digital filter, a moving average of input data is obtained using a plurality of stages of latch circuits LT and adder circuits ADD cascaded together, and the moving average result is obtained as a signal of an input signal from which a high frequency noise component has been removed. Generated as output data representing the level. In this digital filter, the number of stages of the latch circuit LT becomes the width of the moving average, and the filter delay time is “1/2” of the input data shift time (the number of latch circuit LT connection stages × clock CK period) by all the latch circuits LT. "

  By the way, among the above-mentioned two types of filters conventionally used for removing high-frequency noise from an analog input signal, the analog filter has a characteristic that the characteristics of the capacitor C and resistors R1 and R2 constituting the filter change depending on the temperature. As described above, when used as a filter for removing high-frequency noise from an analog input signal in a control device, the filter characteristics (filter delay time) change with changes in temperature, and the analog input signal input from the sensor There was a problem that noise components could not be removed well and it was difficult to construct a highly accurate sensor circuit (signal level detection circuit).

  On the other hand, the digital filter sequentially shifts input data obtained by A / D converting an analog input signal using a plurality of stages of latch circuits LT, and adds the outputs of the latch circuits LT by an adder circuit ADD. In addition, since a stable clock that is normally generated based on the output from the crystal oscillator is used as the clock CK, the filter characteristics (filter delay time) are not temperature-dependent like analog filters, and output data Can be stably generated without being affected by temperature change.

  However, since the digital filter handles multi-bit (n-bit) data generated using an A / D converter, a large number of transistors are used in the latch circuit LT and the adder circuit ADD. Therefore, as described above, if a digital filter is used as a filter for removing high-frequency noise from an analog input signal in the control device, the circuit scale of the sensor circuit (signal level detection circuit) increases and the cost of the control device increases. There was a problem of inviting.

  Further, as shown in FIG. 7B, the digital filter has a noise passing band at an integer multiple interval of the sampling period (clock CK period) (folding phenomenon), so that it is not affected by this folding phenomenon. In order to filter the analog input signal, an analog filter (pre-filter) is provided before the A / D converter that performs A / D conversion of the analog input signal to remove high-frequency noise components that cannot be removed by the digital filter. It is necessary to do so.

  Therefore, a control device that removes high-frequency noise components from an analog input signal using a digital filter may have a gentle frequency characteristic compared with an analog filter that removes high-frequency noise components alone, but an analog signal separate from a digital filter. A filter (pre-filter) must be provided, and the same problem as in the case where the analog filter is used alone occurs, and there is a problem that the cost is increased by separately providing the analog filter.

  The present invention has been made in view of such a problem, and a stable filter characteristic can be obtained without providing a pre-filter like a digital filter, and an analog input signal from which a high-frequency noise component has been removed by the filter characteristic is obtained. It is an object of the present invention to provide a signal level detection method and apparatus capable of accurately detecting a signal level.

  The signal level detection method according to claim 1, which has been made to achieve such an object, provides an analog input signal for each delay to a pulse delay circuit formed by cascading a plurality of delay units each including a gate circuit. While inputting as a signal which controls the delay time of a unit, a pulse signal is input into a pulse delay circuit, and a pulse signal is transmitted, delaying sequentially by the delay time of each delay unit. Each time a clock is input at each set time, the pulse signal arrival position in the pulse delay circuit is detected, and the arrival position of the pulse signal detected at the time of this clock input and the previous clock input are detected. By obtaining a difference from the arrival position of the pulse signal, the number of stages of the delay unit through which the pulse signal has passed in the pulse delay circuit per set time is detected as a signal representing the signal level.

  That is, when the pulse delay circuit is operated as described above, the delay time when the pulse signal passes through each delay unit in the pulse delay circuit depends on the positive and negative high frequency noise components superimposed on the analog input signal. fluctuate. However, as the pulse signal passes through each delay unit, the fluctuation component is canceled out. When the average delay time in each delay unit when the pulse signal passes through a plurality of delay units is seen, This corresponds to the signal level of the analog input signal.

  In other words, when a pulse signal is transmitted in a pulse delay circuit, the average value of the delay time of the pulse signal in each delay unit increases as the number of delay units that the pulse signal has passed increases. You will approach the level. Therefore, in the present invention, the pulse delay circuit is operated as described above, and the pulse signal passes through each delay unit by detecting the number of stages of the delay unit through which the pulse signal has passed in the pulse delay circuit within the set time. The moving average of the time required to do this is taken, and this is output as information representing the true signal level of the analog input signal from which the high frequency noise component has been removed.

  Therefore, if the method of the present invention is used, a signal level detection functioning as a filter (low-pass filter) that removes high-frequency noise components from an analog input signal using a pulse delay circuit in which delay units comprising gate circuits are connected in cascade. The apparatus can be easily realized.

  Further, in the method of the present invention, the delay time of the delay unit constituting the pulse delay circuit is varied by the high frequency noise component, and the number of stages of the delay unit through which the pulse signal has passed within the set time is detected, thereby providing a low-pass filter. Since the function (high-frequency noise removal function) is realized, even if the analog voltage signal is periodically sampled at the set time as in the conventional digital filter, the high-frequency component aliasing phenomenon does not occur.

  Therefore, according to the method of the present invention, it is not necessary to provide a pre-filter like a conventional digital filter, and a function as a low-pass filter that can obtain stable filter characteristics with a single device using a pulse delay circuit. realizable. Further, according to the method of the present invention, since the information indicating the signal level of the analog input signal is detected from the number of stages of the delay unit through which the pulse signal has passed within the set time in the pulse delay circuit, the function as an A / D converter If it is applied to a sensor circuit that takes in an analog input signal from a sensor in a digital control device, there is no need to separately provide an A / D converter, and the analog input signal input circuit can be configured very simply. Is possible.

  Here, in the method of the present invention, the analog input signal is input to the pulse delay circuit as a signal for controlling the delay time of each delay unit. The delay time of each delay unit is controlled according to the analog input signal. However, as a specific input method thereof, for example, as described in claim 2, an analog input signal may be input to the pulse delay circuit as a drive voltage of each delay unit. Alternatively, as described in claim 3, an analog input signal may be input to the pulse delay circuit as a signal for controlling a drive current to flow through each delay unit.

  That is, since the gate circuit constituting the delay unit operates faster as the drive voltage or drive current increases, the analog input signal is supplied to the drive voltage of each delay unit as described in claim 2 or claim 3. Alternatively, if the signal is input to the pulse delay circuit as a drive current control signal, the delay time of each delay unit constituting the pulse delay circuit can be easily changed according to the signal level of the analog input signal. Become.

  Further, in the method of the present invention, the delay time of each delay unit constituting the pulse delay circuit is controlled using the analog input signal, and the number of stages of the delay unit through which the pulse signal has passed in the pulse delay circuit within the set time is detected. Therefore, the function as a low-pass filter is realized. However, the greater the number of delay units through which the pulse signal passes in the pulse delay circuit, the lower the cutoff frequency of the filter. To set, it is not necessary to change the value of a capacitor or a resistor as in an analog filter, or to change the number of connection stages of a latch circuit as in a digital filter. Thus, the set time for detecting the number of stages of the delay unit through which the pulse signal has passed may be changed. Therefore, according to the method of the present invention, the filter characteristics can be set very easily without changing the hardware configuration as in the conventional filter.

  As described above, according to the method of the present invention, it is possible to realize a low-pass filter having a lower cutoff frequency as the number of delay units through which the pulse signal passes in the pulse delay circuit within the set time is increased. It is necessary to increase the number of delay units constituting the pulse delay circuit. However, if the number of delay units is increased, the number of transistors constituting the pulse delay circuit also increases, leading to an increase in circuit scale.

  Therefore, in realizing the method of the present invention, as described in claim 5, a ring delay line that circulates a pulse signal by connecting delay units in a ring shape is used as a pulse delay circuit, and a set time is set. The number of delay units through which the pulse signal has passed may be detected from the circulation position and the number of circulations of the pulse signal on the ring delay line.

  In other words, in this way, in the pulse delay circuit, the pulse signal repeatedly passes through the delay units connected in a ring shape, so even if the number of delay units constituting the pulse delay circuit is reduced, The number of delay units through which the pulse signal passes within the set time can be increased freely. Therefore, according to the invention method described in claim 5, a low-pass filter with a low cut-off frequency can be realized without increasing the circuit scale, which is extremely effective in realizing the method of the present invention. Become.

  On the other hand, the invention described in claim 6 is a signal level detection apparatus suitable for realizing the method of the present invention (claim 1), and delays an input pulse by a delay time corresponding to the signal level of the analog input signal. A delay circuit consisting of a plurality of delay units consisting of gate circuits that are output in a cascade manner, and a pulse delay circuit that transmits a pulse signal while sequentially delaying the delay time of each delay unit, and a clock that is input from outside at a predetermined cycle And detecting means for detecting the arrival position of the pulse signal in the pulse delay circuit when the clock is input, and the detection result by the detecting means is output as information representing the input signal level.

  According to this apparatus, since the detection means detects the arrival position of the pulse signal in the pulse delay circuit every time a clock is input from the outside, the arrival position of the pulse signal detected when the clock is input. And the arrival position of the pulse signal detected at the time of the previous clock input, the number of stages of the delay unit that the pulse signal has passed through the pulse delay circuit per clock cycle (in other words, within the set time) ( As a result, the signal level of the analog input signal) can be detected. Therefore, according to this apparatus, the inventive method according to claim 1 can be easily realized, and the above-described effects can be obtained.

  The invention according to claim 7 is a signal level detection apparatus suitable for realizing the method according to claim 2, wherein each delay unit constituting the pulse delay circuit drives an analog input signal. By receiving the voltage, the input pulse is delayed by a delay time corresponding to the signal level of the analog input signal.

  The invention described in claim 8 is a signal level detection apparatus suitable for realizing the method of the invention described in claim 3, wherein the pulse delay circuit includes a control for controlling the drive current of each delay unit. Means are provided, and the control means receives the analog input signal as a control signal and controls the delay time of each delay unit.

  Therefore, according to the apparatus described in claims 7 and 8, the delay time of each delay unit constituting the pulse delay circuit is set to the signal of the analog input signal as in the invention method described in claim 2 or claim 3 described above. It can be easily changed according to the level. On the other hand, the device according to claim 9 is the device according to any one of claims 6 to 8, wherein the detection means converts the arrival position of the pulse signal in the pulse delay circuit into digital data of a predetermined bit. An encoder for output is provided.

  Therefore, according to this apparatus, information indicating the arrival position of the pulse signal in the pulse delay circuit is output as digital data of a predetermined bit, and as described above, the pulse signal detected at the time of clock input is output. When the signal level of the analog input signal is obtained from the difference in the arrival positions, the calculation can be performed very easily.

  Further, the invention described in claim 10 is an apparatus suitable for realizing the method of the invention described in claim 5, wherein the pulse delay circuit is connected to the delay unit in the form of a ring. Consists of a ring delay line that circulates the signal. In addition to the encoder according to claim 9, the detection means is provided with a counter for detecting the number of laps of the pulse signal in the ring delay line, and the output from the encoder is the lower bit of the information representing the input signal level. The count value by the data and the counter is output as the upper bit data of the information indicating the input signal level.

  Therefore, according to this device, the same effect as that of the method of the invention of claim 5 can be obtained, and the information indicating the arrival position of the pulse signal in the pulse delay circuit is the predetermined bit as in the case of claim 9. Since it is output as digital data, it is possible to very easily perform arithmetic processing when obtaining the signal level of the analog input signal from the difference in arrival position of the pulse signal detected at the time of clock input.

  According to the signal level detecting device of the ninth aspect, since the counter counts the number of circulations of the pulse signal in the ring delay line constituting the pulse delay circuit, the number of delay units constituting the pulse delay circuit is determined. The circuit scale can be reduced by reducing the number of delay units, but the number of stages of this delay unit is at least the time required for the pulse signal to go around the ring delay line. It is necessary to set it to be more than time.

  In other words, the number of stages of the delay units constituting the ring delay line is made too small, and the time required for the pulse signal to go around the ring delay line is shorter than the operation time required for the counter to count the number of laps. Since the counter operation of the number of laps by the counter is delayed and normal digital data cannot be output, the number of stages of the delay units constituting the ring delay line must be set in consideration of the operation time of the counter. There is.

  For example, the count value by the counter is 10 bits or more, and 10 nsec. In the case of a general counter that requires about the above time, it is desirable that the number of stages of delay units constituting the ring delay line be 63 or more. Further, for example, the counter is a counter capable of high-speed operation (for example, a synchronous counter described in Japanese Patent Laid-Open No. 7-254853 previously proposed by the present inventors), and the time required for the count operation is 10 nsec. In such a case, the number of stages of delay units constituting the ring delay line can be set to 15 stages or more, which is smaller than when a general counter is used.

  Further, as the ring delay line, for example, a ring delay pulse generating circuit described in JP-A-3-220814, JP-A-7-154256, or the like can be used.

  Examples of the present invention will be described below. FIGS. 1A and 1B are explanatory diagrams showing the configuration and operation of the signal level detection apparatus of the first embodiment to which the present invention is applied.

  As shown in FIG. 1 (a), the signal level detection apparatus of this embodiment is a pulse delay circuit configured by cascading a plurality of delay units 2 that output an input pulse by delaying it by a predetermined delay time. 10, the arrival position of the delay pulse Pin in the pulse delay circuit 10 is detected at the rising (or falling) timing of the clock CK input from the outside, and the detection result is a delay unit through which the delay pulse Pin has passed. And an encoder 20 that converts and outputs n-bit digital data DT indicating the number of stages 2 from the head.

  Each delay unit 2 included in the pulse delay circuit 10 is configured by a gate circuit including an inverter (see FIG. 4) described later. Each delay unit 2 receives an analog input signal ( Voltage) Vin is applied as a drive voltage.

  The pulse delay circuit 10 receives a delay pulse Pin (High level or Low level pulse signal) in synchronization with the clock CK input to the encoder 20, and each delay unit 2 receives the delay pulse Pin, The signals are delayed by a predetermined delay time and sequentially output to the delay unit 2 at the next stage.

  The period of the clock CK input to the encoder 20 is set to be sufficiently longer than the delay time of the delay unit 2 (for example, several tens of times the delay time of the delay unit 2), and the pulse delay circuit 10 The delay unit 2 is provided with, for example, several tens to several hundreds of stages so that the delay pulse can be continuously transmitted even after the time of one cycle of the clock CK has elapsed after the input of the delay pulse Pin. ing.

  In the signal level detection apparatus of this embodiment configured as described above, the delay time of each delay unit 2 is a time corresponding to the signal level (voltage level) of the analog input signal Vin, and the analog input signal Vin has high frequency noise. When components are superimposed, the delay time of each delay unit 2 varies depending on the high frequency noise component.

  That is, FIG. 1B shows an output waveform from each delay unit when the delay pulse Pin is input to the pulse delay circuit 10 and the delay pulse Pin is transmitted through the pulse delay circuit 10. However, as is clear from this figure, when the high frequency noise component is superimposed on the analog input signal Vin, the drive voltage of each delay unit 2 fluctuates due to the high frequency noise component. The delay time when passing through the unit 2 varies.

  Specifically, the delay time of the delay unit 2 that passes the delay pulse Pin at the timing when the positive high frequency noise component is superimposed on the analog input signal Vin is the standard time when the high frequency noise component is not superimposed on the analog input signal Vin. On the contrary, the delay time of the delay unit 2 that passes the delay pulse Pin at the timing when the negative high frequency noise component is superimposed on the analog input signal Vin is shorter than the standard time. (See “Large” in the figure).

  Therefore, in the present invention, one cycle of the clock CK is set as a set time, and the number of stages of the delay unit 2 through which the delay pulse Pin has passed within the set time is detected by the encoder 20, and the detection result (the number of stages of the delay unit 2 is determined). The digital data DT) is output as data representing the signal level (voltage level) of the analog input signal Vin.

  That is, the delay time of the delay unit 2 constituting the pulse delay circuit 10 becomes shorter as the signal level of the analog input signal Vin becomes higher according to the signal level of the analog input signal Vin as shown in FIG. However, the fluctuation in the delay time due to the positive and negative high frequency noise signal components superimposed on the analog input signal Vin is canceled by inputting the delay pulse Pin to the pulse delay circuit 10 and sequentially transmitting each delay unit 2 ( In other words, in this embodiment, as shown in FIG. 2B, the delay unit 2 in which the delay pulse Pin has passed within the time period is defined as the sampling period Ts as shown in FIG. Are sequentially detected by the encoder 20 so that the signal level of the analog input signal Vin is detected at each sampling period Ts. It is to generate a Le moving average taken value equivalent digital data DT (n1, n2 ...).

  Therefore, the signal level detection apparatus of the present embodiment alone has a function as a low-pass filter that removes high-frequency noise from the analog input signal and a function as a level detector that detects the signal level of the analog input signal. Moreover, since the encoder 20 outputs digital data DT corresponding to the signal level of the analog input signal, it also has a function as an A / D converter.

  Therefore, according to the signal level detection apparatus of the present embodiment, if the control circuit is used as a signal processing circuit for processing an input signal from the sensor, the circuit scale of the control circuit is reduced and the cost of the control circuit is reduced. Will be able to. In this embodiment, the encoder 20 corresponds to the detection means of the present invention.

  By the way, in the signal level detection apparatus of the present embodiment, the characteristic as a low-pass filter (noise removal effect) is caused by the pulse delay circuit 10 during a set time (sampling period Ts) determined by the period of the clock CK. It is determined by the number of stages of the delay unit 2 through which the delay pulse Pin passes, and the greater the number of stages, the lower the cut-off frequency of the low-pass filter and the higher the noise removal effect.

  For example, since the high frequency noise superimposed on the analog input signal Vin is generally normally distributed, in order to reduce the noise level to 1/10, a delay pulse using a delay unit of 100 stages (10 = √100) is used. In order to reduce the noise level further, it is only necessary to further increase the number of delay units that allow the delay pulse Pin to pass.

  Further, the number of stages of the delay unit 2 through which the delay pulse Pin passes in the pulse delay circuit 10 increases as the sampling period Ts increases. Therefore, according to the signal level detection apparatus of the present embodiment, the characteristic as a low-pass filter (noise removal effect) can be arbitrarily set by adjusting the cycle of the clock CK input to the encoder 20. .

  For this reason, for example, as shown in FIG. 3 (a), in the control device, the detection speed is not so required, and an analog input signal (for example, from the sensor element (A) that needs to detect signals with high accuracy (for example, Detection signals such as pressure, acceleration, angular velocity, stress, torque, etc.) and analog input signals from the sensor element (B) where speed is prioritized over detection accuracy (for example, detection signals such as rotational speed, rotational position, rotational angle, etc.) ), It is necessary to take in two or more types of analog input signals, and if the signal level detection device of this embodiment is used in the signal input circuit, the signal input circuit detects one signal level. This can be realized using an apparatus.

  That is, as shown in FIG. 3A, when the analog input signal from the sensor element (A) is taken in, the switch SW1 is turned on and the analog input signal is input to the signal level detection device at the same time. When the frequency of the clock CK input to the detection device is lowered and the sampling cycle Ts is lengthened, on the contrary, when the analog input signal from the sensor element (B) is taken in, the switch SW2 is turned on to detect the signal level. When the analog input signal is input to the apparatus and the frequency of the clock CK input to the signal level detection apparatus is increased and the sampling period Ts is shortened, each analog input can be performed using one signal level detection apparatus. The signal can be A / D converted at an appropriate speed.

  On the other hand, FIG. 3B shows the configuration of the signal input circuit when the analog input signal from each of the sensor elements (A) and (B) is captured using a conventional analog filter. In this case, when the switch SW1 is turned on to acquire an analog input signal from the sensor element (A), and when the switch SW2 is turned on to acquire an analog input signal from the sensor element (B), an analog input signal is used. It is necessary to switch the analog filter that passes the signal to one corresponding to the characteristics of each analog input signal.

  Therefore, according to the signal level detection device of the present embodiment, the signal input circuit using the conventional analog filter is used in the control device as a signal input circuit when taking in the analog input signals from the plurality of sensor elements. It can be seen that the cost of the control device can be reduced by simplifying the configuration of the signal input circuit compared to the configuration of

  Here, in each signal input circuit shown in FIGS. 3A and 3B, on the signal path of the analog input signal from the sensor element (A) or (B) input through the switch SW1 or SW2. An amplifier AMP is provided, and each signal is amplified by the amplifier AMP and then input to a signal level detection device or an analog filter. In this way, instead of the buffer 12 shown in FIG. Even if an analog input signal is captured using the amplifier AMP and applied as a drive voltage for the pulse delay circuit 10, the signal level detection device of this embodiment can exhibit the above-described effects. .

  By the way, the delay unit 2 constituting the pulse delay circuit 10 may be a general gate circuit that can output the delayed pulse Pin after being delayed by a predetermined delay time, and the delay time varies depending on the drive voltage. For example, any delay unit 2 may be configured as shown in FIG. 4A in order to simplify the circuit configuration.

  That is, in FIG. 4A, each delay unit 2 constituting the pulse delay circuit 10 is composed of two stages of CMOS inverter (negative circuit) INV composed of a P-channel transistor (FET) and an n-channel transistor (FET), The input pulse is delayed by a predetermined time determined by the operation time of the P-channel transistor and the n-channel transistor constituting the front and rear CMOS inverters INV. If each delay unit 2 is configured in this way, The delay unit 2 can be composed of four transistors, and each of these transistors can be created very easily when manufacturing a CMOS integrated circuit, so that the pulse delay circuit 10 can be realized at low cost.

  In the above embodiment, the analog input signal Vin is applied as a drive voltage to each delay unit 2 in order to control the delay time of each delay unit 2 according to the signal level of the analog input signal Vin. For example, as shown in FIG. 4B, when each CMOS inverter INV constituting the delay unit 2 is provided with a control transistor (FET) Trc for externally controlling the drive current, An analog input signal Vin may be input as a control signal to the control terminal (gate) of the control transistor via the buffer 12 (or the amplifier AMP).

  That is, since the operation time of the gate circuit such as the inverter INV changes depending on the drive current supplied from the DC power supply, the drive current is based on the analog input signal Vin as shown in FIG. Even if it controls, the signal level detection apparatus which can acquire the effect similar to the above is realizable.

  The control transistor Trc corresponds to the control means of the present invention (specifically, described in claim 8). Next, FIG. 5 is an explanatory diagram showing the configuration of the signal level detection apparatus of the second embodiment to which the present invention (particularly claims 5 and 10) is applied.

  The signal level detection apparatus of the second embodiment shown in FIG. 5 connects the delay unit 2 constituting the pulse delay circuit 10 in a ring shape so that the pulse delay circuit 10 circulates the pulse signal in the pulse delay circuit 10. In addition to the encoder 20 similar to that of the first embodiment for detecting the rotation position of the pulse signal on the ring delay line, the ring delay line can be configured to generate the pulse signal on the ring delay line. A circulation counter 30 for counting the number of circulations is provided.

  In this embodiment, the ring delay line constituting the pulse delay circuit 10 includes, for example, a delay unit 2, a NAND circuit that receives a start pulse Pk (High level) from the outside at one input terminal, And an even-numbered inverter that transmits a pulse signal while inverting the signal level of the output pulse, and by inputting the output of the final-stage inverter to the other input terminal of the NAND circuit, pulses are generated in each odd-numbered delay unit 2. The pulse signal is circulated by sequentially inverting the signal level of the signal. The configuration of such a ring delay line is described in detail in JP-A-3-220814, JP-A-7-154256, etc. Since it has been described and is conventionally known, the description thereof is omitted.

  Then, from the signal level detection device of this embodiment, the a-bit digital data output from the encoder 20 is converted into lower-order bit data representing the signal level of the analog input signal Vin, and the count value (b-bit digital data) by the counter is used. Data) is the upper bit data representing the input signal level, and digital data DT of a total of n bits (n = a + b) is output.

  Therefore, according to the signal level detection device of the present embodiment, not only the same effect as the signal level detection device of the first embodiment can be obtained, but also the number of connection stages of the delay unit 2 constituting the pulse delay circuit 10 can be reduced. However, the function as a low-pass filter can be sufficiently realized, so that the circuit scale can be reduced compared to the signal level detection device of the first embodiment, and the device can be reduced in size and cost. Become.

It is explanatory drawing explaining the structure and its operation | movement of the signal level detection apparatus of 1st Example. It is explanatory drawing explaining the principle of operation of the signal level detection apparatus of 1st Example, and its effect. It is explanatory drawing which represents the usage method of the signal level detection apparatus of 1st Example in comparison with the conventional analog filter. It is explanatory drawing explaining an example of the delay unit which comprises a pulse delay circuit, and its modification in 1st Example. It is explanatory drawing showing the structure of the signal level detection apparatus of 2nd Example. It is explanatory drawing showing the structure of the conventional analog filter, and its operation characteristic. It is explanatory drawing explaining the structure of the conventional analog filter, and its specific usage example.

Explanation of symbols

2 delay unit 10 pulse delay circuit 12 buffer 20 encoder 30 lap counter AMP amplifier INV CMOS inverter Trc control transistor

Claims (10)

A signal level detection method having a filter function for removing high frequency noise components from an analog input signal and detecting a true input signal level after noise removal,
The analog input signal is input as a signal for controlling the delay time of each delay unit to a pulse delay circuit formed by cascading delay units each including a gate circuit, and a pulse signal is input to the pulse delay circuit. To transmit the pulse signal while sequentially delaying by the delay time of each delay unit,
Each time a clock is input at every set time, the pulse signal arrival position in the pulse delay circuit is detected, the arrival position of the pulse signal detected at the time of this clock input, and the pulse detected at the previous clock input. A filter function characterized by detecting the number of delay units through which a pulse signal has passed in the pulse delay circuit per set time as a signal representing the signal level by obtaining a difference from a signal arrival position. A signal level detection method. 2. The signal level detection method having a filter function according to claim 1, wherein the delay time of each delay unit is controlled by using the analog input signal as a driving voltage for each delay unit. 2. The signal level detection method having a filter function according to claim 1, wherein a delay time of each delay unit is controlled by controlling a driving current that flows to each delay unit by the analog input signal. 4. The signal level detection method having a filter function according to claim 1, wherein a filter characteristic as a low-pass filter for removing the high-frequency noise component is adjusted by changing the set time. As the pulse delay circuit, a ring delay line that circulates the pulse signal by connecting the delay units in a ring shape is used, and the number of stages of the delay unit that the pulse signal has passed within the set time is determined by the ring delay circuit. 5. The signal level detection method having a filter function according to claim 1, wherein the detection is performed from a circulation position and a circulation number of the pulse signal on the delay line. A signal level detection device that has a filter function to remove high frequency noise components from an analog input signal and detects a true input signal level after noise removal,
A delay unit consisting of a gate circuit that delays and outputs an input pulse with a delay time corresponding to the signal level of the analog input signal is cascade-connected to delay the pulse signal sequentially by the delay time of each delay unit. A pulse delay circuit to transmit while
Each time a clock is input from the outside at a predetermined cycle, the arrival position of the pulse signal in the pulse delay circuit is detected, and the arrival position of the pulse signal detected at the time of this clock input and detected at the previous clock input Detecting means for detecting, as a signal representing the signal level, the number of stages of the delay unit through which the pulse signal has passed in the pulse delay circuit per cycle of the predetermined period by obtaining a difference from the arrival position of the pulse signal; A signal level detecting device having a filter function. 7. The filter function according to claim 6, wherein each delay unit delays an input pulse by a delay time corresponding to a signal level of the analog input signal by receiving the analog input signal as a drive voltage. Signal level detection device. The pulse delay circuit includes control means for controlling the drive current of each delay unit, and the control means controls the delay time of each delay unit by receiving the analog input signal as a control signal. The signal level detection apparatus having a filter function according to claim 6. 9. The filter function according to claim 6, wherein the detection unit includes an encoder that converts a pulse signal arrival position in the pulse delay circuit into digital data of a predetermined bit and outputs the digital data. A signal level detection device having: The pulse delay circuit includes a ring delay line that circulates the pulse signal by connecting the delay units in a ring shape, and the detection means includes, in addition to the encoder, the pulse signal in the ring delay line. A counter for detecting the number of laps is provided, and the output from the encoder is output as lower bit data of information representing the input signal level, and the count value by the counter is output as upper bit data of information representing the input signal level. A signal level detection device having a filter function according to claim 9.

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