JP3814953B2 - Drive device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a recording medium such as an optical disk or a magneto-optical disk.To the bodyThe present invention relates to a drive device that performs a recording / reproducing operation correspondingly.
[0002]
[Prior art]
For example, in a recording medium such as an optical disk or a magneto-optical disk, an address serving as absolute position information is recorded on the data track in some form.
In the disk drive device corresponding to the disk, for example, during recording / reproducing operation, the address on the data track is detected to determine whether or not the target position has been reached, and it has been detected that this has been reached. Depending on the situation, execution control of the recording or reproducing operation is performed.
[0003]
FIG. 21 shows an example of an address recording form on the disc. The sectors in FIGS. 21A and 21B indicate data units to which one address value is assigned. In this specification, “sector” is used to mean one data unit to which one address value is given in this way.
[0004]
In FIG. 21A, an address area is set in a sector, and for example, address information is recorded as data recorded on a data track in the same manner as main data. For example, address information is recorded in the address area in the form of phase pits, magnetic field pits, or the like. Subsequently to the address area, a main data area in which main data (main data such as audio, video, and file data to be recorded / reproduced) is recorded is formed. In the present specification, for the sake of explanation, the term main data (main data area) refers to data including not only actual file data but also error detection codes, error correction codes, and other control data associated with those data ( As a region).
[0005]
In FIG. 21A, address information and main data are recorded by physically dividing an area within a sector. As the address information, an actual address value Ad and a CRC error detection code added to the address value Ad are recorded, and the address information is, for example, three times in order to reduce the probability of an address read error. Recorded repeatedly.
[0006]
On the other hand, FIG. 21B shows an example in which lands or grooves serving as data tracks are wobbling (meandering).
A unit area in which main data is recorded as one sector is formed (of course, an address may be recorded as data in the sector), and address information is expressed by wobbling.
For example, an address value Ad as address information and a CRC error detection code added to the address value Ad are generated, and a groove or land is wobbled by a signal obtained by performing a predetermined modulation process such as FM modulation on the address information. In this case, the drive device can extract the address information by detecting and demodulating the wobbling period.
[0007]
On the drive device side, it is determined whether or not the address extracted by the processing as shown in FIG. 22 is an address indicating the target position for recording / reproducing, and for example, a signal AOK having a meaning of permitting recording / reproducing is output.
In FIG. 22, an address detection unit 101 is a so-called address decoder, and decodes address information recorded on a disc in various forms as shown in FIGS. The decoded address value is stored in a register serving as the address holding unit 103.
On the other hand, the decoded address information and the CRC error detection code are sent to the CRC error detection unit 102 to detect whether or not an error bit exists as an address value (error detection).
[0008]
The address value taken into the address holding unit 103 is compared with the address value output from the R / W address counter 105 by the equality comparison circuit 104. The R / W address counter 105 outputs an address value as a target position of the recording / reproducing operation.
When the equality comparison circuit 104 obtains a coincidence result, the signal AOK is output via the logic circuit 106. The signal AOK is an address match, that is, a signal for permitting the recording / reproducing operation because the scanning position by the optical pickup has reached the target position, and the recording / reproducing control unit that has received this signal performs the recording / reproducing operation for the disc. Will start.
However, when an address error is detected by the CRC error detection unit 102, the signal AOK is not output from the logic circuit 106.
That is, in such a processing block, the address value can be detected without error, and the signal AOK is output when the address value matches the target address, thereby starting the recording / reproducing operation for the disc.
[0009]
[Problems to be solved by the invention]
By the way, as can be seen from the description of FIG. 21 and FIG. 22, the conventional address information includes only an address value and a CRC error detection code for performing error detection on the address value.
That is, there is no error correction function for the address value itself.
For this reason, on the drive device side, there is a problem that the output of the signal AOK permitting recording / reproduction is delayed and the operation becomes inefficient or the reliability is lowered. In addition, there is a problem that the probability that the disk itself becomes unsuitable for recording / reproduction due to an address error is increased, or the life is likely to be reduced. Furthermore, there is a problem that the main data area becomes relatively narrow, that is, a recording capacity limitation occurs, because the address area must be wide within the sector.
[0010]
The recording capacity problem occurs in the type as shown in FIG.
That is, since it cannot be corrected in the case of an address error, it is necessary to increase the probability that the address can be correctly read as much as possible. For this reason, the address information is repeatedly recorded many times such as three times. The main data area is reduced accordingly.
[0011]
In addition, the inability to correct the address error increases the probability of disc quality failure and also reduces the lifetime. In other words, as the disk deteriorates due to changes over time and usage, etc., the situation where an address error occurs frequently occurs, but since error correction cannot be performed, this situation cannot be handled (that is, address without error). You have to wait until it can be read), and in extreme cases it becomes an unusable disk.
[0012]
Further, the inefficiency and the decrease in reliability of the recording / reproducing operation due to the inability to correct the address error can be understood from the operation model shown in FIGS.
In FIG. 23 to FIG. 26, “◯” indicates that the address read is OK (CRC error detection result OK) for a certain sector, and “×” indicates that the address read is NG (CRC error detection result NG) for a certain sector. It was shown that.
In these figures, a recording operation is taken as an example, and the drive device performs a seek to search for an address that is a target position on the disc, and after that seek, performs an address check (check whether it is a target address) and records. The operation to start is shown. A solid line arrow indicates landing from a seek and an address reading operation from the position, and a thick line arrow with a diagonal line indicates a recording operation started.
n-1, n, n + 1,... are address values of each sector.
[0013]
FIG. 23 shows a case where the address n-1 and the address n of the next sector are read NG when landing to the sector of the address n-1 after the seek. Since the sector where recording can be started is the next sector whose address check is OK, the recording operation cannot be started from sector (n + 1). As shown in the figure, if the address read is OK in the sector (n + 1) and the address check is OK here, the recording operation can be started from the next sector (n + 2).
That is, in the example of FIG. 23, since the address n−1 and the address n are read NG, the start of the recording operation is delayed.
[0014]
FIG. 24 shows a case where, after the seek, when landing on the sector of the address n-1, the address n-1 is read NG and the address n of the next sector is read OK. The sector that can start recording is from the next sector (n + 1). However, it is assumed that the address n + 1 is read NG in the sector where recording is started.
In this case, the recording operation can be started from the sector (n + 1), but it cannot be determined whether or not the sector (n + 1) is an accurate recording position during the recording operation. Therefore, it is necessary to trust that the sector (n + 1) is recorded by the tracking operation during recording, and the recording reliability is lacking.
[0015]
Further, FIG. 25 shows a case where, when landing on the sector of address n-1, the address n-1 is read OK, and recording can be started from the next sector (n). However, it is assumed that addresses n + 1 and n + 2 are read NG in the sector where recording has started and the next sector.
In this case, the recording operation can be started from the sector (n), but during the recording operation, the sector (n + 1) (n + 2) cannot be determined whether or not it is an accurate recording position, and this is also a tracking operation during recording. I can only trust that they are recording those sectors. That is, it lacks in terms of recording reliability.
[0016]
FIG. 26 shows a case where address read NG is continuously performed for each sector when landing to the sector at address n−1 after seek.
In this case, the process waits until the address read is OK, and recording cannot be started unless the read address matches the target address. That is, the disk rotation waiting period until the start of recording becomes longer, and the recording operation efficiency is greatly deteriorated.
Although the above examples have been described with respect to the recording operation, the situation is the same in the case of the reproducing operation.
[0017]
[Means for Solving the Problems]
The present invention eliminates various problems associated with the uncorrectable address information as described above, improves the efficiency of recording / reproducing operations, improves reliability, improves drive adaptability to recording medium degradation, The purpose is to realize the superiority of the recording capacity.
[0019]
  The present invention provides a recording or reproducing operation corresponding to a recording medium in which address information as absolute position information on the recording medium is recorded with an address code and a correction code having an error correction capability related to the address value. As a drive device capable of performing the above, a decoding unit that decodes the address information from information read from a recording medium, and an error detection is performed on the address information decoded by the decoding unit using an added correction code A detection unit; a correction unit that performs error correction using an added correction code for the address information decoded by the decoding unit; an interpolation unit that can interpolate and generate an address value; and an error of the detection unit If there is no error in the detection result, the decoding means performs decoding. Select address value, the error detection result of the detection means is not more there is an error, and the interpolationInterpolated by meansAs the address existsAs a result of comparing the decoded address value with the interpolated address value, the values satisfy a predetermined condition.Have compatibilityIt was assumedIfInterpolated by the interpolation meansThe address value is the decision address,The error detection result of the detecting means is an error, and there is an address interpolated by the interpolating means, and the result of comparing the decoded address value with the interpolated address value If these values do not meet the prescribed conditions and are not compatible, record them. / Does not output a signal that permits playback,The error detection result of the detection means has an error, and the interpolationInterpolated by meansWhen there is no address, the address value corrected by the correcting means is used as a determined address, and the determined address is further used for generating an interpolation address.Records and / Or playbackOperation control means for setting operation permission / non-permission is provided.
[0020]
That is, in the present invention, even if there is an error in the read address (decoded address), it is possible to correct or interpolate the error, greatly improving the probability of reading OK, and for such an address. It is possible to check whether or not it is the target position.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, examples as embodiments of the recording medium and the drive device of the present invention will be described in the following order.
1. Sector format example
2. Address processing example
3. Example of operation with address processing
4). Drive device configuration
5). Address processing configuration and operation when non-binary BCH code is adopted
6.2 Address processing configuration and operation when adopting binary BCH code
[0022]
1. Sector format example
1 to 4 show examples of the sector format of the disk-shaped recording medium.
In FIG. 1A, an address area is set in a sector, and address information is recorded as data to be recorded on a data track, for example, similarly to main data. For example, address information is recorded in the address area in the form of phase pits, magnetic field pits, or the like. Following the address area, main data (main data such as audio, video, and file data to be recorded / reproduced, and error detection code, error correction code, and other control data associated with the data) are recorded. The main data area to be processed is formed.
That is, in FIG. 1A, the address information and main data are recorded by physically dividing the area within the sector. As the address information, an actual address value Ad and an error correction code (ECC: ERROR CORRECTION CODE) added to the address value Ad are recorded.
[0023]
On the other hand, FIG. 1B shows an example in which a land or groove serving as a data track is wobbling (meandering).
A unit area in which main data is recorded is formed as one sector, and address information is represented by track wobbling.
For example, an address value Ad as address information and an error correction code ECC added to the address value Ad are generated, and a groove or land is wobbled by a signal obtained by performing a predetermined modulation process such as FM modulation on the address information. In this case, the drive device can extract the address information by detecting and demodulating the wobbling period.
[0024]
As shown in FIGS. 1A and 1B, a code having an error correction capability is added to the address value Ad, so that even in the case of an address read error, it is possible to recover to a read OK state by correction.
This eliminates the need to repeatedly record address information many times as described with reference to FIG.
[0025]
FIG. 2A shows an example in which an address area is set in a sector. As an address information in the address area, an address value Ad, a CRC error detection code added to the address value Ad, and an address value are shown. An error correction code ECC added to Ad is recorded.
FIG. 2B shows the case of a disk whose address is expressed by wobbling. Similarly to FIG. 2A, address information for wobbling a track (land or groove) includes an address value Ad and its address value. A CRC error detection code added to Ad and an error correction code ECC added to the address value Ad.
As shown in FIGS. 2A and 2B, by allowing CRC error detection to be executed, it is possible to reduce the risk that the correction process using the error correction code is erroneously corrected.
[0026]
In FIG. 3, as in FIG. 1A, an address value Ad and an error correction code ECC added to the address value Ad are recorded as address information in an address area provided in the sector. The address value Ad and the error correction code ECC are repeatedly recorded twice.
By adopting such a method, for example, the correction process for the first address information is performed when the second address information is read, and the correction process for the second address information is the same as the first address information. It is also possible to perform processing that is simply performed by taking the exclusive OR of.
[0027]
FIG. 4A is basically the same format as FIG. 1A, but this is an example in which a BCH code (Bose Chaudhuri Hocquenghem code) is adopted as the error correction code ECC. FIG. 4B is an example in which a BCH code is adopted as the error correction code ECC in FIG.
By adopting a BCH code having both error detection capability and error correction capability, a more useful format can be obtained.
[0028]
The sector formats as shown in the examples of FIGS. 1 to 4 are conceivable. Examples of the format of the address information itself are shown in FIGS.
In the example of FIG. 5, the entire address information is 44 bits, and 11 bits are assumed to be 4 bits as one unit (nibble). The address value Ad is 6 nibbles, the reserve is 1 nibble, and the error correction code ECC is 4 nibbles.
This address format is 2 with 4 bits as 1 nibble.^Four And a 4-parity with a non-binary BCH code (for example, Reed-Solomon code). Correction ability is 2 nibbles or less.
Primitive polynomial: f (x) = X^Four + X + 1
Assuming that the solution of the primitive polynomial is a,
Generator polynomial: g (x) = (X + a⁰ ) (X + a¹ ) (X + a² ) (X + a^Three )
Let's add parity.
[0029]
In the example of FIG. 6A, the entire address information is 44 bits, the address value Ad is 24 bits, the reserve is 8 bits, and the error correction code ECC is 12 bits.
This is a double error correction (63, 51) binary BCH code with 12 parity added, and the correction capability is 2 nibbles or less.
Primitive polynomial: f (x) = X⁶ + X + 1
age,
Generator polynomial: g (x) = X¹²+ X^Ten+ X⁸ + X^Five + X^Three +1
To add parity.
[0030]
In the example of FIG. 6B, the entire address information is 44 bits, the address value Ad is 24 bits, the reserve is 2 bits, and the error correction code ECC is 18 bits.
This is obtained by adding 18-bit parity as a binary BCH code for triple error correction (63, 45).
[0031]
Since each example of FIGS. 6A and 6B is a cyclic code, the address processing circuit is as simple as that for the CRC error detection code, and correction processing also uses the comparison of exclusive OR and the relationship before and after. It is possible to calculate easily.
5 and 6 are merely examples, and for example, a format with higher correction capability is naturally possible.
[0032]
2. Address processing example
As described above, an example of an address processing operation at the time of recording / reproducing with respect to a disc including an error correction code as address information will be described with reference to FIGS. The operation described here is processing in the disk drive device corresponding to the disk.
[0033]
FIG. 7 shows a series of operations such as a recording operation and a reproducing operation as a process that needs to check an address at the start of the operation, that is, whether an execution start position is an address indicating a target position for recording / reproducing. Is shown.
For example, when a recording or reproducing operation is instructed as step F100, the address of the sector that is the target of the requested recording or reproducing operation is calculated in step F101. That is, the start sector address, the end sector address, and the like are calculated.
Subsequently, in step F102, a seek operation for moving the recording / reproducing head to the start sector calculated as the recording or reproducing target position is executed.
[0034]
During the seek, as shown as step F103, it is determined from the read address value whether or not the seek operation has reached the target position, thereby continuing seek, seek end, seek restart, seek direction control, etc. Various necessary seek operation controls for landing to the target position are executed.
In step F104, when the seek operation is terminated based on the determination from the read address value, the process proceeds to recording or reproduction processing in step F105.
First, in step F106, an address check is performed on the read address to determine whether or not the current address matches the target address.
When it is detected that the current address read from a certain sector matches the target address, the process proceeds from step F107 to F108, and the recording or reproducing operation is started from the next sector.
[0035]
During the recording or reproducing operation, an address check is performed on the address read from each sector in step F109, so that the operation has reached the sector of the end address, or recording / reproducing is performed at the correct position without any tracking error. Monitor whether or not
When it is detected that the end sector has been reached, the process proceeds from step F110 to step F111 to end the recording / reproducing operation.
[0036]
For example, in such a series of processes, address reading and address checking are performed in the processes of steps F103, F106, and F109 with hatching, and these processes are as shown in FIG. 8, for example. .
As described above, the address area in the sector and the address information recorded in the wobbling track are extracted by the address decoder in the disk drive device and supplied to the processing unit for address check. The processing procedure of the processing part for a check is typically shown.
[0037]
When the address information decoded in step S1, that is, the address value and the error correction code are supplied, syndrome calculation is performed in step S2 to detect an error.
If error detection is OK, that is, if the address value can be read properly without error, an address check is performed in step S4. That is, the target address in each case such as seek, recording / reproducing operation start, recording / reproducing operation end, etc. is compared with the address read after being decoded, and coincidence detection is performed. If they match, a signal AOK indicating that the address matches the target address is output.
For example, in step F106 in FIG. 7, the recording / reproduction start address is detected. In this case, the operation start address generated by the read / write address counter is compared with the decoded read address. In this case, the signal AOK is a permission signal for starting the recording or reproducing operation.
Further, in step F103 in FIG. 7, the signal AOK has a meaning as a seek end determination signal, and in step F109, the signal AOK has a meaning as a recording / playback operation end determination signal.
[0038]
By the way, when it is determined in step S2 in FIG. 8 that error detection NG, that is, an error exists in the decoded and input address value, correction processing or interpolation processing is performed in step S3.
If correction OK or interpolation address generation is possible, the corrected address value or the interpolation generated address value is used for the address check in step S4.
[0039]
That is, in this example, even if there is an error in the decode address, an appropriate address value can be generated by correction or interpolation processing, thereby enabling address check. Therefore, if it is the timing when the address is read from the target position, the signal AOK can be output without delay.
Needless to say, if the address check is NG, or if there is an address error and the address check cannot be performed because the address cannot be corrected and cannot be interpolated, the signal AOK indicating the address match is not output.
[0040]
3. Example of operation with address processing
Since the error correction code is added to the address information read as described above, there is an error in the decode address (the address read from the disk and decoded and supplied to the address check processing unit) as described in FIG. Even in this case, an address check can be performed by generating a correct address by error correction or by generating an address by interpolation processing, thereby realizing an increase in the efficiency of processing such as recording and reproduction and an improvement in reliability.
[0041]
These points will be described with reference to FIGS. 9 to 12.
Each of FIGS. 9 to 12 corresponds to FIGS. 23 to 26 described above.
In FIG. 9 to FIG. 12, “◯” indicates the case where the address read is OK (error detection result OK) for a certain sector and the signal AOK is obtained by the address check OK, as in FIG. 23 to FIG. Yes. However, “×” indicates a case where address reading is NG (error detection result NG) for a certain sector, correction processing cannot be performed, and interpolation processing cannot be performed. Further, “△” indicates that the address read for a certain sector is NG (error detection result NG), but an appropriate address value can be obtained by the correction process or the interpolation process, and the signal AOK is obtained due to the address match. The obtained case is shown.
[0042]
In these figures, a recording operation is taken as an example, and the drive device performs a seek to search for an address that is a target position on the disc, and after that seek, performs an address check (check whether it is a target address) and records. The operation to start is shown. A solid line arrow indicates landing from a seek and an address reading operation from the position, and a thick line arrow with a diagonal line indicates a recording operation started.
n-1, n, n + 1,... are address values of each sector.
Each model shows the case where the address is a groove address (that is, the address cannot be extracted unless it is read for one sector), but FIG. 1 (a), FIG. 2 (a), FIG. 3, FIG. In the case of a format in which an address is added to the head of a sector as in a) (that is, when an address can be extracted before entering the main data area), the recording operation starts from the sector indicated by the thick arrow in each model. It will be possible one sector before.
[0043]
In FIG. 9, when landing to the sector of address n−1 after seek, the address n−1 and the address n of the next sector could not be read correctly, but the address check was OK by correction or interpolation processing. This is the case. Since the sector where recording can be started is the next sector whose address check is OK, the recording operation can be started from sector (n + 1).
That is, not only when the address can be satisfactorily decoded in a certain sector and the address check is OK, but even if there is an error in the decode address, an appropriate address value is obtained by correction processing and interpolation processing, and the address check is OK. Thus, recording can be started, and recording can be started without waiting until a decoding address without error is obtained as shown in FIG.
[0044]
FIG. 10 shows a case where the address n−1 and the address n of the next sector are “Δ” when landing to the sector of the address n−1 after the seek. That is, as in FIG. 9, even if there is an error in the decode address, recording can be started and no error can be started when an appropriate address value is obtained by correction processing or interpolation processing and the address check is OK. Recording can be started without waiting until a decode address is obtained. Further, even if there is an error in the decode address in reading the address of sector (n + 1) (n + 2) (n + 3) after the start of recording, an appropriate address can be detected by correction or interpolation as indicated by “Δ”.
Therefore, the sector address of the current recording operation can be confirmed, and it is possible to determine whether or not an appropriate recording operation is performed without depending on the tracking performance. That is, the reliability of the recording operation can be improved so that it can be easily understood compared with FIG.
[0045]
FIG. 11 shows a case where the address n-1 can be read without error when landing to the sector of the address n-1 after seek. In this case, recording can be executed from the next sector (n).
Here, even if there is an error in the decode address when reading the address of sector (n) (n + 1) (n + 2) after the start of recording, an appropriate address can be detected by correction or interpolation as shown by “Δ”. As can be seen from the comparison with FIG. 25, the reliability of the recording operation can be improved.
[0046]
FIG. 12 shows a case where address reading NG (with error) is continuously performed for each sector when landing on the sector of address n−1 as in the case of FIG. 26 described above.
However, for each sector after address n, for example, correct addresses can be obtained by correction or interpolation processing, and recording can be started from sector (n + 2). Compared with the case of FIG. 26, significant operational efficiency can be realized.
Although the above examples have been described with respect to the recording operation, the situation is the same in the case of the reproducing operation.
Further, in the case of the format in which the address is added to the head of the sector as described above, recording can be performed from the previous sector in each of the illustrated examples. Therefore, in the case of FIG. 9, the recording operation starts from sector (n). In the case of FIG. 10, it is possible from the sector (n), in the case of FIG. 11 from the sector (n−1), and in the case of FIG. 12 from the sector (n + 1), and recording can be started more quickly.
[0047]
4). Drive device configuration
An example of a disk drive apparatus (recording / reproducing apparatus) that performs recording / reproducing operations on the disk having the address format described above will be described with reference to the block diagram of FIG.
The disk 1 is a disk having an address format having an error correction code as described with reference to FIGS. For example, it is assumed that this is a magneto-optical disk, and the illustrated disk drive apparatus has a configuration example in which recording / reproduction is performed on the magneto-optical disk.
[0048]
The disk 1 is driven to rotate at a predetermined rotational speed by a spindle motor 2. The spindle speed control of the spindle motor 2 is performed by the spindle controller 3. For example, the spindle controller 3 detects the rotational speed of the spindle motor 2 based on the FG pulse (frequency signal synchronized with the rotational speed) from the spindle motor 2, and the reference speed information SK for each zone is supplied from the controller 6 to the reference. The speed information SK and the rotational speed of the spindle motor 2 are compared, and the spindle motor 2 is accelerated / decelerated based on the error information, thereby realizing the disk rotation operation at the required rotational speed.
[0049]
The rotating optical disk 1 is irradiated with laser light from the optical pickup 4. The optical pickup 4 includes, for example, a laser light source 4c using a laser diode or a laser coupler, an optical system 4e using various lenses or a beam splitter, an objective lens 4a serving as an output end of laser light, and a detector 4d for detecting reflected light from the disk. A biaxial mechanism 4b that holds the objective lens 4a so as to be movable in the tracking direction and the focus direction is provided.
On / off of the laser output from the laser light source 4 c and the output level in the optical pickup 4 are controlled by the laser control unit 5.
[0050]
The recording / reproducing apparatus is connected to the host computer 90 by the interface unit 19, and the data recording / reproducing operation is executed when the controller 6 receives a recording request and a reproducing request from the host computer 90. .
At the time of recording, data to be recorded is supplied from the host computer 90 together with a recording request. Recorded data D_REC Is supplied from the interface unit 19 to the encoder 25 to perform a required encoding process.
[0051]
Data recording methods for the disk 1 are roughly classified into an optical modulation method and a magnetic field modulation method.
The light modulation method is a method of modulating laser light with recording data in a state where an external magnetic field is applied in a fixed direction perpendicular to the disk recording surface.
That is, when this method is employed, the controller 6 causes the magnetic head driver 26 to apply an N or S external magnetic field from the magnetic head 27 to the disk recording surface during recording. Then, the recording data encoded by the encoder 25 is supplied to the laser controller 5, and the laser controller 5 turns on / off the laser output from the laser light source 4c according to the recording data. As a result, the portion irradiated with the laser has the polarity of the external magnetic field, and the recorded data is recorded on the disk 1 as magnetic field information.
[0052]
On the other hand, as a magnetic field modulation method, a magnetic field modulated based on recording data is applied to the disk recording surface, and a simple magnetic field modulation method in which laser light is continuously irradiated with a constant light amount, and also to the disk recording surface. There is a laser strobe magnetic field modulation method in which a magnetic field modulated based on recording data is applied and laser light is pulsed.
[0053]
When these magnetic field modulation methods are employed, the controller 6 controls the laser controller 5 so that the laser output from the laser light source 4c is continuously emitted or pulsed during recording. The recording data encoded by the encoder 25 is supplied to the magnetic head driver 26, and the magnetic head driver 26 applies an N or S magnetic field from the magnetic head 27 according to the recording data. As a result, the recording data is recorded on the disk 1 as magnetic field information.
[0054]
The data reading position by the optical pickup 4 is movable in the radial direction. Although not specifically shown, a sled mechanism is provided that allows the entire optical pickup 4 to be moved in the radial direction of the disk, whereby the reading position is moved greatly, and the objective lens 4a is moved to the biaxial mechanism 4b. The reading position is moved by a small amount by the tracking servo operation.
[0055]
Instead of the thread mechanism for moving the optical pickup 4, a mechanism for sliding the disk 1 together with the spindle motor 2 may be provided.
Further, the focus control of the laser spot is performed by moving the objective lens 4a in the direction in which the objective lens 4a is moved toward and away from the disk 1 by the biaxial mechanism 4b.
[0056]
When the disk 1 is loaded by a loading mechanism (not shown), rotation drive by the spindle motor 2 is started. When the disk 1 reaches a predetermined rotational speed, the reading position is controlled so that the optical pickup 4 reads data at a predetermined position on the inner or outer peripheral side of the disk 1. At that position, necessary start-up processing such as focus pull-in is performed, and thereafter a recording or reproducing operation in response to a request from the host computer 90 is started.
[0057]
As the detector 4d of the optical pickup 4, for example, a quadrant detector having a quadrant light receiving area, or magnetic field data (MO data) in a rewritable area that can be recorded / reproduced is detected for each polarization component by the magnetic Kerr effect and used as MO data. A detector for obtaining the RF signal is provided.
[0058]
From each light receiving region of the detector 4d, a current signal S1 corresponding to the amount of received light is output, which is supplied to the I / V conversion matrix amplifier 7. The I / V conversion matrix amplifier 7 performs current-voltage conversion on the received light quantity signal S1, and generates necessary signals such as an RF signal, a push-pull signal, and a focus error signal FE by calculating signals from each light receiving area. To do.
If the disk 1 is a disk whose address is formed by a wobbling track, information corresponding to the wobbling is also extracted.
On the other hand, when the address is recorded as a phase pit or a magnetic field pit, the address information is extracted from the RF signal.
[0059]
A focus error signal FE serving as focus state error information is supplied to the servo controller 8. The servo controller 8 is equipped with a focus phase compensation circuit, a focus driver, and the like as a processing unit of the focus system, and generates a focus drive signal based on the focus error signal FE and applies it to the focus coil of the biaxial mechanism 4b. Thus, a focus servo system for converging the objective lens 4a to the just focus point is configured.
[0060]
From the I / V conversion matrix amplifier 7, an RF signal used for generating the servo clock SCK and the data clock DCK is output as a signal S2. The signal S2 is a signal S3 digitized by the A / D converter 10 after the low frequency fluctuation of the RF signal is removed by the clamp circuit 9.
This signal S3 is supplied to the controller 6, the PLL circuit 11, and the tracking error generator 16.
[0061]
The PLL circuit 11 generates a servo clock SCK synchronized with the RF signal by controlling the oscillation frequency of the internal oscillator based on the phase error between the signal S3 and the oscillation output and performing a predetermined frequency division process. The servo clock SCK is used as a sampling clock in the A / D converter 10 and is supplied to the timing controller 17.
The PLL circuit 11 divides the servo clock SCK to generate a data clock DCK, which is supplied to the timing controller 17, the data detector 14, and the laser controller 5.
[0062]
The timing controller 17 generates necessary timing signals for each unit based on the servo clock SCK and the data clock DCK.
For example, a sampling timing Ps for extracting servo pits for tracking operation, a synchronization timing DSY for decoding operation in the data detection unit 14 and the like are generated.
A tracking error signal TE is generated by the PLL circuit 11, the timing controller 17, and the tracking error generator 16 and supplied to the servo controller 8.
The servo controller 8 is equipped with a tracking phase compensation circuit, a tracking driver, etc. as a processing unit of the tracking system, and generates a tracking drive signal based on the tracking error signal TE and applies it to the tracking coil of the biaxial mechanism 4b. Thus, a tracking servo system for converging the objective lens 4a to the just tracking point is configured.
.
[0063]
The I / V conversion matrix amplifier 7 outputs an RF signal or push-pull signal used for extracting pit data as a signal S4 when the ROM area of the disk 1 is reproduced. At the time of reproducing the rewritable area, a land track MO signal and a groove track MO signal obtained by simultaneous scanning of the land track and the groove track are output as a signal S4.
This signal S4 is a signal S5 digitized by the A / D converter 13 after the low frequency fluctuation of the RF signal is removed by the clamp circuit 12.
[0064]
This signal S5 is supplied to the data detection unit (ie, decoder) 14. In the data detection unit 14, the data is decoded based on the synchronization timing DSY generated by the timing controller 17 based on the data clock DCK, and the reproduced data D_PBGet. For example, a waveform equalization process, a demodulation process for the modulation process employed as a recording format, an error correction process, etc. are performed and the reproduced data D_PBIs encoded as
This reproduction data D_PBIs supplied to the host computer 90 via the interface unit 19.
[0065]
From the I / V conversion matrix amplifier 7, a signal corresponding to the wobbling of the wobbling track or an RF signal is supplied to the address decoder 15.
The address decoder 15 extracts address information by decoding the supplied signal and supplies it to the controller 6. In the controller 6, as the internal address processing unit 6a, as described with reference to FIG. 8, not only error detection but also error correction and interpolation processing are performed as necessary, and then an address check operation is performed. Accordingly, the controller 6 performs the start and end of various operations, operation position confirmation, and the like.
[0066]
Various functional configurations and operations of the address processing unit 6a are conceivable. In the following, the address processing unit is respectively used when the non-binary BCH code is used as the address format and when the binary BCH code is used. The configuration and operation as 6a will be described.
The configuration of the disk drive device is not limited to the example shown in FIG.
[0067]
5). Address processing configuration and operation when non-binary BCH code is adopted
FIG. 14 shows a configuration example of the address processing unit 6a when the address format as shown in FIG. 5 is adopted as a method of adding a non-binary BCH code such as a Reed-Solomon code as an error correction code for an address value.
[0068]
For example, the address information (decoded address) extracted by the decoding process, that is, the address value and the error correction code is supplied from the address decoder 15 of the disk drive device as shown in FIG. 13 to the address processor 6a as shown in FIG. It will be.
The decode address supplied in a serial series for each bit is first input to the serial-parallel converter 61 in the address processor 6a and converted into parallel data in units of 4 bits (1 nibble). The decode address as the parallel data is taken into a register as the decode address holding unit 62 and supplied to the syndrome calculation circuit 63.
The syndrome calculation circuit 63 performs syndrome calculation for error detection on the input decode address, and outputs OK (no error) or NG (error present) information depending on the result. This error detection result information (OK / NG) is supplied to the correction circuit 64 and the terminal LS2 of the selector 68.
[0069]
The correction circuit 64 is a part that performs error correction processing of an address value using an error correction code. When information NG is input as an error detection result from the syndrome calculation circuit 63, the correction circuit 64 is held in the decode address holding unit 62. The address value and error correction code are loaded and correction processing is performed.
The address value and the error correction code (correction address) corrected by the correction circuit 64 are held in a register as the correction address holding unit 65.
Information OK (correction processing OK) or information NG (uncorrectable) as result information in the correction circuit 64 is supplied to the terminal LS3 of the selector 68.
[0070]
The decode address held in the decode address holding unit 62 is loaded into the address holding unit 69 when the selector 68 selects the L1 terminal.
The correction address held in the correction address holding unit 65 is loaded into the address holding unit 69 when the selector 68 selects the L2 terminal.
The address holding unit 69 is a register that holds address information determined as the current address value.
The address loaded into the address holding unit 69 via the selector 68 is supplied to the interpolation address encoder 70 together with the equal sign comparison circuit 72.
The interpolation address encoder 70 is supplied with a value “1”, and adds “1” to the address value supplied from the address holding unit 69 to generate an interpolation address. That is, the address value of the next sector is generated from the address value determined as the address of the current sector.
The interpolation address generated in this way is taken into a register as the interpolation address holding unit 67.
[0071]
The interpolation address held in the interpolation address holding unit 67 is loaded into the address holding unit 69 when the selector 68 selects the L3 terminal.
The interpolation address value held in the interpolation address holding unit 67 and the decode address value held in the decode address holding unit 62 are compared by the comparison circuit 66. In the comparison circuit, if the difference between the interpolation address value and the decode address value is “2” or less, the information OK is used as the comparison result. Is output to the terminal LS1 of the selector 68.
[0072]
The R / W address counter 71 is a counter that generates an address value that is a target position for recording or reproducing operation, and counts up the address value according to the recording / reproducing operation.
FIG. 15A schematically shows the count output of the R / W address counter 71.
The output of the R / W address counter 71 and the address value held in the address holding unit 69 are compared as an address check by the equality comparison circuit 72, and they match (when the address check is OK). Outputs a signal AOK indicating an address match as shown in FIG. This signal AOK is a signal for permitting recording / reproduction and for confirming the recording / reproducing position.
[0073]
In this address processing unit 6 a, that is, one of the decode address held in the decode address holding unit 62, the correction address held in the correction address holding unit 65, and the interpolation address held in the interpolation address holding unit 67. It is selected by the selector 68 and loaded into the address holding unit 69, and is used for comparison processing in the equal sign comparison circuit.
The selection by the selector 68 is determined by information on the terminals LS1, LS2, and LS3, that is, an error detection result, a correction result, and an interpolation address compatibility result.
[0074]
For example, if the error detection result in the syndrome calculation circuit 63 is OK, the decode address held in the decode address holding unit 62 is an appropriate value, and as shown in FIGS. The selector 68 selects the terminal L1 and the decode address is loaded into the address holding unit 69 as a determined address. Then, the equality comparison circuit 72 performs an address check, and if the result is OK, a signal AOK is output.
[0075]
When the error detection result in the syndrome calculation circuit 63 is NG, the decode address held in the decode address holding unit 62 is an inappropriate value. Therefore, in this case, a correction address or an interpolation address is used.
For example, if the correction result is OK in the correction circuit 64, the terminal L2 is selected by the selector 68 as shown in FIGS. 15D and 15F, and the correction address is loaded into the address holding unit 69 as the determined address. Then, the equality comparison circuit 72 performs an address check, and if the result is OK, a signal AOK is output.
If the interpolated address suitability determination result is OK in the comparison circuit 66, the terminal L3 is selected by the selector 68 as shown in FIGS. 15 (e) and 15 (f), and the interpolated address is used as the determined address. To be loaded. Then, the equality comparison circuit 72 performs an address check, and if the result is OK, a signal AOK is output.
Whether to give priority to the correction address or the interpolation address depends on the processing setting (selection logic configuration of the selector 68).
[0076]
Examples of the operation procedure of the address processing unit 6a are shown in FIGS. FIG. 16 shows an example of processing that prioritizes correction addresses, and FIG. 17 shows an example of processing that prioritizes interpolation addresses.
[0077]
First, in the processing example of FIG. 16, in step F201, the input decode address is fetched into the decode address holding unit 62, and in step F202, error detection is performed on the decode address in the syndrome calculation circuit 63.
If information OK indicating no error is supplied to the terminal LS2 of the selector 68 as the error detection result, the selector 68 selects the terminal L1. That is, the process proceeds from step F203 to F204, and the decode address is loaded into the address holding unit 69 as the determined address.
In step F212, the equality comparison circuit 72 performs an address check. If the addresses match, a signal AOK is output as an affirmative result in step F213. If they do not match, the signal AOK is not output as the address check NG (signal ANG).
The decode address loaded in the address holding unit 69 as the determined address is used for generating an interpolation address in step F214. That is, “1” is added to the decode address determined by the interpolation address encoder 70 to generate an interpolation address, which is stored in the interpolation address holding unit 67 as an interpolation address for the next sector in step F215.
[0078]
When information NG indicating that there is an error is output as an error detection result in step F203, in step F205, the correction circuit 64 loads the decode address and performs correction processing using the error correction code.
Here, when the correction processing result is correction OK, the process proceeds from step F206 to F207, and the correction address is loaded into the address holding unit 69 as the determined address. That is, the selector 68 selects the terminal L2 when the error correction result supplied to the terminal LS2 is NG and the correction result supplied to the terminal LS3 is OK.
Then, for the loaded correction address, the address check in steps F212 and F213 is performed, and the signal AOK is output according to the result.
The correction address loaded in the address holding unit 69 as the determined address is used for generating an interpolation address in step F214, and the generated interpolation address is used for processing in the next sector in step F215. 67 is stored.
[0079]
If correction NG is output as the correction result in step F206, the presence / absence of an interpolation address is determined in step F208. That is, it is determined whether or not an interpolation address is stored in the interpolation address holding unit 67 at that time.
If there is no interpolation address, the address check is not performed (that is, the signal AOK is not output), and the processing for the sector is completed.
If the interpolation address exists, the compatibility of the interpolation address is checked in step F209. That is, the comparison circuit 66 compares the decode address and the interpolation address, and if the difference is two or less and the compatibility of the interpolation address is OK, the process proceeds from step F210 to F211 and the interpolation address is set as the determination address. It is loaded into the address holding unit 69. That is, the selector 68 determines that the error correction result supplied to the terminal LS2 is NG, the correction result supplied to the terminal LS3 is NG, and the comparison result supplied to the terminal LS1 is OK. Terminal L3 is selected.
Then, for the loaded interpolation address, the address check in steps F212 and F213 is performed, and the signal AOK is output according to the result.
The interpolation address loaded in the address holding unit 69 as the determined address is used for generating an interpolation address in step F214, and the generated interpolation address is used for processing in the next sector in step F215. 67 is stored.
[0080]
According to the above procedure, one of a decode address, a correction address, and an interpolation address is selected, and an address check is performed to determine whether the signal AOK is output / not output.
[0081]
Next, FIG. 17 shows an example of processing that prioritizes interpolation addresses.
In the processing example of FIG. 17, in step F301, the input decode address is taken into the decode address holding unit 62, and in step F302, the syndrome calculation circuit 63 performs error detection on the decode address.
If information OK indicating no error is supplied to the terminal LS2 of the selector 68 as the error detection result, the selector 68 selects the terminal L1. That is, the process proceeds from step F303 to F304, and the decode address is loaded into the address holding unit 69 as the determined address.
Then, in steps F312 and F313, as in steps F212 and F213 in FIG. 16, an address check is performed in the equality comparison circuit 72, and the signal AOK is output / not output.
Similarly to steps F214 and F215 in FIG. 16, the decode address loaded in the address holding unit 69 as a decision address is used for generating an interpolation address in steps F314 and F315, and an interpolation address for the next sector is set. It is generated and stored in the interpolation address holding unit 67.
[0082]
When information NG indicating that there is an error is output as an error detection result in step F303, the presence / absence of an interpolation address is determined in step F305. That is, it is determined whether or not an interpolation address is stored in the interpolation address holding unit 67 at that time.
If the interpolation address exists, the compatibility of the interpolation address is checked in step F306. That is, the comparison circuit 66 compares the decode address and the interpolation address. If the difference is two or less and the compatibility of the interpolation address is OK, the process proceeds from step F307 to F308, and the interpolation address is loaded into the address holding unit 69 as a determined address. That is, the selector 68 selects the terminal L3 when the error correction result supplied to the terminal LS2 is NG and the comparison result supplied to the terminal LS1 is OK.
The loaded interpolation address is checked in steps F312 and F313, and the signal AOK is output in accordance with the result, and the interpolation address determined as the determined address is generated as an interpolation address in steps F314 and F315. And used for memory.
[0083]
If it is determined in step F305 that there is no interpolation address, the process proceeds to step F309. Here, the correction circuit 64 loads the decode address and performs correction processing using the error correction code.
If the correction processing result is correction OK, the process proceeds from step F310 to F311 and the correction address is loaded into the address holding unit 69 as a determination address. That is, the selector 68 determines that the error correction result supplied to the terminal LS2 is NG, the comparison result supplied to the terminal LS1 is NG, and the correction result supplied to the terminal LS3 is OK. Terminal L2 is selected.
For the loaded correction address, the address check in steps F312 and F313 is performed, and the signal AOK is output according to the result, and the correction address used as the determined address is generated as an interpolation address in steps F314 and F315. And used for memory.
[0084]
According to the above procedure, one of a decode address, a correction address, and an interpolation address is selected, and an address check is performed to determine whether the signal AOK is output / not output.
Although the two processing examples in FIGS. 16 and 17 have been described, of course, other processing examples are conceivable.
For example, a method may be considered in which the correction address is not used as a decision address but is used only for generating an interpolation address.
Furthermore, if the correction capability is sufficient, a configuration and a processing procedure that do not perform the processing related to the interpolation address can be considered.
[0085]
6.2 Address processing configuration and operation when adopting binary BCH code
Next, FIG. 18 shows a configuration example of the address processing unit 6a when the address format as shown in FIG. 6 is adopted as a method of adding a binary BCH code as an error correction code for an address value.
[0086]
For example, the address information (decoded address) extracted by the decoding process, that is, the address value and the error correction code are supplied from the address decoder 15 of the disk drive device as shown in FIG. 13 to the address processing unit 6a as shown in FIG. It will be.
The decode address supplied serially for each bit is taken into the register as the decode address holding unit 81 for each bit and supplied to the syndrome calculation circuit 82.
The syndrome calculation circuit 82 performs syndrome calculation for error detection on the input decode address, and outputs OK (no error) or NG (error present) information according to the result. This error detection result information (OK / NG) is supplied to the terminal LS12 of the selector 85 and the logic circuit 91.
[0087]
The correction circuit 83 is a part that performs error correction processing of the address value using the error correction code, and performs correction processing of the decode address supplied from the syndrome calculation circuit 82.
The address value and the error correction code (correction address) corrected by the correction circuit 83 are held in a register as the correction address holding unit 84.
Information OK (correction processing OK) or information NG (uncorrectable) as result information in the correction circuit 83 is supplied to the terminal LS11 of the selector 85.
[0088]
The decode address held in the decode address holding unit 81 is supplied to the L11 terminal of the selector 85, the comparison circuit 88, and the equality comparison circuit 89.
The correction address held in the correction address holding unit 84 is supplied to the L12 terminal of the selector 85.
The address information selected by the selector 85 is supplied to the interpolation address encoder 86.
The interpolation address encoder 86 is supplied with a value “1”, and adds “1” to the address value supplied from the selector 85 to generate an interpolation address. That is, the address value of the next sector is generated from the address value determined as the address of the current sector.
The interpolation address generated in this way is taken into a register as the interpolation address holding unit 87.
The interpolation address held in the interpolation address holding unit 87 is supplied to the L13 terminal of the selector 85.
The interpolation address value held in the interpolation address holding unit 67 and the decode address value held in the decode address holding unit 81 are compared by the comparison circuit 88.
[0089]
In this example, the selector 85 performs an operation of selecting an address for generating an interpolation address. That is, the terminal according to the error detection result information (OK / NG) from the syndrome calculation circuit 82 supplied to the terminal LS12 and the correction result information (OK / NG) from the correction circuit 83 supplied to the terminal LS11. One of L11, L12, and L13 is selected. That is, any one of the decode address, the correction address, and the interpolation address is loaded into the interpolation address encoder 86 for use in generating the next interpolation address.
[0090]
Similarly to the example of FIG. 14 described above, the R / W address counter 90 is a counter that generates an address value serving as a target position for recording or reproducing operation. The R / W address counter 90 counts up the address value according to the recording / reproducing operation. Go.
The output of the R / W address counter 90 and the address value held in the decode address holding unit 81 are compared as an address check by the equal sign comparison circuit 89, and information is obtained as a comparison result of whether or not they match. OK or information NG is output to the logic circuit 91.
[0091]
The comparison circuit 88 compares whether the difference between the interpolation address value and the decode address value is “2” or less. Further, the output of the R / W address counter 90 is also supplied to the comparison circuit 88. If it is determined that the difference between the interpolation address value and the decode address value is “2” or less, the interpolation address and the R / W The output of the W address counter 90 is compared (address check), and information OK or information NG is output to the logic circuit 91 as a comparison result of whether or not they match.
[0092]
The logic circuit 91 includes error detection result information (OK / NG) from the syndrome calculation circuit 82, information (OK / NG) as an address check result for the interpolation address from the comparison circuit 88, and an equality comparison circuit. The logical operation is performed on the address check result information (OK / NG) from 89, and it is considered that the decode address or interpolation address that is the current address matches the address value from the R / W address counter 90. In this case, a signal AOK indicating an address match is output. This signal AOK is a signal for permitting recording / reproduction and for confirming the recording / reproducing position, as in the example of FIG.
[0093]
That is, in the address processing unit 6a in FIG. 18, when the error detection result for the decoded address is OK, the equality comparison circuit 72 performs an address check for the decoded address held in the decoded address holding unit 62. If the result is OK, the signal AOK is output.
At this time, the decode address is used to generate an interpolation address for the next sector.
[0094]
If the error detection result in the syndrome calculation circuit 82 is NG, the interpolation address is used and an address check is performed in the comparison circuit 88. If the result is OK, a signal AOK is output.
If the error detection result in the syndrome calculation circuit 82 is NG, error correction processing is performed in the correction circuit 83. If the correction is OK, the correction address is the next address in the interpolation address encoder 86. Used for interpolation address generation. On the other hand, if the correction is NG, the current interpolation address is used to generate the next interpolation address in the interpolation address encoder 86.
[0095]
Examples of the operation procedure of such an address processing unit 6a are shown in FIGS.
As shown in FIG. 19, in step F401, the input decode address is taken into the decode address holding unit 81, and in step F402, the syndrome calculation circuit 82 performs error detection on the decode address.
When information OK indicating no error is supplied to the logic circuit 91 as the error detection result, the logic circuit 91 determines the output of the signal AOK based on the address check in the equality comparison circuit 89.
That is, when the address check is performed by the equality comparison circuit 89 in step F405 and the information OK is supplied as the address check result, an affirmative result is obtained in step F406, and the signal AOK is output. .
In the case of address check NG, the signal AOK is not output (signal ANG).
[0096]
On the other hand, when information NG indicating that there is an error is supplied to the logic circuit 91 as the error detection result, the logic circuit 91 determines the output of the signal AOK based on the address check in the comparison circuit 88.
In this case, the presence / absence of an interpolation address is determined in step F407. That is, it is determined whether or not the interpolation address is stored in the interpolation address holding unit 87 at that time.
If there is no interpolation address, the address check is not performed (that is, the signal AOK is not output), and the processing for the sector is completed.
When there is an interpolation address, the compatibility of the interpolation address is checked by the comparison circuit 88 in step F408, and an address check is performed to determine whether the interpolation address matches the output of the R / W address counter 90. .
If the information OK is supplied as the address check result, an affirmative result is obtained in step F409, and the signal AOK is output.
In the case of address check NG, the signal AOK is not output (signal ANG).
[0097]
In addition, the process for generating the interpolation address differs depending on the error detection result in step F403. When the information OK indicating no error is supplied to the selector 85 as the error detection result, the process proceeds to the process of FIG. 20A as indicated by the broken line “F1” in FIG. 19 as the interpolation address generation process.
In this case, as step F410, the selector 85 selects the terminal L11, loads the decode address to the interpolation address encoder 86, and causes the interpolation address encoder 86 to execute interpolation address generation using the decode address. In step F411, the generated interpolation address is stored in the interpolation address holding unit 87 for processing in the next sector.
[0098]
On the other hand, when information NG indicating that there is an error is supplied to the selector 85 as an error detection result, the process proceeds to the process of FIG. 20B as indicated by the broken line “F2” in FIG. 19 as the interpolation address generation process.
In this case, address correction processing is performed in the correction circuit 83 as step F412, but in step F413, the selector 85 branches the processing according to the correction result information (OK / NG).
If the correction is OK, the process proceeds to step F414, and the selector 85 selects the terminal L12 and loads the correction address held in the correction address holding unit 84 into the interpolation address encoder 86. Then, the interpolation address encoder 86 executes interpolation address generation using the correction address, and the generated interpolation address is stored in the interpolation address holding unit 87 for processing in the next sector in step F415.
[0099]
In the case of correction NG, the process proceeds to step F416, and it is first determined whether or not an interpolation address exists in the interpolation address holding unit 87 at that time. If it exists, in step F417, the selector 85 selects the terminal L13 and loads the interpolation address held in the interpolation address holding unit 87 into the interpolation address encoder 86. Then, the interpolation address encoder 86 executes interpolation address generation using the interpolation address, and the generated interpolation address is stored in the interpolation address holding unit 87 for processing in the next sector in step F418.
[0100]
In this example, either the decode address or the interpolation address is selected by the above procedure, the address check is performed, and the output / non-output of the signal AOK is determined. In addition, any one of a decode address, a correction address, and an interpolation address is selected to generate an interpolation address.
In this example, the correction address is not used for the address check in the direct comparison circuit 88 or the equality comparison circuit 89, but by using the correction address for the interpolation address generation, the address check by the correction address is indirectly performed. It can be executed, and the effect of enabling the address correction can be sufficiently obtained. Of course, a configuration example in which the correction address is directly used for the address check is also conceivable. In that case, if the correction capability is sufficient, a configuration and a processing procedure may be considered in which processing related to the interpolation address is not performed.
In this example, since serial processing is performed in units of 1 bit, there is an advantage that the circuit configuration is simplified compared to the example of the address processing unit in FIG.
[0101]
【The invention's effect】
As described above, according to the present invention, the address information of the recording medium is added with the correction code having the error correction capability regarding the address value together with the address value. Therefore, even if the address read is NG, the read address value can be restored to a correct value by correction processing and used to determine whether the address is an address at the target position.
As a result, when an address check is necessary at the start of the operation, such as at the start of a recording / reproducing operation, it is not necessary to wait until the address can be read without error, and the operation efficiency can be greatly improved. . In addition, since an address check operation can be performed after an address read error is corrected, the positional reliability at the time of recording / reproducing operation or the like can be improved.
[0102]
Further, the error correction capability weakens the necessity of a format in which address information is repeatedly recorded in a sector, for example, for example, address information is only once in a sector (or at most twice). By recording, the main data area can be relatively widened and the recording capacity can be improved.
In addition, address read errors are covered by error correction capability, so that even if there are many address read errors due to deterioration of the recording medium, address check and address value can be taken in, and recording / playback etc. due to address read errors It is almost impossible to prevent the operation of. As a result, the life of the recording medium can be increased and the reliability can be improved.
[0103]
Also, in the drive device, whether the current address is the target address is determined by using one of the decoded address, the corrected address, and the interpolation generated address according to the error detection result. By performing the address check, the address check can be executed efficiently, and the operation efficiency of the recording / reproducing operation and the like can be improved.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a sector format example according to an embodiment of the present invention;
FIG. 2 is an explanatory diagram of a sector format example according to the embodiment;
FIG. 3 is an explanatory diagram of a sector format example according to the embodiment;
FIG. 4 is an explanatory diagram of a sector format example according to the embodiment;
FIG. 5 is an explanatory diagram of an example of an address format according to the embodiment.
FIG. 6 is an explanatory diagram of an example of an address format according to the embodiment.
FIG. 7 is a flowchart of an operation example involving address processing according to the embodiment;
FIG. 8 is an explanatory diagram of an operation procedure of address processing according to the embodiment;
FIG. 9 is an explanatory diagram of an operation example at the start of recording according to the embodiment.
FIG. 10 is an explanatory diagram of an operation example at the start of recording according to the embodiment.
FIG. 11 is an explanatory diagram of an operation example at the start of recording according to the embodiment.
FIG. 12 is an explanatory diagram of an operation example at the start of recording according to the embodiment.
FIG. 13 is a block diagram of the disk drive device according to the embodiment.
FIG. 14 is a block diagram of an address processing unit corresponding to a non-binary BCH code according to the embodiment;
FIG. 15 is an explanatory diagram of an operation of the address processing unit according to the embodiment;
FIG. 16 is a flowchart illustrating an operation example of the address processing unit according to the embodiment;
FIG. 17 is a flowchart of an operation example of the address processing unit according to the embodiment;
FIG. 18 is a block diagram of an address processing unit corresponding to a binary BCH code according to the embodiment;
FIG. 19 is a flowchart of an operation example of the address processing unit according to the embodiment;
FIG. 20 is a flowchart illustrating an operation example of the address processing unit according to the embodiment;
FIG. 21 is an explanatory diagram of a conventional sector format.
FIG. 22 is an explanatory diagram of a configuration of a conventional address processing unit.
FIG. 23 is an explanatory diagram of an operation example at the start of conventional recording.
FIG. 24 is an explanatory diagram of an operation example at the start of conventional recording.
FIG. 25 is an explanatory diagram of an operation example at the start of conventional recording.
FIG. 26 is an explanatory diagram of an operation example at the start of conventional recording.
[Explanation of symbols]
1 disk, 2 spindle motor, 3 spindle control unit, 4 optical pickup, 4a objective lens, 4b biaxial mechanism, 4c laser light source, 4d detector, 4e optical system, 5 laser control unit, 6 controller, 6a address processing unit, 7 I / V conversion matrix amplifier, 8 servo controller, 9, 12 clamp circuit, 10, 13 A / D converter, 11 PLL circuit, 14 data detector, 15 address decoder, 16 tracking error generator, 17 timing controller, 19 Interface unit, 25 encoder, 26 magnetic head driver, 27 magnetic head, 61 serial-parallel conversion unit, 62, 81 decode address holding unit, 63, 82 syndrome calculation circuit, 64, 83 correction circuit, 65, 84 correction address Holding unit, 66, 88 comparison circuit, 67, 87 Interpolation address holding unit, 68, 85 selector, 69 Address holding unit, 70, 86 Interpolation address encoder, 71, 90 R / W address counter, 72, 89 Equal sign comparison circuit 91 logic part

Claims (1)

The address information as absolute position information on the recording medium is recorded or reproduced corresponding to the recording medium on which the address code is added with the correction code having the error correction capability related to the address value. As a drive device that can
Decoding means for decoding the address information from information read from the recording medium;
About the address information decoded by the decoding means, detection means for performing error detection using an added correction code;
For the address information decoded by the decoding means, a correction means for performing error correction using the added correction code;
Interpolation means capable of interpolating and generating address values;
If the error detection result of the detection means is no error, select the address value decoded by the decoding means,
The error detection result of the detecting means is an error, and there is an address interpolated by the interpolating means , and the result of comparing the decoded address value with the interpolated address value , if the values with each other is to have compatible satisfies a predetermined condition, the address value interpolated generated by the interpolation means is the determined address,
The error detection result of the detecting means is an error, and there is an address interpolated by the interpolating means, and the result of comparing the decoded address value with the interpolated address value If the values do not meet the specified conditions and are not compatible, the recording / playback operation is not output.
When the error detection result of the detection means is an error and there is no address generated by interpolation by the interpolation means, the address value corrected by the correction means is set as a decision address,
The determination address is further used for interpolation address generation,
Operation control means for setting permission / non-permission of recording and / or reproducing operation on the recording medium;
A drive device comprising:

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