JP3807134B2 - Oscillator circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an oscillation circuit for generating a radio frequency.
[0002]
[Prior art]
Conventionally, an oscillation circuit composed of PLLIC or the like has been used as an oscillation circuit used in a low-power wireless device, and this oscillation circuit outputs a correct oscillation frequency when in a locked state. Therefore, the frequency lock signal output from the PLLIC is monitored, and if there is no frequency lock signal output from the PLLIC, the oscillation is stopped as a lock abnormality.
[0003]
[Problems to be solved by the invention]
However, the oscillation circuit having the above-described configuration has a problem that even if the lock abnormality occurs and the oscillation is stopped, the cause of the lock abnormality cannot be specified.
[0004]
The present invention has been made in view of the above problems, and an object of the present invention is to provide an oscillation circuit that can identify the cause of lock abnormality.
[0005]
[Means for Solving the Problems]
The invention described in claim 1 is an oscillator, a PLL circuit that outputs a lock signal using the oscillation frequency of the oscillator, a frequency divider that divides the output of the oscillator and outputs a frequency-divided signal, a lock signal, The frequency signal is received and the presence / absence of the lock signal is determined. When there is no lock signal, it is determined whether or not the desired frequency division signal is obtained, and the desired frequency division signal is obtained. If not, whether it is within the set time, it is determined, a signal processing unit for the processing corresponding to the determination result, a holding portion for holding the processing content performed by the signal processing unit consists The cause of the lock abnormality can be specified by analyzing the processing content held in the holding unit.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an oscillation circuit according to an embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a schematic configuration diagram of an oscillation circuit according to the present embodiment. FIG. 2 is a flowchart showing the operation of the oscillation circuit according to the present embodiment.
[0007]
As shown in FIG. 1, the oscillation circuit according to the present embodiment has a level that can be detected by a voltage-controlled oscillator 11, a crystal oscillator 12 that serves as a reference for the oscillation frequency, a PLLIC (PLL circuit) 13, and a signal processing unit 15. The frequency divider 14 that divides the output frequency of the crystal oscillator 12 and the lock signal from the PLLIC 13 or the signal from the frequency divider 14 are received, and whether or not the signal is a desired signal (for example, the control voltage is a predetermined value) A signal processing unit 15 that performs processing such as detecting whether or not it is within a range, and a holding unit 16 that includes an EEPROM or the like that holds a result processed by the signal processing unit 15. In the present embodiment, the frequency divider 14 is provided outside the PLLIC 13, but may be configured inside the PLLIC 13. The oscillation circuit having the above-described configuration is incorporated in a part of the receiver or the transmitter to constitute a low power radio apparatus.
[0008]
In the oscillation circuit according to the present embodiment, when the signal processing unit 15 recognizes the lock abnormality from the PLLIC 13 at the time of oscillation, the signal from the frequency division unit 14 is confirmed, and when the signal is not a desired one, the crystal oscillator 12 When an abnormality or a desired signal can be confirmed, it is possible to identify a defect as an abnormality of the voltage controlled oscillator 11 or the PLLIC 13 itself.
[0009]
Next, the operation of the oscillation circuit according to the present embodiment will be described with reference to FIG. First, the signal processing unit 15 outputs an oscillation command in response to an input button or sensor input (S21), and a timer count is started by a timer provided in the signal processing unit 15 (S22). The measurement time by this timer is arbitrarily set according to the system. The signal processor 15 monitors the lock signal from the PLLIC 13 (S23), and if there is a lock signal, oscillates (S24). If there is no lock signal, the frequency-divided signal from the frequency-dividing unit 14 is confirmed (S25), and if it is not the desired frequency-divided signal, it is written in the holding unit 16 that an abnormality has occurred in the crystal oscillator 12 (S28). . If a desired frequency-divided signal is obtained, the set time of the timer is confirmed (S26), and if within the set time, the signal processing unit 15 performs the operation of locking the PLLIC 13 again (S27). If it is not within the timer set time, it is determined that the voltage controlled oscillator 11 or the PLLIC 13 itself is abnormal, and that fact is written in the holding unit 16 (S29).
[0010]
DETAILED DESCRIPTION OF THE INVENTION
In the oscillation circuit having the above-described configuration, the reason why the desired frequency cannot be oscillated can be confirmed by analyzing the data held in the holding unit, thereby easily identifying the reason why the oscillation cannot be performed. It can be done. In particular, it is very important to be able to specify the reason why a desired frequency cannot be transmitted in a low-power radio apparatus in which the transmission frequency needs to be extremely stable.
[0011]
【The invention's effect】
As described above, in the first aspect of the present invention, the oscillator, the PLL circuit that operates using the oscillation frequency of the oscillator, the frequency divider that divides the output of the oscillator, and the frequency-divided signal are received. The signal processing unit that can perform processing corresponding to the results and the holding unit that holds the processing contents performed by the signal processing unit are held in the holding unit when the desired frequency cannot be oscillated. By reading the recorded data, it can be used as a clue to identify the cause, so that an oscillation circuit capable of identifying the cause of the lock abnormality can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of an oscillation circuit according to the present embodiment.
FIG. 2 is a flowchart showing the operation of the oscillation circuit according to the present embodiment.
[Explanation of symbols]
11 Voltage controlled oscillator 12 Crystal oscillator 13 PLLIC
14 Dividing unit 15 Signal processing unit 16 Holding unit

Claims (1)

The oscillator, the PLL circuit that outputs the lock signal using the oscillation frequency of the oscillator, the frequency divider that divides the output of the oscillator and outputs the divided signal, and the lock signal and the frequency-divided signal are received. If there is no lock signal, determine if the desired divided signal is obtained, and if the desired divided signal is not obtained, within the set time And a signal processing unit that performs processing corresponding to the determination result, and a holding unit that holds the content of processing performed by the signal processing unit, and is held in the holding unit An oscillation circuit characterized in that the cause of a lock abnormality can be identified by analyzing processing contents.

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