JP3794547B2 - Semiconductor device having test function, charge / discharge protection circuit, battery pack incorporating the charge / discharge protection circuit, and electronic apparatus using the battery pack - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a test function, and in particular, using a single test terminal, the delay time of a delay circuit can be arbitrarily controlled between two different delay times and no delay. The present invention relates to a semiconductor device having a test function, a charge / discharge protection circuit such as a Li-ion secondary battery having a test function, a battery pack incorporating the charge / discharge protection circuit, and an electronic device such as a mobile phone using the battery pack.
[0002]
[Prior art]
Li-ion secondary batteries are often used for portable electronic devices. Li-ion secondary batteries have a risk of causing an accident due to precipitation of metallic Li when overcharged, and have a problem that the number of repeated charge / discharge cycles decreases when overdischarged. For this reason, a protection switch is provided in the charging / discharging path between the secondary battery and the device main body, and this is detected when the battery is overcharged above a predetermined voltage or overdischarged below a predetermined voltage. Is turned off to prevent further overcharge and overdischarge.
[0003]
For example, Japanese Patent Laid-Open No. 9-182283 discloses a protection circuit that detects overcharge, overdischarge, and overcurrent of a Li ion secondary battery. FIG. 3 is an example of a conventional charge / discharge protection circuit disclosed in the above publication. In general, when the battery voltage becomes close to the end voltage at which the discharge operation should be stopped, the voltage margin becomes small and malfunctions due to sudden load fluctuations are likely to occur. Accordingly, it is not necessary to turn off the protection switch immediately even if the voltage is lower than the end voltage, but it is necessary to turn off the protection switch only when the state continues for a certain period or longer. For this purpose, FIG. 3 uses a timer composed of an internal oscillation circuit and a frequency dividing counter.
[0004]
In FIG. 3, the voltage comparison circuit COMP504 compares the reference voltage V4 and the divided voltage VCC / N, and when the battery voltage VCC becomes equal to or lower than the end voltage, a low level signal is output and the frequency division counter 502 is reset. To start counting. When the counted value reaches a value set in advance by the decoder 505, the latch circuit 505 is set to turn off the protection switch 507 composed of a MOS transistor.
[0005]
However, if the battery voltage VCC returns to a voltage equal to or higher than the original end voltage before the frequency dividing counter 502 reaches a preset value, a reset signal is generated and the frequency dividing counter 502 is reset during counting. Thus, if the setting by the decoder circuit 505 is set to a relatively long time in consideration of the load fluctuation, the protection switch 507 is provided when the battery voltage VCC temporarily drops below the end voltage with respect to the load fluctuation. The malfunction that turns off is eliminated.
[0006]
As in the case of the overdischarge described above, all of the delay times when overcharge or overcurrent is detected can be determined by the internal oscillation circuit and the counter. According to this, it is not necessary to provide an external capacitor for determining the delay time, and the number of parts of the protection circuit board can be reduced.
[0007]
However, since the delay time when detecting overdischarge and overcurrent is generally about 10 mS to several tens of mS, the test time does not have a significant effect, but the delay time when detecting overcharge is usually set to about several seconds. Has been. Therefore, in the above technique, a time of several seconds or more is always required when testing an overcharge detection operation. Furthermore, when measuring an accurate overcharge detection voltage value, a waiting time of several seconds or more is required every time the voltage is stepped. Therefore, assuming that the detection voltage can be measured in 25 steps, the waiting time is 2 seconds. Then, the time required for measuring the overcharge detection voltage value is 50 seconds, which is too long for mass production and is not at a practical level.
[0008]
Therefore, the applicant first shortens the delay time of the delay circuit that determines the delay time when overcharge, overdischarge, or overcurrent is detected by using a single test terminal by increasing the oscillation frequency. Has been proposed (see Japanese Patent Application No. 2000-83375).
[0009]
FIG. 4 is a diagram showing a charge / discharge protection circuit and a battery pack using the circuit in the above application, and is an example of a circuit to which the present invention is applied.
First, the operation of the charge / discharge protection circuit in the above application will be described with reference to FIG.
As shown in the figure, the semiconductor device (charge / discharge protection circuit) 1 constituting the main part of the battery pack is roughly divided into an overcharge detection circuit 11, an overdischarge detection circuit 12, an overcurrent detection circuit 13, and a short circuit detection. The circuit 14 includes an abnormal charger detection circuit 15, an oscillator 16, and a counter 17.
[0010]
When overcharge, overdischarge, overcurrent, or short circuit is detected by the overcharge detection circuit 11, overdischarge detection circuit 12, overcurrent detection circuit 13, or short circuit detection circuit 14, the oscillator 16 starts operation and the counter 17 counts. Begin. When the delay time set at the time of each detection is counted by the counter 17, in the case of overcharge, the Cout output becomes a low level through the logic circuit (latch etc.) 18 and the level shift 19, and the charge control FET Q1 is turned on. In the case of overdischarge, overcurrent, or short circuit, the Dout output goes low through the logic circuit 20 to turn off the discharge control FET Q2.
[0011]
The abnormal charger detection circuit 15 prevents a large voltage (V-potential) from being applied to the inputs of the overcurrent detection circuit 13 and the short-circuit detection circuit 14 when a large voltage is applied to the battery pack when an abnormal charger or the like is connected. In this circuit, the switches SW1 and SW2 are turned off to prevent the overcurrent detection voltage value and the short-circuit detection voltage value from shifting due to the change in Vth of the transistors constituting the switches SW1 and SW2. .
[0012]
Normally, the delay time when overdischarge is detected by the overdischarge detection circuit 12 is about 16 mS, the delay time when overcurrent is detected by the overcurrent detection circuit 13 is about 10 mS, and the delay time when short circuit is detected by the short circuit detection circuit 14 is about 1 mS. However, the delay time at the time of overcharge detection by the overcharge detection circuit 11 is 1S or more. Therefore, when testing the semiconductor device 1 or the protection circuit board, the test terminal is fixed at a low level (for example, the switch SW3 is turned on), thereby increasing the output frequency of the oscillator 16 and shortening the delay time. By doing so, the test time can be shortened. This configuration is effective when detecting overcharge, overdischarge, or overcurrent, but is particularly effective when detecting overcharge.
[0013]
5 and 6 are diagrams for explaining a configuration in which the delay time is changed by changing the frequency of the oscillator with a single test terminal in the above application.
The oscillator 16 of FIG. 5 is a ring oscillator using constant current inverters 111 to 115 and capacitors 116 and 117. The oscillation frequency of this ring oscillator can be changed by (1) the constant current value of the constant current sources 105 and 109, (2) the values of the capacitors 116 and 117, and (3) the thresholds of the inverters 112 and 115.
[0014]
FIG. 5 shows an example in which the oscillation frequency is changed by changing the constant current values of the constant current sources 105 and 109.
In FIG. 5, the test terminal is pulled up to Vdd by a resistor 101. For example, when the switch SW3 connected to the test terminal is turned off and the test terminal is opened, the gate voltages of the Pch MOS transistors 102 and 103 are set to the high level by the pull-up resistor 101. Therefore, the Pch MOS transistor 102 and 103 are off. Therefore, the oscillation frequency at this time is determined by the values of the constant currents 105 and 109 and the capacitors 116 and 117.
[0015]
However, when the switch SW3 is turned on and the test terminal is set to the low level, the gate voltage of the Pch MOS transistors 102 and 103 is set to the low level and the Pch MOS transistors 102 and 103 are turned on. Is the sum of the constant current values in the constant current source 105 and the constant current source 104, and the sum of the constant current values in the constant current source 109 and the constant current source 108, so that the oscillation frequency is increased, resulting in overcharging. The delay time at the time of detection can be shortened.
[0016]
For example, when the ratio of the constant current between the constant current source 105 and the constant current source 104 and the ratio of the constant current between the constant current source 109 and the constant current source 108 are set to 1: 9, the oscillation frequency becomes 10 times and the delay time becomes 1 / 10. In this case, the test time of the semiconductor device 1 or the protection circuit board on which the semiconductor device 1 is mounted can be shortened to 1/10.
[0017]
FIG. 6 shows an example in which the values of the capacitors 116 and 117 are changed.
In FIG. 6, when the switch SW3 is off and the test terminal is open, Vdd is applied to the gates of the Nch MOS transistors 216 and 217, and the Nch MOS transistors 216 and 217 are on, so that the oscillation frequency is determined. The values of the capacitors are capacitor 212 + 213 and capacitor 214 + 215.
[0018]
However, when the switch SW3 is turned on and the test terminal is set to the low level, the gates of the Nch MOS transistors 216 and 217 are grounded, the Nch MOS transistors 216 and 217 are turned off, and the values of the capacitors are limited to the capacitors 213 and 215. Thus, the oscillation frequency is increased, the delay time is shortened, and as a result, the test time can be shortened.
In addition to the above, the oscillation frequency can also be obtained by changing the threshold of the constant current inverter constituting the ring oscillator.
[0019]
[Problems to be solved by the invention]
As described above, the prior art shown in FIG. 3 takes too much time for mass production and is not suitable for practical use. The invention previously filed enables the test time to be shortened by making the frequency of the oscillator variable between the normal frequency and the acceleration frequency higher than that using the test terminal. It solves the problems in the prior art.
[0020]
However, in a semiconductor device including a delay circuit, for example, a semiconductor device in which the delay time after detection by the voltage detector is 5 seconds (for example, an IC such as the above-described charge / discharge protection circuit), the test time is shortened and 5 seconds. The delay time must be guaranteed. Furthermore, in the test of the semiconductor device, when it is necessary to repeat the detection state and the non-detection state due to the circuit configuration (including the circuit under test), the state can be changed between the detection state and the non-detection state without delay time. Otherwise, it takes a lot of test time. A semiconductor device including such a delay circuit having a long test time has a problem that it is inferior in mass productivity as compared with a semiconductor device having a short test time.
[0021]
That is, for example, in a large-volume production IC for Li-ion protection, the recovery time when the yield drops due to a sudden cause, the test time is long, so the test time has a large impact, and the response to mass production may be delayed. There was a problem. In addition, the same problem occurred in the Li-ion battery pack test at the customer site.
[0022]
It is an object of the present invention to further improve the above-described invention of the prior application, and to use a single test terminal to set a delay time by a delay circuit, a normal delay time mode, a delay time shortening mode, or a no delay time mode. If the test time can be shortened and a long delay time is guaranteed, and it is necessary to repeat the detection state and the non-detection state (including the circuit under test), the delay Semiconductor device capable of changing state between detection state and non-detection state without time (Claims 1 and 2), charge / discharge protection circuit such as Li ion secondary battery (Claims 3 to 5), charge / discharge A battery pack incorporating a protection circuit (Claim 6), and various electronic devices (Claim 7) such as a mobile phone using the battery pack.
[0023]
[Means for Solving the Problems]
In order to achieve the above object, the present invention has the following configuration.
According to the first aspect of the present invention, there is provided a semiconductor device having a test function having a test terminal (TEST) and determining a delay time when a predetermined state is detected by the test terminal (TEST). And the delay circuit (oscillator B3, counter B4) and the test terminal (TEST) are any one of the first level range (L), the second level range (H), and the third level range (M). The delay time of the delay circuit is switched to any one of a normal delay time mode, a delay time shortening mode, and a no delay time mode according to the means for inputting the voltage of the test signal and the voltage input to the test terminal. It is characterized by doing so.
[0024]
According to the second aspect of the present invention, the frequency of the oscillator (B3) that configures the delay circuit based on the voltage input to the test terminal (TEST) is configured by the oscillator (B3) and the counter (B4). It is characterized by switching.
[0025]
The invention according to claim 3 is a charge / discharge protection circuit that detects overcharge, overdischarge, or overcurrent of a secondary battery and protects the secondary battery from overcharge, overdischarge, or overcurrent, A delay circuit for determining a delay time upon detection of overcharge, overdischarge, or overcurrent comprising an oscillator (B3) and a counter (B4), and a first level range (L) as a potential of a test terminal (TEST), The delay time of the delay circuit is switched based on the means for inputting the potential of the second level range (H) and the third level range (M) and the potential of the test terminal (TEST). Yes.
[0026]
According to a fourth aspect of the present invention (see FIG. 5), the oscillator is constituted by a ring oscillator (16) in which a plurality of delay elements each including a constant current inverter and a capacitor are connected in a closed loop, and means for switching the delay time is defined as the delay element. A feature is that the constant current value of the constant current source constituting the current inverter is substantially changed.
[0027]
In the invention according to claim 5 (see FIG. 6), the oscillator is constituted by a ring oscillator (16) in which a plurality of delay elements each comprising a constant current inverter and a capacitor are connected in a closed loop, and means for switching the delay time is constituted by the delay element. It is characterized in that it is a means for substantially changing the capacitance of the capacitor.
[0028]
A sixth aspect of the present invention is a battery pack incorporating the charge / discharge protection circuit according to any of the third to fifth aspects, and the seventh aspect of the present invention relates to an electronic device using the battery pack ( For example, a mobile phone, a digital camera, and a portable audio device).
[0029]
DETAILED DESCRIPTION OF THE INVENTION
(Overview)
By selecting one of the three voltage levels “L”, “H”, and “M” as the input for a single test terminal, the delay time of the delay circuit can be changed to the normal delay time mode and delay time reduction mode. , And switch to the no delay time mode. At this time, if the ratio between the normal delay time mode and the delay time reduction mode is fixed, for example, if the delay time reduction mode is 1/100, the delay time in the delay time reduction mode is usually measured. If it is designed to guarantee the delay time, it is possible to shorten the test time including the customer test time. Even when it is necessary to repeat the detection state and the non-detection state (when there is a circuit under test), changing the state in the no delay time mode greatly contributes to the improvement of the test time efficiency.
[0030]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram for explaining an embodiment of the present invention.
In the figure, 1 is a semiconductor device (for example, an IC such as a charge / discharge protection circuit), B1 and B2 are inverters having different threshold voltages, B3 is an oscillator, B4 is a counter, C is a comparator, and A is a circuit on a semiconductor integrated circuit. A test circuit, TEST represents a test terminal, and Out represents an output terminal.
[0031]
In this configuration, an input 1 that is a detection voltage (for example, a detection voltage from an overvoltage detection circuit) and an input 2 that is a reference voltage from a reference voltage source are input to the comparator C, and the detection voltage is more than the reference voltage. When it is high, that is, when (voltage of input 1 of comparator C)> (voltage of input 2 of comparator C), the output of comparator C becomes “H”, and only at this time, oscillator B3 is in an operating state and the output of comparator C is output. When “L” is “L”, the non-operating state is continued.
[0032]
The frequency of the oscillator B3 is a normal frequency when the output of the inverter B2 is “H” (corresponding to the case where the test terminal TEST is “L”), and when the output of the inverter B2 is “L” (test) It is assumed that an accelerated frequency (acceleration frequency) is generated (corresponding to the case where the terminal TEST is “H”).
[0033]
In FIG. 1, it is assumed that the applied maximum voltage is Vdd, the applied minimum voltage is Gnd, and the circuit block B1 and the circuit block B2 are inverters having different threshold voltages. In the present embodiment, the threshold voltage (VB1) of the inverter B1 <the threshold voltage (VB2) of the inverter B2.
[0034]
FIG. 2 is a diagram showing an input range of an applied voltage to the test terminal TEST, a range in which the output of the inverter B2 is “L”, and a range in which the output of NOR1 is “H”. As shown in the figure, the range of the applied voltage to the test terminal TEST from “Vdd to VB2” is represented by “H”, the range of “VB2 to VB1” is represented by “M”, and “VB1 to Gnd” The range is represented by “L”.
[0035]
Hereinafter, an operation when the potential of the test terminal TEST is in the ranges of “L”, “H”, and “M” as described above will be described. “L”, “H”, and “M” in this embodiment correspond to the first level range, the second level range, and the third level range in the claims.
[0036]
(1) Operation when the voltage range of the test terminal TEST is “L”:
When the voltage range of the test terminal TEST is “L”, that is, lower than the threshold voltage VB1 of the circuit block B1, “H” is applied to the input of NOR1 and its output becomes “L”. To be fixed. Therefore, the NAND3 enters a state of waiting for an input from the NAND1.
[0037]
Here, when the voltage at the input 1 of the comparator C becomes higher than the voltage at the input 2 and the output of the comparator C becomes “H”, the oscillator B3 enters an operating state, and a clock input is given from the oscillator B3 to the counter B4. The clock input at this time is a normal clock input that is not accelerated because the output of the inverter B2 is “H”. When the output of the counter B4 becomes “H”, NAND1 is inverted, and the output terminal voltage changes from Vdd to Gnd potential.
[0038]
(2) When the voltage range of the test terminal TEST is “H”:
In the case of (1) above, when the voltage range of the test terminal TEST is “H”, that is, higher than the threshold voltage VB2 of the circuit block B2, “H” is applied to the input of NOR1 and its output becomes “L”. Similarly to the above, the output of NAND2 is fixed to “H”. Therefore, the NAND3 enters a state of waiting for an input from the NAND1.
[0039]
Here, when the voltage of the input 1 of the comparator C becomes higher than the voltage of the input 2 and the output of the comparator C becomes “H”, the oscillator B3 is in an operating state, and a clock input is given from the oscillator B3 to the counter B4. Since the clock input at this time is accelerated because the output of the inverter B2 is “L”, the output of the counter B4 is output in a significantly shorter time than in the case of (1), and this short time In response to the output from the counter B4, NAND1 is inverted and the output terminal voltage Out changes from Vdd to Gnd potential.
[0040]
The ratio of one cycle of clock input to the counter B4 in the case of (1) above and one cycle of clock input to the counter B4 in this example is set to about 1: 100, for example. The ratio of one cycle is the delay time in the case of (1) above (when the voltage range of the test terminal TEST is “L”) and in this example (when the voltage range of the test terminal TEST is “H”) ) Delay time ratio.
[0041]
(3) When the voltage range of the test terminal TEST is “M”:
When the voltage range of the test terminal TEST is “M”, that is, higher than the threshold voltage VB1 of the circuit block B1 and lower than the threshold voltage VB2 of the circuit block B2, “L” is applied to both inputs of NOR1 and the output is Becomes “H”. Since the “H” output of NOR1 is inverted and input to NAND1, the output of NAND1 is fixed to “H”, and NAND3 enters a state of waiting for the input of NAND2.
[0042]
Here, when the voltage of the input 1 of the comparator C becomes higher than the voltage of the input 2 and the output of the comparator C becomes “H”, the output of the NAND 2 is inverted and becomes “L” and is input to the NAND 3. The output terminal voltage changes from Vdd to Gnd potential.
[0043]
In this case, that is, when the voltage range of the test terminal TEST is between the threshold voltage VB1 of the circuit block B1 and the threshold voltage VB2 of the circuit block B2, the voltage change of the input 1 using the comparator C is changed to the oscillator B3 or the counter B4. Can be detected without waiting time.
[0044]
In the above embodiment, the oscillator B3 is in an operating state when the output of the comparator C is “H”, and conversely, when the output of the comparator C is “L”, the oscillator B3 is in a non-operating state. In this configuration, for example, as shown by the broken line in FIG. 5, the Nch MOS transistors 161 and 162 and the inverter 163 are provided in the middle stage of the ring oscillator 16, and as shown by the broken line in FIG. Further, this can be realized by providing Nch MOS transistors 164 and 165 and an inverter 166.
[0045]
5 and 6, the normal frequency is obtained when the test terminal is at the high level “H”, and the high frequency is obtained when the test terminal is at the low level “L”. 5 and FIG. 6, the pull-up connected test terminals are pulled down, and an inverter is inserted between the test terminals TEST and the gates of the Pch MOS transistors 102 and 103 and the Nch MOS transistors 216 and 217. When the test terminal is at the high level “H”, the frequency is high, and when the test terminal is at the low level “L”, the frequency is low, and the operation as in the present embodiment can be performed.
[0046]
As described above, according to the present embodiment, the oscillator B3 and the counter B4 are set by setting the input voltage range of the single test terminal TEST to any one of “L”, “H”, and “M”. The delay time of the delay circuit can be switched to either the normal delay time mode, the delay time shortening mode, or the no delay time mode, so that the test time can be shortened and the delay is long A semiconductor device capable of changing the state between a detection state and a non-detection state without delay time when the time is guaranteed and it is necessary to repeat the detection state and the non-detection state (including a circuit under test) realizable.
[0047]
This configuration is particularly effective when applied to a charge / discharge protection circuit such as a Li-ion secondary battery as described with reference to FIG. 4, and a battery pack incorporating the charge / discharge protection circuit having this configuration or the battery pack is provided. The present invention can also be applied to used electronic devices such as mobile phones, digital cameras, and portable audio devices.
[0048]
【The invention's effect】
According to the present invention, the delay time of the delay circuit can be switched to the normal delay time mode, the delay time shortening mode, or the no delay time mode by using a single test terminal. When the test time can be shortened and a long delay time is ensured, and it is necessary to repeat the detection state and the non-detection state (including the circuit under test), the detection state Semiconductor device capable of changing state to detection state (Claims 1 and 2), charge / discharge protection circuit such as Li ion secondary battery (Claims 3 to 5), and battery pack incorporating the charge / discharge protection circuit (Claim 6), various electronic devices (claim 7) such as a mobile phone using the battery pack can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining an embodiment of the present invention.
FIG. 2 is a diagram showing an input range of an applied voltage to a test terminal TEST, a range in which an output of an inverter B2 is “L”, and a range in which an output of NOR1 is “H”;
FIG. 3 is a diagram showing an example of a conventional charge / discharge protection circuit.
FIG. 4 is a diagram showing a charge / discharge protection circuit and a battery pack using the circuit in the prior application.
FIG. 5 is a diagram for explaining a configuration in which the delay time is changed by changing the frequency of an oscillator with a single test terminal in the prior application (part 1);
FIG. 6 is a diagram for explaining a configuration in which the delay time is changed by changing the frequency of the oscillator with a single test terminal in the prior application (part 2);
[Explanation of symbols]
TEST: Test terminal,
A: Circuit under test,
Out: Output terminal,
B1, B2: circuit block (inverter),
B3: circuit block (oscillator),
B4: circuit block (counter),
1: Semiconductor integrated circuit (IC such as charge / discharge protection circuit),
11: Overcharge detection circuit,
12: Overdischarge detection circuit
13: Overcurrent detection circuit,
14: short circuit detection circuit,
15: Abnormal charger detection circuit,
16: Oscillator
17: Counter
18, 20: logic circuit (latch),
19: Level shift circuit,
Q1, Q2: transistors,
SW1, SW2, SW3: switch,
101, 201: pull-up resistors,
102, 103, 302: Pch MOS transistor,
104-110, 202-206, 301: constant current source,
111 to 115, 207 to 211: constant current inverter,
116, 117, 212 to 215: capacitors,
161, 162, 164, 165: Nch MOS transistors,
163, 166: inverter,
303, 304: Nch MOS transistor,
401, 402: Transmission gate,
501: built-in oscillator,
502: Frequency division counter,
503: Gate,
504: Comparator (COMP),
505: Decoder (latch circuit),
506: Inverter,
507: Protection switch.

Claims (7)

A semiconductor device having a test function having a test terminal and determining a delay time when a predetermined state is detected by the test terminal,
A delay circuit; means for inputting a voltage of any one of a first level range, a second level range, and a third level range to the test terminal; and the delay circuit according to the voltage input to the test terminal. And a means for switching the delay time to any one of a normal delay time mode, a delay time shortening mode, and a no delay time mode. 2. The semiconductor having a test function according to claim 1, wherein the delay circuit is constituted by an oscillator and a counter, and the frequency of the oscillator constituting the delay circuit is switched based on a voltage input to the test terminal. apparatus. A charge / discharge protection circuit that detects overcharge, overdischarge, or overcurrent of a secondary battery and protects the secondary battery from overcharge, overdischarge, or overcurrent,
A delay circuit that determines an overcharge, overdischarge, or overcurrent detection time including an oscillator and a counter, and potentials of a first level range, a second level range, and a third level range as potentials of test terminals. A charge / discharge protection circuit comprising means for inputting and means for switching a delay time of the delay circuit based on a potential of the test terminal. The oscillator is composed of a ring oscillator in which a plurality of delay elements including a constant current inverter and a capacitor are connected in a closed loop, and the means for switching the delay time is a constant current value of a constant current source constituting the constant current inverter of the delay element. 4. The charge / discharge protection circuit according to claim 3, wherein the charge / discharge protection circuit is substantially changed. The oscillator is constituted by a ring oscillator in which a plurality of delay elements each including a constant current inverter and a capacitor are connected in a closed loop, and the means for switching the delay time is a means for substantially changing the capacitance of the capacitor constituting the delay element. The charge / discharge protection circuit according to claim 3. A battery pack incorporating the charge / discharge protection circuit according to claim 3. An electronic device using the battery pack according to claim 6.

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