JP3948435B2 - Secondary battery protection IC and battery pack and electronic device using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention overcharges and overcharges a secondary battery such as a lithium (Li) ion / lithium (Li) polymer secondary battery of a battery pack used in various electronic devices such as a mobile phone, a notebook computer, and a PDA (Personal Digital Assistance). The present invention relates to technology for protecting against discharge and overcurrent, and particularly relates to a secondary battery protection IC capable of improving the efficiency of overcharge, overdischarge and overcurrent detection confirmation tests, and battery packs and electronic devices using the same. is there.
[0002]
[Prior art]
For example, Patent Document 1 discloses a conventional technique for protecting secondary batteries of battery packs used in various electronic devices such as mobile phones, notebook computers, and PDAs (Personal Digital Assistance) from overcharge, overdischarge, and overcurrent. There is a technology.
[0003]
In this prior art, as shown in FIG. 3, a timer circuit including an internal oscillator and a frequency dividing counter and a latch circuit (LT2) are provided so that a delay time is provided when overcharge, overdischarge, and overcurrent are detected. In particular, the internal impedance of the secondary battery (lithium (Li) ion battery) prevents the battery voltage (VCC) from being temporarily determined to be lower than the end voltage and erroneously determined that the discharge voltage itself is lower than the end voltage. can do.
[0004]
In the conventional technique, the delay time when detecting overcharge, overdischarge, and overcurrent can all be determined by the internal oscillation circuit and the counter. Therefore, an external capacitor for determining the delay time is not necessary, and the number of parts of the protection circuit board can be reduced.
[0005]
When testing a protection circuit board provided with such an internal oscillation circuit and a counter, the delay time when overdischarge and overcurrent are detected is generally about 20 mS (milliseconds), so the test time is very long. Although there is no effect, the delay time when detecting overcharge is usually set to about a few seconds. Therefore, when testing the overcharge detection operation, a time of several seconds or more is necessary.
[0006]
In particular, when measuring (testing) an accurate overcharge detection voltage value, a waiting time of several seconds or more is required every time the voltage is stepped. Therefore, assuming that the detection voltage can be measured in 25 steps, the waiting time Is 2 seconds, the time required to measure the overcharge detection voltage value is 50 seconds, which is not at a level where mass production is possible.
[0007]
[Patent Document 1]
JP-A-9-182283
[Problems to be solved by the invention]
The problem to be solved is that in the conventional technology, the delay time for overcharge detection in the protection circuit of the secondary battery is set to about several seconds, and it takes time to test the overcharge detection operation. Is a point.
[0009]
The object of the present invention is to solve these problems of the prior art, improve the efficiency of a test of a circuit for protecting a secondary battery from overcharge, overdischarge, and overcurrent, and to provide a battery pack using the protection circuit and the battery pack. The purpose is to increase the efficiency of the manufacturing process of various electronic devices such as mobile phones, notebook computers, and PDAs used.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, in the present invention, when testing the overcharge detection operation of the secondary battery protection IC, the delay time for overcharge detection is shortened by increasing the frequency of the oscillation circuit. It is characterized by shortening the time required. In particular, in order to increase the frequency of the oscillation circuit, the value of the constant current that determines the oscillation frequency is increased. In order to increase the value of the constant current, the values of the overcharge detection output terminal (Cout), the ground terminal (Vss), and the charger minus potential input terminal (V−) are input, and the overcharge detection output The terminal (Cout) is at a level at which the charge control FET is turned on (high level when the charge control FET is N-channel) , and the charger minus potential input terminal (V−) is at a level lower than the ground terminal (Vss). When set, an additional constant current circuit is additionally connected.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0012]
FIG. 1 is a block diagram showing a configuration example of a secondary battery protection IC and a battery pack using the same according to the present invention, and FIG. 2 shows an oscillation circuit provided in the secondary battery protection IC in FIG. 2 is a block diagram showing a configuration example of a test control circuit for changing the frequency thereof.
[0013]
In FIG. 1, 1 is a secondary battery protection IC according to the present invention (denoted as “protection device” in the figure), 2 is an overcharge detection circuit comprising comparators 2a and 2b, and 3 is an overdischarge comprising comparators 3a and 3b. Detection circuit, 4 is an overcurrent detection circuit, 5 is a short circuit detection circuit, 6 is an abnormal charger detection circuit, 6a is an N-channel FET, 7 is an oscillation circuit, 8 is a counter circuit, 9a and 9b are logic circuits, and 10 is a level. Shift, 11 is a battery pack, 12 is a positive terminal, 13 is a negative terminal, 14 is a charger, 15 is a secondary battery cell such as a lithium (Li) ion / lithium (Li) polymer secondary battery, C Is a capacitor, R is a resistor, Vdd is a base potential terminal of the secondary battery protection IC1, Vss is a ground terminal of the secondary battery protection IC1, Dout is an overdischarge detection output terminal, and Cout is overcharged. Detection output terminal, V- is charger negative potential input terminal.
[0014]
The battery pack 11 using the secondary battery protection IC 1 of this example is used for various electronic devices such as a mobile phone, a notebook computer, and a PDA.
[0015]
As shown in FIG. 1, the secondary battery protection IC 1 provided in the battery pack 11 of this example is roughly composed of an overcharge detection circuit 2, an overdischarge detection circuit 3, an overcurrent detection circuit 4, and a short circuit detection circuit 5. And an abnormal charger detection circuit 6, an oscillation circuit 7, and a counter circuit 8, and detects overcharge, overdischarge, overcurrent, etc. of the secondary battery cell 15 to overcharge, overdischarge the secondary battery cell 15. And protect against overcurrent.
[0016]
For example, when different overcharge, overdischarge, or short circuit is detected by the overcharge detection circuit 2, the overdischarge detection circuit 3, or the short circuit detection circuit 5, the oscillation circuit 7 starts to operate and the counter circuit 8 starts to operate.
[0017]
When the delay time set at each detection is counted, the output of the Cout terminal becomes low level in the case of overcharge through the logic circuits 9a and 9b and the level shift 10, and the charge control FET is turned off and over. In the case of discharge or short circuit, the output of the Dout terminal is at a low level, and the discharge control FET is turned off.
[0018]
The abnormal charger detection circuit 6 is connected to the input of the overcurrent detection circuit 4 and the short-circuit detection circuit 5 when the abnormal charger 14 or the like is connected and a large voltage is applied to the battery pack 11. This is a circuit for preventing the shift of the overcurrent detection voltage value and the short-circuit detection voltage value due to the change with time of Vth of the transistor by turning off the FET switch 6a so that no potential is applied.
[0019]
In the secondary battery protection IC 1 having such a configuration, the delay time when overdischarge is detected is usually about 20 mS (milliseconds), the delay time when overcurrent is detected is about 10 mS, and the delay time when short circuit is detected is about 1 mS. However, the delay time when overcharge is detected is 1 S (seconds) or more.
[0020]
In the secondary battery protection IC 1 of this example, as shown in FIG. 2, a test control circuit 20 is provided in the oscillation circuit 7, and the Cout terminal is connected when the secondary battery protection IC 1 is tested. The test time is shortened by increasing the frequency of the oscillation circuit 7 and shortening the delay time by fixing the V-terminal at a high level (in a state where no overcharge is detected) and a level lower than the Vss terminal.
[0021]
That is, the oscillation circuit 7 shown in FIG. 2 is a ring oscillator using a constant current inverter and a capacitor, and a normal oscillation frequency includes constant current values of constant currents 26 and 28, values of capacitors 29 and 30, inverters 31, It is determined by the threshold of 32, and the delay time when overcharge is detected is 1 S (seconds) or more.
[0022]
However, in this example, in the test control circuit 20, the values of the Cout terminal (overcharge detection output terminal), the Vss terminal (ground terminal), and the V− terminal (charger minus potential input terminal) are input, When the charge detection output terminal (Cout) is set to a high level and the charger minus potential input terminal (V−) is set to a level lower than the ground terminal (Vss), the P-channel transistors 23 and 24 as switch circuits are turned on. The current values of the constant currents 25 and 27 as the current increasing circuit are added, and the frequency of the oscillation circuit 7 is increased.
[0023]
The test control circuit 20 of this example gives a hysteresis characteristic to the value of the charger minus potential input terminal (V−), inverts the low level input from the ground terminal (Vss), and outputs a high level hysteresis inverter 33. And an inverter 34 for inputting the high level output of the hysteresis inverter and inverting the low level output, and inputting the low level output of the inverter 34 and the high level signal of the overcharge detection output terminal (Cout) to output the low level. NAND circuit 35 to be turned on, P channel transistors 23 and 24 that are turned on by the low level output of NAND circuit 35, and the constant current value that determines the frequency of oscillation circuit 7 is increased by the on operation of P channel transistors 23 and 24. And a constant current 25, 27 as a current increasing circuit .
[0024]
The Cout terminal is normally at a high level. When the low level of the normal Vss terminal is input to the input of the hysteresis inverter 33 of the test control circuit 20, the output of the hysteresis inverter 33 is high and the output of the inverter 34 is low. Thus, the input of the NAND circuit 35 becomes the high level of the Cout terminal and the low level output of the inverter 34, and the output becomes the high level.
[0025]
Thus, when the output of the NAND circuit 35 becomes high level, since the gate voltages of the P channel transistors 23 and 24 are high level, the P channel transistors 23 and 24 are turned off. Accordingly, the oscillation frequency of the oscillation circuit 7 in this case is determined by the values of the constant currents 26 and 28 and the capacitors 29 and 30.
[0026]
However, when testing the overcharge detection operation of the secondary battery protection IC, if the Cout terminal remains at the high level and the V− terminal is lowered to a level lower than the Vss terminal, the high level is input to the hysteresis inverter 33. Therefore, the output of the hysteresis inverter 33 is low level, the output of the inverter 34 is high level, the input of the NAND circuit 35 is high level of the Cout terminal and the high level output of the inverter 34, and the output is low level. .
[0027]
Thus, when the output of the NAND circuit 35 becomes low level, since the gate voltages of the P channel transistors 23 and 24 are low level, the P channel transistors 23 and 24 are turned on, and the oscillation frequency of the oscillation circuit 7 is determined. The constant current values are constant current 26 + constant current 25, constant current 28 + constant current 27, and the oscillation frequency increases.
[0028]
As a result, the delay time when overcharge is detected can be shortened. For example, when the ratio of the constant current 26 to the constant current 25 and the ratio of the constant current 28 to the constant current 27 is 1: 9, the delay time can be reduced to 1/10. In this case, the test time of the secondary battery protection IC 1 can be shortened to 1/10.
[0029]
As described above with reference to FIGS. 1 and 2, in this example, when the overcharge detection operation of the secondary battery protection IC 1 is tested, the frequency of the oscillation circuit 7 is increased to detect overcharge. The delay time can be shortened, and the time required for the test can be shortened. In particular, in this example, in order to increase the frequency of the oscillation circuit during the test, the value of the constant current that determines the oscillation frequency is increased.
[0030]
In order to increase the value of the constant current, in this example, the P channel transistors 23 and 24 for additionally connecting the constant currents 25 and 27 and the P channel transistors 23 and 24 are connected to the Cout terminal (overcharge). Hysteresis inverter 33 and inverter 34 for ON control based on the high level set value of the detection output terminal) and the set value of the V− terminal (charger minus potential input terminal) lower than the Vss terminal (ground terminal). In addition, a test control circuit 20 including a NAND element 35 is provided.
[0031]
In particular, the test control circuit 20 in this example includes a high-level set value of Cout terminal (overcharge detection output terminal), lower than Vss terminal (ground terminal) level V- terminal (charger negative potential input terminal) The frequency of the oscillation circuit 7 is increased by the set value, and only a terminal provided in the normal secondary battery protection IC 1 is required, and it is not necessary to provide a special test terminal.
[0032]
Further, in this example, the test control circuit 20 includes a hysteresis inverter 33, an inverter 34, and a NAND element 35, so that the circuit scale can be kept small, and the battery provided with the secondary battery protection IC 1 of this example is provided. The size of the pack 11 and various electronic devices such as a mobile phone, a notebook computer, and a PDA that use the battery pack 11 can be kept small.
[0033]
In addition, this invention is not limited to the example demonstrated using FIG. 1 and FIG. 2, It can change variously in the range which does not deviate from the summary. For example, in this example, the test control circuit 20 is provided in the oscillation circuit 7, but the test control circuit 20 may be provided outside the oscillation circuit 7.
[0034]
In the test control circuit 20 of this example, P channel transistors 23 and 24 are provided as the switching means for increasing the constant currents 25 and 27 and the constant currents 25 and 27 are increased. Other switching elements such as channel transistors may be used.
[0035]
【The invention's effect】
According to the present invention, it is possible to efficiently test a circuit that protects a secondary battery from overcharge, overdischarge, and overcurrent. A battery pack using the protection circuit, a mobile phone, a notebook computer, and a PDA using the battery pack are provided. It is possible to improve the efficiency of the manufacturing process of various electronic devices.
[0036]
Further, in the present invention, a high-level set value of Cout terminal (overcharge detection output terminal), the setting value of Vss terminals (ground terminals) lower levels of the V- terminal (charger negative potential input terminal), the oscillator circuit The terminal of the secondary battery protection IC can be used, and there is no need to provide a special test terminal. .
[0037]
Furthermore, in the present invention, a hysteresis inverter, an inverter, and a NAND circuit are used as a circuit for increasing the frequency of the oscillation circuit, so that the circuit scale can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a secondary battery protection IC and a battery pack using the same according to the present invention.
2 is a block diagram showing a configuration example of an oscillation circuit provided in the secondary battery protection IC in FIG. 1 and a test control circuit for changing the frequency thereof. FIG.
FIG. 3 is a block diagram showing a configuration example of a conventional secondary battery protection IC.
[Explanation of symbols]
1: secondary battery protection IC ("protection device"), 2: overcharge detection circuit, 2a, 2b: comparator, 3: overdischarge detection circuit, 3a, 3b: comparator, 4: overcurrent detection circuit, 5: Short circuit detection circuit, 6: abnormal charger detection circuit, 6a: N-channel FET, 7: oscillation circuit, 8: counter circuit, 9a, 9b: logic circuit, 10: level shift, 11: battery pack, 12: positive terminal , 13: negative terminal, 14: charger, 15: secondary battery cell, 20: test control circuit, 23, 24: P-channel transistor (switch circuit), 25, 27: constant current (current increase circuit), 26, 28: constant current, 29, 30: capacitor, 31, 32: inverter, 33: hysteresis inverter, 34: inverter, 35: NAND circuit, C: capacitor, R: resistance Vdd: base potential terminal, Vss: Ground terminals, Dout: overdischarge detection output terminal, Cout: overcharge detection output terminal, V-: Charger negative potential input terminal.

Claims (4)

Secondary battery is protected from overcharge, overdischarge and overcurrent by detecting overcharge, overdischarge and overcurrent of the secondary battery and turning off the charge control FET or discharge control FET. A battery protection IC,
An oscillation circuit and a counter circuit for delaying detection times of overcharge, overdischarge and overcurrent;
The values of the overcharge detection output terminal (Cout), the ground terminal (Vss), and the charger minus potential input terminal (V−) are input, and the overcharge detection output terminal (Cout) turns on the charge control FET. And a test control circuit for increasing the frequency of the oscillation circuit when the charger minus potential input terminal (V−) is set to a level lower than the ground terminal (Vss). IC for secondary battery protection. The secondary battery protection IC according to claim 1,
The test control circuit is
A hysteresis inverter that gives a hysteresis characteristic to the value of the charger minus potential input terminal (V−) and outputs the input from the ground terminal (Vss) at a low level;
An inverter that inputs a low level output of the hysteresis inverter and inverts it to a high level;
A NAND circuit that inputs a high level output of the inverter and a high level signal of the overcharge detection output terminal (Cout) and outputs a low level;
A switch circuit that is turned on by a low-level output of the NAND circuit;
A secondary battery protection IC comprising: a current increasing circuit that increases a constant current value that determines a frequency of the oscillation circuit by an ON operation of the switch.   A battery pack using the secondary battery protection IC according to claim 1.   An electronic device using the battery pack according to claim 3.

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