JP4539582B2 - Charge protection circuit - Google Patents

Description

  The present invention relates to a charge protection circuit and relates to a charge protection circuit for preventing overcharge of a secondary battery.

  There is a charge protection circuit that is connected between a DC power source such as an AC adapter or a USB port and a secondary battery such as a lithium ion battery to protect the secondary battery from being overcharged.

  FIG. 4 shows a block diagram of an example of a conventional charge protection circuit. In the figure, a charge protection circuit 1 is constituted by a semiconductor integrated circuit, and performs on / off control of a switching transistor 4 connected between a DC power source 2 and a secondary battery 3. The charge protection circuit 1 turns on the switching transistor 4 to charge the secondary battery 3. Further, the time when the voltage of the secondary battery 3 exceeds a predetermined value is measured by a timer circuit. If the predetermined time such as several minutes is exceeded, it is determined that the secondary battery 3 is overcharged, and the switching transistor 4 It has a function to turn off and end charging.

Patent Document 1 describes that a voltage detection circuit that detects that a capacitor terminal is out of a predetermined voltage range is added in a circuit that uses charging and discharging of a capacitor to set a delay time.
JP 11-31968 A

  Conventionally, when the operation check is performed at the time of manufacturing the charge protection circuit, it takes a long time to check the operation of the timer circuit. In order to shorten the operation check of the timer circuit, it is conceivable to increase the speed of the clock signal used in the timer circuit, that is, increase the frequency.

  In order to speed up the clock signal, an element such as a capacitor that determines the time constant of the oscillator that generates the clock signal is externally attached to the external terminal of the semiconductor integrated circuit that constitutes the charge protection circuit. It is conceivable to replace an element such as a capacitor at the time of use. However, in this case, an external terminal must be added to the semiconductor integrated circuit, and there is a problem that it cannot be realized if there is no room for adding the external terminal.

  The present invention has been made in view of the above points, and it is an object of the present invention to provide a charge protection circuit that can shorten the time required for operation confirmation and therefore does not require an external terminal.

The charge protection circuit of the present invention compares a voltage across each of a plurality of secondary batteries that are connected in series with a DC power supply with a first predetermined value to determine whether or not the battery is overcharged. A comparison means;
The voltage of each of the external terminals to which the plurality of secondary batteries are connected is compared with a second predetermined value that is lower than the voltage at the time of charging the secondary battery, and the voltage of the external terminal is less than the second predetermined value. A plurality of second comparison means for determining whether or not a time reduction instruction;
Oscillating means that oscillates when any of the plurality of first comparing means determines overcharge;
Oscillating frequency changing means for increasing the oscillating frequency of the oscillating means when any of the plurality of second comparing means determines that the time is instructed;
Timer means for timing the oscillation signal output from the oscillation means and outputting a charge stop signal after a predetermined time;
By preventing the secondary battery from being overcharged, the time required for operation check can be shortened, and therefore it is not necessary to provide an external terminal.

In the charge protection circuit,
The oscillating means is a ring oscillator configured by cascading inverters and capacitors, supplying a constant current to each capacitor from each inverter, and charging.
The oscillation frequency changing means can increase the constant current when the time reduction instruction is given.

  According to the present invention, the time required for the operation check can be shortened, and therefore it is not necessary to provide an external terminal.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Circuit configuration of the charge protection circuit>
FIG. 1 shows a circuit configuration diagram of an embodiment of a charge protection circuit of the present invention. This charge protection circuit is a device for controlling the charging of secondary batteries BTA, BTB, BTC, and BTD connected in series, and is configured in the semiconductor integrated circuit 10. During charging, the secondary battery BTA is connected between the external terminals 11A and 11B, the secondary battery BTB is connected between the external terminals 11B and 11C, and the secondary battery BTC is connected between the external terminals 11C and 11D. The battery BTD is connected between the external terminal 11D and the ground.

  In this charge protection circuit, the secondary batteries BTB, BTC, and BTD can be removed and only the secondary battery BTA can be charged, and the secondary batteries BTC and BTD can be removed and only the secondary batteries BTA and BTB can be charged. It is also possible to remove the secondary battery BTD and charge only the secondary batteries BTA, BTB, and BTC.

  As shown in FIG. 2, the voltage across the secondary batteries BTA, BTB, BTC, and BTD is, for example, in the range of 2.0V to 4.3V when normally charged, and overcharged at 4.3V or higher. It is. Further, at the time of charging, the voltage between both ends is not 0 V or less or 9 V or more. For this reason, in this invention, -1V or less is used as a time-short mode instruction voltage.

  In the operation check at the time of manufacture, a tester applies 4.3V or more, for example, 4.5V to the external terminals 11A, 11B, and 11C, and applies 0V or less, for example, -1.0V to the external terminal 11D. Further, 4.5 V is applied to the external terminals 11B, 11C, and 11D, and −1.0 V is applied to the external terminal 11A.

  In the semiconductor integrated circuit 10, the external terminal 11A is connected to the non-inverting input terminal of the differential amplifier 12A, the external terminal 11B is connected to the inverting input terminal of the differential amplifier 12A, and the differential amplifier 12A is between the external terminals 11A and 11B. The difference voltage is output. Further, the external terminal 11B is connected to the non-inverting input terminal of the differential amplifier 12B, the external terminal 11C is connected to the inverting input terminal of the differential amplifier 12B, and the differential amplifier 12B calculates the difference voltage between the external terminals 11B and 11C. Output. Further, the external terminal 11C is connected to the non-inverting input terminal of the differential amplifier 12C, the external terminal 11D is connected to the inverting input terminal of the differential amplifier 12C, and the differential amplifier 12C calculates the differential voltage between the external terminals 11C and 11D. Output.

  The output terminal of the differential amplifier 12A is connected to the non-inverting input terminal of the comparator 13A and the inverting input terminal of the comparator 14A. The first voltage V1 (V1 = 4.3V) is applied to the inverting input terminal of the comparator 13A, and the second voltage V2 (V2 = −1.0V) is applied to the non-inverting input terminal of the comparator 14A.

  The comparator 13A generates a high-level overcharge determination signal and supplies it to the OR circuit 15 when the difference voltage between the external terminals 11A and 11B exceeds the first voltage V1. The comparator 14 </ b> A generates a high-level time-short instruction signal when the external terminal 11 </ b> A is less than the second voltage V <b> 2 and supplies it to the OR circuit 16.

  The output terminal of the differential amplifier 12B is connected to the non-inverting input terminal of the comparator 13B and the inverting input terminal of the comparator 14B. The first voltage V1 is applied to the inverting input terminal of the comparator 13B, and the second voltage V2 is applied to the non-inverting input terminal of the comparator 14B.

  The comparator 13B generates a high-level overcharge determination signal and supplies it to the OR circuit 15 when the voltage difference between the external terminals 11B and 11C exceeds the first voltage V1. Further, the comparator 14B generates a high-level time-short instruction signal when the external terminal 11B is less than the second voltage V2, and supplies it to the OR circuit 16.

  The output terminal of the differential amplifier 12C is connected to the non-inverting input terminal of the comparator 13C and the inverting input terminal of the comparator 14C. The first voltage V1 is applied to the inverting input terminal of the comparator 13C, and the second voltage V2 is applied to the non-inverting input terminal of the comparator 14C.

  The comparator 13C generates a high-level overcharge determination signal and supplies it to the OR circuit 15 when the external terminal 11C exceeds the first voltage V1. The comparator 14 </ b> C generates a high-level time-shortening instruction signal when the external terminal 11 </ b> C is less than the second voltage V <b> 2 and supplies it to the OR circuit 16.

  The external terminal 11D of the semiconductor integrated circuit 10 is connected to the non-inverting input terminal of the comparator 13D and the inverting input terminal of the comparator 14D. The first voltage V1 is applied to the inverting input terminal of the comparator 13D, and the second voltage V2 is applied to the non-inverting input terminal of the comparator 14D.

  The comparator 13D generates a high-level overcharge determination signal and supplies it to the OR circuit 15 when the external terminal 11D exceeds the first voltage V1. Further, the comparator 14D generates a high-level time reduction instruction signal when the external terminal 11D is less than the second voltage V2, and supplies it to the OR circuit 16.

  When the OR circuit 15 is supplied with a high-level overcharge determination signal from any of the comparators 13A to 13D, the OR circuit 15 supplies the overcharge determination signal to the oscillator 17 and the timer circuit 18 as an enable signal. When the OR circuit 16 is supplied with a short time instruction signal at a high level from any of the comparators 14A to 14D, the OR circuit 16 supplies the short time instruction signal to the oscillator 17 at this time.

  The oscillator 17 oscillates when an enable signal is supplied. At this time, the obtained oscillation signal has a high frequency when the high-level time-short indication signal is supplied, and has a low frequency when the high-level time-short indication signal is not supplied.

  The timer circuit 18 counts and counts the oscillation signal supplied from the oscillator 17, generates a charge stop signal after a predetermined time, and supplies it to the output circuit 19.

  During charging, the output circuit 19 supplies a high level switching signal from the external terminal 20 to the gate of an n-channel FET (field effect transistor) 21 to turn on the FET 21. As a result, current is supplied from the DC power source 22 to the secondary batteries BTA, BTB, BTC, and BTD, and the secondary batteries BTA, BTB, BTC, and BTD are charged.

  On the other hand, when the charge stop signal is supplied, the output circuit 19 turns off the FET 21 by setting the switching signal supplied from the external terminal 20 to the gate of the n-channel FET (field effect transistor) 21 to the low level, and the secondary batteries BTA, BTB. , BTC, BTD charging is stopped.

<Circuit configuration of the oscillator>
FIG. 3 shows a circuit configuration diagram of an embodiment of the oscillator 17.
In the figure, the drain and gate of an n-channel FET (field effect transistor) M1 are commonly connected to the gates of n-channel FETs M2 and M4. The gate areas of the FETs M1, M2 and M4 are 1: 1: N (N is a real number of 1 or more).

  The drain of the FET M1 is connected to the power supply VDD via the constant current source 30 for supplying the constant current Ia and the switch SW1, and the drain of the FET M2 is connected to the drain and gate of the p-channel FET M3. The drain of the FET M4 is connected to the drain and gate of the FET M3 via the switch SW2, and the sources of the FETs M1, M2, and M4 are grounded. The FET M1 and the FETs M2 and M4 constitute a current mirror circuit, and the drain current of the FET M3 is Ia × (N + 1). The constant current source 30 and the FETs M1, M2, and M4 constitute a constant current generator.

  The switch SW1 is turned on only when a high level overcharge determination signal is supplied from the OR circuit 15 to the terminal 31. The switch SW2 is turned on only when the terminal 32 is supplied with a short time instruction signal at a high level from the OR circuit 16.

  The FET M3 has a source connected to the power supply VDD and a gate commonly connected to the gates of the p-channel FETs M11, M12, M15, M16, M19, and M20. Each of the FET M3 and the FETs M11, M12, M15, M16, M19, and M20 constitutes a current mirror circuit. The gate areas of the FETs M3, M11, M12, M15, M16, M19, and M20 are substantially the same.

  The source of the FET M11 is connected to the power supply VDD, the gate and drain of the FET M11 are connected to the source of the FET M12, and the drain of the FET M12 is connected to the source of the p-channel FET M13. Similarly, the source of the FET M15 is connected to the power supply VDD, the gate and drain of the FET M15 are connected to the source of the FET M16, and the drain of the FET M16 is connected to the source of the p-channel FET M17.

  The source of the FET M19 is connected to the power supply VDD, the gate and drain of the FET M19 are connected to the source of the FET M20, and the drain of the FET M20 is connected to the source of the p-channel FET M21. As a result, the drain currents of the FETs M12, M16, and M20 are Ia × (N + 1).

  The gate and drain of the FET M13 are connected in common to the gate and drain of the n-channel FET M14, the source of the FET M14 is grounded to form an inverter, and the drains of the FETs M13 and M14 are one end of the capacitor C1 and the gates of the FETs M17 and M18. It is connected to the.

  The gate and drain of the FET M17 are connected in common to the gate and drain of the n-channel FET M18, the source of the FET M18 is grounded to form an inverter, and the drains of the FETs M17 and M18 are one end of the capacitor C2 and the gates of the FETs M21 and M22. It is connected to the.

  The gate and drain of the FET M21 are connected in common to the gate and drain of the n-channel FET M22, the source of the FET M22 is grounded to form an inverter, and the drains of the FETs M21 and M22 are one end of the capacitor C3 and the gates of the FETs M23 and M24. It is connected to the. The capacitances of the capacitors C1, C2, C3 are substantially the same.

  The gate and drain of the FET M23 are connected in common to the gate and drain of the n-channel FET M24, the source of the FET M23 is connected to the power supply VDD, the source of the FET M24 is grounded to constitute an inverter, and the drains of the FETs M21 and M22 are In addition to being connected to the output terminal 12, it is feedback connected to the gates of the FETs M13 and M14. That is, ring oscillators (FETs M11 to M24, capacitors C1 to C3) are configured by cascading inverters and capacitors in multiple stages.

  Here, at the time of confirming the operation, the switches SW1 and SW2 are on, and the capacitors C1, C2, and C3 are charged by the drain currents Ia × (N + 1) of the FETs M12, M16, and M20, respectively. The oscillation frequency to be performed is approximately (N + 1) times that when the drain currents of the FETs M12, M16, and M20 are Ia.

  During normal use, the switch SW2 is turned off, the drain currents of the FETs M12, M16, and M20 are Ia, and the oscillation frequency output from the ring oscillator is 1 / (N + 1) when the operation is confirmed. That is, the oscillation frequency at the time of confirming the operation can be (N + 1) times that during normal use, and the inspection time of the charge protection circuit can be greatly shortened.

<Operation check operation>
For example, when 4.5V is applied to the external terminals 11A, 11B, and 11C and −1.2V is applied to the external terminal 11D in the operation confirmation during manufacturing, the comparators 13A to 13C generate high-level overcharge determination signals, This overcharge determination signal is supplied to the oscillator 17 and the timer circuit 18 as an enable signal. At the same time, the comparator 14D generates a high-level time reduction instruction signal and supplies it to the oscillator 17. As a result, the oscillation frequency at the time of confirming the operation can be made significantly higher than that during normal use, and the inspection time of the charge protection circuit can be greatly shortened. In addition, for example, 4.5 V may be applied to the external terminals 11B, 11C, and 11D, and -1.2 V may be applied to the external terminal 11A to confirm the operation.

  The differential amplifiers 12A to 12C and the comparators 13A to 13D correspond to the first comparison means, the comparators 14A to 14D correspond to the second comparison means, the oscillator 17 corresponds to the oscillation means, and the switch SW1 FET M4 corresponds to the oscillation frequency changing means, and the timer circuit 18 corresponds to the timer means.

It is a circuit block diagram of one Embodiment of the charge protection circuit of this invention. It is a figure for demonstrating the both-ends voltage of a secondary battery, and a time-short mode instruction | indication voltage. It is a circuit block diagram of one Embodiment of an oscillator. It is a block diagram of an example of the conventional charge protection circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor integrated circuit 11A-11D, 20 External terminal 12A-12C Differential amplifier 13A-13D, 14A-14D Comparator 15,16 OR circuit 17 Oscillator 18 Timer circuit 21, M1-M24 FET
22 DC power supply 30 Constant current source BTA, BTB, BTC, BTD Secondary battery

Claims (2)

A plurality of first comparison means for comparing the voltage across each of a plurality of secondary batteries to be charged in series connected to a DC power supply with a first predetermined value to determine whether or not overcharge;
The voltage of each of the external terminals to which the plurality of secondary batteries are connected is compared with a second predetermined value that is lower than the voltage at the time of charging the secondary battery, and the voltage of the external terminal is less than the second predetermined value. A plurality of second comparison means for determining whether or not a time reduction instruction;
Oscillating means that oscillates when any of the plurality of first comparing means determines overcharge;
Oscillating frequency changing means for increasing the oscillating frequency of the oscillating means when any of the plurality of second comparing means determines that the time is instructed;
Timer means for timing the oscillation signal output from the oscillation means and outputting a charge stop signal after a predetermined time;
A charge protection circuit for preventing overcharge of the secondary battery. The charge protection circuit according to claim 1,
The oscillating means is a ring oscillator configured by cascading inverters and capacitors, supplying a constant current to each capacitor from each inverter, and charging.
The oscillation frequency changing means increases the constant current when the time reduction instruction is given.

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