JP2013055762A - Secondary battery protection semiconductor device and secondary battery pack - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a secondary battery protection semiconductor device which can reversibly switch operation modes including at least two types of test modes.SOLUTION: The secondary battery protection semiconductor device comprises: a cell state detection circuit 11 detecting a voltage value or a current value of a secondary battery 21; an input determination circuit 10 generating any one among a plurality of operation mode signals Modes 1-4 by comparing a voltage applied to one control input terminal 40 with threshold voltages TH1, TH2, TH3; a control signal generation circuit 12 connected to the cell state detection circuit 11 for receiving a detection signal from the cell state detection circuit 11 and also connected to the input determination circuit 10 for receiving any one of the plurality of operation mode signals Modes 1-4 to generate a control signal; and a protection control part 14 controlled by reception of the control signal from the control signal generation circuit 12.

Description

  The present invention relates to a secondary battery protection semiconductor device and a secondary battery pack provided with the protection semiconductor device.

  Conventionally, secondary battery packs that are easy to handle have been widely used in portable electronic devices and the like.

  In such a secondary battery pack, one to a plurality of secondary batteries are stored in one package.

  Since this secondary battery uses a high-capacity battery such as a lithium ion battery, the amount of energy held inside is extremely large, so when overcharge, overdischarge or overcurrent occurs. There is a risk of overheating and sometimes igniting.

  Therefore, a secondary battery protection semiconductor device that protects the secondary battery from overcharge, overdischarge, or overcurrent is also incorporated in the secondary battery pack.

  For example, Patent Document 1 discloses a technique that can be implemented at a low cost by using only one terminal dedicated for testing a secondary battery protection semiconductor device.

  Here, since such a secondary battery has a high internal impedance, the voltage at the time of charging / discharging appears to change apparently, so that it is necessary to provide a detection delay time in order to use it efficiently.

  Also, in order to prevent erroneous cancellation due to noise, it is necessary to provide a cancellation delay time.

  Therefore, in a conventional semiconductor device for protecting a secondary battery as disclosed in Patent Document 1, a test mode in which the detection delay time of a test mode signal is shortened as much as possible in order to improve productivity in mass production at a factory, In order to perform more accurate evaluation at the next measurement, customer, etc., there are two types of test modes: a test mode in which the detection delay time of the test mode signal is slightly increased.

  However, in a conventional secondary battery protection semiconductor device such as Patent Document 1, when switching modes, a fuse provided therein is cut, so switching between both test modes is irreversible.

  Therefore, for example, even if the test is performed in the test mode before cutting the fuse in order to perform simple maintenance of the semiconductor device for protecting the secondary battery, it must be replaced with a new fuse.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device for protecting a secondary battery in which switching of operation modes including at least two types of test modes is reversible, and a secondary battery pack including the semiconductor device for protection. It is said.

  In order to achieve the above object, the secondary battery protection semiconductor device of the present invention detects overcharge, overdischarge, or overcurrent of the secondary battery, and detects the secondary battery from the overcharge, overdischarge, or overcurrent. A semiconductor device for protecting a secondary battery for protecting a secondary battery, connected to a positive power supply terminal and a negative power supply terminal of the secondary battery and detecting a voltage value or a current value of the secondary battery A plurality of operation modes including at least two types of test mode signals and normal protection mode signals by comparing a circuit and one control input terminal and comparing a voltage applied from the control input terminal with a threshold voltage An input determination circuit that generates a signal and the cell state detection circuit are connected to receive the detection signal, and is also connected to the input determination circuit and receives the plurality of operation mode signals to generate a control signal. Characterized in that it comprises a signal generating circuit, and a protection control unit which is controlled by receiving the control signal of the control signal generating circuit.

  A secondary battery pack according to the present invention includes a semiconductor device for protecting a secondary battery according to the present invention.

  Such a semiconductor device for protecting a secondary battery according to the present invention detects overcharge, overdischarge or overcurrent of the secondary battery and protects the secondary battery from overcharge, overdischarge or overcurrent. A semiconductor device for protecting a secondary battery.

  And connected to the positive power supply terminal and the negative power supply terminal of the secondary battery, connected to one control input terminal, a cell state detection circuit for detecting the voltage value or current value of the secondary battery, and the control input terminal An input determination circuit that compares a voltage applied from the threshold voltage and a threshold voltage to generate a plurality of operation mode signals including at least two types of test mode signals and a normal protection mode signal; and a cell state detection circuit; A control signal generation circuit that receives the detection signal and is connected to the input determination circuit and receives a plurality of operation mode signals to generate a control signal; and a protection control unit that is controlled by receiving the control signal of the control signal generation circuit; It is set as the structure provided with.

  With such a configuration, switching of operation modes including at least two types of test modes is reversible.

  Therefore, simple maintenance of the semiconductor device for protecting the secondary battery can be easily performed.

  Such a secondary battery pack of the present invention is configured to include the secondary battery protection semiconductor device of the present invention.

  With such a configuration, a secondary battery pack that exhibits the effects of the above-described secondary battery protection semiconductor device of the present invention can be obtained.

1 is a block diagram showing a schematic configuration of a secondary battery pack of Example 1. FIG. 3 is a circuit diagram illustrating details of an input determination circuit in the secondary battery protection semiconductor device of Example 1. FIG. FIG. 6 is an explanatory diagram illustrating a relationship between a voltage applied to a control input terminal and an operation mode signal in the input determination circuit according to the first embodiment. 3 is a table exemplifying operation mode signal allocation patterns according to the first embodiment. It is a block diagram which shows schematic structure for performing cascade transmission mode. 6 is a circuit diagram showing details of an input determination circuit in the secondary battery protection semiconductor device of Example 2. FIG. FIG. 10 is an explanatory diagram illustrating a relationship between a voltage applied to a control input terminal and an operation mode signal in the input determination circuit according to the second embodiment. FIG. 6 is a circuit diagram illustrating details of an input determination circuit in the secondary battery protection semiconductor device according to the third embodiment. FIG. 6 is a circuit diagram showing details of an input determination circuit in the secondary battery protection semiconductor device of Example 4; It is explanatory drawing which shows the relationship between the voltage applied to the control input terminal in an input determination circuit at the time of setting the positive power supply terminal of a secondary battery as an upper limit, and an operation mode signal. It is explanatory drawing which shows the relationship between the voltage applied to the input terminal for control in an input determination circuit at the time of providing seven threshold voltages, and an operation mode signal.

  EMBODIMENT OF THE INVENTION Hereinafter, the form for implementing this invention is demonstrated based on Examples 1-4 shown in drawing.

  First, the configuration of the first embodiment will be described.

  FIG. 1 shows a schematic configuration of the secondary battery pack 20 of the first embodiment.

  First, the secondary battery pack 20 is mainly composed of a secondary battery protection semiconductor device 1 and a secondary battery 21.

  Here, the load device 30 is connected to the plus terminal 22 and the minus terminal 23 of the secondary battery pack 20.

  The load device 30 is a charger when charging the secondary battery pack 20, and is a portable electronic device or the like when discharging from the secondary battery pack 20.

  Next, the secondary battery protection semiconductor device 1 will be described.

  The secondary battery protection semiconductor device 1 includes a cell state detection circuit 11 connected to a positive power supply terminal (VDD) 21a and a negative power supply terminal (VSS) 21b of a secondary battery 21, and one control input terminal. 40, an input determination circuit 10 connected to 40, a control signal generation circuit 12 connected to the cell state detection circuit 11 and the input determination circuit 10, a control signal generation circuit 12, a charge control output terminal 41, and a discharge control output terminal 42. And a protection control unit 14 connected through an output circuit 13 having the same.

  Here, the cell state detection circuit 11 detects and manages the voltage value and current value of the secondary battery 21, and is used for operation determination that constitutes the control signal generation circuit 12 when an abnormal value is detected. The abnormal value detection signal is sent to the logic circuit 121.

  The input determination circuit 10 compares the voltage applied from the control input terminal (INPUT) 40 with the threshold voltage and generates an operation mode signal including a test mode signal and a normal protection mode signal. Details thereof will be described later.

  The control signal generation circuit 12 includes an operation determination logic circuit 121, a counter circuit 122, and an oscillator circuit 123.

  Here, the counter circuit 122 and the oscillator circuit 123 function as a delay time generation circuit, and the operation determination logic circuit 121 receives the abnormal value detection signal received from the cell state detection circuit 11 and receives an input determination circuit. In response to the operation mode signal from 10, the control signal is generated.

  The output circuit 13 outputs the control signal from the charge control output terminal (COUT) 41 or the discharge control output terminal (DOUT) 42 when receiving the control signal generated by the operation determination logic circuit 121. .

  Further, the protection control unit 14 includes a switching circuit and the like, and is controlled by receiving a control signal from the output circuit 13. For example, when the load device 30 is a charger and the secondary battery 21 is overcharged, the switch is turned off to prohibit further charging. Alternatively, when the load device 30 is a portable electronic device or the like and the secondary battery 21 is overdischarged, the switch is turned off to prevent further discharge.

  Next, details of the input determination circuit 10 will be described.

  FIG. 2 shows a more detailed configuration of the input determination circuit 10.

  The input determination circuit 10 includes a threshold voltage generation circuit 101 and an operation mode signal generation logic circuit 102.

  The threshold voltage generating circuit 101 is composed of a plurality of MOS transistors MN1, MN2, MP1, MP2, MP3, and MP4.

  More specifically, the threshold voltage TH1 is set by the N-type depletion transistor MN1 and the N-type enhancement transistor MN2, the threshold voltage TH2 is set by the P-type enhancement transistor MP1 and the P-type depletion transistor MP2, and the threshold voltage is set by the P-type depletion transistors MP3 and MP4. TH3 is logically created in the operation mode signal generation logic circuit 102.

  Note that the N-type depletion transistor MN1 and the P-type depletion transistors MP2 and MP4 of the threshold voltage generation circuit 101 can be similarly implemented by replacing them with constant current sources or resistors.

  FIG. 3 shows the relationship between the voltage applied to the control input terminal (INPUT) 40 and the operation mode signal. The operation mode signal generation logic circuit 102 outputs the output of the threshold voltage generation circuit 101. It is determined in which range the input voltage is from the signals MD1, MD2, and MD3, and any one of the operation mode signals Mode1 to Mode4 is generated and output.

  As shown in FIG. 3, the voltage applied to the control input terminal (INPUT) 40 is the voltage of the positive power supply terminal (VDD) 21a and the voltage of the negative power supply terminal (VSS) 21b of the secondary battery 21. Therefore, an appropriate mode is assigned to the operation mode signals Mode1 to Mode4 so that extra elements are not added as much as possible.

  Here, FIG. 4 shows three patterns of assignment examples of the operation mode signals Mode1 to Mode4.

  First, in pattern 1, the operation mode signal Mode1 is set to the charge or discharge prohibition mode, the operation mode signal Mode2 is set to the test mode 1 (counter-through method), and the operation mode signal Mode3 is set to the normal protection mode (auto release type). Test mode 2 (oscillator speed-up method) is assigned to signal Mode4.

  Here, the test mode 1 (counter-through method) is, as can be seen from FIG. 1, since the operation mode signal Mode2 that is a test mode signal is input from the counter circuit 122 without passing through the oscillator circuit 123, so that the secondary measurement is performed. This is a test mode in which the detection delay time of the test mode signal is slightly long in order to perform more accurate evaluation at customers and customers.

  In addition, as shown in FIG. 1, test mode 2 (oscillator speeding-up method) is mass-produced at the factory because the operation mode signal Mode4, which is a test mode signal, is input via the oscillator circuit 123 and the counter circuit 122. This is a test mode in which the detection delay time is as short as possible in order to improve productivity.

  The charge or discharge prohibition mode refers to a mode for forcibly prohibiting charge or discharge or both.

  Furthermore, the normal protection mode (auto-release type) will be described by taking as an example a case where the load device 30 is a charger and detects high voltage. When the voltage of the secondary battery 21 exceeds the high voltage detection voltage, the high voltage is detected. This is a mode in which charging is prohibited when charging is prohibited and the voltage is lower than the high voltage recovery voltage, and charging is possible after returning from the high voltage detection state.

  Next, in pattern 2, the normal protection mode (latch type) is set for the operation mode signal Mode1, the test mode 1 (counter-through method) is set for the operation mode signal Mode2, and the normal protection mode (auto release type) is set for the operation mode signal Mode3. The test mode 2 (oscillator speed-up method) is assigned to the operation mode signal Mode4.

  Here, the normal protection mode (latch type) will be described by taking as an example the case where the load device 30 is a charger and detects high voltage. When the voltage of the secondary battery 21 exceeds the high voltage detection voltage, the high voltage is detected. This is a mode in which charging is prohibited in the detection state, but it does not return from the high voltage detection state only when the voltage falls below the high voltage recovery voltage, and charging is not possible unless a recovery process such as connecting a load is performed.

  Next, in pattern 3, test mode 2 (oscillator speed-up method) is set as operation mode signal Mode1, test mode 1 (counter-through method) is set as operation mode signal Mode2, and normal protection mode (auto release type) is set as operation mode signal Mode3. ) Is assigned to the operation mode signal Mode4, respectively.

  Here, the cascade transmission mode refers to a case where a plurality of secondary batteries 21 are assembled in series as shown in FIG. The charge control output terminal (Cout) 41 and the control input terminal (INPUT) 40 of the protective semiconductor devices 1 and 1 are connected so that a plurality of secondary batteries 21 can be protected or tested at a time. It means the mode to do.

  That is, the input determination circuit 10 generates the operation mode signal Mode4 in the test mode 1 (counter-through method), the test mode 2 (oscillator speed-up method), the normal protection mode (auto release type), or the normal protection mode (latch type). Cascade transmission is possible.

  However, in this case, the output signal of the output circuit 13 shown in FIG. 1 is inverted and output so that the output of the secondary battery protection semiconductor device 1 becomes the same.

  In addition, you may implement this cascade transmission mode using the discharge control output terminal (Dout) 42 instead of the charge control output terminal (Cout).

  Next, the effect of Example 1 is demonstrated.

  The secondary battery protection semiconductor device 1 according to the first embodiment detects overcharge, overdischarge, or overcurrent of the secondary battery, and removes the secondary battery from the overcharge, overdischarge, or overcurrent. A semiconductor device for protecting a secondary battery to be protected.

  The cell state detection circuit 11 is connected to the positive power supply terminal (VDD) 21a and the negative power supply terminal (VSS) 21b of the secondary battery 21, and detects the voltage value or current value of the secondary battery 21, and one control. Is connected to the input terminal (INPUT) 40, and the voltage applied from the control input terminal (INPUT) 40 is compared with the threshold voltages TH1, TH2, TH3, and two types of test mode signals and normal protection mode signals are obtained. An input determination circuit 10 that generates any one of a plurality of operation mode signals Mode 1 to 4 and a cell state detection circuit 11 are connected to receive the detection signal and are also connected to the input determination circuit 10, and a plurality of operation mode signals Any one of Modes 1 to 4 is received and controlled by receiving a control signal generation circuit 12 that generates a control signal and a control signal from the control signal generation circuit 12. It is a protection controller 14 and configuration with that.

  However, in the test modes 1 and 2, the detection signal from the cell state detection circuit 11 may be zero.

  Because of such a configuration, switching between operation modes including the two types of test modes 1 and 2 is reversible.

  Thus, simple maintenance of the secondary battery protection semiconductor device 1 can be easily performed.

  Here, the input determination circuit 10 has four operation mode signals Mode1 to Mode4.

  For this reason, it is possible to additionally provide an operation mode signal necessary for the portable electronic device to be applied.

  The input determination circuit 10 includes a threshold voltage generation circuit 101 that generates threshold voltages TH1, TH2, and TH3 between the voltages of the plurality of operation mode signals Mode1 to Mode4, and a plurality of operation modes from the threshold voltages TH1, TH2, and TH3. And an operation mode signal generation logic circuit 102 for generating signals Mode1 to Mode4.

  For this reason, the input determination circuit 10 can be implemented with a simple configuration.

  Further, the threshold voltage generating circuit 101 is composed of a plurality of MOS transistors MN1, MN2, MP1, MP2, MP3, and MP4.

  Therefore, the threshold voltage generating circuit 101 can be implemented with a simple configuration.

  In addition, a charge control output terminal (Cout) 41 and a discharge control output terminal (Dout) 42 are provided, and adjacent charge control output terminals (Cout) 41 in the plurality of secondary battery protection semiconductor devices 1,. When the discharge control output terminal (Dout) 42 and the control input terminal (INPUT) 40 are connected, test mode 1 (counter-through method), test mode 2 (oscillator speed-up method), normal protection mode (auto release) Type) or normal protection mode (latch type) operation mode signal Mode4 is generated by the input determination circuit 10 to enable cascade transmission.

  For this reason, in particular, in this cascade transmission, when the test mode 2 (oscillator speed-up method) is set to be able to be performed, the quality control of the plurality of secondary battery protection semiconductor devices 1,... Since it can be done in time, productivity can be further improved when mass-producing in a factory.

  Such a secondary battery pack 20 of Example 1 is configured to include the secondary battery protection semiconductor device 1 of Example 1 described above.

  With such a configuration, it is possible to provide a secondary battery pack that achieves the operational effects of the secondary battery protection semiconductor device 1 of Example 1 described above.

  Next, Example 2 will be described.

  In addition, the description which attaches | subjects the same code | symbol about the description of the same thru | or equivalent part as the content demonstrated in Example 1, and demonstrates.

  FIG. 6 illustrates a more detailed configuration of the input determination circuit 10 in the secondary battery protection semiconductor device 1 according to the second embodiment.

  The input determination circuit 10 also includes a threshold voltage generation circuit 101 and an operation mode signal generation logic circuit 102.

  However, the threshold voltage generation circuit 101 is formed by using more MOS transistors MN1, MN2, MN3, MN4, MN5, MP1, MP2, MP3, and MP4.

  More specifically, the threshold voltage TH1 is set by the N-type depletion transistor MN1 and the N-type enhancement transistor MN2, the threshold voltage TH2 is set by the N-type depletion transistor MN3, the N-type enhancement transistor MN4, and the N-type enhancement transistor MN5, and the P-type enhancement transistor. The threshold voltage TH3 is logically generated in the operation mode signal generation logic circuit 102 by the MP1 and the P-type depletion transistor MP2, and the threshold voltage TH4 is generated by the P-type depletion transistors MP3 and MP4.

  FIG. 7 shows the relationship between the voltage applied to the control input terminal (INPUT) 40 and the operation mode signal. The operation mode signal generation logic circuit 102 outputs the output of the threshold voltage generation circuit 101. The range of the input voltage is determined from the signals MD1, MD2, MD3, and MD4, and any one of the operation mode signals Mode1 to Mode5 is generated and output.

  That is, as the threshold voltages TH1, TH2, TH3, and TH4 are increased by one, one more operation mode signal Modes 1 to 5 can be generated.

  Other configurations and functions and effects are substantially the same as those in the first embodiment, and thus description thereof is omitted.

  Next, Example 3 will be described.

  In addition, the description which attaches | subjects the same code | symbol about the description of the same thru | or equivalent part as the content demonstrated in Example 1, and demonstrates.

  FIG. 8 shows a more detailed configuration of the input determination circuit 10 in the secondary battery protection semiconductor device 1 of the third embodiment.

  The input determination circuit 10 also includes a threshold voltage generation circuit 101 and an operation mode signal generation logic circuit 102.

  However, the threshold voltage generating circuit 101 is formed by using resistors R1, R2, R3, R4 in addition to a plurality of MOS transistors MN1, MN2, MN3, MN4, MN5, MN6.

  More specifically, the threshold voltage TH1 is formed by the N-type depletion transistor MN1 and the N-type enhancement transistor MN2, the threshold voltage TH2 is formed by the N-type depletion transistor MN3 and the N-type enhancement transistor MN4, and the N-type depletion transistor M5 and the N-type enhancement transistor. The threshold voltage TH3 is logically generated in the operation mode signal generation logic circuit 102 by MN6.

  The threshold voltages TH1, TH2, TH3 are determined by the resistance ratio of the resistors R1, R2, R3, R4.

  That is, by using the resistance ratio of the resistors R1, R2, R3, and R4, the threshold voltages TH1, TH2, and TH3 are easily generated without requiring complicated processing in the operation mode signal generation logic circuit 102. be able to.

  Other configurations and functions and effects are substantially the same as those in the first embodiment, and thus description thereof is omitted.

  Next, Example 4 will be described.

  In addition, the description which attaches | subjects the same code | symbol about the description of the same thru | or equivalent part as the content demonstrated in Example 1, and demonstrates.

  FIG. 9 shows a more detailed configuration of the input determination circuit 10 in the secondary battery protection semiconductor device 1 of the fourth embodiment.

  The input determination circuit 10 also includes a threshold voltage generation circuit 101 and an operation mode signal generation logic circuit 102.

  However, the threshold voltage generating circuit 101 is composed of a plurality of comparators Comp1, Comp2, and Comp3.

  More specifically, in addition to the comparators Comp1, Comp2, and Comp3, a reference power supply Vref and resistors R1, R2, R3, and R4 are used, and threshold voltages TH1, TH2, TH2, TH2, and R4 are used by using these resistance ratios. TH3 is logically created in the operation mode signal generation logic circuit 102.

  Therefore, since the threshold voltage generation circuit 101 includes a plurality of comparators Comp1, Comp2, and Comp3, it can be implemented with a simple configuration.

  Further, by using the resistance ratio of the resistors R1, R2, R3, and R4, the threshold voltages TH1, TH2, and TH3 are easily generated without requiring complicated processing in the operation mode signal generation logic circuit 102. be able to.

  Other configurations and functions and effects are substantially the same as those in the first embodiment, and thus description thereof is omitted.

  As mentioned above, although the form for implementing this invention was explained in full detail based on Examples 1-4 with reference to drawings, the specific structure is not restricted to these Examples 1-4, but the present invention. Design changes that do not depart from the gist are included in the present invention.

  For example, in Examples 1 to 4 described above, only one secondary battery 21 is used per secondary battery pack 20 so that the present invention can be easily understood. However, the present invention is not limited to this. You may implement using the battery 21 with two or more.

  In Examples 1 to 4 described above, the lower limit value of the voltage applied to the control input terminal (INPUT) 40 is implemented as the negative power supply terminal (VSS) 21b of the secondary battery 21, but the present invention is not limited thereto. For example, when the control input terminal (INPUT) 40 is provided on the positive power supply terminal (VDD) 21a side, the number of threshold voltages TH1, TH2, TH3 is the same as shown in FIG. The positive power supply terminal (VDD) 21a of the battery 21 may be used as the upper limit value.

  In the first, second, and fourth embodiments, the input determination circuit 10 is provided with three threshold voltages TH1, TH2, and TH3. In the third embodiment, the input determination circuit 10 includes four threshold voltages TH1. , TH2, TH3, and TH4 are provided, but the present invention is not limited to this.

  For example, two threshold voltages may be used to implement a total of three operation modes: two test modes and one normal protection mode.

  Alternatively, as shown in FIG. 11, seven threshold voltages TH1, TH2, TH3, TH4, TH5, TH6, and TH7 are set, for example, so that a total of eight operation modes of three test modes and five operation modes are obtained. May be implemented.

  In other words, the number of operation modes can be set and implemented so as to be more suitable for the function of the mobile electronic device to be applied.

DESCRIPTION OF SYMBOLS 1 Protection semiconductor device 10 Input determination circuit 101 Threshold voltage generation circuit 102 Operation mode signal generation logic circuit 11 Cell state detection circuit 12 Control signal generation circuit 121 Operation determination logic circuit 122 Counter circuit 123 Oscillator circuit 13 Output circuit 14 Protection Control unit 20 Secondary battery pack 21 Secondary battery 21a Positive power supply terminal (VDD)
21b Negative power supply terminal (VSS)
22 Positive terminal 23 Negative terminal 30 Load device 40 Control input terminal (INPUT)
41 Charge control output terminal (Cout)
42 Discharge control output terminal (Dout)
TH1, TH2, TH3, TH4 Threshold voltage Modes 1-5 Operation mode signals MN1-MN6 MOS transistors MP1-MP4 MOS transistors Comp1, Comp2, Comp3 Comparator R1, R2, R3, R4 Resistor Vref Reference power supply

Japanese Patent No. 3926718

Claims (9)

A secondary battery protection semiconductor device that detects overcharge, overdischarge or overcurrent of a secondary battery and protects the secondary battery from these overcharge, overdischarge or overcurrent,
A cell state detection circuit that is connected to a positive power supply terminal and a negative power supply terminal of the secondary battery and detects a voltage value or a current value of the secondary battery;
A plurality of operation mode signals including at least two kinds of test mode signals and normal protection mode signals are generated by comparing the voltage applied from the control input terminal and the threshold voltage with one control input terminal. An input determination circuit to
A control signal generation circuit that is connected to the cell state detection circuit, receives the detection signal, is also connected to the input determination circuit, receives the plurality of operation mode signals, and generates a control signal;
And a protection control unit that is controlled in response to the control signal of the control signal generation circuit.   2. The semiconductor device for protecting a secondary battery according to claim 1, wherein the input determination circuit includes four or more of the plurality of operation mode signals.   The input determination circuit includes a threshold voltage generation circuit that generates the threshold voltage between voltages of the plurality of operation mode signals, and an operation mode signal generation logic circuit that generates the plurality of operation mode signals from the threshold voltage. The semiconductor device for protecting a secondary battery according to claim 1 or 2, characterized by comprising:   4. The semiconductor device for protecting a secondary battery according to claim 3, wherein the threshold voltage generation circuit includes a plurality of MOS transistors.   5. The threshold voltage generation circuit also uses a plurality of resistors, and the threshold voltage is logically generated in the operation mode signal generation logic circuit using a resistance ratio thereof. A semiconductor device for protecting a secondary battery as described in 1.   The semiconductor device for protecting a secondary battery according to claim 3, wherein the threshold voltage generation circuit includes a plurality of comparators.   7. The threshold voltage generation circuit also uses a plurality of resistors, and the threshold voltage is logically generated in the operation mode signal generation logic circuit using a resistance ratio thereof. A semiconductor device for protecting a secondary battery as described in 1.   When the charge control output terminal and the discharge control output terminal are connected, and the adjacent charge control output terminal or the discharge control output terminal and the control input terminal in the semiconductor device for protecting a plurality of secondary batteries are connected, respectively. The secondary battery protection semiconductor according to any one of claims 1 to 7, wherein cascade transmission in which the test mode signal or the normal protection mode signal is generated by the input determination circuit is enabled. apparatus.   A secondary battery pack comprising the secondary battery protection semiconductor device according to claim 1.