JP3776202B2 - アドレス衝突検出回路 - Google Patents

アドレス衝突検出回路

Info

Publication number
JP3776202B2
JP3776202B2 JP11673297A JP11673297A JP3776202B2 JP 3776202 B2 JP3776202 B2 JP 3776202B2 JP 11673297 A JP11673297 A JP 11673297A JP 11673297 A JP11673297 A JP 11673297A JP 3776202 B2 JP3776202 B2 JP 3776202B2
Authority
JP
Japan
Prior art keywords
address
latest
access
memory
received
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP11673297A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1083346A5 (enExample
JPH1083346A (ja
Inventor
ジョエル・バック・ジェングラー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPH1083346A publication Critical patent/JPH1083346A/ja
Publication of JPH1083346A5 publication Critical patent/JPH1083346A5/ja
Application granted granted Critical
Publication of JP3776202B2 publication Critical patent/JP3776202B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP11673297A 1996-05-29 1997-05-07 アドレス衝突検出回路 Expired - Fee Related JP3776202B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US655,054 1996-05-29
US08/655,054 US5777628A (en) 1996-05-29 1996-05-29 Method and apparatus for detecting cache collisions in a two dimensional memory

Publications (3)

Publication Number Publication Date
JPH1083346A JPH1083346A (ja) 1998-03-31
JPH1083346A5 JPH1083346A5 (enExample) 2005-03-17
JP3776202B2 true JP3776202B2 (ja) 2006-05-17

Family

ID=24627312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11673297A Expired - Fee Related JP3776202B2 (ja) 1996-05-29 1997-05-07 アドレス衝突検出回路

Country Status (2)

Country Link
US (1) US5777628A (enExample)
JP (1) JP3776202B2 (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6577776B1 (en) * 1999-02-24 2003-06-10 Media 100, Inc. Transforming video images
JP2006505845A (ja) * 2002-11-05 2006-02-16 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 周期的アドレスパターンに応答してアドレスをリダイレクトするデータ処理装置
GB2415060B (en) * 2004-04-16 2007-02-14 Imagination Tech Ltd Dynamic load balancing
US8687010B1 (en) 2004-05-14 2014-04-01 Nvidia Corporation Arbitrary size texture palettes for use in graphics systems
US20060007234A1 (en) * 2004-05-14 2006-01-12 Hutchins Edward A Coincident graphics pixel scoreboard tracking system and method
US8736620B2 (en) * 2004-05-14 2014-05-27 Nvidia Corporation Kill bit graphics processing system and method
US8736628B1 (en) 2004-05-14 2014-05-27 Nvidia Corporation Single thread graphics processing system and method
US7079156B1 (en) * 2004-05-14 2006-07-18 Nvidia Corporation Method and system for implementing multiple high precision and low precision interpolators for a graphics pipeline
US8743142B1 (en) 2004-05-14 2014-06-03 Nvidia Corporation Unified data fetch graphics processing system and method
US8860722B2 (en) * 2004-05-14 2014-10-14 Nvidia Corporation Early Z scoreboard tracking system and method
US8416242B1 (en) 2004-05-14 2013-04-09 Nvidia Corporation Method and system for interpolating level-of-detail in graphics processors
US8432394B1 (en) 2004-05-14 2013-04-30 Nvidia Corporation Method and system for implementing clamped z value interpolation in a raster stage of a graphics pipeline
US8711155B2 (en) * 2004-05-14 2014-04-29 Nvidia Corporation Early kill removal graphics processing system and method
US8411105B1 (en) 2004-05-14 2013-04-02 Nvidia Corporation Method and system for computing pixel parameters
US8234577B1 (en) * 2005-05-23 2012-07-31 Glance Networks, Inc. Method and apparatus for the transmission of changed host display information
US8537168B1 (en) 2006-11-02 2013-09-17 Nvidia Corporation Method and system for deferred coverage mask generation in a raster stage
US8441497B1 (en) 2007-08-07 2013-05-14 Nvidia Corporation Interpolation of vertex attributes in a graphics processor
US9183607B1 (en) 2007-08-15 2015-11-10 Nvidia Corporation Scoreboard cache coherence in a graphics pipeline
US9256514B2 (en) 2009-02-19 2016-02-09 Nvidia Corporation Debugging and perfomance analysis of applications
US9411595B2 (en) 2012-05-31 2016-08-09 Nvidia Corporation Multi-threaded transactional memory coherence
US9824009B2 (en) 2012-12-21 2017-11-21 Nvidia Corporation Information coherency maintenance systems and methods
US10102142B2 (en) 2012-12-26 2018-10-16 Nvidia Corporation Virtual address based memory reordering
US9367437B2 (en) 2013-03-15 2016-06-14 Freescale Semiconductor, Inc. Method and apparatus for reducing the number of speculative accesses to a memory array
US9323534B2 (en) 2013-03-15 2016-04-26 Freescale Semiconductor, Inc. Method and apparatus for detecting a collision between multiple threads of execution for accessing a memory array
US9477575B2 (en) 2013-06-12 2016-10-25 Nvidia Corporation Method and system for implementing a multi-threaded API stream replay
US9116799B2 (en) 2013-06-30 2015-08-25 Freescale Semiconductor, Inc. Method for detecting bank collision at a memory and device therefor
US9569385B2 (en) 2013-09-09 2017-02-14 Nvidia Corporation Memory transaction ordering

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8700092D0 (en) * 1987-01-05 1987-02-11 Crosfield Electronics Ltd Image processing
US5287446A (en) * 1990-10-15 1994-02-15 Sierra On-Line, Inc. System and methods for intelligent movement on computer displays
US5513307A (en) * 1992-11-20 1996-04-30 Sega Of America, Inc. Video game with switchable collision graphics

Also Published As

Publication number Publication date
US5777628A (en) 1998-07-07
JPH1083346A (ja) 1998-03-31

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