JP3762185B2 - Drawing device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a drawing apparatus that draws a bitmap image and is used in an apparatus that displays an image using bitmap data, such as a page printer.
[0002]
[Prior art]
Conventionally, in this type of drawing apparatus, when image memory mapping is performed using a memory bank, a hit and a miss of a row address are simply determined in units of access. Further, the destination prefetching device simply reads the next address after the continuous address.
[0003]
[Problems to be solved by the invention]
However, in the conventional system for controlling a memory bank, when data with a small number of words, such as characters, is drawn, line breaks occur frequently and row address mishits occur frequently, resulting in a decrease in processing speed. There was a drawback.
[0004]
In addition, in the system that pre-reads the destination data, when drawing data with a small number of words such as characters as described above, the pre-read data cannot be used for line breaks, and a new line The process of re-reading the destination data is repeated, and there is a drawback that the drawing speed is remarkably reduced.
[0005]
Accordingly, an object of the present invention is to provide a drawing apparatus capable of dramatically improving the frequency of frequent row address miss-hits and executing a drawing operation at high speed.
[0006]
[Means for Solving the Problems]
In the present invention, the mapping means for alternately mapping the banks of the memory to be drawn by the odd lines and the even lines, and the writing of the previous logical operation and the reading of the next destination are performed in parallel with the logical operation of the data. Control means is provided for performing control so that the next line is prefetched at the time of a line break, so that a bank is always different and a row address mishit at the time of data writing does not occur.
[0007]
【Example】
Example 1
1 to 6 are diagrams for explaining a drawing apparatus embodying the present invention, of which FIG. 1 is a block diagram. In FIG. 1, 101 is a drawing apparatus that implements the present invention, 102 is an address generator, 103 is a DMA controller, 104 is a bitmap memory, 105 is a sequence controller, 106 is an image generator, 107 is a logical operation circuit, 110 is a selector, 111-113 are buffer 1, buffer 2, and buffers 3, 114, 115 are selectors, respectively.
[0008]
FIG. 2 is a diagram for explaining the drawing operation of this embodiment. In FIG. 2, 201 is a bitmap image generated by the image generator 106, 202 is destination image data already drawn on the bitmap memory to be drawn, 203 is a drawing start address on the bitmap memory 104, and 204 is This is image data obtained by performing a logical operation on the bitmap image 201 and the destination image 202.
[0009]
FIG. 3 is a diagram showing the memory address of the drawing data of this embodiment, 301 is the drawing image data, and 302 is the drawing address. Reference numeral 303 denotes bitmap data in the address.
[0010]
The drawing apparatus embodying the present invention uses, for example, a letter A (shown by 201 in FIG. 2) generated by the image generator 106 shown in FIGS. (Shown at 203). At this time, if there is already drawn data (for example, the letter B in FIG. 2) in the drawing target area, the data (that is, the destination data) is logically operated with the designated logic, and a composite image ( And a drawing band or a drawing page image is formed by writing in the bitmap memory. In order to realize this drawing operation, the drawing apparatus has the configuration shown in FIG.
[0011]
In FIG. 1, an image generator 106 is a drawing processing list composed of coordinate positions to be drawn from a data bus, types of logical operations, line heights to be drawn, numbers for specifying object data such as character fonts and image images, and the like. , Generates a bitmap-format drawing image from the specified object data, and outputs the image data. At the same time, the line position of the drawing reference point from the drawing coordinate position, the horizontal position, and the actual drawing object data From the left coordinate of the current line, the left coordinate of the next line, and the width of the drawing object, the right coordinate of the current line indicating the position of the final data of the drawing data of the processing line is output. The data transfer timing is performed by a data enable signal, a data request signal, and a line end signal.
[0012]
As the left coordinates, “0” is output when a rectangle is drawn, and the coordinates of the left edge of the graphic are output in the case of a graphic such as a circle. The address generator 102 receives the current line left coordinate signal and the right coordinate signal of the current line from the image generator 106 and generates a drawing address from the band head address and bandwidth data held in the internal register and the drawing bank. Make a selection.
[0013]
The DMA controller 103 receives address information and bank information from the address generator 102, drives an address line, a bank switching signal (bank selection signal) line and a memory control line of the bitmap memory 104, and generates a memory cycle. The destination data read by the generated memory cycle is held in any of the buffers 111 to 113 by the selectors 108 to 110. The destination data held in the buffer is selected by the selector 115 and input to the logical operation circuit 107.
[0014]
On the other hand, the logical operation circuit 107 receives image data from the image generation device 106, performs logical operation on the input image data and destination data, is selected by the selectors 108 to 110, and is stored in any of the buffers 111 to 113. Stored as drawing data. The held drawing data is selected by the selector 114 and written on the bitmap memory 104. Drawing in the present embodiment is performed as described above.
[0015]
Here, one of the buffers 1 to 3 (111 to 113) is for outputting write data and inputting read data, one for outputting read data held therein to the logical operation circuit, and one from the logical operation circuit. Used for data input. For example, drawing data is held in the buffer 2 from the destination data held in the buffer 1 through a logical operation circuit. In parallel with the data processing, the previous data already stored in the buffer 3 is written to the bitmap memory, and when the writing is completed, the next data is read from the bitmap data to prepare for the next processing. Holds nation data.
[0016]
When these are finished, the selectors 108 to 110 and 114 to 115 are switched, and the drawing data is held in the buffer 1 from the destination data held in the buffer 3 through the logic operation circuit 107. In parallel with the data processing, the data previously held in the buffer 2 is written to the bitmap memory, and when the writing is completed, the next data is read from the bitmap data and the new destination data is held. .
[0017]
In this way, the generation of the drawing data and the input / output to the memory are performed in parallel using the buffer one after another. The sequence controller 105 controls these series of constituent blocks. The sequence controller 105 operates so as to perform the above-described processing in a sequence, outputs a sequence number being executed and an enable signal to the address generator 102, and controls which address such as writing or reading is generated.
[0018]
The address generator 102 recognizes a line feed position from the input line right coordinate and the number of output access addresses and outputs a line feed signal. The address generator 102 generates a read address of the next line from the left coordinate of the next line where the line feed is performed, and outputs the destination address after the line feed. For the DMA controller 103, the sequence controller 105 requests read DMA access by the RDRQ signal and write DMA access by the WDRQ signal, and the DMA controller starts a memory cycle according to the address generated by the address generator 102.
[0019]
At a predetermined timing of the memory cycle, an RDACK signal is output to the sequence controller 105 for a read request, and a WDACK signal is output to the sequence controller 105 for a write request. The sequence controller 105 switches the selectors 108 to 110 and the selectors 114 to 115 according to the current sequence state, and outputs the RD signal or the WR signal to each of the buffers 111 to 113 to realize the drawing process.
[0020]
FIG. 3 is a diagram showing the correspondence between the drawing data and the memory cells of the bitmap memory. In FIG. 3, reference numeral 301 denotes drawing data obtained by a logical operation, and 302 denotes a memory address to which it is written. The address S in 302 corresponds to the drawing start address S in FIG. The bitmap memory 104 uses a memory such as a synchronous DRAM that can be accessed by a bart and has a plurality of banks therein. As shown in FIG. 0, bank 1... Are alternately mapped for each line.
[0021]
In the example of FIG. 3, the bitmap memory is assumed to be capable of burst access of 8 words at a time, and each line is drawn in two memory cycles of 8 word cycles of address S to address S + 1Ch and 1 word access of address S + 20h. Divided into two. Reference numeral 303 indicates that the data in each word is bitmap data in which the logic “1” and “0” of the bit of the memory data correspond to the black dots and the white dots.
[0022]
FIG. 4 is a diagram representing the memory access and the execution of the logical operation when the drawing operation described above is performed. In the figure, the white area is the process related to the memory bank 0, and the gray area is the process related to the memory bank 1. It is. The drawing operation starts at time tss, and 8 words of the drawing address and the destination data of the address S of bank 0 are read into the first buffer.
[0023]
At times t00 to t02, the data in the first buffer is sequentially subjected to logical operation and written to the second buffer. From time t01 to t02, the destination data of the next drawing address, bank 0 address S + 20, is read into the third buffer. From time t02 to t03, the logically processed data of the second buffer is written to the bank 0 address S, and from time t03 to t04, the next line data and the destination data of the address S of the bank 1 are stored in the second buffer. Is read. At the same time from time t02 to t04, the drawing address already read into the third buffer, the data of one word at bank 0 and address S + 20 are logically calculated with the input image data, and written into the first buffer.
[0024]
Thereafter, the input / output of data and the logical operation are performed in parallel while the respective buffers circulate similarly, and the image drawing operation is performed efficiently. The lower diagram of FIG. 4 is a diagram summarizing the memory access for each memory bank, and it can be seen that the memory address is executed at high speed because the row address mishit occurs only once at the time of line break in each bank. . As described above, according to the present invention, the drawing operation can be executed at a high speed by performing the memory data input / output and the logical operation in parallel. By mapping each time alternately, it is improved drastically and further high-speed drawing is realized.
[0025]
(Example 2)
FIG. 5 shows an example in which the present invention is applied to a memory having four banks. Of course, four banks may be mapped alternately every four lines. However, since this can be easily inferred from the first embodiment, in the second embodiment, two banks are alternately mapped to memory access units in one line. An example in which mapping is alternately performed for each line will be described.
[0026]
FIG. 5 explains memory access and logical operation of the data drawing operation of FIG. 2 by this mapping method. In the case of FIG. 4, one bank of data is accessed alternately in two banks, and this bank set is accessed alternately for each line. In the case of this example, each bank is sequentially accessed as addresses S, S + W, S + 2W... As shown in FIG. Therefore, since address return, that is, S, S + 20, S, S + 20 does not occur as in the first embodiment, for example, a row miss can be prevented when there is a row address boundary between the addresses S and S + 20.
[0027]
In this embodiment, since there are two banks in one line, when performing small drawing with many line breaks, the frequency of low miss increases, which is disadvantageous. However, when wide data is drawn, the address is returned. It is very advantageous because it is not.
[0028]
Example 3
FIG. 6 is a configuration diagram of Embodiment 3 of the present invention. In FIG. 6, reference numeral 606 denotes an image generator, and 607 denotes a logical operation circuit. Other configurations are the same as those in the first embodiment. In this embodiment, the image generator 606 outputs a mask image for designating an area to be clipped, a background image as a pasting pattern, and a gray image expressing the color and density to be applied, and the logical operation circuit 607 generates these. Perform complex logic operations on the image and destination data. Other processes are the same as those in the first embodiment.
[0029]
Thus, the present invention does not limit the type and number of images to be input, and does not limit the number of bits of the bitmap memory that constitutes one pixel of the drawn image.
[0030]
【The invention's effect】
As described above, according to the present invention, frequent input and output of a memory data and logical operation are performed in parallel, and two banks of the bitmap memory are alternately mapped for each line, thereby causing frequent row addresses. The number of miss hits can be drastically improved and the drawing operation can be executed at high speed.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of Embodiment 1. FIG.
FIG. 2 is a diagram illustrating a drawing operation.
FIG. 3 is a diagram illustrating a configuration of a bitmap memory.
FIG. 4 is a diagram illustrating a memory cycle for rectangular drawing.
FIG. 5 is a diagram illustrating a memory cycle of rectangular drawing according to the second embodiment.
FIG. 6 is a configuration diagram of the third embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 101 Drawing apparatus 102 Address generator 103 DMA controller 104 Bitmap memory 105 Sequence controller 106 Image generator 107 Logic operation circuit 108-110 Selector 111-113 Buffer 114-115 Selector

Claims (5)

A drawing apparatus that generates bitmap format image data based on a drawing processing list and draws the image data in a memory, reads a destination image already drawn on the memory, and reads the destination image and In a drawing apparatus that performs drawing by performing logical operation on the generated image data and writing the logically calculated image data into the memory, the memory having a plurality of banks is used, and odd lines and even lines of the drawing lines are set. A mapping means for mapping to different memory banks, and a control means for controlling the writing of the previous logical operation data and the reading of the next destination data in parallel with the logical operation of the data are provided. Drawing device to do.   The control means writes the logical operation of the predetermined amount of data of the odd line in parallel with the logical operation of the predetermined amount of data of the read odd line and the next destination data of the predetermined amount of the even line. The drawing apparatus according to claim 1, wherein control is performed so as to read out.   The control means writes the logical operation of the predetermined amount of data of the even line and the next destination data of the predetermined amount of the odd line in parallel with the logical operation of the predetermined amount of data of the read odd line. The drawing apparatus according to claim 1, wherein control is performed so as to read out the image.   The control means writes a logical operation of a predetermined amount of data of an even line in parallel with a logical operation of a predetermined amount of data of the read even line and a next destination data of a predetermined amount of an odd line. 4. The drawing apparatus according to claim 1, wherein the drawing apparatus is controlled so as to perform reading.   The control means writes the logical operation of the predetermined amount of data on the odd line and the next destination data of the predetermined amount on the even line in parallel with the logical operation of the predetermined amount of data of the even line read out. 5. The drawing apparatus according to claim 1, wherein control is performed so as to read out the data.

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