JP3742423B1 - Charger - Google Patents

Abstract

In a charging device for charging an electric double layer capacitor (hereinafter referred to as “capacitor”) by a solar cell, the flow of electric energy from the solar cell to the capacitor is controlled in order to improve the charging efficiency of the capacitor by the solar cell. To do.
A charging device includes: (a) a DC-DC converter having at least a switch and converting electric power supplied from a solar cell to a capacitor in accordance with a variable duty ratio of the switch; , (B) a detection circuit 50 for detecting the charging current of the capacitor, and (c) a charging current Ic detected by the detecting circuit is referred to, but the charging voltage Vc of the capacitor is not referred to, and the charging current of the capacitor is referred to. And a controller 60 that controls the switch so as to realize the determined duty ratio.
[Selection] Figure 1

Description

  The present invention relates to a technology for charging an electric double layer capacitor with a solar cell, and in particular, controls the flow of electric energy from the solar cell to the electric double layer capacitor in order to improve the charging efficiency of the electric double layer capacitor with the solar cell. Related to technology.

  There is a solar cell as an example of a power generation element that uses natural energy to generate electrical energy. There is also an electric double layer capacitor (hereinafter simply referred to as “capacitor”) as an example of a storage element that stores electric energy generated by such a power generation element.

  In order to charge a capacitor with a solar cell, a charging device is connected to the solar cell and the capacitor. In an example of this charging device, a converter that converts a DC voltage generated by the solar cell and supplies the capacitor to the capacitor is used to increase the charging efficiency of the capacitor by the solar cell. An example of this converter is a switching converter.

  Generally, a solar cell has a characteristic that generated power has a maximum point with respect to a generated voltage and a generated current. Therefore, when using a solar cell, when the power generation voltage or power generation current of the solar cell changes, the generated power, that is, the output energy of the solar cell changes accordingly.

  On the other hand, a capacitor is characterized in that the voltage changes greatly according to its charge state, that is, the amount of electric charge accumulated in the capacitor. This feature is unique to the capacitor and does not exist in other types of power storage elements.

  There is a conventional example of a charging device that is used by being connected to a solar cell and a capacitor having the characteristics and characteristics described above (see, for example, Patent Document 1). This conventional example includes a switching converter having a switch, a coil, and a diode, a current detection circuit that detects a power generation current of the solar battery, a voltage detection circuit that detects a power generation voltage of the solar battery, the switching converter and the current detection. A controller is connected to the circuit and the voltage detection circuit.

In this conventional example, the controller sets the duty ratio of the switch so that the generated power of the solar cell is maximized based on the generated current detected by the current detecting circuit and the generated voltage detected by the voltage detecting circuit. Determine the optimal value. This controller controls the on / off state of the switch so that the optimum value of the determined duty ratio is realized.
JP 2002-199614 A

  In this conventional example, in order to maximize the generated power of the solar cell, two types of physical quantities, voltage and current, must be detected for the solar cell. Therefore, the hardware configuration for detecting these two types of physical quantities is likely to be more complicated than when only one physical quantity needs to be detected.

  Further, in this conventional example, in order to determine the duty ratio of the switch so that the generated power of the solar cell is maximized, (a) the relationship between the generated voltage and the generated current for realizing the maximized generated power is determined in advance. A method for determining the optimum value of the duty ratio of the switch in accordance with the relationship, and (b) calculating the generated power as the product of the detected value of the generated voltage and the detected value of the generated current, and the generated power is the maximum It is possible to employ a method of exploringly determining the optimum value of the duty ratio of the switch so that

  However, in this conventional example, regardless of which of these two types of methods is employed, all three physical quantities of voltage, current, and power must be handled as variable values for the solar cell. Therefore, the logic configuration (electronic circuit configuration or software configuration) for determining the optimum value of the duty ratio of the switch is more complicated than the case where it is sufficient to handle a smaller number of physical quantities as variable values.

  Against the background described above, the present invention relates to a technology for charging an electric double layer capacitor by a solar cell, in order to improve the charging efficiency of the electric double layer capacitor by the solar cell, from the solar cell to the electric double layer capacitor. An object of the present invention is to more accurately determine the duty ratio of a switch that controls the flow of electric energy.

  The following aspects are obtained by the present invention. Each aspect is divided into sections, each section is given a number, and is described in a form that cites other section numbers as necessary. This is to facilitate understanding of some of the technical features that the present invention can employ and combinations thereof, and the technical features that can be employed by the present invention and combinations thereof are limited to the following embodiments. Should not be interpreted. That is, it should be construed that it is not impeded to appropriately extract and employ the technical features described in the present specification as technical features of the present invention although they are not described in the following embodiments.

  Further, describing each section in the form of quoting the numbers of the other sections does not necessarily prevent the technical features described in each section from being separated from the technical features described in the other sections. It should not be construed as meaning, but it should be construed that the technical features described in each section can be appropriately made independent depending on the nature.

(1) A charging device that is used by being connected to a solar cell and an electric double layer capacitor in order to charge the electric double layer capacitor with a solar cell in which the generated power has a maximum point with respect to the generated voltage and the generated current. ,
A DC-DC converter having at least a switch and converting electric power supplied from the solar cell to the electric double layer capacitor according to a variable duty ratio of the switch;
A detection circuit for detecting a charging current of the electric double layer capacitor;
The duty ratio is determined so that the charging current of the electric double layer capacitor is substantially maximized without referring to the charging voltage of the electric double layer capacitor, while referring to the charging current detected by the detection circuit. And a controller that controls the switch so that the determined duty ratio is realized.

  As will be described in detail later, the instantaneous value of the electric energy flowing from the solar cell to the electric double layer capacitor (hereinafter simply referred to as “capacitor”) through the switch is represented by the product of the charging voltage and the charging current. Further, when observed within a short time range, the charging voltage of the capacitor is almost constant. Therefore, the amount of electrical energy flowing into the capacitor is proportional to the current flowing into the capacitor, that is, the charging current.

  Therefore, within a short time range, as long as the charging current of the capacitor is taken into consideration, it can be determined sufficiently accurately whether the electric energy flowing into the capacitor is large or small without considering the charging voltage.

  Based on the knowledge described above, in the charging device according to this section, the charging current of the capacitor detected by the detection circuit is referred to, but the duty ratio of the switch is determined without referring to the charging voltage of the capacitor. .

  Therefore, according to this charging device, in order to improve the charging efficiency of the capacitor, it is possible to detect a necessary physical quantity, compared to the case where two kinds of physical quantities, voltage and current, must be detected for a solar cell or a capacitor. It is easy to simplify the hardware configuration (for example, the detection circuit).

  Furthermore, according to this charging device, it is not necessary to treat all three physical quantities of voltage, current and power as variable values for the solar cell or the capacitor in order to improve the charging efficiency of the capacitor. It is also easy to simplify the logic configuration (electronic circuit configuration or software configuration) for determining the optimum value of the duty ratio.

  By the way, in this type of charging device, the ultimate purpose is to maximize the power taken into the capacitor from the solar cell, that is, to maximize the charging power of the capacitor. On the other hand, in the above-described conventional example, if the switch for controlling the flow of electric energy from the solar cell to the capacitor is controlled so that the generated power of the solar cell is maximized, the charging power of the capacitor is also maximized. Based on the assumption of linear dependence, the switch is controlled so that the power generated by the solar cell is maximized.

  However, the dependency relationship is not necessarily established in all charging devices. For example, in an environment in which an electric circuit that supplies electric energy from a solar cell to a capacitor is configured as a linear circuit in the charging device, the linear dependency relationship is established. On the other hand, in an environment where the electric circuit includes a non-linear element (for example, many semiconductor elements including a diode), the linear dependence relationship is not established. For this reason, when the above-described conventional example is implemented, the generated power of the solar cell is maximized, but the charging power of the capacitor is not maximized.

  On the other hand, in the charging device according to this section, the duty ratio of the switch is determined so that the charging current of the capacitor is substantially maximized. Therefore, according to this charging device, regardless of the characteristics of the electric circuit between the solar cell and the capacitor, it is easy to reliably achieve the ultimate purpose of maximizing the power taken into the capacitor from the solar cell. It becomes.

  An example of the “DC-DC converter” in this section is configured to include a switch, a coil, and a diode, and another example includes a switch, a coil, and a transistor or FET of a commutation circuit. It is configured as a synchronous rectification method.

(2) Furthermore, in order to stabilize the power generation voltage of the solar cell, a capacitor connected in parallel to the solar cell is included, and the capacitance of the capacitor is smaller than the capacitance of the electric double layer capacitor (1 ) The charging device according to item.

  In this charging device, the release of electrical energy from the solar cell to the capacitor is permitted when the switch is off. Therefore, according to this charging device, the generation of electric energy from the solar cell, that is, the terminal voltage of the capacitor is stabilized as a result of permitting the release of electric energy from the solar cell regardless of the on / off operation of the switch.

  Therefore, according to this charging device, the generated voltage of the solar cell is stabilized in spite of the on / off operation of the switch, and thus the charging voltage of the capacitor is also stabilized, which is possible without detecting the charging voltage of the capacitor. It contributes effectively to maximize the charging power of the capacitor with high accuracy.

(3) The controller
A storage unit for storing the charging current;
The charging device according to (1) or (2), including: a determination unit that determines the duty ratio based on the charging current.

(4) The charging device according to (3), wherein the storage unit includes a digital memory that stores a detection value of the charging current by the detection circuit as digital data.

(5) The charging device according to (3), wherein the storage unit includes an analog memory that stores a detected value of the charging current by the detection circuit as an analog signal.

(6) The charging device according to (5), wherein the analog memory includes a sample and hold circuit that samples and holds a detected value of the charging current by the detection circuit at a commanded sampling timing.

(7) The analog memory includes at least two sample and hold circuits that sample and hold the detection values of the charging current by the detection circuit at different sampling timings, respectively.
The determination unit includes an analog voltage signal representing a current detection value of at least two detection values respectively held by the at least two sample hold circuits, and an analog voltage signal representing at least one past detection value. The charging device according to item (6), including a voltage comparison circuit that compares the duty ratios with each other and determining the duty ratio based on the comparison result.

(8) The analog memory includes a sample-and-hold circuit that samples a detection value of the charging current by the detection circuit at a sampling timing and holds it as a past detection value,
The determination unit includes a voltage comparison circuit that compares an analog voltage signal representing a past detection value held by the sample hold circuit with an analog voltage signal representing a current detection value of a charging current by the detection circuit, and The charging device according to (6), wherein the duty ratio is determined based on a comparison result.

(9) The determination unit repeats a forced change cycle for discretely and forcibly changing the duty ratio in order to exploratively determine the optimum value of the duty ratio, and in each forced change cycle The method according to any one of (3) to (8), wherein the duty ratio is determined so that the charging current is substantially maximized according to a response of the charging current to the forced change of the duty ratio. Charging device.

  In one specific example of the charging device according to this section, the slope of the response (increase or decrease) of the capacitor charging current to the forced change (increase or decrease) of the switch duty ratio is the maximum value of the charge current. Focusing on the fact that it decreases as it approaches, the optimal value of the duty ratio is determined exploratoryly.

Specifically, for example, in each forcible change cycle, the determination unit determines whether the response (increase or decrease) of the capacitor charging current to the forced change (increase or decrease) of the switch duty ratio is the current forced change cycle. The next forced change is made in the same direction as the current forced change, and if the charge current response is substantially zero, the charge current Assuming that the current value is a local maximum, the next forced change is omitted, and if the charge current response is opposite to the direction of the current forced change, the next forced change Make changes in the opposite direction of the forced changes.

(10) In each of the forced change cycles, the determination unit performs a previous detection value that is a charging current detected by the detection circuit before the current forced change is performed, and a current forced change. (9) The charging device according to item (9), in which the current detection value, which is the charging current detected by the detection circuit after being detected, is compared with each other, and the response of the charging current is monitored using the comparison result.

  In a specific example of the charging device according to this section, the determination unit determines a magnitude relationship between the previous detection value and the current detection value regarding the charging current of the capacitor in each forced change cycle, and the two coincide with each other. If not, the change state of the current detection value from the previous detection value (including at least the change amount between the change direction and the change amount) is monitored as a response of the charging current to the current forced change, and the next time In the forced change cycle, the content of the current forced change of the duty ratio is determined based on the monitored change state.

(11) The storage unit
First and second sample-and-hold circuits that sample and hold the detected value of the charging current by the detection circuit at different sampling timings;
A timing circuit that determines the sampling timing of the detection value by each sample-and-hold circuit so that the detection values are sampled alternately by the first and second sample-hold circuits,
The determination unit
A comparison circuit for comparing the two detection values held in the first and second sample and hold circuits with each other;
A storage circuit for storing a change history of the duty ratio;
A logic circuit that determines a current value of the duty ratio in accordance with a predetermined rule based on a change history stored in the storage circuit and a comparison result by the comparison circuit; (3) to (10) The charging apparatus in any one of.

(12) The storage unit
A sample-and-hold circuit that holds a detection value of the charging current by the detection circuit;
A timing circuit for determining the sampling timing of the detection value by the sample and hold circuit,
The determination unit
A comparison circuit that compares the detection value held by the sample hold circuit with the latest value of the detection value of the charging current detected by the detection circuit;
A storage circuit for storing a change history of the duty ratio;
A logic circuit that determines a current value of the duty ratio in accordance with a predetermined rule based on a change history stored in the storage circuit and a comparison result by the comparison circuit; (3) to (10) The charging apparatus in any one of.

(13) The charging device according to any one of (1) to (12), wherein the controller further includes a switch control circuit that controls the switch so that the determined duty ratio is realized.

(14) The charging device according to (13), wherein the switch control circuit switches the switch between an on state and an off state based on a signal from a computer of the controller.

(15) The switch control circuit includes:
A switching circuit that is electrically connected to the switch and switches the switch between an on state and an off state;
The counter value is set in accordance with the duty ratio determined by the controller and is electrically connected to the switching circuit, and the switching circuit keeps the switch in the ON state in accordance with the set counter value. And a counter circuit that changes the length of the charging device according to item (13).

(16) The switch control circuit includes:
An oscillation circuit for generating a triangular wave signal;
The switch is electrically connected to the oscillation circuit and the switch, and the triangular wave signal generated by the oscillation circuit is binarized at a threshold level to selectively generate an on signal and an off signal, and the switch A binarization circuit that outputs to
A threshold level signal generation circuit which is electrically connected to the binarization circuit and generates a signal representing the threshold level according to a duty ratio determined by the controller and outputs the signal to the binarization circuit; (13) The charging device according to item.

(17) The controller includes a holding unit that holds the duty ratio until a predetermined condition is satisfied after the latest value of the duty ratio is determined. The charging device described.

  When the latest value of the duty ratio of the switch is determined and realized, the operating state of the charging device shifts to a transient state. It takes time until the transient state is settled, and if the charging current of the capacitor is detected before the settling and a new duty ratio is determined using the detected value, the determination accuracy may be lowered. .

  On the other hand, in the charging device according to this section, after the latest value of the duty ratio is determined, the duty ratio is maintained until a predetermined condition is satisfied. Therefore, according to this charging device, although the charging device temporarily shifts to a transient state due to the on / off operation of the switch, the accuracy of determining the next duty ratio due to the transient state is reduced. It becomes possible to suppress.

(18) The charging according to any one of (1) to (17), wherein the controller includes a current limiting unit that determines the duty ratio so that a charging current detected by the detection circuit does not exceed an upper limit value. apparatus.

(19) The charging device according to any one of (1) to (18), wherein the DC-DC converter is a step-down type.

  According to this charging device, the generated voltage of the solar cell is stepped down and applied to the capacitor, so that the generated current of the solar cell can be increased and supplied to the capacitor. As a result, the charging efficiency of the capacitor can be improved.

  Hereinafter, some of more specific embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows an electric circuit diagram of a charging device 10 according to a first embodiment of the present invention together with a solar cell 12 and an electric double layer capacitor (hereinafter simply referred to as “capacitor”) 14. FIG. 1 also shows a load 16 that consumes the electrical energy generated by the solar cell 12.

  As shown in FIG. 1, the charging device 10 has a positive electrode line 20 and a negative electrode line 22. The positive electrode line 20 has external terminals 24, 26, 28, and 30 at both ends. The charging device 10 is electrically connected to the positive terminal and the negative terminal of the solar cell 12 at the external terminal 24 of the positive line 20 and the external terminal 28 of the negative line 22, respectively. Further, the charging device 10 is electrically connected to the positive terminal and the negative terminal of the capacitor 14 at the external terminal 26 of the positive line 20 and the external terminal 30 of the negative line 22, respectively.

  In FIG. 1, the generated voltage of the solar cell 12 is expressed as “Vs” and the generated current is expressed as “Is”, while the charging voltage of the capacitor 14 is expressed as “Vc” and the charging current is expressed as “Ic”. Yes.

  The solar cell 12 converts solar energy into electric energy. The solar cell 12 has a characteristic that the generated power changes according to the illuminance of sunlight. The solar cell 12 also has a characteristic that the generated power has a maximum point with respect to the generated voltage Vs and the generated current Is, as shown in the graph of FIG. Therefore, when this solar cell 12 is used, when the generated voltage Vs or the generated current Is of the solar cell 12 changes, the generated power, that is, the output energy of the solar cell changes accordingly.

  FIG. 2 is a graph showing characteristics in which the generated voltage Vs and the generated current Is change under the condition that the illuminance of sunlight is constant. In FIG. 2, the intersection of the graph and the straight line A indicates that the product of the generated current Is and the generated voltage Vs, that is, the generated power is a maximum value because the resistance of the load 16 is optimal. Further, in FIG. 2, the intersection of the graph and the straight line B indicates that the generated power is not the maximum value because the resistance of the load 16 is too large. Further, in FIG. 2, the intersection of the graph and the straight line C indicates that the generated power is not the maximum value because the resistance of the load 16 is too small.

  The capacitor 14 stores the electrical energy generated by the solar cell 12. The capacitor 14 is characterized in that the voltage varies greatly depending on the state of charge thereof, that is, the amount of charge accumulated in the capacitor 14. This feature is unique to the capacitor 14 and does not exist in other types of power storage elements.

  In order to increase the energy that can be stored, the capacitor 14 is composed of a plurality of individual capacitors connected in series as shown in FIG. In the case where it is necessary to further increase the energy that can be stored, the capacitor 14 can be configured by connecting a plurality of parallel circuits of a plurality of individual capacitors in series with each other.

  As shown in FIG. 1, the charging device 10 includes a step-down DC-DC converter (hereinafter simply referred to as “converter”) 32.

  The converter 32 includes a chopper type switch (for example, a semiconductor switch) 40, a coil (inductor) 42, and a diode (flyhole diode) 44. The switch 40 and the coil 42 are connected in series with each other in the positive electrode line 20 in that order. The diode 44 is connected to an intermediate line 46 extending from a portion of the positive electrode line 20 between the switch 40 and the coil 42 and reaching the negative electrode line 22.

  In this converter 32, a voltage lower than the power generation voltage Vs of the solar cell 12 is applied to the capacitor 14, while a current larger than the power generation current Is of the solar cell 12 is supplied to the capacitor 14. Has a function of converting the power supplied to the.

  As is well known, this converter 32 is a method of smoothing a square wave (intermittent waveform) generated by turning on and off the switch 40. This method is employed when the output voltage, that is, the charging voltage Vc of the capacitor 14 is lower than the input voltage, that is, the generated voltage Vs of the solar battery 12.

  In the converter 32, the electrical energy of the solar cell 12 is stored as magnetic energy in the coil 42 via the switch 40 during a period in which the switch 40 is in an on (conducting) state. Thereafter, when the switch 40 is switched to an off (cut-off) state, the magnetic energy stored in the coil 42 is converted into electric energy by the closed circuit including the coil 42, the capacitor 14, and the diode 44 and supplied to the capacitor 14. . By repeatedly turning the switch 40 on and off, the electric energy of the solar cell 12 is supplied to the capacitor 14, whereby the capacitor 14 is charged by the solar cell 12.

At this time, the charging voltage Vc of the capacitor 14 is a value obtained by dividing the duty ratio of the switch 40, that is, the conduction time T _ON when the switch 40 is turned on by the sum of the conduction time T _ON and the non-conduction time T _OFF. The generated voltage Vs of the solar cell 12 has a reduced height based on the above. If the voltage obtained by stepping down the generated voltage Vs becomes the charging voltage Vc, the current obtained by increasing the generated current Is of the solar battery 12 becomes the charging current Ic of the capacitor 14 in return.

  That is, the converter 32 performs voltage / current conversion (power conversion) between the solar cell 12 and the capacitor 14, and specifically, the power is stored between the solar cell 12 and the capacitor 14. Under the conditions, high voltage and small current electricity in the solar cell 12 is converted into low voltage and large current electricity in the capacitor 14. Thereby, the charging efficiency of the capacitor 14 by the solar cell 12 is improved.

  As shown in FIG. 1, the charging device 10 further includes a capacitor 48 on the upstream side of the converter 32. The capacitor 48 is connected in parallel to the solar cell 12 in a state of being connected to the positive electrode line 20 and the negative electrode line 22. The capacitor 48 allows the electric energy to be discharged from the solar cell 12 and temporarily stores the discharged electric energy when the switch 40 is in the OFF state. On the other hand, the capacitor 48 sends the electrical energy accumulated in the capacitor 48 to the capacitor 14 via the switch 40 together with the electrical energy generated by the solar cell 12 when the switch 40 is in the ON state.

  If the charging device 10 does not include the capacitor 48, the release of electric energy from the solar cell 12 is prevented when the switch 40 is in the OFF state. Therefore, the power generation voltage Vs of the solar cell 12 is a voltage represented by a portion corresponding to the no-load state in the characteristic curve of the solar cell 12 shown in FIG. In the ON state, the voltage is represented by a portion corresponding to the amount of current flowing through the switch 40 in the characteristic curve of the solar cell 12. Therefore, regardless of whether the switch 40 is in an off state or an on state, the solar cell 12 is not in an optimal load state in which electric energy extracted from the solar cell 12 is maximized.

  On the other hand, in the present embodiment, as shown in FIG. 1, since the charging device 10 includes the capacitor 48, the electrical energy is released from the solar cell 12 to the capacitor 48 in the off state of the switch 40. Allowed. Therefore, according to the present embodiment, as a result of permitting the release of electric energy from the solar cell 12 despite the on / off control of the switch 40, the generated voltage Vs of the solar cell 12, that is, the terminal voltage of the capacitor 48 is stabilized. . Therefore, it becomes possible to maintain the solar cell 12 in the optimum load state in which the electric energy extracted from the solar cell 12 is maximized.

In short, the capacitor 48 has a function of stabilizing the power generation voltage Vs of the solar cell 12 regardless of the on / off operation of the switch 40. In order to perform this function, the voltage of the capacitor 48 needs to change sensitively during one cycle of duty ratio control of the switch 40. Therefore, the capacitor 48 has a capacitance smaller than that of the capacitor 14. is doing. The capacitance of the capacitor 48 is set according to the length of the switching period T (for example, 10 μs ) of the switch 40, the amount of current flowing out from the solar cell 12 through the switch 40 in the ON state of the switch 40, and the like. .

  As shown in FIG. 1, the charging device 10 further includes a detection circuit 50 that detects a charging current Ic of the capacitor 14.

  The detection circuit 50 detects the current flowing through the capacitor 14, that is, the amount of the charging current Ic, by detecting the current connected to the portion of the negative line 22 between the connection point of the negative terminal of the capacitor 14 and the ground point. A resistor 52 is provided. The current detection resistor 52 has a function of converting a current flowing through the capacitor 14 into a voltage.

  The detection circuit 50 further includes an amplifier (DC amplifier) 54 that amplifies the voltage of the current detection resistor 52 at a constant magnification. The amplifier 54 outputs an analog signal representing the charging current Ic of the capacitor 14. In order to convert the analog signal output from the amplifier 54 into a digital signal, the charging apparatus 10 includes an AD converter 56.

  As shown in FIG. 1, the charging device 10 further includes a controller 60. The controller 60 is mainly composed of a computer 70 as conceptually shown in a block diagram in FIG. The computer 70 includes a CPU 72, a ROM 74, and a RAM 76 that are connected to each other via a bus 78. The controller 60 further includes an I / O interface 80, and the computer 70 is electrically connected to the switch 40 and the AD converter 56 via the I / O interface 80.

  As shown in FIG. 3, the ROM 74 stores in advance various programs including a switching control program and a duty ratio determination program. The duty ratio determination program is executed by the CPU 72 to detect the charging current Ic of the capacitor 14 in a time discrete manner via the detection circuit 50 and to determine the duty ratio τ of the switch 40 based on the detected value. The switching control program is executed by the CPU 72 in order to control the switch 40 with the determined duty ratio τ.

  The switching control program and the duty ratio determination program are repeatedly executed by the CPU 72 alternately and in a cycle that is extremely short as compared with the operation response time of the charging apparatus 10. Therefore, the duty ratio determination process by the execution of the duty ratio determination program and the switching control by the execution of the switching control program are apparently executed in parallel with each other. The switching control program is repeatedly executed at the same cycle as the switching cycle T of the switch 40.

  On the other hand, the RAM 76 includes a plurality of memories assigned to store various digital data. These memories include (a) a duty ratio memory 90 that temporarily stores the determined duty ratio τ, and (b) a current current memory 92 that temporarily stores a current detection value of the charging current Ic by the detection circuit 50. And (c) a current current memory 94 that temporarily stores the previous detection value of the charging current Ic by the detection circuit 50.

  FIG. 4 conceptually shows a switching control program in a flowchart. This switching control program is repeatedly executed by the CPU 72. At the time of each execution, first, the duty ratio τ is read from the duty ratio memory 90 in step S10 (hereinafter, simply expressed as “S10”. The same applies to other steps). Next, in S <b> 11, the current i is read from the current current memory 92.

  Subsequently, in S12, it is determined whether or not the read current i is equal to or greater than the maximum value iMAX. This time, if it is assumed that the current i is not equal to or greater than the maximum value iMAX, the determination is NO, and in S13, a switching control signal suitable for realizing the read duty ratio τ in the switch 40 is the switch. 40 is output. Thus, one execution of this switching control program is completed.

  On the other hand, this time, assuming that the current i read in S11 is equal to or greater than the maximum value iMAX, the determination in S12 is YES, and the process proceeds to S14. In S14, it is determined whether or not the duty ratio τ read in S10 is equal to or greater than a regulation value τ0. If it is assumed that the duty ratio τ is not equal to or greater than the regulation value τ0 this time, the determination is NO and the process immediately proceeds to S13.

  If it is assumed that the duty ratio τ read in S10 is equal to or greater than the regulation value τ0, the determination in S14 is YES, and in S15, the duty ratio τ is decreased to the regulation value τ0, and then the process proceeds to S13. Transition.

  Therefore, in the present embodiment, when the charging current Ic of the capacitor 14 is neither excessive nor likely to be excessive, the duty ratio τ determined by the execution of the duty ratio determination program described in detail later is realized as it is. Thus, the switch 40 is controlled to be turned on and off. On the other hand, when the charging current Ic of the capacitor 14 is excessive or may be excessive, the determined duty ratio τ is decreased, and as a result, a smaller duty ratio τ is realized. Thus, the switch 40 is controlled to be turned on / off. This protects the switch 40, the diode 44, the capacitor 14 and the like from damage due to overcurrent.

  In the present embodiment, the on time Ton and the off time Toff of the switch 40 are directly controlled by the controller 60. However, as a method for the controller 60 to control the switch 40, other methods can be adopted as will be described later in another embodiment.

  FIG. 5 conceptually shows the above-described duty ratio determination program in a flowchart. Hereinafter, the determination process of the duty ratio τ in the controller 60 will be described with reference to FIG. 5. Prior to that, the basic principle will be described.

  When the entire system including the charging device 10, the solar battery 12, and the capacitor 14 is operatively in a steady state, the relationship represented by the following expression (1) is established between the solar battery 12 and the capacitor 14. .

Vs × I s = Vc × Ic

  In the solar cell 12, due to the presence of the capacitor 48, the temporal variation of the generated voltage Vs is small when observed within a time range comparable to the duty ratio control cycle of the switch 40. Since the temporal variation of the generated voltage Vs is small, the temporal variation of the generated power of the solar cell 12 is also small, and as a result, the temporal variation of the generated current Is of the solar cell 12 is also small.

  On the other hand, in the capacitor 14, the inductance of the coil 42 is normally designed to a value that is large enough to make the direct current component larger than the current change of the coil 42. However, since there is some current fluctuation in the coil 42, the current flowing through the coil 42 is a ripple current. On the other hand, the capacitance of the capacitor 14 has such a large value that the charging voltage Vc of the capacitor 14 does not change in a short time.

  The instantaneous value of the electric energy flowing into the capacitor 14 is represented by the product of the charging voltage Vc and the charging current Ic. As described above, the charging voltage Vc of the capacitor 14 is substantially constant when observed within a short time range. Therefore, the amount of electric energy flowing into the capacitor 14 is proportional to the current flowing into the capacitor 14, that is, the charging current Ic.

  Therefore, within a short time range, the determination of whether the electric energy flowing into the capacitor 14 is large or small is sufficient by determining whether the charging current Ic is large or small without considering the charging voltage Vc of the capacitor 14. Can be done accurately.

By the way, if the switching period of the switch 40 is represented by T, the on time is represented by Ton, and the off time is represented by Toff, the relationship represented by the following equation (2) is established among these three members.

  T = Ton + Toff

  Further, the duty ratio τ is expressed by the following equation (3).

  τ = Ton / T

  When the duty ratio τ of the switch 40 is determined, the relationship expressed by the following equation (4) is approximately established between the power generation voltage Vs of the solar cell 12 and the charging voltage Vc of the capacitor 14.

  (Vs−Vc) ÷ L × Ton≈Vc ÷ L × Toff = Vc ÷ L × (T-Ton)

  In this equation, “L” represents the inductance value of the coil 42. In this equation, the left side means an increase in the current of the coil 42 when the switch 40 is in the on state, while the right side means a decrease in the current of the coil 42 when the switch 40 is in the off state. From this equation, the following equations (5) to (7) are derived.

  Vs × Ton = Vc × T

  Ton / T = Vc / Vs

  Ton / T = Is / Ic

  Due to the characteristics of the capacitor 14 described above, the charging voltage Vc of the capacitor 14 does not change sensitively. On the other hand, the power generation voltage Vs of the solar cell 12 can change within the voltage range represented by the characteristic curve shown in FIG. Thus, since the charging voltage Vc of the capacitor 14 does not change within a short time range, when the duty ratio τ of the switch 40 is changed, the power generation voltage Vs of the solar cell 12 changes. Immediately after the change of the duty ratio τ, the charging device 10, the solar cell 12, and the capacitor 14 are in a transient state, but eventually the generated voltage Vs of the solar cell 12 converges to a value represented by the following equation (8). .

  Vs = Vc × T ÷ Ton

  When the power generation voltage Vs of the solar cell 12 changes in this way, the power generation current Is of the solar cell 12 also changes. The generated current Is after the change is determined according to the characteristic curve of the solar cell 12 and the illuminance of sunlight at that time. When the power generation voltage Vs and the power generation current Is of the solar battery 12 change in this way, the power generation of the solar battery 12 also changes. If the generated power of the solar cell 12 changes, the charging power of the capacitor 14 also changes, and the change is reflected only in the charging current Ic, not in the charging voltage Vc of the capacitor 14.

  FIG. 6 is a graph showing an example of a change indicated by the charging current Ic of the capacitor 14 when the duty ratio τ of the switch 40 is changed under the condition that the illuminance of sunlight is constant. As described above, because the generated power of the solar cell 12 has a maximum value with respect to the generated voltage Vs and the generated current Is, the charging power of the capacitor 14 also has a maximum value. On the other hand, in the capacitor 14, as described above, within a short time range, the charging voltage Vc does not change with time, whereas the charging current Ic is variable. Therefore, the phenomenon that the generated power of the solar cell 12 has a maximum value is manifested as a phenomenon in which the charging current Ic of the capacitor 14 has a maximum value.

  Therefore, if the duty ratio τ is continuously increased from the value corresponding to the point A in FIG. 6, the charging current Ic continues to decrease, whereas if the duty ratio τ is continuously decreased from the value corresponding to the point A, the charging current Ic increases. Then, after reaching the maximum value, it starts to decrease. On the other hand, if the duty ratio τ continues to decrease from the value corresponding to the point B in FIG. 6, the charging current Ic continues to decrease, whereas if the duty ratio τ continues to increase, the charging current Ic increases and reaches a maximum value. Later it starts to decrease. Therefore, the optimum value of the duty ratio τ, that is, the value corresponding to the maximum value of the charging current Ic can be determined in an exploratory manner by forcibly changing the duty ratio τ.

  Based on the knowledge described above, in the duty ratio determination program shown in FIG. 5, generally, in order to exploratively determine the optimum value of the duty ratio τ, the duty ratio τ is discretely determined under a predetermined condition. A forced change cycle that forcibly changes to is repeated in a time discrete manner. In each forced change cycle, depending on the response of the charging current Ic of the capacitor 14 to the forced change of the duty ratio τ, the forced change condition of the duty ratio τ in the next forced change cycle (whether it is increased or decreased) ) Is determined. These multiple forcible change cycles are repeated until the charging current Ic of the capacitor 14 is substantially maximized.

  Furthermore, in each forced change cycle, the previous detection value that is the charging current Ic detected by the detection circuit 50 before the current forced change is performed, and the detection circuit 50 after the current forced change is performed. Are compared with the current detection value, which is the charging current Ic detected by. Using the comparison result, the response to the current forced change of the duty ratio τ of the charging current Ic of the capacitor 14 is monitored. As will be described later, one forcible change cycle includes measurement of the charging current Ic, determination of the duty ratio τ, and a series of duty control of the switch 40 (which is continued for a time equal to a waiting time WT described later). Configured.

  Here, the duty ratio determination program will be specifically described with reference to FIG. 5. When this duty ratio determination program is executed by the CPU 72, first, in S100, the current value of the duty ratio τ is set to the initial value τ0. Is set and stored in the duty ratio memory 90. The switching control program takes in the latest value of the duty ratio τ determined by executing the duty ratio determination program through the duty ratio memory 90. The initial value τ0 is set to the duty ratio τ corresponding to the minimum value of the on-time actually realized in the switch 40 (for example, the minimum length of the pulse output to the switch 40 to switch the switch 40 to the on state). It is desirable to avoid overcurrent of the capacitor 14.

  Next, in S110, a certain waiting time WT is awaited. The length of the waiting time WT (for example, 10 ms) is until the operating state of the charging device 10, the solar battery 12, and the capacitor 14 is set to the transient state as a result of the change of the duty ratio τ of the switch 40. It is set so as not to be shorter than the time required for. The length of the waiting time WT is set in consideration of the time constant of the capacitor 14 and the coil 42 (for example, the time constant of the LC filter described above).

  If the waiting time WT is set to 10 ms and the switching period T of the switch 40 is set to 10 μsec, the period of one forced change cycle of the duty ratio τ becomes approximately 10 ms, during which the switching operation of the switch 40 is performed. (Minimum unit of on / off control) is performed 1,000 times. If a switching operation of such a length is performed, it is expected that the transient phenomenon of the entire circuit due to the change of the duty ratio τ converges well.

  Subsequently, in S120, the current value of the charging current Ic of the capacitor 14 is measured as the current i through the detection circuit 50. The measured current i is stored in the previous current memory 94.

  Thereafter, in S200 to S270, the duty ratio τ is forcibly increased by a fixed step width Δτ and the response appearing in the charging current Ic of the capacitor 14 is monitored to search for the maximum value of the charging current Ic.

  Specifically, in S200, the current value of the duty ratio τ is updated so as to increase by the step width Δτ, and the content is stored in the duty ratio memory 90. Thereafter, in S210, it is waited for the waiting time WT to elapse. Subsequently, in S220, the current value of the charging current Ic of the capacitor 14 is measured as the current i1 via the detection circuit 50. The measured current i1 is stored in the current memory 92 this time.

  Subsequently, in S230, it is determined whether or not the change amount of the current i1 (currently detected value) from the current i (previous detected value) (hereinafter simply referred to as “current change amount Δi”) is larger than the reference change amount Δi0. Is done. That is, it is determined whether or not the charging current Ic has increased with respect to the forced increase of the duty ratio τ. If it is assumed that the current change amount Δi is larger than the reference change amount Δi0 this time, the determination is YES, and in S240, the contents of the previous current memory 94 are changed from the current i to the current in preparation for the next execution of S200 to S250. Updated to i1. Thereafter, the process returns to S200.

  In contrast, if it is assumed that the current change amount Δi is equal to or smaller than the reference change amount Δi0, the determination in S230 is NO and the process proceeds to S250. In S250, it is determined whether or not the absolute value of the current change amount Δi is equal to or less than the reference change amount Δi0. In this S250, it is determined whether the charging current Ic is substantially maximized or lowered in combination with the presence of the preceding S230.

  Since the charging current Ic is substantially maximized this time, assuming that the absolute value of the current change amount Δi is equal to or smaller than the reference change amount Δi0, the determination in S250 is YES, and in S260, the same as S240. Thus, the contents of the previous current memory 94 are updated from the current i to the current i1 in preparation for the next execution of S200 to S250. Thereafter, in S270, in order to cancel the influence of the previous execution of S200 on the current value of the duty ratio τ, the current value of the duty ratio τ is updated so as to decrease by the step width Δτ, It is stored in the duty ratio memory 90. Thereafter, the process returns to S200.

  This time, since the charging current Ic is decreasing, assuming that the absolute value of the current change amount Δi is larger than the reference change amount Δi0, the determination in S250 is NO, and in S280, S300 is performed in the same manner as S240. In preparation for the next execution of S350, the content of the previous current memory 94 is updated from the current i to the current i1.

In S300 to S370, the duty ratio τ is forcibly decreased by the step width Δτ and the response appearing in the charging current Ic of the capacitor 14 is monitored to search for the maximum value of the charging current Ic.

  Specifically, in S300, the current value of the duty ratio τ is updated so as to decrease by the step width Δτ, and the content is stored in the duty ratio memory 90. Thereafter, in S310, it is waited for the waiting time WT to elapse. Subsequently, in S320, the current value of the charging current Ic of the capacitor 14 is measured as the current i1 via the detection circuit 50. The measured current i1 is stored in the current memory 92 this time.

  Subsequently, in S330, it is determined whether or not the current change amount Δi is larger than the reference change amount Δi0. That is, it is determined whether or not the charging current Ic has increased with respect to the forced decrease of the duty ratio τ. If it is assumed that the current change amount Δi is larger than the reference change amount Δi0 this time, the determination is YES, and in S340, the contents of the previous current memory 94 are changed from the current i to the current in preparation for the next execution of S300 to S350. Updated to i1. Thereafter, the process returns to S300.

  In contrast, if it is assumed that the current change amount Δi is equal to or smaller than the reference change amount Δi0, the determination in S330 is NO and the process proceeds to S350. In S350, it is determined whether or not the absolute value of the current change amount Δi is equal to or less than the reference change amount Δi0. In this S350, it is determined whether the charging current Ic is substantially maximized or lowered in combination with the presence of the preceding S330.

  Since the charging current Ic is substantially maximized this time, assuming that the absolute value of the current change amount Δi is equal to or less than the reference change amount Δi0, the determination in S350 is YES, and in S360, the same as S340 Thus, in preparation for the next execution of S300 to S350, the content of the previous current memory 94 is updated from the current i to the current i1. Thereafter, in S370, in order to cancel the influence of the previous execution of S300 on the current value of the duty ratio τ, the current value of the duty ratio τ is updated so as to increase by the step width Δτ. It is stored in the duty ratio memory 90. Thereafter, the process returns to S300.

  In this case, since the charging current Ic is decreasing, assuming that the absolute value of the current change amount Δi is larger than the reference change amount Δi0, the determination in S350 is NO, and in S380, similar to S280, S200 is performed. In preparation for the next execution of S250, the content of the previous current memory 94 is updated from the current i to the current i1.

  In addition, when the switch 40 is configured as a switch element that allows current to flow not only in the forward direction but also in the reverse direction, current flows from the capacitor 14 to the solar cell 12 and the capacitor 14 is discharged. In order to prevent this, it is desirable to add a backflow prevention element (for example, a diode) as will be described in a later embodiment.

  As is clear from the above description, in this embodiment, the controller 60 constitutes an example of the “controller” in the item (1), and the capacitor 48 constitutes an example of the “capacitor” in the item (2). -ing Further, each of the current current memory 92 and the previous current memory 94 in FIG. 3 constitutes an example of the “storage unit” in the item (3), and constitutes an example of the “digital memory” in the item (4). The portion of the computer 70 for executing the duty ratio determination program of FIG. 5 constitutes an example of the “determination unit” in the above item (3).

  Further, in the present embodiment, the portion for executing the duty ratio determination program of FIG. 5 in the computer 70 constitutes an example of the “determination unit” in each of the items (9) and (10), and FIG. S200 to S280 and S300 to S380 in FIG. 10 constitute an example of “each forced change cycle” in the above-mentioned item (9).

  Furthermore, in the present embodiment, the part for executing the switching control program of FIG. 4 in the computer 70 constitutes an example of the “current limiting part” in the item (18).

  Next, a second embodiment of the present invention will be described. However, this embodiment differs from the first embodiment only in the software configuration related to the duty ratio determination, and the other software configuration and hardware configuration are common, so only the different parts will be described in detail and shared. The part which performs is quoted using the same code | symbol or name, and the duplicate description is abbreviate | omitted.

  In the present embodiment, as in the first embodiment, a forcible change cycle for forcibly changing the duty ratio τ of the switch 40 in a discrete manner under a predetermined condition is repeated in a time discrete manner, thereby The optimum value of the duty ratio τ, that is, the value at which the charging current Ic of the capacitor 14 and thus the charging power is maximized, is determined in an exploratory manner.

  In the present embodiment, one forcible change cycle is the same as the first embodiment in the measurement of the charging current Ic, the determination of the duty ratio τ, and a series of duty control of the switch 40 (the waiting time WT described later is equal). Continuing time). Further, in order to determine the optimum value of the duty ratio τ, a plurality of forced change cycles are repeated, and one duty ratio determination process is completed by the plurality of forced change cycles.

  In the present embodiment, when the latest value of the optimum value of the duty ratio τ is determined, the determination and update of the duty ratio τ are stopped for a time longer than the period of one forced change cycle. That is, a hold period HP (for example, 1 min) in which the duty ratio τ is held is set between the end time of the current duty ratio determination process and the start time of the next duty ratio determination process.

  FIG. 7 conceptually shows a duty ratio determination program in the present embodiment in a flowchart. Hereinafter, this duty ratio determination program will be described with reference to FIG. 7, but the steps common to the duty ratio determination program shown in FIG. To do.

  When the duty ratio determination program shown in FIG. 7 is executed by the CPU 72, first, in S1100, the initial value τ0 is set to the current value of the duty ratio τ in the same manner as S100, and is stored in the duty ratio memory 90. The Next, in S1110, it is waited for the waiting time WT to elapse as in S110. Subsequently, in S1120, the current value of the charging current Ic of the capacitor 14 is measured as the current i through the detection circuit 50 in the same manner as in S120. The measured current i is stored in the previous current memory 94.

  After that, S1200 to S1250 monitors the response appearing in the charging current Ic of the capacitor 14 by forcibly increasing the duty ratio τ by the step width Δτ and monitoring the response appearing in the charging current Ic of the capacitor 14 in the same manner as S200 to S270. The maximum value is searched.

  Specifically, in S1200, as in S200, the current value of the duty ratio τ is updated so as to increase by the step width Δτ, and the content is stored in the duty ratio memory 90. After that, in S1210, it is waited for the waiting time WT to elapse as in S210. Subsequently, in S1220, the current value of the charging current Ic of the capacitor 14 is measured as the current i1 through the detection circuit 50 in the same manner as in S220. The measured current i1 is stored in the current memory 92 this time.

  Subsequently, in S1230, it is determined whether or not the current i1 (current detection value) is substantially equal to the current i (previous detection value). In this case, since the charging current Ic is a maximum value, it is assumed that the current i1 (current detection value) is substantially equal to the current i (previous detection value) despite the forced increase of the duty ratio τ. The determination is YES, and the process proceeds to S1300.

  In this S1300, it is waited for the above-mentioned hold period HP to elapse from the execution end time of S1210, S1220 or S1230. If the hold period HP has elapsed, the determination in S1300 is YES. Thereafter, the process returns to S1120, and the current i is measured and stored in the previous current memory 94. Subsequently, the flow proceeds to S1200.

  On the other hand, it is assumed that the current i1 (currently detected value) has changed from the current i (previously detected value) due to the forced increase of the duty ratio τ because the charging current Ic is not the maximum value this time. Then, the determination in S1230 is NO, and then the process proceeds to S1240. In S1240, it is determined whether or not the current i1 (current detection value) is larger than the current i (previous detection value).

  Since it is assumed that the current i1 (current detection value) has increased from the current i (previous detection value) due to the forced increase in the duty ratio τ because the charging current Ic is not a local maximum value this time, S1240 Is YES, and in S1250, the contents of the previous current memory 94 are updated from the current i to the current i1 in preparation for the next execution of S1200 to S1240. Thereafter, the process returns to S1200.

  In addition, since the charging current Ic is not a maximum value this time, it is assumed that the current i1 (currently detected value) has decreased from the current i (previously detected value) due to the forced increase of the duty ratio τ. , S1240 is NO.

  Thereafter, in S1400 to S1450, the duty ratio τ is forcibly decreased by the step width Δτ and the response of the charging current Ic of the capacitor 14 is monitored to search for the maximum value of the charging current Ic.

  Specifically, in S1400, the content of previous current memory 94 is updated from current i to current i1. Subsequently, in S1410, as in S300, the current value of the duty ratio τ is updated so as to decrease by the step width Δτ, and the content is stored in the duty ratio memory 90. Thereafter, in S1420, it is waited for the waiting time WT to elapse as in S310. Subsequently, in S1430, as in S320, the current value of the charging current Ic of the capacitor 14 is measured as the current i1 through the detection circuit 50. The measured current i1 is stored in the current memory 92 this time.

  Subsequently, in S1440, it is determined whether or not the current i1 (current detection value) is substantially equal to the current i (previous detection value). In this case, since the charging current Ic is a maximum value, it is assumed that the current i1 (current detection value) is substantially equal to the current i (previous detection value) despite the forced decrease in the duty ratio τ. The determination is YES, and the process proceeds to S1300.

  On the other hand, it is assumed that the current i1 (currently detected value) has changed from the current i (previously detected value) due to the forced increase of the duty ratio τ because the charging current Ic is not the maximum value this time. If it does, determination of S1440 will be NO and it will transfer to S1450 after that. In S1450, it is determined whether or not current i1 (current detection value) is larger than current i (previous detection value).

  Since it is assumed that the current i1 (currently detected value) has increased from the current i (previously detected value) due to the forced increase of the duty ratio τ because the charging current Ic is not the maximum value this time, S1450 Is YES, and then the process returns to S1400. In addition, since the charging current Ic is not the maximum value this time, it is assumed that the current i1 (currently detected value) has decreased from the current i (previously detected value) due to the forced decrease of the duty ratio τ. , S1450 is NO, and then returns to S1200 via S1250.

  Next, a third embodiment of the present invention will be described. However, this embodiment differs from the first embodiment only in the hardware configuration in which the controller 60 controls the switch 40, and the other hardware configuration and software configuration are common, so only the different parts are detailed. Explanation will be given, and common parts will be referred to using the same reference numerals or names, and duplicate explanation will be omitted.

  As shown in FIG. 8, the charging device 120 according to the present embodiment includes a switch control circuit 122 in order to enable the controller 60 to control the switch 40. The switch control circuit 122 converts a triangular wave source 124 as an oscillation circuit that generates a triangular wave signal and a digital signal output from the controller 60 that represents the target duty ratio of the switch 40 into an analog signal. Converter 126. The DA converter 126 converts the digital signal output from the controller 60 into an analog signal that represents a threshold level.

  The switch control circuit 122 further includes a comparator 128 connected to the switch 40, the triangular wave source 124, and the DA converter 126. The comparator 128 functions as an example of a binarization circuit. Specifically, the comparator 128 generates a triangular wave signal generated by the triangular wave source 124 at a threshold level represented by an analog signal output from the DA converter 126. By binarizing, an on signal and an off signal for turning off the switch 40 are selectively generated and supplied to the switch 40.

In the switch control circuit 122, the comparator 128 converts a triangular wave signal having a constant frequency into a rectangular wave signal converted into a PMW so that the pulse width increases in proportion to the threshold level. Therefore, in the switch control circuit 122, the duty ratio of the switch 40 can be changed by changing the output analog signal of the DA converter 126 .

  According to the present embodiment, in order to control the switch 40 by the controller 60, a clock oscillator and a counter of a wired logic circuit that counts the number of clock pulse signals output from the clock oscillator are external to the controller 60. Thus, there is no need to provide a flip-flop for controlling the on / off state of the switch 40 in accordance with the time-up of the counter.

  As shown in FIG. 8, in the present embodiment, a filter 130 is connected between the input side of the amplifier 54 and the current detection resistor 52 in the first embodiment. This filter 130 is provided to remove a ripple component generated in the charging current of the capacitor 14 due to the on / off operation of the switch 40. In the present embodiment, a backflow preventing diode 132 is further connected to a portion of the positive line 20 between the connection point of the capacitor 48 and the external terminal 24.

  Next, a fourth embodiment of the present invention will be described. However, this embodiment is different from the first embodiment only in that the operation basically realized by the computer 70 of the controller 60 is realized by a wired logic circuit, and is common in other points. Therefore, in the present embodiment, only elements different from those of the first embodiment will be described in detail, and common elements will be referred to using the same reference numerals or names, and redundant description will be omitted.

  As shown in FIG. 9, the charging device 150 according to the present embodiment is used by being connected to the solar cell 12 and the capacitor 14 in the same manner as the charging device 10 according to the first embodiment. Similarly to charging device 10, charging device 150 includes a converter 32 having a switch 40, a coil 42, and a diode 44, a capacitor 48, a detection circuit 50 having a current detection resistor 52 and an amplifier 54. It is configured.

  As illustrated in FIG. 9, the charging device 150 includes a storage unit 160 connected to the detection circuit 50, a determination unit 162 connected to the storage unit 160, and a switch connected to the determination unit 162 and the switch 40. And a control circuit 164. The charging device 150 further includes a timing unit 166 connected to the storage unit 160, the determination unit 162, and the switch control circuit 164. In the present embodiment, the storage unit 160, the determination unit 162, the switch control circuit 164, and the timing unit 166 constitute a controller 168.

  The storage unit 160 stores the charging current of the capacitor 14 detected by the detection circuit 50 as an analog signal (a signal in which the value of the charging current is converted into a voltage by the current detection resistor 52 and the amplifier 54). 50, two sample and hold circuits 170 and 172 connected in common, and a flip-flop 174 as a selection circuit for selectively enabling the sample and hold circuits 170 and 172 are provided. The flip-flop 174 operates so as to alternately output an enable signal to the two sample hold circuits 170 and 172 every time the sampling timing T1 arrives. As a result, the two sample and hold circuits 170 and 172 operate so that the current detection value and the previous detection value of the charging current are alternately sampled from the detection circuit 50 and temporarily stored.

  Specifically, first, one of the sample and hold circuits is validated, and the validated sample and hold circuit is caused to perform a sampling operation for sampling the detection value of the charging current from the detection circuit 50, and the detection value is temporarily stored. Memorize. Thereafter, when the sampling timing T1 arrives, the other sample-and-hold circuit is validated, and the validated sample-and-hold circuit performs a sampling operation to temporarily store the detected value of the charging current. When the current sampling operation is completed, one sample-and-hold circuit stores the previous detection value of the charging current, while the other sample-and-hold circuit stores the current detection value of the charging current. become.

  When the next sampling timing T1 arrives, this time, a sample hold circuit different from the sample hold circuit enabled at the previous sampling timing T1 is enabled, and the charging current of the sample hold circuit is enabled in the enabled sample hold circuit. The detected value is sampled and stored. At the current sampling timing T1, the charging current stored in the sample hold circuit validated at the previous sampling timing T1 means the previous detected value of the charging current.

  As is clear from the above description, a flip-flop 174 is provided to selectively enable the two sample hold circuits 170 and 172 each time the sampling timing T1 arrives.

  As shown in FIG. 9, the switch control circuit 164 includes a flip-flop 180 configured as an RS flip-flop. The flip-flop 180 operates to turn on the switch 40 in the set state and turn off the switch 40 in the reset state.

  The switch control circuit 164 further outputs a clock oscillator 182 that outputs a clock pulse (for example, 25 MHz, 0.04 μs) of a basic clock that controls the entire operation of the controller 168, and the number of clock pulses output from the clock oscillator 182. And a counter 184 for counting. The counter 184 supplies the flip-flop 180 with a set signal S for switching the flip-flop 180 from the reset state to the set state every time up (its count value reaches the maximum value).

  In an example of a specific specification setting, in order to set the switching frequency of the switch 40 to 100 kHz, the count value of the counter 184 is composed of binary 8 bits, and an output pulse signal (time-up is output from the counter 184). It is conceivable to set the output frequency of the signal to be 100 kHz and the output interval (cycle time) to 10 μs.

  As shown in FIG. 9, the determination unit 162 includes a determination logic circuit 190 that performs a logical operation for determining the target duty ratio of the switch 40, that is, the length of the on-time, and the previous determination determined by the determination logic circuit 190. And a previous determination memory 192 for storing the result. The functions and operations of the determination logic circuit 190 and the previous determination memory 192 will be described in detail later. The determination logic circuit 190 is designed to perform a predetermined logical operation every time the determination logic timing T2 arrives. .

  As shown in FIG. 9, the switch control circuit 164 further includes a reversible counter 200 and a coincidence detection logic circuit 202 provided between the counter 200 and the counter 184 described above.

  The counter 200 is provided for storing a target count value corresponding to the target duty ratio determined by the determination unit 162. This counter 200 performs a designated one of the count-up operation and the count-down operation every time the duty ratio change timing T3 arrives. On the other hand, the coincidence detection logic circuit 202 is provided for detecting that the target count value stored in the counter 200 and the count value of the counter 184 coincide with each other.

  When the count value of the counter 200 matches the target count value of the counter 184, the match detection logic circuit 202 supplies the flip-flop 180 with a reset signal R for switching the flip-flop 180 from the set state to the reset state. As a result, the switch 40 is switched from the on state to the off state, whereby the actual on time of the switch 40 is controlled to achieve the target duty ratio.

  As shown in FIG. 9, the timing unit 166 includes a counter 210 that counts up one by one in response to an output pulse signal (a signal indicating time-up) from the counter 184. When the time is up, the counter 210 outputs an output pulse signal indicating that the sampling timing T1 has arrived to the flip-flop 174.

  In an example of specific specification setting, in order to set the period of the above-described sampling timing T1 to 10 ms, the count value of the counter 210 is composed of binary 10 bits, and the output interval of the output pulse signal is set to 10 ms. It is possible.

  As shown in FIG. 9, the timing unit 166 further includes a timing generator 212. The timing generator 212 measures the determination logic timing T2 and the duty ratio change timing T3 described above by counting the number of output pulse signals output from the counter 210.

  In the present embodiment, the length of the period of the sampling timing T1 is set in consideration of the time required for the transient phenomenon of the charging device 150 accompanying the change of the duty ratio of the switch 40 to converge. Further, the length of the cycle of the determination logic timing T2 is set in consideration of the time required for one operation completion of the sample hold circuits 170 and 172. Also, the duty ratio change timing T3 is set in consideration of the time required for completing one logic determination of the determination logic circuit 190. In FIG. 10, a sequence in which these three timings T1, T2, and T3 are established is represented by a timing chart.

  As shown in FIG. 9, the determination unit 162 further includes two voltage setting circuits 220 and 222 connected to the output terminals of the two sample and hold circuits 170 and 172, respectively, and the two voltage setting circuits 220. , 222 are connected to two comparators 230, 232, respectively.

  Each voltage setting circuit 220, 222 is configured as a series circuit of two voltage dividing resistors R11, R12, R21, R22, and is stored in a corresponding one of the two sample hold circuits 170, 172. The voltage of the signal representing the charging current is divided at a predetermined ratio and output to the corresponding one of the two comparators 230 and 232.

  Specifically, if the output voltages of the two sample and hold circuits 170 and 172 are represented by Vh1 and Vh2, respectively, the comparator 230 compares Vh1 and Vh2 × R22 / (R21 + R22) with each other. 232 compares Vh2 and Vh1 × R12 / (R11 + R12) with each other. Comparator 230 is used to detect that Vh2 is higher than Vh1 by a certain voltage or more, while comparator 232 is used to detect that Vh1 is higher than Vh2 by a certain voltage or more.

  Here, the logical operation of the determination logic circuit 190 will be described.

  The input signal of the determination logic circuit 190 includes an output signal of the flip-flop 174, output signals from the two comparators 230 and 232, and an output signal from the previous determination memory 192. The output signal of the flip-flop 174 is used to specify which of the two sample and hold circuits 170 and 172 is valid this time. As the output signals from the two comparators 230 and 232, only the output signals from the comparators corresponding to the currently validated one of the two sample and hold circuits 170 and 172 are used. The output signal from the previous determination memory 192 is used to specify whether the counting direction of the counter 200 is counting up or counting down.

  On the other hand, in the output signal of the determination logic circuit 190, (a) the count value of the counter 200 (corresponding to the target on time of the switch 40) is set to 1 so that the on time of the switch 40 is increased by the first change amount. A small count-up signal for counting up, and (b) a large count for counting up the count value of the counter 200 by 2 so that the ON time of the switch 40 increases by a second change amount greater than the first change amount. An up signal, (c) a small countdown signal for counting down the count value of the counter 200 by 1 so that the ON time of the switch 40 is decreased by the first change amount, and (d) a second ON time of the switch 40. (E) a large countdown signal for counting down the count value of the counter 200 by 2 so as to decrease by the amount of change; There is a 0 signal to the count value of the counter 200 without adding changes.

  In FIG. 11, the operation of the determination logic circuit 190 is divided into cases and represented in a table. According to this table, for example, the previous determination is a count-up of the counter 200 (regardless of whether the previous increment of the count value was 1 or 2), and the two sample hold circuits 170 and 172 When 170 of these is valid this time, the large countdown signal D2 is sent to the counter 200 on condition that the comparator 230 determines that Vh2 (previous detection value) is larger than Vh1 (current detection value). On the other hand, a small count-up signal U1 is output to the counter 200 on condition that the comparator 232 determines that Vh1 (current detection value) is greater than Vh2 (previous detection value).

  In addition, the previous determination is a countdown of the counter 200 (regardless of whether the previous decrease amount of the count value was 1 or 2), and 172 of the two sample hold circuits 170 and 172 is valid this time. If it is determined that the comparator 230 outputs a small countdown signal D1 to the counter 200 on the condition that Vh2 (current detection value) is determined to be larger than Vh1 (previous detection value), A large count-up signal U2 is output to the counter 200 on the condition that it is determined at 232 that Vh1 (previous detection value) is greater than Vh2 (current detection value).

  The operation of the decision logic circuit 190 has been described above by taking two cases as an example. In the remaining cases, the description in text is omitted by citing the table of FIG.

  In addition, in this embodiment, when the target duty ratio determined by the determination logic circuit 190 does not change for a certain time (for example, 10 seconds), the target duty ratio is forcibly changed by a certain amount in a certain direction. If a logic circuit is added, it becomes easy to reliably follow the actual value of the charging current of the capacitor 14 by its maximum value.

  Next, a fifth embodiment of the present invention will be described. However, this embodiment differs from the first embodiment only in that the same operation as the operation realized by the computer 70 is realized by a hybrid system combining a wired logic circuit and a computer. Is common. Therefore, in the present embodiment, only elements different from those of the first embodiment will be described in detail, and common elements will be referred to using the same reference numerals or names, and redundant description will be omitted.

  As shown in FIG. 12, the charging device 250 according to the present embodiment is used by being connected to the solar cell 12 and the capacitor 14 in the same manner as the charging device 10 according to the first embodiment. Similar to the charging device 10, the charging device 150 includes a converter (step-down switching regulator) 32 having a switch (semiconductor switch) 40, a coil 42, and a diode 44, a capacitor 48, a current detection resistor 52, and an amplifier 54. Is included.

  The detection circuit 50 removes a ripple component generated in the charging current of the capacitor 14 due to the on / off operation of the switch 40, thereby ensuring the subsequent processing using the detected value of the charging current. A countermeasure circuit 252 is provided. The ripple countermeasure circuit 252 may be, for example, a method using an average current (such as a low-pass filter or an integration circuit), a method using a peak current (such as a rectifier circuit using a diode), or a method using a current of a specific phase (the switch 40 is Sampling hold or synchronous detection at the timing of turning off) is possible.

  As shown in FIG. 12, the charging device 250 includes a sample hold circuit 254 connected to the detection circuit 50 and a determination unit 256 connected to the sample hold circuit 254. The determination unit 256 is connected to a comparator 258 connected to the sample hold circuit 254 and the detection circuit 50 at two input terminals, an output terminal of the comparator 258, and a control terminal of the sample hold circuit 254, respectively. Controller 260.

  The comparator 258 receives a voltage signal representing the current detection value of the charging current by the detection circuit 50 and a voltage signal representing the previous detection value of the charging current and stored in the sample hold circuit 254. . The comparator 258 is provided for comparing the magnitudes of these voltage signals.

  As shown in FIG. 13, the controller 260 is mainly configured by a computer 262. The computer 262 includes a CPU 72, a ROM 74, a RAM 76, and a bus 78, as in the first embodiment shown in FIG. It is comprised so that it may contain. The controller 260 further includes an I / O interface 80 as in the first embodiment shown in FIG. 3, and is connected to the sample hold circuit 254 and the comparator 258 via the I / O interface 80. Yes.

  The ROM 74 stores a duty ratio control program conceptually represented in the flowchart of FIG. Further, as shown in FIG. 13, the RAM 76 is provided with a determination result memory 270 and a comparison result memory 272.

  As shown in FIG. 12, the charging device 250 includes a determination unit 256 and a switch control circuit 280 connected to the switch 40. The switch control circuit 280 includes a triangular wave source 282 as an oscillation circuit, and a comparator 284 as a binarization circuit that binarizes the triangular wave signal generated by the triangular wave source 282 according to a threshold level. By the binarization processing, a rectangular wave having a high level and a low level is output from the comparator 284 to the switch 40, and the duty ratio of the rectangular wave changes according to the threshold level of the comparator 284.

  As shown in FIG. 12, the switch control circuit 280 includes a threshold level signal generation circuit 290 that outputs a threshold level signal to the comparator 284. The threshold level signal generation circuit 290 generates a threshold level signal, a capacitor 292 as an element for holding a variable voltage for a predetermined time, and an on-state voltage for boosting the voltage accumulated in the capacitor 292. And a step-down switch (eg, semiconductor switch) 296 that is turned on to step down. A signal representing the voltage of the capacitor 292 is supplied to the comparator 284 as a threshold level signal.

  The switch control circuit 280 further includes two timing circuits 298 and 300 connected to the step-up switch 294 and the step-down switch 296, respectively. These two timing circuits 298 and 300 are connected to a computer 262 via an I / O interface 80 as shown in FIG.

  In the threshold level signal generation circuit 290, when the booster switch 294 is turned on and the capacitor 292 is conducted to the positive power supply terminal via the resistor R1, the voltage of the capacitor 292 is set according to the length of the on-time of the booster switch 294. Is raised. On the other hand, when the step-down switch 296 is turned on and the capacitor 292 is conducted to the negative power supply terminal through the resistor R2, the voltage of the capacitor 292 is stepped down according to the length of the on-time of the step-down switch 296.

  The step-up switch 294 and the step-down switch 296 are connected to the controller 260 via two timing circuits 298 and 300, respectively. Each timing circuit 298, 300 is configured as a monostable vibrator, for example, and when a trigger signal is input from the controller 260, a signal for turning on the corresponding one of the boost switch 294 and the buck switch 296 for a predetermined time. Continue to output.

  As shown in FIG. 12, the switch control circuit 280 further includes a buffer amplifier 302 connected to the capacitor 292 and the input terminal of the comparator 284. The buffer amplifier 302 is configured as an amplifier having high input impedance and low input leakage current. The buffer amplifier 302 is provided in order to prevent voltage drift from occurring in the capacitor 292 due to leakage current.

  In the initial state of the charging device 250 (immediately after the power is turned on), an initial circuit state in which the switch 40 is off and the voltage of the capacitor 292 is 0 is realized before the computer 262 is activated.

  When the computer 262 is finally activated and the duty ratio control program shown in FIG. 14 is executed, first, in S2000, it is waited for a predetermined time to elapse. Next, in S2010, the charging device 250 is released from the circuit reset state. Subsequently, in S2020, a sampling command is sent to the control terminal of the sample hold circuit 254. Thereafter, in S2030, it is awaited that a predetermined time longer than the acquisition time of the sample hall circuit 254 elapses.

  Subsequently, in S2040, a signal for forcibly changing the duty ratio of the switch 40 from the current value to a predetermined amount (for example, an increasing direction) corresponds to one of the two timing circuits 298.300. Sent to things. As a result, the corresponding one of the step-up switch 294 and the step-down switch 296 is turned on for a predetermined time, and accordingly, the voltage of the capacitor 292, that is, the threshold voltage of the comparator 284, and thus the duty ratio of the switch 40 is changed from the current value. A predetermined amount is forcibly changed in a predetermined direction (for example, an increasing direction). Thereafter, in S2050, it is awaited that the operating state of charging device 250 is settled.

  Thereafter, in S2060, the comparison result of the comparator 258 is input. Subsequently, in S2070, the input comparison result is stored in the comparison result memory 272. Thereafter, in S2080, the previous determination result is read from the determination result memory 270. The previous determination result indicates whether the step-up switch 294 was turned on or the step-down switch 296 was turned on last time.

  Subsequently, in S2090, based on the comparison result and the previous determination result, it is determined which of the step-up switch 294 and the step-down switch 296 should be turned on this time.

  Specifically, as shown in the table in FIG. 15, the logical determination by the computer 262 is, for example, the previous determination result is that the boost switch 294 is turned on, and the current comparison is performed. If the result is that the current value of the detected value of the charging current is larger than the previous value, it is determined that the boost switch 294 should be turned on again this time. On the other hand, if the previous determination result is to turn on the boost switch 294 and the current comparison result is that the current value of the detected value of the charging current is smaller than the previous value, It is determined that 296 should be turned off. With respect to the logical determination in other cases, the description in text is omitted by citing the table of FIG.

  Thereafter, in S2100 in FIG. 14, the content of the determination result memory 270 is updated from the previous determination result to the current determination result. Subsequently, in S2110, a sampling command is sent to the control terminal of the sample hold circuit 254. Thereafter, in S2120, it is awaited that a predetermined time having a length equal to or longer than the acquisition time of the sample hall circuit 254 elapses.

  Subsequently, in S2130, according to the current determination result, a signal for changing the duty ratio of the switch 40 from the current value to a predetermined amount in a predetermined direction (for example, an increasing direction) is out of the two timing circuits 298 and 300. Sent to the appropriate one. As a result, the duty ratio of the switch 40 is changed so as to approach the maximum value. Thereafter, in S2140, the operation of charging device 250 waits for settling. Subsequently, the process returns to S2060, and the execution of S2060 to S2140 is periodically repeated.

  In an example of specific specification setting, the execution cycle is on the order of 10 ms, the respective waiting times in S2030 and S2120 are 100 μs, and the waiting times in S2050 and S2140 are 10 ms.

  Next, a sixth embodiment of the present invention will be described. However, this embodiment is different from the fifth embodiment only in that the same operation as that realized by the computer 262 is realized by a wired logic circuit, and is common in other points. Therefore, in the present embodiment, only elements different from those of the first embodiment will be described in detail, and common elements will be referred to using the same reference numerals or names, and redundant description will be omitted.

  As shown in FIG. 16, the charging device 330 according to the present embodiment includes a logic circuit 332 instead of the controller 260 in the fifth embodiment. The logic circuit 332 includes a clock oscillator (for example, oscillation period: 10 μs) 334 that generates clock pulses, and a counter 336 that counts the number of clock pulses output from the clock oscillator 334. The counter 336 is configured as a flip-flop having a predetermined number of bits.

  The logic circuit 332 further includes a timing circuit 338 that decodes the output of the counter 336 by an AND logic element and generates three periodic timing pulses t0, t1, and t2, respectively. The logic circuit 332 further includes two flip-flops 340 and 342, an XOR logic element 350, and two AND logic elements 360 and 362.

  The flip-flop 340 is a shift type, and stores the result of the operation of the XOR logic element, that is, information indicating which of the step-up switch 294 and the step-down switch 296 is turned on next time, in response to the timing pulse t0. . The flip-flop 340 holds the stored contents until the next timing pulse t0 arrives.

  The flip-flop 342 is also a shift type, and stores the stored contents of the flip-flop 340 in response to the timing pulse t1. The flip-flop 342 also holds the stored contents until the next timing pulse t1 arrives.

  If the output of the comparator 250 and the output of the flip-flop 342 are respectively input to the XOR logic element 350 and the two inputs have the same logic value, the XOR logic element 350 outputs a logic value “0”, but may have different logic values. For example, the logic value “1” is output. The output of the flip-flop 342 represents the previous determination result in FIG. 15, whereas the output of the comparator 250 represents the current comparison result in FIG. Therefore, this XOR logic element 350 performs the same logical operation as the logical operation shown in the table of FIG.

  Both of the two AND logic elements 360 and 362 operate so as to output a logical value “1” when both inputs have a logical value “1”. Since the AND logic element 360 inputs the output of the Philip flop 342, when the logical value of the output of the flip-flop 342 is “1”, the AND logic element 360 outputs an output pulse to the timing circuit 298 when the timing pulse t2 arrives. . On the other hand, since the AND logic element 362 inputs the NOT of the output of the flip-flop 342, when the logical value of the output of the flip-flop 342 is “0”, the timing circuit 300 is reached when the timing pulse t2 arrives. Output pulse to.

  In FIG. 17, the generation timings of the three timing pulses t0, t1, and t2 are shown in a timing chart. The period D of the timing pulse t0 is, for example, 10 ms, the time interval d1 between the timing pulses t0 and t1 is, for example, 10 μs, and the time interval d2 between the timing pulses t1 and t2 is, for example, 100 μs.

  The operation of the logic circuit 332 will be described. When the transient phenomenon of the charging device 330 caused by the on / off operation of the switch 40 has converged, the timing pulse t0 rises, and in response thereto, the logical operation result of the XOR logic element 350 is flip-flops. 340. Next, when the timing pulse t1 rises, a sampling command is sent to the sample hold circuit 254, and at the same time, the stored contents of the flip-flop 340 are stored in the flip-flop 342.

Thereafter, when the timing pulse t2 rises, an output pulse is output from the corresponding AND logic elements 360 and 362 to one of the two timing circuits 298 and 300 according to the stored contents of the flip-flop 342. As a result, the voltage is stepped up or down of the capacitor 292 shown in FIG. 12, du chromatography duty ratio of the switch 40 is changed accordingly. When the transient phenomenon of the charging device 330 caused by this change converges, the next timing pulse t0 rises and the above-described operation is repeated.

  As described above, some of the embodiments of the present invention have been described in detail with reference to the drawings. However, these are exemplifications, and are based on the knowledge of those skilled in the art including the aspects described in the section of [Disclosure of the Invention]. The present invention can be implemented in other forms with various modifications and improvements.

It is an electric circuit diagram which shows the charging device according to 1st Embodiment of this invention. It is a graph showing the characteristic of the solar cell in FIG. FIG. 2 is a block diagram conceptually showing a controller in FIG. 1. 4 is a flowchart conceptually showing a switching control program in FIG. 3. 4 is a flowchart conceptually showing a duty ratio control program in FIG. 3. 6 is a graph for explaining the characteristics of the duty ratio control program shown in FIG. 5. It is a flowchart which represents notionally the duty ratio control program performed by the computer of the charging device according to 2nd Embodiment of this invention. It is an electric circuit diagram which shows the charging device according to 3rd Embodiment of this invention. It is an electric circuit diagram which shows the charging device according to 4th Embodiment of this invention. 10 is a timing chart for explaining the operation of the timing unit in FIG. 9. 10 is a table for explaining a logical operation of a determination logic circuit in FIG. 9. It is an electric circuit diagram which shows the charging device according to 5th Embodiment of this invention. FIG. 13 is a block diagram conceptually showing the controller in FIG. 12. 14 is a flowchart conceptually showing a duty ratio control program in FIG. 13. 15 is a table for explaining the logic determination of S2090 in FIG. It is an electric circuit diagram which shows the controller in the charging device according to 6th Embodiment of this invention with a peripheral component. FIG. 17 is a timing chart for explaining the operation of the timing circuit in FIG. 16. FIG.

Claims (8)

For generated power to charge the electric double layer capacitor by the solar cell having a local maximum point with respect to the power generation voltage and the power generation current, a charging apparatus used by being connected to, and the solar cell and an electric double layer capacitor,
A DC-DC converter having at least a switch and converting electric power supplied from the solar cell to the electric double layer capacitor according to a variable duty ratio of the switch;
A detection circuit for detecting a charging current of the electric double layer capacitor;
A controller that repeatedly executes a duty ratio control cycle configured by a plurality of switching operations that share the duty ratio with respect to the switch, wherein the duty ratio is set for each duty ratio control cycle. Determining the variable and controlling the switch so that the determined duty ratio is realized,
The controller refers to the charging current detected by the detection circuit, but does not refer to the charging voltage of the electric double layer capacitor, and the charging current of the electric double layer capacitor is substantially maximized. Including a duty ratio determination unit that performs each process of exploringly determining the optimum value of the duty ratio as a duty ratio determination process ;
The duty ratio determination unit performs a forced change cycle for forcibly changing the duty ratio discretely by a step width in each duty ratio determination process, and changes the duty ratio during execution of each forced change cycle. In each forced change cycle, the charge current is substantially maximized in response to the response of the charge current to the forced change of the duty ratio in the previous forced change cycle. Determine the duty ratio as follows:
Its duty ratio determining section, the force change cycle, are performed by the same cycle as the duty ratio control cycle,
The duty ratio determining unit ends the duty ratio determining process each time when the charging current is substantially maximized . The controller includes a switch control unit that controls the switch in each duty ratio control cycle,
The switch control unit monitors the current value of the charging current in each duty ratio control cycle,
(A) If the current value of the charging current is not equal to or greater than the maximum value, the switch is controlled so that the duty ratio determined by the duty ratio determination unit is realized,
(B) If the current value of the charging current is greater than or equal to the maximum value, and if the duty ratio is not greater than or equal to a regulation value, the switch is controlled to achieve the duty ratio, and the duty ratio is 2. The charging device according to claim 1 , wherein the duty ratio is decreased if the control value is equal to or greater than the regulation value, and the switch is controlled so that the reduced duty ratio is realized . The duty ratio determination unit performs the current forced change and the previous detection value that is the charging current detected by the detection circuit before the current forced change is performed in each forced change cycle. 3. The charging device according to claim 1, wherein a current detection value that is a charging current detected by the detection circuit is compared with each other and a response of the charging current is monitored using the comparison result. The duty ratio determining unit discretely monitors the charging current through the detection circuit, and waits for a waiting time having a predetermined length to elapse after a certain number of times of monitoring the charging current. The charging device according to any one of claims 1 to 3 , wherein next charging current monitoring is performed. The charging device according to claim 4 , wherein the waiting time is substantially equal to a duration per time of the duty ratio control cycle. After the controller determines the latest value of the optimum value of the duty ratio, the controller maintains the duty ratio until a predetermined time elapses that is longer than the period of the one forced change cycle. The charging device according to any one of claims 1 to 5 , comprising a holding portion. The duty ratio determining unit detects the charging current via the detection circuit at the end of execution of each forced change cycle, and detects the charge current detected at the end of execution of the previous forced change cycle. A previous detection value and a current detection value that is a charging current detected at the end of execution of the current forced change cycle are compared with each other, and the comparison result is used to determine the duty ratio in the current forced change cycle. Monitoring the response of the charging current to a forced change;
  The duty ratio determination unit, in each of a plurality of forced change cycles constituting the duty ratio determination process of each time,
(A) When the response of the charging current in the current forced change cycle has the same direction as the direction of the forced change of the duty ratio in the current forced change cycle, the response in the next forced change cycle Perform the forced change of the duty ratio in the same direction as this forced change cycle,
(B) When the response of the charging current in the current forced change cycle is substantially zero, the current duty ratio determination process is terminated assuming that the current value of the charging current is substantially a maximum value. And
(C) When the response of the charging current in the current forced change cycle has a direction opposite to the direction of the forced change of the duty ratio in the current forced change cycle, the next forced change cycle 7. The charging device according to claim 1, wherein the forced change of the duty ratio is performed in a direction opposite to the current forced change cycle.   The electric double layer capacitor accumulates charge and changes its charge voltage according to the amount of accumulated charge.
  The charging device according to claim 1, further comprising a capacitor having a capacitance smaller than that of the electric double layer capacitor and connected in parallel to the solar cell. .

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