JP3741929B2 - Control device for gaming machine - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a control device in a gaming machine, and more particularly to a device provided with a CPU for controlling various devices in the gaming machine. More specifically, the present invention relates to a method of repeatedly starting a game machine program using a CPU or a game machine control system.
[0002]
[Prior art]
There are various types, such as slot games, that are classified as so-called gaming machines, including pachinko machines. In recent years, it has become common for these gaming machines to use a CPU to control game contents, image display including image generation, sound reproduction including sound generation, or a mechanical mechanism. In addition, game content and image display are also changing year by year using advanced technology.
[0003]
FIG. 1 shows an example of a front view of a gaming machine, in this case, a pachinko machine. The mechanical structure of the pachinko machine can be the same as that of a conventional example as disclosed in, for example, Japanese Patent Laid-Open No. 11-319252.
[0004]
In FIG. 1, reference numeral 100 denotes a special symbol display device that performs so-called “variable display” of an image pattern based on a winning in a special symbol starting winning opening provided on the game board surface. 101, when three sets of stop symbol displays (special identification information) displayed on the special symbol display device become a predetermined combination of specific numbers or symbols (for example, big role identification information), that is, a special prize state This is a variable winning device in which the winning opening is opened when it becomes. Reference numeral 102 denotes a specific area. When a game ball wins during the special prize state, the special prize state is continued.
[0005]
103 is a normal symbol display device. When a game ball wins a specific winning opening, different numbers or symbols are displayed while fluctuating.
[0006]
FIG. 2 shows the circuit configuration of the control system of the gaming machine. In addition, the same code | symbol is attached | subjected to the part similar to FIG. 1, and detailed description is abbreviate | omitted. The thick line portion is included in the main control unit.
[0007]
In FIG. 2, reference numeral 200 denotes a CPU that functions as a processing device of the main control unit of the gaming machine. The CPU 200 uses a CPU chip that incorporates a ROM 201 and a RAM 202, but the ROM and RAM may be connected by a bus.
[0008]
The ROM 201 stores a program for controlling the gaming machine. In this program, a random number is usually generated to determine the stop symbol after the variable display based on the winning at the special symbol starting winning opening, that is, the stop symbol that is stopped and displayed on the special symbol display device is a specific combination. The program which performs the control which instruct | indicates a display mode with respect to a special symbol display apparatus according to the winning to a special symbol starting winning opening is set. The ROM 201 further stores various parameter values for controlling the gaming machine. The RAM 202 stores input / output data for the CPU 200, data for arithmetic processing, and the like.
[0009]
Reference numeral 203 denotes an input port which inputs signals from the special symbol start switch 22, the normal symbol operation switch 23, the big prize opening switch 34, and other switches (not shown), and transmits them to the CPU 200.
[0010]
Reference numeral 213 denotes an output port, which transmits instructions from the main control unit to devices such as the special symbol display device 100, the normal symbol display device 103, the variable winning device 209, various lamp display devices 211, and the sound effect generator 212. .
[0011]
A synchronization signal generator 220 receives a clock signal from the clock generator, outputs a signal having a period of about 2 ms to 4 ms, and includes a power-on reset signal from the power supply circuit. The IC including the CPU 200 is reset. The CPU 200 of the main control unit receives this hardware reset signal and performs a periodic operation. A signal input from the power supply circuit to the input port 203 is a signal that tells the CPU that the power is on in response to the above-described hardware reset signal.
[0012]
The special symbol display device 100 that receives a signal from the output port 213 is a device that drives an LCD 305 (shown as 100 in FIG. 1) as shown in FIG. 3, and a signal from the main control unit 200 as a gaming machine. The apparatus has a CPU 301 and an image processing LSI 304 that operate in response to the above.
[0013]
As described above, the control system by the CPU of the gaming machine is completely separated from the input and output as the control system of the gaming machine, and the main control unit 200 is located between the input and the output. ing.
[0014]
The sound effect generator 212 that receives a signal from the output port 213 also has a CPU inside, as in the special symbol display device 100 described above.
[0015]
Under the control of the CPU 200, when the number or symbol of the stop special symbol displayed by the special symbol display device 100 displays a combination of specific numbers, if it is a special prize (big hit), the CPU 200 passes through the output port 213. Then, the variable winning device 209 is controlled to open the winning port of the variable winning device 101 of FIG. 1, that is, to enlarge the winning port. Here, according to the control of the special symbol display device 100, the combination of the stop special symbols is determined and displayed, but in reality, these display controls are performed under the control of the CPU 200, and the interface is displayed. No data is sent from the special symbol display device to the CPU 200, except for the control signal related to. The special symbol display device 100 is under the control of the CPU 200 for both the so-called “variable display” time and the stop symbol data.
[0016]
Here, unlike an environment where what is called a computer or an electronic computer is used in a general sense, a CPU used for controlling a gaming machine is placed under an unfavorable environmental condition. It has been.
[0017]
Generally, a CPU integrated circuit element or a circuit board including these is easily affected by ambient environmental conditions including temperature, humidity, electromagnetic noise, power supply circumstances, grounding, and the like. Usually, it is devised to adapt to.
[0018]
When the CPU receives the above-described electromagnetic noise or noise from the AC power source, the contents of various data processed by the CPU change, and as a result of these changes, information on addresses other than the program instructions predetermined when the CPU fetches instructions. Capture or import data contents. When such a situation occurs, the CPU generates a so-called program runaway, and the subsequent operation is not a predetermined operation, or does not accept any external command and falls into a completely inoperable state. To prevent such a situation, there are measures to prevent external noise and use of a watch dog timer. The latter is based on the assumption that the normal CPU program operation repeats a predetermined routine, and detects that the predetermined routine is not repeated outside the CPU (actually, the normal routine is executed). In this case, a reset signal is sent to the watch dog timer counter at a fixed period), and a hardware reset signal is sent to the CPU. Usually, this watch dog timer is composed of a counter having a reset input and a reset signal output circuit for outputting a hardware reset signal when the counter reaches a predetermined maximum countable value. .
[0019]
In addition, as shown in Japanese Patent Application No. 60-102443, the game machine is operated in such a manner that the operation of stopping the supply of the reset signal to the watch dog timer is stopped and the influence of external noise is minimized. A method for causing a CPU to execute complicated control in the above is disclosed. That is, in a gaming machine controlled by a CPU having a built-in program, reset signal generating means for resetting the CPU at regular intervals and completely initializing is provided outside. The period of the reset signal generated from the reset signal generating means is set to be longer than the processing time required to execute a predetermined program instruction. This period is set to 3 ms in this embodiment, and is generally about 2 ms to 4 ms. This period is used for temporal control in the gaming machine, for example, counting the opening time of the special electric accessory.
[0020]
A conventional example using this hardware reset signal is shown in FIGS. FIG. 4 shows a flow of basic program steps of a gaming machine using a conventional CPU, and shows an outline of a basic flowchart in the case of using a hardware reset. Here, a main board in a so-called gaming machine is assumed, but it can also be applied to a peripheral board including a CPU inside.
[0021]
  In FIG. 4, various random number update processing, basic timer update processing, input port processing, switch check processing, symbol control processing, and the like of the gaming machine are designated as job A, job B,...(The processing from job A to job M is called so-called normal processing in gaming machines, and is hereinafter referred to as “normal processing”). However, with respect to job N, a random number is usually used as the time remaining until hardware reset is performed after various jobs shown in FIG. 4 (for example, jobs up to job M), which are referred to as normal remaining time, are completed. This represents processing for updating the counter for occurrence. The line 115 in FIG. 4 shows how the CPU processing is forcibly returned to the beginning of a predetermined program by a hardware method by hardware reset. Lines other than this line show the flow according to the program.
[0022]
FIG. 7 is a diagram showing a schematic circuit of the power-on reset and hardware reset of the CPU 200 in the conventional example, in which the synchronous signal generator 220 and the clock generator 221 shown in FIG. 2 are extracted. is there.
[0023]
  When the power of the gaming machine is turned on, the power-on reset signal 20 shown in FIG. 7 maintains a low state for a while, and the power supply for the CPU 200 settles to the nominal voltage during this time. A clock is supplied from the clock generator. However, even at this stage, since the power-on reset signal 20 remains low, the CPU 200 and peripheral circuits (for example, the PIO 14) are in a reset state. When the time elapses thereafter and the power-on reset signal changes from low to high, the reset state is released and the CPU 200 starts executing the programmed command according to the programmed procedure. Normally, in step S102 in FIG. 4, the signal at the A0 input of the PIO in FIG. 7 is checked (polled). At this time, immediately after the power-on reset, the A0 input signal of the PIO 14 is kept low by the delay circuit 30. Therefore, in step S102, it is determined that the state is immediately after power-on reset, and the process proceeds to step S103 in FIG. 4 to perform initialization processing including initial setting of the data area of the RAM called normal cold start. Here, when step S101 is executed via the line 115 in FIG. 4, that is, when a hardware reset other than the power-on reset is performed, the power-on reset signal is in the high state. The A0 input of PIO 14 is high. Therefore, in this case, in step S102, the CPU 200 determines that it is not a power-on reset, and proceeds to step S104. In step S104, the stack pointer is initialized in preparation for interrupt control from the peripheral device.Normal processing, ieJob A in step S105 and job B in step S106 are executed one after another. Thereafter, the programmed jobs are sequentially executed. When the job M is executed up to step S110, the job N is repeatedly executed for the remaining time until the next hardware reset. During this repetition, a hardware reset is performed and the process is forcibly returned to the first step S101. By repeating the above, the program processing in the gaming machine is performed.
[0024]
  In FIG. 7, the CPU 200 operates in accordance with the clock from the clock generator 221, and this clock is usually divided and a lower frequency clock is sent to the synchronization signal generator 220. The synchronization signal generator is usually composed of a counter having a reset input. A power-on reset signal (not shown) is inputted to the reset input, and this counter is kept for a while after the power-on. Has been reset. When the reset state is released, since the clock signal from the clock generator is input to the clock input, counting is started. When a predetermined number of clocks are counted, a low output is output to the OR gate, and the reset input of the CPU 200 is set to low via the OR gate to reset the CPU 200. Where the synchronization signal generator220Naturally, the time from when the reset is released until the first reset signal is output is substantially equal to the period of the reset signal output one after another from the synchronization signal. If a certain amount of time is required for the initialization process in step S103, the configuration of the synchronization signal generator is changed, and immediately after the synchronization signal generator is powered on / reset, the necessary time elapses. The first hardware reset signal as a synchronization signal may be output later.
[0025]
Although not illustrated, in another method, a timer that outputs a pulse at a predetermined time interval is provided outside the CPU, and the output pulse of this timer is input to the CPU interrupt input (for example, NMI; Non Maskable Interrupt, with the highest priority). A high interrupt is input to an interrupt input that is not masked even if another interrupt occurs, and the same operation is performed.
[0026]
The hardware reset or timer interrupt method described above has been performed not only on the so-called main board but also on peripheral boards. This is because time control is often required for each board, and it is convenient to use time intervals resulting from such signals for such control.
[0027]
The above method is considered to be a necessary condition for efficiently controlling complex control in a gaming machine in a compact form and efficiently under the ambient conditions in a gaming machine that has been considered to be poor. Has been.
[0028]
[Problems to be solved by the invention]
At present, pachinko and pachislot machines are prominently introduced with cutting-edge technology for sound, images, etc., but on the other hand, only those that have been inspected and passed by public authorities are allowed to be manufactured and sold. ing. In general, if the latest technology is adopted, there is a problem that inspection becomes very difficult. In order to solve such problems while adopting the most advanced technology, various functions such as sound and image are physically divided as a printed board, and these are so-called main boards that mainly control the game ( A configuration is desired in which a main CPU board operates in response to a command from a main control unit). In the inspection by the public organization, the peripheral board that receives commands from the main board eliminates the conventional complicated inspection process as a system configuration that can be inspected by a simple method such as a simulator, etc. Also, the game management function mainly by function division The main board (main CPU board) is focused on the inspection. This is achieved by transferring many of the conventional control functions for sound and image display to the peripheral board (sub board) from the main board (main board) whose functions are limited to the game management function. This means that the overall inspection items including the substrate and the peripheral substrate are greatly reduced, and further, the inspection content itself is simplified.
[0029]
Changes in environmental conditions surrounding the gaming machine as described above, in this case, not the physical ambient environmental conditions including the temperature, humidity, electromagnetic noise, power supply situation, grounding, etc. On the other hand, the above-described control method causes many problems. This is a problem related to the ease of verifying the operation specifications and operation status of the main board. Although it existed as a problem even under conventional soft environmental conditions, the ratio is still larger under new soft environmental conditions.
[0030]
That is, the above-described test is performed while an in-circuit emulator is connected to a so-called main board, and the execution of the program is operated and confirmed on the in-circuit emulator. The operation related to the execution of the program is performed step by step in some cases, and continuously in some cases up to a predetermined step. Also, confirmation of signal exchange with the sub-board, program execution procedure, confirmation of output signal, and the like are performed. Here, the test using the in-circuit emulator is performed in a state different from the operation mode as a normal gaming machine. That is, normally, the CPU continuously executes the built-in program in order according to the input clock signal, but in the verification, it is not always executed continuously according to the clock signal. Depending on the operation of the in-circuit emulator, the stop state may continue for several minutes during the program.
[0031]
In such a state of use of the in-circuit emulator, for example, when the technique disclosed in Japanese Patent Application No. 60-102443 described above is used, a problem occurs. In this case, a periodic hardware reset signal is actually generated on the board of the connected gaming machine, and the stop state described above is actually a very short time. When input, the CPU is reset to the initial state regardless of the operation of the in-circuit emulator. In other words, the execution of the program up to that point ends at an intermediate stage. This means that the subsequent program will not be executed, and there may be a difference in operation between when the program being tested is actually executed and when an in-circuit emulator is used. Yes, it creates some difficulties in the way of testing.
[0032]
The above problems are not only problems during verification, but also occur at the stage of program confirmation / verification in the development of new programs.
[0033]
In addition, if a method using a periodic hardware reset is adopted, program processing may be interrupted, rather than being forced to return to the beginning after a predetermined time. Therefore, it is necessary to calculate the processing time carefully so that all possible jobs are completed within one cycle of hardware reset, and to design a program so as not to exceed this cycle. In addition, when trying to check the data contents using an in-circuit emulator, the program processing may be forcibly terminated due to a hardware reset. Therefore, in order to proceed with debugging and verification using an in-circuit emulator efficiently, it must be designed so that interrupts and hardware reset signals may be input at any timing. Careful design and verification was necessary to construct the control program design of the machine consistently and consistently.
[0034]
In a normal gaming machine, a random number to be used for controlling the gaming machine is not used until the next hardware reset is input after the hardware reset is released and the execution of a predetermined job is completed. In order to generate the counter, the counter is incremented. Such a program operation for generating random numbers is also affected by debugging and verification using an in-circuit emulator, and produces a result (random number value) different from the actual operation state.
[0035]
In addition, measures have not been taken in the past when the power supply of the gaming machine is momentarily interrupted or a power failure occurs for a short time, but in the future, although the probability of occurrence is low, it is desirable to take measures . Measures against instantaneous power interruption, instantaneous power interruption, or power interruption include monitoring the AC power supply waveform to detect the waveform interruption and holding it for a short time from the detection point to when the control voltage starts to drop. Data to be saved is saved, and the state before saving is made based on the data saved when the power is restored, and the execution before saving is continued. That is, after the CPU is reset, it returns to the state immediately before the reset, and the values of various registers in the CPU or peripheral IC (for example, PIO 14 in the case of FIG. 4) necessary for continuing to execute the program, Then, information indicating that the data has been saved due to power-off is stored in a nonvolatile RAM or a battery-backed memory. Using the saved data based on the information that is saved when the power is restored, the operation state of the CPU is restored to the state before the instantaneous interruption or power failure. Or, it is automatically affected by noise caused by a momentary power interruption, or automatically when a predetermined time elapses without the hardware reset being performed. , Software reset) to restore operation.
[0036]
If this measure is taken, it becomes possible to continue to operate various states during the game of the gaming machine in spite of momentary power interruption or short-time power outage. In particular, when a gaming machine is in a state advantageous to the player or when a right advantageous to the player has been generated, it is important to interrupt such state and continue without ending. However, it is only about the CPU.
[0037]
Here, the countermeasure against the instantaneous power failure usually starts from detecting a missing or abnormal waveform of the AC power supply, and this detection signal is usually input to an unmasked interrupt input signal (NMI). However, this normal method cannot be adopted if the NMI input is already used for the above-described operation. If the control method using the hardware reset method described above is adopted, the NMI can be used as an AC disconnection detection signal input for this power supply countermeasure. However, during the NMI processing, that is, the above-described data, etc. If a hardware reset signal is input during the save processing or data restoration processing, the processing ends halfway. The saving process and the restoring process require a certain amount of time and are generated regardless of the hardware reset signal. Therefore, the input of a hardware reset signal during these processes occurs with a probability that cannot be ignored.
[0038]
The object of the present invention is to eliminate such inconveniences in verification, and even when an in-circuit emulator is used, the operation at the time of actual program execution is verified without losing the consistency between the program and the result. There is also to do. That is, it is an object of the present invention to provide an improved control device for a gaming machine that reproduces an actual operation more easily, more efficiently, and more easily inspecting a board of a gaming machine.
[0039]
In addition, an object of the present invention is to provide a control device for a gaming machine that allows a game to be continuously performed even in the event of a momentary power interruption, or after a temporary power failure.
[0040]
[Means for Solving the Problems]
  In order to achieve such an object, the present inventionThe gaming machine control device (FIGS. 8 and 9)CPU(200) and synchronization signal generating means (220) for outputting a synchronization signal at a preset cycle;Control device for gaming machine equipped withAnd beforeSynchronous signal generationmeansOrBeforeInput to CPUBe doneSaidSync signalTheBy pollingDetectDetectionmeans(200, 14, A1, S112A, S112B), The inspectionAcquaintanceIn stepsSo beforeRecordEvery period until a sync signal is detectedExecutionBe doneNormal processingofExecution(S112A, S112B NO to S112A, S112B loop processing again, S112A, S112B YES, S105-S110 in FIGS. 5 and 6).
[0041]
  Here, while waiting for the execution of the normal processing,Update the counter that generates random elementsprocessingTheIt can be characterized by performing (loop processing from NO of S112A and S112B to S112A and S112B again, S111A and S111B).
Further, the synchronization signal generating means and the detecting means are integrally formed in the CPU.
[0042]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments to which the present invention is applied will be described below with reference to the drawings. FIG. 8 shows an embodiment to which the invention is applied, and shows the relationship between the power-on reset and synchronization signal of the main control unit and the CPU. The same portions corresponding to the portions of FIG. 7 shown as the conventional example are indicated by the same numbers. FIG. 5 shows an embodiment to which the present invention is applied, and shows an operation flow of the main control unit. Parts corresponding to FIG. 4 shown as the conventional example are given the same numbers.
[0043]
  FIG. 8 showing the embodiment of the present invention differs from FIG.7 OR13 is removed, the power-on reset signal 20 is directly input to the reset of the CPU 200, and the output of the synchronization signal generator is the part that is input to the A1 input of the PIO. The CPU 200 polls the A1 input of the PIO 14 and checks whether the input is high (1) or low (0), thereby detecting the presence or absence of a synchronization signal. Here, of course, the polling is performed according to a program. In FIG. 7, the delayed signal of the power-on reset signal 20 is input to the A0 input of the PIO 14. In FIG. 8, the A0 input of the PIO 14 has the same meaning as the signal in FIG. A signal is being input.
[0044]
  The Warm / Cold signal can be set manually, or can be a signal determined by whether or not the voltage of the backup power source backing up the memory for the momentary power interruption described above is equal to or higher than a predetermined value. Come out. That is, when this signal is checked, if the voltage of the backup power supply is a signal indicating a predetermined value or less, it is determined as Cold in step S102 and initialization processing is performed.Step SWhen the process 103 is executed and the voltage of the backup power supply indicates a predetermined value or more, the process can proceed to step S104.
[0045]
In addition, when this part detects the AC power supply abnormality and causes all the registers and flags used in the CPU to be saved in the RAM backed up by a battery or a large-capacitance capacitor, etc. In the initialization process, this can be detected, and a restoration process for restoring the inside of the CPU using the data saved in the RAM driven by the backed up power supply can be included. In such a case, it is natural that an interrupt processing program for saving processing is provided separately from the operation flow shown in FIG. 5 or FIG.
[0046]
  FIG. 5 shows Embodiment 1 of the present invention and shows an operation flow of the main control unit. Conventionally, the program is forcibly restarted by a periodic hardware reset signal. In the present invention, a method of polling a periodic synchronization signal by a program is used. This polling process is added as step S112A inside the repetition loop of job N. In this step S112A, the polarity of the synchronizing signal input to the A1 input is checked by controlling the PIO in FIG. 8, and if it is determined that the synchronizing signal is generated periodically, this loop processing is performed. Stop and start first after the initialization processAt the beginning of normal processingJump to Job A.
[0047]
FIG. 6 shows the second embodiment of the present invention, and unlike the method of FIG. 5, initialization processing is performed after reset release, and thereafter, job N, that is, processing for updating a counter for generating random numbers is performed. And a polling process for checking the presence / absence of the synchronization input described with reference to FIG. 5 is placed in a part of the loop process. A conditional jump instruction is included for performing an operation of continuing the job N or starting the next job A according to the data obtained by the polling. If the synchronization input signal exists, the process proceeds to step S105. If the synchronization input signal does not exist, the job N is repeated.
[0048]
  The difference between the method of FIG. 5 and FIG. 6 is how to handle the initialization process after reset, the original job as a normal gaming machine, how to distribute these with respect to synchronous input, and the time required for initialization ,Normal processingEither method is used depending on the execution time from job A to job M, the synchronization signal period, and the like. There is no substantial difference between the methods of FIGS. 5 and 6 except that the first synchronization signal is input after reset.
[0049]
The difference between the flow in FIG. 5 and FIG. 6 is, in other words, the problem of which step S should be proceeded to after completion of the initialization process, that is, after step S104. In FIG. 5, step S104 is changed to step S111A. 6 corresponds to FIG.
[0050]
In FIG. 5, step S112A is set after step S111A and 112B is set after step S111B in FIG. 6. However, even if this order is changed, there is no substantial difference. That is, in FIG. 5, it is possible to perform job N in the return flow from step S112A. However, if this is done, the possibility of starting the first job A without executing job N is left, and it is assumed that the in-circuit emulator is used regardless of the actual operation. 5 or the job preferably proceeds in the order shown in FIG. By doing so, at least one job N is always performed before the job A is completed and the job A is started again. Normally, the number of continuous repetitions of job N is random, and the resulting random number generated by job N is assumed to be more random.
[0051]
FIG. 9 is a block diagram showing the circuit configuration of the control system of the gaming machine of the present invention including FIG. The common parts with FIG. 2 are indicated by the same numbers. In addition, the thick line part has shown the range of the main control part.
[0052]
The control system described above is an indispensable system for realizing functions or regulations required for present and future gaming machines. By using this method, it is not necessary to create a program considering the ease of verification at the time of verification, and the design of the program itself is facilitated. At the same time, it is possible to shorten the test period in the certification. That is, in the verification, even if an in-circuit emulator is used or the program is temporarily stopped, the CPU is not reset, and the program can maintain the state before the stop. This facilitates program specification confirmation and operation confirmation in verification. The same can be said when verifying and confirming new programs in the development stage of new models.
[0053]
  At the time of verifying the CPU board using the in-circuit emulator, for example, in FIG. 5 only when the synchronization signal is input at the time when step S112A is executed.At the beginning of normal processingIf the process proceeds to job A and no synchronization signal is detected, job N is repeated.
[0054]
When an in-circuit emulator is used in the conventional control method, job A is often started without job N being executed once. This means that the random number generated by job N is fixed. In the normal operation state, the job N is executed at least as many times as to make the counter incremented by the job N one turn or more. In the control device of the present invention, random numbers distributed almost in the same degree as in a normal operation state can be obtained even when an in-circuit emulator is used. This is because the interval between the execution timing of step S112A by the in-circuit emulator and the repetition period of the synchronization signal is random, and job N is performed during this random period.
[0055]
In addition, with the control device using the method of the present invention, the game progress of the gaming machine can be continued in the previous game after the AC power is restored even in the event of a momentary AC power interruption or a temporary power failure. Make it easier to take measures. In particular, the CPU of the main control unit is basically of the Z80 (Zylog) specification, and can take effective measures. In general, in Z80, the NMI is used to cause the CPU to take measures in an emergency such as a power failure or a memory parity error. The power supply abnormality includes a drop in power supply voltage supplied to the CPU, a momentary voltage abnormality in the AC power supply, a momentary interruption, a power failure, etc .. Processing is performed to save all registers and flags to be used in a RAM backed up by a battery or a large-capacity capacitor. Although it has been impossible to perform such operations in the past, the gaming machine according to the present invention enables such processing.
[0056]
Although the present invention has been described based on the drawings illustrating the present invention, the illustrated drawings are for ease of understanding, and each block does not necessarily indicate an IC (integrated circuit) of one package. Represents a function. In order to achieve the same object as the present invention, the functional configuration shown in FIG. 8 can be incorporated in one LSI, or can be configured by an independent IC. Currently, Z80 and software are fully compatible at binary level, and a so-called Z80 peripheral IC (PIO, CTC, SIO) or clock generator function is incorporated in a 100-pin package.
[0057]
In addition, the word “CPU” is treated as a so-called Z80 CPU having a ROM and a RAM inside the package in the main control unit 200, and a CPU having a ROM and a RAM outside the package in the special symbol display device 100. This difference is irrelevant to the present invention and does not affect the implementation of the present invention.
[0058]
【The invention's effect】
As described above, according to the present invention, the problems in the conventional method, particularly the problems at the time of program verification using an in-circuit emulator (this verification includes verification at the time of program development, And verification rules based on “type verification rules” are included), and it is easy to check program specifications and operations.
[0059]
In addition, the program design for avoiding the problem at the time of the above-described verification is unnecessary, and the program design is facilitated.
[0060]
In addition, preconditions for taking measures against instantaneous interruption of AC power supply and temporary power failure are given.
[Brief description of the drawings]
FIG. 1 is a front view showing an example of a front appearance of a gaming machine.
FIG. 2 is a block diagram showing a circuit configuration of a control system of a conventional gaming machine.
FIG. 3 is a block diagram showing an internal configuration of a special symbol display device 100 of a conventional gaming machine.
FIG. 4 is a diagram showing a basic flow of program steps of a gaming machine using a conventional CPU, and is a diagram showing an outline of a basic flowchart when hardware reset is used.
FIG. 5 is a diagram showing a flowchart of basic program steps of the improved gaming machine according to the first embodiment of the present invention.
FIG. 6 is a diagram showing a flowchart of basic program steps of the improved gaming machine according to the second embodiment of the present invention.
FIG. 7 is a diagram showing a schematic circuit of CPU power-on reset and hardware reset in a conventional example.
FIG. 8 is a diagram illustrating an embodiment according to the present invention, in which a power-on reset of the CPU and a synchronization signal are given to the CPU.
FIG. 9 is a block diagram showing a circuit configuration of a control system of the gaming machine according to the embodiment of the present invention.
[Explanation of symbols]
13 OR gate
14 PIO (parallel input / output)
20 Power-on reset signal
30 delay circuit
100 Special symbol display device
101 Variable prize winning device
102 Specific area
200 CPU
203 Input port
208 Power supply circuit
220 Sync signal generator
221 clock generator

Claims (3)

In a control device for a gaming machine comprising a CPU and synchronization signal generating means for outputting a synchronization signal at a preset cycle ,
It said synchronizing signal input before Symbol synchronizing signal generating means or et previous SL CPU, further comprising a detection means for detecting by polling,
Until said detecting the test Shitte stage thus pre Symbol synchronizing signal and waits for the execution of the normal processing performed in each of the periods
Controller of the gaming machine characterized by and this. Wherein while waiting for execution of the normal process, the control unit of the gaming machine according to claim 1, which comprises carrying out a process of updating a counter for generating a random element. The synchronization signal generating means and the detecting means are integrally formed in the CPU.
  The gaming machine control device according to claim 1 or 2, wherein the control device is a gaming machine.

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