JP3729843B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a manufacturing technique of a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a manufacturing method of a semiconductor integrated circuit device using a phase shift lithography technique in exposure processing.

  In a photolithography technique for transferring a circuit pattern on a photomask onto a semiconductor substrate using light such as g-line (436 nm) or i-line (365 nm), the degree of element integration of the semiconductor integrated circuit device is improved. Accordingly, there is a limit on the minimum processing dimension of the pattern that can be transferred satisfactorily.

  As a method of reducing the minimum processing size of a pattern that can be transferred well, it is conceivable to further shorten the wavelength of the exposure light. However, in reality, there are various problems, and it is easy to shorten the wavelength of the light. I can't.

  Therefore, there is a technique for increasing the numerical aperture (NA) of the optical system in the exposure apparatus in order to improve the resolution without changing the exposure wavelength. However, in this case, there has been a problem that the depth of focus becomes extremely shallow with the increase of NA and the use of short-wavelength light.

  For this reason, various exposure techniques for improving the resolution without reducing the depth of focus have been studied. As a representative means, there is a phase shift lithography technique using a phase shift mask.

  Phase shift lithography is a technique for improving the resolution and contrast of a projected image by manipulating the phase of light transmitted through a phase shift mask (including a reticle). A phase shifter that causes a phase difference in the transmitted light is formed.

  For example, in Japanese Patent Publication No. 62-59296 (Patent Document 1), a transparent film is provided on one of a pair of light transmissive regions adjacent to each other with a light shielding region interposed therebetween. A phase shift technique is disclosed in which a phase difference is generated between light transmitted through the light source and the interference light is weakened at a portion that becomes a light shielding region on the semiconductor wafer.

  Japanese Patent Application Laid-Open No. 62-67514 (Patent Document 2) discloses that a part of the light shielding area of the mask is removed to form a fine opening pattern, and then the light transmission area existing in or near the opening pattern. By providing a transparent film on one of these, a phase difference is generated between the light transmitted through the light-transmitting region and the light transmitted through the aperture pattern, and the amplitude distribution of the light transmitted through the light-transmitting region is in the horizontal direction. A phase shift technique for preventing the spread is disclosed.

In Japanese Patent Laid-Open No. 2-140743 (Patent Document 3), a phase shifter is provided in a part of a light transmitting region of a mask, thereby causing a phase difference in transmitted light and emphasizing a phase shifter boundary portion. A shift technique is disclosed.
Japanese Examined Patent Publication No. 62-59296 JP 62-67514 A Japanese Patent Laid-Open No. 2-140743

  However, in the phase shift lithography technology, there is no problem when applied to transfer of a simple repetitive pattern, but when applied to transfer of a complicated pattern such as a pattern constituting a semiconductor integrated circuit device, the phase shift lithography technique has no problem. There is a problem that it is difficult to arrange the shifter and the like, and the pattern cannot be transferred satisfactorily.

  For example, between the adjacent word lines of the DRAM, the region where the connection hole for the bit line and the connection hole for the capacitor are arranged has an interval between the word lines because of the alignment margin of the connection hole. There is a portion that is wider than the interval in the adjacent region of the word line.

  When such a word line is transferred using a phase shift mask, a phase shifter is disposed on one of light transmission regions (for word line transfer) adjacent to each other. If there are areas with different intervals between the transmissive areas, the phase of the light cannot be manipulated well at that point, and as a result, the part that is originally desired to be widened is thinned or the part that is thin is thickened. In some cases, the shape, dimensions, etc. cannot be as designed, and the pattern cannot be transferred satisfactorily.

  Further, for example, in a DRAM, the overall memory capacity tends to increase, and the degree of element integration is improved. However, as the element integration degree is improved, the interval between adjacent capacitor patterns is also narrowed.

  For this reason, when transferring the connection holes for capacitors using a phase shift mask, an auxiliary pattern is arranged around the light transmission region for opening the connection holes, but the interval between adjacent capacitor patterns is narrow as described above. As a matter of fact, if the auxiliary pattern is simply arranged, the pattern is formed at a position between the auxiliary patterns due to interference of light transmitted through adjacent auxiliary patterns, that is, an area where the pattern should not be formed originally. May occur.

  An object of the present invention is to provide a technique capable of faithfully transferring the shape and dimensions of a transfer pattern to a design pattern when a predetermined pattern is transferred using a photomask having a phase shifter.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

That is, the present invention is a method for manufacturing a semiconductor integrated circuit device in which a plurality of wirings extending in parallel to each other are provided on a semiconductor substrate, and includes the following steps:
(A) a step of depositing a conductor film for wiring formation on the semiconductor substrate and then depositing a photoresist film on the conductor film;
(B) a plurality of light transmission regions extending in parallel to each other provided for transferring the plurality of wirings, and one of the light transmission regions adjacent to each other among the plurality of light transmission regions; A photomask in which a phase shifter for changing the phase of transmitted light is disposed on the optical mask, and a constant interval is always formed between the light transmitting regions adjacent to each other along the extending direction of the light transmitting region. A step of preparing a photomask provided with a light shielding region;
(C) transferring the pattern of the plurality of wirings by irradiating the photoresist film with exposure light through the photomask;
(D) A step of forming the plurality of wirings by patterning the wiring forming conductor film using the wiring pattern transferred to the photoresist film as a mask.

In addition, the present invention is a method for manufacturing a semiconductor integrated circuit device in which a wiring having a wide region and a narrow region is provided on a semiconductor substrate, and includes the following steps:
(A) a step of depositing a conductor film for wiring formation on the semiconductor substrate and then depositing a photoresist film on the conductor film;
(B) A photomask provided for transferring the wiring and having a light transmission region having a wide region and a narrow region, wherein a light shielding region is formed in a part of the wide region of the light transmission region. And in the light shielding area surrounding the light transmission area, light having a phase opposite to that of the light transmitted through the light transmission area is formed in the vicinity of the boundary area between the wide area and the narrow area of the light transmission area. A step of preparing a photomask having an auxiliary pattern composed of such a fine light transmission region;
(C) transferring the pattern of the wiring by irradiating the photoresist film with exposure light through the photomask;
(D) forming the wiring by patterning the wiring forming conductor film using the wiring pattern transferred to the photoresist film as a mask;

A method for manufacturing a semiconductor integrated circuit device according to the present invention is a method for manufacturing a semiconductor integrated circuit device having a plurality of connection holes connecting predetermined layers on a semiconductor substrate, and includes the following steps:
(A) depositing a photoresist film on the semiconductor substrate;
(B) a plurality of light transmission regions provided to transfer the plurality of connection holes, and an auxiliary pattern provided around each of the light transmission regions, and the plurality of light transmission regions or A photomask in which a phase shifter for changing the phase of transmitted light is arranged on one of the auxiliary patterns, and the auxiliary pattern is arranged asymmetrically in each of the plurality of light transmission regions according to the surrounding environment. Preparing a photomask comprising:
(C) transferring the pattern of the plurality of connection holes by irradiating the photoresist film with exposure light through the photomask;
(D) A step of drilling a connection hole using the pattern of the connection hole transferred to the photoresist film as a mask.

Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
(1). According to the above-described present invention, for example, the interval between the light transmission regions for transferring word lines adjacent to each other is made constant in each interval line, so that the phase difference of the light transmitted through the light transmission regions adjacent to each other is obtained. The operation can be performed satisfactorily as designed (including errors) in the entire area between both light transmission areas. As a result, the shape and dimensions of the transfer pattern (word line WL) can be faithfully formed as designed.
(2) According to the above-described present invention, for example, a fine light-shielding region is arranged in the wide region of each light-transmitting region for forming a bit line, and the light-transmitting region wide area and the width in the surrounding light-shielding region By arranging the auxiliary pattern in the vicinity of the boundary area with the narrow area, it is possible to suppress a large fluctuation in transmitted light due to the difference in the area ratio between the wide area and the narrow area of the light transmission area. Thus, it is possible to transfer the wide region and the narrow region of the light transmission region satisfactorily as designed. As a result, the shape and dimensions of the transfer pattern (bit line BL) can be formed as designed.
(3). According to the present invention described above, for example, by arranging the auxiliary patterns arranged on the four sides asymmetrically according to the arrangement state of the light transmission region for forming the connection hole for the capacitor, It is possible to satisfactorily transfer the light transmission region for the connection hole without transferring an unnecessary pattern. As a result, the shape and dimensions of the capacitor connection hole can be formed as designed.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail below with reference to the drawings. (In the drawings for explaining the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof is omitted.) To do).

(Embodiment 1)
The semiconductor integrated circuit device according to the first embodiment is, for example, a 64 Mbit DRAM. However, the word bit configuration is not limited to this and can be variously changed. A circuit block configuration of a main part of a semiconductor chip in which the DRAM is formed is shown in FIG.

  In the memory cell region M arranged on the semiconductor chip, a plurality of memory cells MC are laid out in the vertical and horizontal directions in FIG. This memory cell MC is a minimum unit of memory for storing either binary data of High (hereinafter simply abbreviated as “H”) signal level or Low (hereinafter simply abbreviated as “L”) signal level. And is composed of one memory cell selection MOS • FET Qs and one capacitor C.

  Such a memory cell MC is arranged in the vicinity of the intersection of the complementary bit lines BL, / BL and the word line WL extending perpendicularly thereto. Note that “/” in / BL indicates active low. Further, one terminal of the capacitor C of the memory cell MC connected to the bit lines BL, / BL is set to the potential of the power supply voltage VDD / 2, for example.

  The complementary bit lines BL and / BL are arranged in m columns in the vertical direction of FIG. 1, and n memory cells MC are electrically connected to the individual bit lines BL and / BL. . The complementary bit lines BL, / BL extend in the horizontal direction of FIG. 1 and are electrically connected to the column decoder circuit CD and the column driver circuit via the sense amplifier circuit SA and the column selection MOS • FET Qy. Has been.

  The sense amplifier circuit SA is a circuit that detects and amplifies a minute voltage (or current) transmitted to the bit line BL, and is connected to the main amplifier MA via the data input / output signal lines I / O and / I / O. Further, it is electrically connected to the data output buffer circuit DOB. Note that “/” in / BL indicates active low.

  That is, the minute signals of the bit lines BL, / BL are transmitted to the main amplifier MA via the local input / output signal wirings I / O, / I / O, amplified by the main amplifier MA, and further, the data output signal wirings DOL, It is transmitted to the data output buffer circuit DOB via / DOL.

  The data output buffer circuit DOB is a circuit for amplifying the signal read from the memory cell MC so that it can be transmitted to an external device without being attenuated in the middle wiring path, and is electrically connected to the output terminal Dout. ing. Note that “/” in / DOL indicates active low.

  The column decoder circuit CD is a circuit that receives a signal from the column address buffer circuit and selects one predetermined column selection signal line YSL. The column driver circuit is a circuit that supplies a selection pulse voltage to a predetermined one column selection wiring by a signal from the column decoder circuit CD.

  The column address buffer circuit is a circuit that captures and holds a plurality of address signals in accordance with a column selection signal from the timing generation circuit, and forms a complementary internal address signal A based on these column address signals.

  On the other hand, the word lines WL are arranged in n rows in the horizontal direction of FIG. 1, and m memory cells MC are electrically connected to each word line WL. The word line WL extends in the vertical direction of FIG. 1 and is electrically connected to the row decoder circuit and the row driver circuit.

  The row decoder circuit is a circuit that receives a signal from the row address buffer circuit and selects a predetermined one word line WL. The row decoder circuit is supplied with an i + 1 bit complementary internal address signal from the row address buffer circuit.

  The row address buffer circuit captures and holds the row address signal transmitted from the address multiplexer circuit in accordance with the timing signal supplied from the timing generation circuit. The row driver circuit is a circuit that supplies a selection pulse voltage to a predetermined one word line WL by a signal from the row decoder circuit. The power supply voltage of the DRAM is, for example, about 3.3V, and the ground voltage is, for example, about 0V.

  FIG. 2 and FIGS. 3 to 6 show a cross-sectional view and a plan view of main parts in the memory cell region of this DRAM. FIG. 7 is a cross-sectional view of the main part in the peripheral circuit region of this DRAM. The memory cell region M in FIG. 2 is a cross-sectional view taken along line II-II in FIGS.

A semiconductor substrate 1 s constituting the DRAM is made of, for example, p ⁻ -type silicon (Si) single crystal, and a field insulating film 2 for element isolation is formed thereon.

The field insulating film 2 is made of, for example, silicon dioxide (SiO ₂ ), and a region surrounded by the field insulating film 2 is an active region A of the element as shown in FIG.

  This active region A is formed in a planar inverted V shape, for example. The active regions A are arranged at a predetermined distance along the horizontal direction of FIG. However, the active regions A, A adjacent in the vertical direction in FIG. 3 are arranged in a state of being relatively shifted in the horizontal direction by half of the horizontal length. The length L1 is, for example, about 0.4 μm, and the length L2 is, for example, about 0.35 μm.

  A p well 3p is formed in the memory cell region M above the semiconductor substrate 1s. For example, boron of a p-type impurity is introduced into the p well 3p. The memory cell MC described above is formed on the p well 3p.

This memory cell MC is composed of one memory cell selection MOS • FET (hereinafter referred to as selection MOS) 4 (corresponding to Qs on the circuit diagram) and one capacitor 5 (corresponding to C on the circuit diagram). ing. The size of one memory cell MC is, for example, about 1.15 μm ² .

  The selection MOS 4 includes a pair of semiconductor regions 4a and 4b formed on the semiconductor substrate 1s so as to be spaced apart from each other, a gate insulating film 4c formed on the semiconductor substrate 1s, and a gate formed on the gate insulating film 4c. 4d.

  The semiconductor regions 4a and 4b are regions for forming a source region and a drain region of the selection MOS 4. For example, n-type impurity phosphorus or arsenic (As) is introduced into the semiconductor regions 4a and 4b. A channel region of the selection MOS 4 is formed between the semiconductor regions 4a and 4b.

  Note that the channel region under the gate electrode 4d of the selection MOS 4 has an upper side and a lower side that are refracted when viewed in a plane, but the refraction angle is designed to be 135 ° or more. The same bird's beak elongation and end shape of the field insulating film 2 are obtained on the upper side and the lower side.

  As a result, according to the first embodiment, it is difficult to form a step on the surface of the channel region of the selection MOS 4, so that it is possible to introduce impurities into the entire surface of the channel region by substantially the same depth by ion implantation. ing. For this reason, since a channel region having a uniform impurity concentration distribution can be obtained, it is possible to prevent fluctuations in the threshold voltage of the selection MOS 4.

The gate insulating film 4c is made of, for example, of SiO _2. The gate electrode 4d are, for example on the conductor film 4d1 made of low-resistance poly-silicon film, is formed by depositing a conductor film 4d2 made of, for example, tungsten silicide (WSi _2). This conductor film 4d2 reduces the resistance of the gate electrode 4d. However, the gate electrode 4d may be formed of a single film of low-resistance polysilicon or a predetermined metal such as tungsten.

  The gate electrode 4d is also a part of the word line WL. As shown in FIG. 4, the word line WL is formed to extend linearly in a direction orthogonal to the extending direction of the active region A described above.

  A portion of the word line WL that intersects the active region A is a portion constituting the gate electrode 4d of the selection MOS 4 and has a certain width (Lg) necessary for obtaining a predetermined threshold voltage. It is wider than other parts of the word line WL. The width Lg of the wide portion of the word line WL is, for example, about 0.44 μm. The width L3 of the narrow portion of the word line WL is, for example, about 0.3 μm.

  The wide portion of the word line WL is formed by protruding a part of the word line WL from one side surface of the word line WL. However, the word lines WL adjacent to each other so that the protruding portions face each other are shifted from each other in the vertical direction in FIG. 4, that is, the protruding portions and the recesses of the adjacent word lines WL are arranged. They are arranged to engage. Note that the region of the word line WL having the dimension Lg is provided wider than the width of the active region A at least by the amount corresponding to the mask alignment margin in the manufacturing process.

  By the way, in the first embodiment, the distances L4a1 and L4a2 between the adjacent word lines WL are always constant in the extending direction of the word lines WL so that the protruding portions face each other, for example, about 0.3 μm. Is set to Further, the interval L4b between the adjacent word WLs so that the sides without the projecting portions face each other is always constant in the extending direction of the word lines WL, and is set to about 0.3 μm, for example.

  That is, in the first embodiment, the intervals L4a1, L4a2 and the interval L4b between adjacent word lines WL are set to be always constant in each interval line. Further, the interval L4 between the adjacent word lines WL and the width L3 of the narrow portion of the word line WL are the same.

  The upper and side surfaces of the gate electrode 4d (word line WL) are covered with a cap insulating film (first cap insulating film) 7a and a side wall (first side wall insulating film) 7b through insulating films 6a and 6b. . These cap insulating film 7a and sidewall 7b are covered with interlayer insulating films 8a to 8c.

  Then, a connection hole 9a1 is formed in the interlayer insulating films 8a to 8c so as to expose the semiconductor region 4a in the upper layer portion of the semiconductor substrate 1s, and the semiconductor in the upper layer portion of the semiconductor substrate 1s is formed in the interlayer insulating films 8a and 8b. A connection hole 9b1 is formed so that the region 4b is exposed. The dimensions of these connection holes 9a1, 9b1 are, for example, about 0.36 μm × 0.36 μm.

Insulating film 6a, 6b are made of, for example, of SiO _2. In the first embodiment, the cap insulating film 7a and the sidewall 7b are made of, for example, silicon nitride.

  The insulating films 6a and 6b have, for example, the following two functions. That is, the first function is to prevent the inside of the film forming apparatus from being contaminated with the constituent metal elements of the conductor film 4d2 when the cap insulating film 7a and the sidewall 7b are formed. The second function is to alleviate stress applied to the cap insulating film 7a and the sidewall 7b due to the difference in thermal expansion during the heat treatment or the like in the manufacturing process of the semiconductor integrated circuit device.

  Cap insulating film 7a and sidewall 7b function as etching stoppers when connecting holes 9a1, 9b1 are formed in interlayer insulating films 8a, 8b, and connect holes 9a1, 9b1 are self-aligned between adjacent word lines WL. It functions as a film for forming. That is, the cap insulating film 7a and the side wall 7b define the dimensions of the connection holes 9a1, 9b1 in the width direction of the word line WL.

  Therefore, for example, even if the connection holes 9a1 and 9b1 are slightly shifted in the width direction of the word line WL (left and right direction in FIG. 3), the cap insulating film 7a and the sidewall 7b function as an etching stopper. , 9b1 does not expose part of the word line WL. Therefore, the alignment margin of the connection holes 9a1, 9b1 can be reduced.

  Even if the connection holes 9a1 and 9b1 are displaced in the longitudinal direction (vertical direction in FIG. 3) of the word line WL, the thickness of the interlayer insulating films 8a and 8b is secured to some extent here. The upper surface of the semiconductor substrate 1s is not exposed from 9b1.

Interlayer insulating film 8a is made of, for example, SiO _2, an interlayer insulating film 8b is made of, for example, BPSG (Boro Phospho Silicate Glass). The interlayer insulating film 8a has a function of preventing boron or phosphorus in the upper interlayer insulating film 8b from diffusing into the lower semiconductor substrate 1s.

  The interlayer insulating film 8b has a function of flattening the base of the wiring layer. As a result, a margin for photolithography can be secured, and the pattern transfer accuracy of the connection holes 9a1 and 9b1 and wiring can be improved.

On the interlayer insulating film 8b, an interlayer insulating film 8c made of, for example, SiO ₂ is formed. In the interlayer insulating film 8c, when a part of the cap insulating film 7a is exposed from the interlayer insulating film 8b, for example, in a bit line forming process described later, the exposed portion is etched and the word line WL is exposed. This is a film for preventing this. Therefore, when such a problem does not occur, it is not necessary to provide it.

A bit line BL is formed on the interlayer insulating film 8c. The bit lines BL, for example a conductor film of low-resistance polysilicon layer (second conductive film) BL1, for example, conductive film (second conductive film) composed of WSi ₂ becomes BL2 is deposited, a contact hole 9a1 And electrically connected to the semiconductor region 4a.

  Between the conductor film BL1 and the interlayer insulating film 8c, a mask film (second mask film) 10b that remains an etching mask when the connection hole 9a1 is formed remains. The mask film 10b is a film for increasing the etching selection ratio when the connection hole 9a1 is formed. The mask film 10b is made of, for example, low resistance polysilicon and is also a part of the bit line BL.

  A plan view of the bit line BL and the connection hole 9a1 is shown in FIG. The bit line BL extends linearly in the horizontal direction of FIG. 5 so as to be orthogonal to the extending direction of the word line WL. In the bit line BL, a projecting portion is formed at a portion located in the center of the active region A, and a bit line connection hole 9b1 is disposed in the projecting portion.

  The center line of the bit line BL does not necessarily coincide with the center of the connection hole 9a1 for the bit line, but if not, the bit line BL has connection holes 9b1 and 9b2 for the capacitor (see FIG. 2). Requires a protrusion to completely enclose.

  If the protruding portion is formed on the bit line BL, a short circuit failure may occur between the protruding portion and the bit line BL adjacent to the protruding portion side. For this reason, a portion of the adjacent bit line BL facing the protruding portion is bent slightly so as to be separated from the protruding portion.

  The width L5 of the bit line BL is, for example, about 0.28 μm, the interval L6 between the protruding portion of the bit line BL and the adjacent bit line BL is, for example, about 0.3 μm, and the interval L7 between the adjacent bit lines BL is For example, it is about 0.58 μm.

  The upper and side surfaces of the bit line BL are covered with a cap insulating film (second cap insulating film) 11a and a side wall (second side wall insulating film) 11b through insulating films 6c and 6d. The cap insulating film 11a and the sidewall 11b function as an etching stopper when the connection hole 9b2 is formed in the interlayer insulating film 8c and the like, and the connection hole 9b2 is formed in a self-aligned manner between the bit lines BL adjacent to each other. It functions as a film. That is, the cap insulating film 11a and the sidewall 11b define the dimensions of the connection holes 9b1 and 9b2 in the width direction of the bit line BL.

  Therefore, for example, even if the connection holes 9b1 and 9b2 are slightly shifted in the width direction (vertical direction in the figure) of the bit line BL, the cap insulating film 11a and the sidewall 11b function as an etching stopper. Does not enter the element isolation region too much. For this reason, the alignment margin of the connection holes 9b1 and 9b2 can be reduced.

  Further, the cap insulating film 11 a and the sidewall 11 b are covered with an insulating film 12. The insulating film 12 is a film that functions as an etching stopper when the underlying insulating film after the capacitor 5 is formed, and is made of, for example, silicon nitride.

  The thickness of the insulating film 12 is set to, for example, about 100 to 500 mm, preferably about 250 mm. If it is thicker than this, hydrogen will be trapped by the silicon nitride film during the final hydrogen annealing process for terminating dangling bonds, or hydrogen movement will be blocked, and a sufficient termination effect will not be obtained. is there.

  For example, a cylindrical capacitor 5 is formed in an upper layer of the bit line BL. That is, the DRAM of the first embodiment has a COB (Capacitor Over Bitline) structure. The capacitor 5 includes a second electrode 5c formed on a first electrode (third conductor film) 5a via a capacitor insulating film 5b.

  The first electrode 5a is made of, for example, low-resistance polysilicon, and is electrically connected to one semiconductor region 4b of the selection MOS 4 through a conductor film (first conductor film) 13 embedded in the connection hole 9b1. The conductor film 13 is made of, for example, low resistance polysilicon.

  A plan view of the first electrode 5a of the capacitor 5 and the connection holes 9b1 and 9b2 for the capacitor 5 is shown in FIG. One first electrode 5a is arranged on each side of the connection hole 9a1 for the bit line BL. Each first electrode 5a is formed in a rectangular shape so as to straddle two adjacent word lines WL, for example, and its horizontal length is about 1.14 μm, for example, and its vertical length is For example, it is about 0.56 μm.

The capacitor insulating film 5b is formed, for example, by depositing a SiO ₂ film on a silicon nitride film. The second electrode 5c is made of, for example, low-resistance polysilicon and is electrically connected to a predetermined wiring.

  The mask film (third mask film) 10c below the first electrode 5a of the capacitor 5 is a film used as a mask when the connection hole 9b2 is formed. The mask film 10 c is made of, for example, low-resistance polysilicon and is a part of the first electrode 5 a of the capacitor 5.

  On the other hand, as shown in FIG. 7, a p well 3p and an n well 3n are formed in the upper part of the semiconductor substrate 1s in the peripheral circuit region P. For example, boron of a p-type impurity is introduced into the p well 3p. Further, for example, n-type impurity phosphorus or As is introduced into the n-well 3n. For example, an nMOS 14 and a pMOS 15 are formed on the p well 3p and the n well 3n.

  By these nMOS 14 and pMOS 15, DRAM sense amplifier circuit, column decoder circuit, column driver circuit, row decoder circuit, row driver circuit, I / O selector circuit, data input buffer circuit, data output buffer circuit, power supply circuit, etc. A peripheral circuit is formed.

  The nMOS 14 includes a pair of semiconductor regions 14a and 14b formed on the p well 3p so as to be spaced apart from each other, a gate insulating film 14c formed on the semiconductor substrate 1s, and a gate electrode formed on the gate insulating film 14c. 14d.

  The semiconductor regions 14a and 14b are regions for forming a source region and a drain region of the nMOS 14, and n-type impurities such as phosphorus or As are introduced into the semiconductor regions 14a and 14b. A channel region of the nMOS 14 is formed between the semiconductor regions 14a and 14b.

The gate insulating film 14c is made of, for example, of SiO _2. The gate electrode 14d, the conductor film 14d2 made of WSi ₂ is formed by depositing for example on the conductor film 14d1 made of low-resistance poly-silicon. However, the gate electrode 14d may be formed of, for example, a single film of low resistance polysilicon or may be formed of metal.

A cap insulating film 7a and sidewalls 7b are formed on the upper surface and side surfaces of the gate electrode 14d via insulating films 6a and 6b. The insulating films 6a and 6b have the same function as the insulating films 6a and 6b in the memory cell region M described above, and are made of, for example, SiO ₂ .

  The cap insulating film 7a and the sidewall 7b are made of, for example, silicon nitride. However, the side wall 7b in this case is a film mainly constituting an LDD (Lightly Doped Drain) structure.

  The pMOS 15 includes a pair of semiconductor regions 15a and 15b formed on the n well 3n and spaced apart from each other, a gate insulating film 15c formed on the semiconductor substrate 1s, and a gate electrode formed on the gate insulating film 15c. 15d.

  The semiconductor regions 15a and 15b are regions for forming a source region and a drain region of the pMOS 15, and p-type impurities such as boron are introduced into the semiconductor regions 15a and 15b. A channel region of the pMOS 15 is formed between the semiconductor regions 15a and 15b.

The gate insulating film 15c is made of, for example, of SiO _2. The gate electrode 15d, the conductor film 15d2 made of WSi ₂ is formed by depositing for example on the conductor film 15d1 made of low-resistance poly-silicon. However, the gate electrode 15d may be formed of a single film of low resistance polysilicon, for example, or may be formed of metal.

A cap insulating film 7a and sidewalls 7b are formed on the upper surface and side surfaces of the gate electrode 15d via insulating films 6a and 6b. The insulating films 6a and 6b have the same function as the insulating films 6a and 6b in the memory cell region M described above, and are made of, for example, SiO ₂ .

  The cap insulating film 7a and the sidewall 7b are made of, for example, silicon nitride. However, the sidewall 7b in this case is a film mainly for forming an LDD structure.

  The nMOS 14 and the pMOS 15 are covered with the interlayer insulating films 8a to 8c, and the insulating film 12 is deposited on the interlayer insulating film 8c. Further, in such a memory cell region M and peripheral circuit region P, an interlayer insulating film 8 d is formed on the insulating film 12, thereby covering the second electrode 5 b of the capacitor 5.

Interlayer insulating film 8d, for example on the insulating film 8d1 made of SiO _2, an insulating film 8d2 made of, for example, BPSG is formed by deposition. The insulating film 8d1 has a function of preventing boron or phosphorus in the upper insulating film 8d2 from diffusing to the second electrode 5c side of the capacitor 5 or the like.

  Next, a photomask (including a reticle) used in an exposure process which is a manufacturing process of the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS. Here, in FIG. 8, FIG. 10, FIG. 13, FIG. 15 and FIG. 19, in order to make the drawings easy to see, the light shielding area is indicated by hatching, and the area where the phase shifter is arranged is indicated by hatching with dots. The light shielding region is formed by, for example, a chromium (Cr) film. The mask substrate is made of, for example, synthetic quartz.

  FIG. 8 is a plan view of the main part of the photomask PM1 used when forming the field insulating film 2 and the active region A (see FIGS. 2 and 3) in the memory cell region M of the DRAM described above.

  In the photomask PM1, for example, a plurality of light transmissive regions P1 each having an inverted plane V shape are regularly arranged. The light transmission region P1 is arranged at a predetermined distance along the horizontal direction of FIG. However, the light transmission regions P1 adjacent to each other in the vertical direction in FIG. 8 are arranged in a state where their centers are relatively displaced in the horizontal direction in FIG. 8 by half of the horizontal length. The length Lm1 is about 2 μm, for example, and the length Lm2 is about 1.75 μm, for example.

  Further, in the rows of the light transmission regions P1 arranged in the vertical direction in FIG. 8, the phase shifter PS1 is arranged so as to overlap each light transmission region P1 every other row. The phase shifter PS1 is a functional unit that changes the phase difference of transmitted light. For example, after depositing a transparent insulating film such as silicon dioxide on the photomask PM1 by the SOG method or the like, the insulating film is photolithography technology. And it is formed by patterning by dry etching technique.

  FIG. 9 shows a pattern transferred to a positive photoresist film by such a photomask PM1. A hatched portion by a point is a portion where the photoresist film PR1 is left, and a white portion is a portion where the photoresist film PR1 is removed. Note that by making the photoresist film PR1 negative, the photoresist film can be left in the white portions of FIG.

  Next, FIG. 10 is a plan view of an essential part of the photomask PM2 used when forming the word line WL (see FIGS. 2 and 4) in the memory cell region M of the DRAM described above. FIG. 11 is a sectional view taken along line XI-XI in FIG.

  In the photomask PM2, for example, a plurality of linear light transmission regions P2 are regularly arranged along the horizontal direction of FIG. Further, in the row of light transmission regions P2 arranged in the horizontal direction of FIG. 10, every other row, phase shifters PS2 are arranged so as to overlap each light transmission region P2. The function, material, and formation method of the phase shifter PS2 are the same as those of the phase shifter PS1 (see FIG. 8).

  In the light transmission region P2, a region that protrudes in the lateral direction of FIG. 10 from one side surface and is wider than the other portion is formed at predetermined intervals in the extending direction. However, the light transmission regions P2 adjacent in the horizontal direction in FIG. 10 are arranged such that the positions of the protruding regions are shifted from each other in the vertical direction in FIG. The width Lm3 of the wide region of the light transmission region P2 is, for example, about 2.2 μm, and the width Lm4 of the thin region is, for example, about 1.5 μm.

  By the way, in the first embodiment, the interval Lm5a (Lm5a1, Lm5a2) between the light transmission regions P2 adjacent to each other so that the protruding portions face each other is constant in the interval line, for example, about 1.5 μm. Is set to

  Further, the distance Lm5b between the light transmission regions P2 adjacent to each other so that the sides without the projecting portions face each other is also constant in the distance line, and is set to about 1.5 μm, for example.

  That is, in the first embodiment, the distances Lm5a and Lm5b between the light transmission regions P2 adjacent to each other are constant in each distance line. Further, the distances Lm5a and Lm5b between the light transmission regions P2 adjacent to each other and the width Lm4 of the narrow portion of the light transmission region P2 are equal.

  Thus, the phase difference operation of the light transmitted through the light transmission regions P2 adjacent to each other can be satisfactorily performed as designed (including errors) in the entire region between the two light transmission regions P2. As a result, the shape and dimensions of the transfer pattern can be formed as designed (including errors).

  FIG. 12 shows a pattern transferred to a negative photoresist film by using such a photomask PM2. A hatched portion by a point is a portion where the photoresist film PR2 is left. Here, a pattern of a linear photoresist film PR2 having a wide region at predetermined intervals is formed.

  The white portions are portions where the photoresist film has been removed. Note that by making the photoresist film PR2 positive, the photoresist film can be left in the white portions of FIG.

  Next, FIG. 13 is a plan view of the main part of the photomask PM3 used for forming the bit line connection hole 9a1 (see FIGS. 2 and 5) in the memory cell region M of the DRAM.

  In the photomask PM3, for example, a plurality of square light transmission regions P3 are regularly arranged. The size of each light transmission region P3 is, for example, about 1.8 μm × 1.8 μm.

  A phase shifter PS3 is disposed so as to overlap each light transmission region P3. The function, material, and formation method of the phase shifter PS3 are the same as those of the phase shifter PS1 (see FIG. 8).

  Further, auxiliary patterns PA1 are arranged in the vicinity of the four sides of each light transmission region P3. The auxiliary pattern PA1 is to transfer a good pattern by increasing the contrast of the edge of the transfer pattern by causing a phase difference between each light transmitted through the main light transmission region P3 and the auxiliary pattern PA1. For example, a rectangular light transmission region.

  The distance Lm6 between the main light transmission region P3 and each auxiliary pattern PA1 in the vicinity of the four sides thereof is equal in order to favorably control the phase of the transmitted light, and is set to about 0.8 μm, for example. The sizes of the auxiliary patterns PA1 are all the same, for example, about 1.0 μm × 1.7 μm.

  FIG. 14 shows a pattern transferred to a positive photoresist film by such a photomask PM3. A hatched portion by a point is a portion where the photoresist film PR3 is left, and a square white portion is a portion where the photoresist film is removed. Note that by making the photoresist film PR3 negative, it is possible to leave the photoresist film in the white portions of FIG.

  Next, FIG. 15 is a plan view of the main part of the photomask PM4 used when forming the bit line BL (see FIGS. 2 and 5) of the memory cell region M of the DRAM described above. FIGS. 16A and 16B are cross-sectional views taken along lines XVIa-XVIa and XVIb-XVIb in FIG. 15, respectively.

  In the photomask PM4, for example, a plurality of linear light transmission regions P4 are arranged side by side along the vertical direction of FIG. The phase shifter PS4 is arranged so as to overlap the light transmission region P4 every other row of the light transmission regions P4 arranged in the vertical direction in FIG. The function, material, and formation method of the phase shifter PS4 are the same as those of the phase shifter PS1 (see FIG. 8).

  In each light transmission region P4, wide regions are formed at predetermined intervals. The width Lm7a of the wide portion of each light transmission region P4 is, for example, about 2.95 μm, the width Lm7b is, for example, about 3 μm, and the width Lm8 of the thin portion is, for example, about 1.4 μm. The interval Lm9a is, for example, about 2.9 μm, and the interval Lm9b is, for example, about 1.5 μm.

  By the way, in the first embodiment, for example, a square light shielding region S1 is arranged in the wide region of each light transmitting region P4. The dimension of the light shielding region S1 is, for example, about 0.2 μm × 0.2 μm, and the distance from the end of the wide region is, for example, about 1 μm.

  Further, an auxiliary pattern PA2 is arranged in the vicinity of the boundary region between the wide region and the narrow region of the light transmission region P4 in the surrounding light shielding region. This auxiliary pattern PA2 is a functional unit for preventing the transfer pattern portion corresponding to the boundary region from being thinned due to the fact that the areas of the wide region and the narrow region of one light transmission region P4 are significantly different. For example, it consists of a rectangular light transmission region.

  Note that the transmitted light is in reverse phase between the light transmission region P4 and the auxiliary pattern PA2 in the vicinity thereof. That is, the phase shifter PS4 is not disposed in the auxiliary pattern PA2 in the vicinity of the light transmission region P4 where the phase shifter PS4 is disposed. Further, the phase shifter PS4 is disposed in the auxiliary pattern PA2 in the vicinity of the light transmission region P4 where the phase shifter PS4 is not disposed.

  The dimension of each auxiliary pattern PA2 is, for example, about 0.1 μm × 0.2 μm. In addition, the distance Lm10 between each auxiliary pattern PA2 and the light transmission region P4 is equal in order to satisfactorily manipulate the phase of the transmitted light, and is set to about 0.1 μm, for example.

  The distribution of light transmitted through such a photomask PM4 is shown in FIG. A rectangular body LBL indicates a bit line BL (see FIG. 5) in the layout design stage, a rectangular body LPA indicates an auxiliary pattern PA2 (see FIG. 15) in the layout design stage, and a rectangular body LS1 indicates light shielding in the layout design stage. Region S1 (see FIG. 15) is shown. The curve shows the distribution of transmitted light.

  FIG. 18 shows a pattern transferred to a negative photoresist film by using such a photomask PM4. A hatched portion by a point is a portion where the photoresist film PR4 is left.

  In the first embodiment, the wide region and the narrow region of the light transmission region P4 (see FIG. 15) are transferred in a good shape. That is, in order to form a connection hole for the capacitor 5 (see FIG. 2) from the upper layer, a high alignment accuracy and a formation state of the bit line BL (see FIG. 5) that particularly requires pattern formation faithful to the design pattern It is possible to improve.

  The white portion is a portion where the photoresist film PR4 has been removed. Note that the photoresist film PR4 can be made positive so that the photoresist film remains in the white areas of FIG.

  FIG. 19 is a plan view of an essential part of the photomask PM5 used when forming the capacitor connection holes 9b1 and 9b2 (see FIGS. 2 and 6) in the memory cell region of the DRAM. 20 is a cross-sectional view taken along line XX-XX in FIG.

  In the photomask PM5, for example, a plurality of square light transmission regions P5 are regularly arranged. The dimension of the light transmission region P5 is, for example, about 1.8 μm × 1.8 μm.

  A phase shifter PS5 is disposed so as to overlap each light transmission region P5. The function, material and formation method of this phase shifter are the same as those of the phase shifter PS3 (see FIG. 13).

  Further, auxiliary patterns PA3a to PA3d are arranged in the vicinity of the four sides of each light transmission region PS5. The auxiliary patterns PA3a to PA3d increase the contrast of the edge portion of the transfer pattern by causing a phase difference between the light transmitted through the main light transmission region P5 and the light transmitted through the auxiliary patterns PA3a to PA3d. Thus, it is a functional portion that transfers a good pattern, and is composed of, for example, a rectangular light transmission region.

  However, the auxiliary patterns PA3a and PA3c between the light transmission regions P5 adjacent in the vertical direction in FIG. 19 are patterns common to both of the adjacent light transmission regions P5. The distance Lm11 between the light transmission regions P5 adjacent in the vertical direction in FIG. 19 is, for example, about 0.5 μm. The dimensions of the auxiliary patterns PA3a and PA3c are, for example, about 0.22 μm × 0.4 μm.

  Further, the lengths Lm12 and Lm13 of the light transmission regions P5 adjacent in the horizontal direction in FIG. 19 have different lengths, and the distance Lm13 is longer. The interval Lm12 is, for example, about 0.92 μm, and the interval Lm13 is, for example, about 1.04 μm.

  Of the distances Lm12 and Lm13, the auxiliary pattern PA3d arranged between the relatively narrow ones (Lm12) and the auxiliary pattern PA3b arranged between the relatively wide ones (Lm13) have a size. The auxiliary pattern PA3d is formed to be smaller.

  The dimension of the relatively small auxiliary pattern PA3d is, for example, about 0.32 μm × 0.16 μm, and the dimension of the relatively large auxiliary pattern PA3b is, for example, about 0.36 μm × 0.2 μm.

  For example, if an auxiliary pattern PA3b having a large size is arranged on the narrower interval Lm12 side, an original pattern corresponding to an interval between adjacent auxiliary patterns PA3b is formed by interference of light transmitted through the adjacent auxiliary pattern PA3b. This is to prevent unnecessary patterns from being formed in areas that should not be used.

  That is, in the first embodiment, unnecessary patterns are transferred by sharing auxiliary patterns PA3a to PA3d arranged on the four sides according to the arrangement state of the light transmission region P5 or changing dimensions. Therefore, the light transmission region P5 can be transferred, and the shape and size of the connection hole for the capacitor 5 can be formed as designed (including errors).

  The intervals Lm14 between the light transmission region P5 and the auxiliary patterns PA3a to PA3d are all set to the same value, for example, about 0.14 μm.

  FIG. 21 shows a pattern transferred to a positive photoresist film by such a photomask PM5. A hatched portion by a point is a portion where the photoresist film PR5 is left, and a square white portion is a portion where the photoresist film is removed. Note that by making the photoresist film negative, it is possible to leave the photoresist film in the white portions of FIG.

  Next, an example of an exposure apparatus used in an exposure process, which is a manufacturing process of the semiconductor integrated circuit device according to the first embodiment, will be described with reference to FIG.

  The exposure apparatus EX of the first embodiment is, for example, a lens type step-and-repeat 5: 1 reduction projection exposure apparatus, for example, Nikon i-line stepper NRS-1755i7A (for example, NA = 0.5, (Exposure area = 17.5 mm square).

  For example, a high-pressure mercury lamp is used as the exposure light source EX1. The exposure light emitted from the exposure light source EX1 is collected by the condensing mirror EX2 and applied to the first flat reflecting mirror EX3a.

  The exposure light applied to the first flat reflecting mirror EX3a is applied to the second flat reflecting mirror EX3b via the shutter EX4, the fly-eye lens EX5, the aperture EX6, and the shortcut filter EX7.

  The aperture EX6 is a component for adjusting the coherence factor σ. In the first embodiment, for example, σ = 0.3. The shortcut filter EX7 is a filter for cutting the far ultraviolet side having a shorter wavelength than the i-line when i-line (365 nm) is used as the exposure light.

  The exposure light applied to the second plane reflection EX3b is applied to the semiconductor wafer 1w through the mask blind EX8, the condenser lens EX9, the photomask PM, and the reduction projection lens (projection optical system) EX10.

  This mask blind EX8 is a component for setting the range of the transfer area and is detachable. The condenser lens EX10 is a lens for forming Koehler illumination.

  The photomask MA is a normal photomask in which the above-described photomasks PM1 to PM5 (FIGS. 8, 10, 13, 15, and 19) and the like and a phase shifter are not arranged. The photomask PM is placed in a removable state on the mask placement table EX11.

  The reduction projection lens EX10 is a bi-telecentric lens composed of a large number of lens groups. The semiconductor wafer 1w is made of, for example, a Si single crystal having a diameter of about 5 to 8 inches, and is placed on the wafer suction table EX12.

  A Z-axis moving table EX13a is installed below the wafer suction table EX12. The Z-axis moving table EX13a is a moving table for moving the semiconductor wafer 1w in the height direction, and is mechanically connected to the driving unit EX14a so that the moving operation is performed.

  An XY stage EX13b is installed below the Z-axis moving table EX13a. The XY stage EX13b includes an X-axis moving table 13b1 and a Y-axis moving table 13b2. The X-axis moving table 13b1 is a moving table that horizontally moves the semiconductor wafer 1w in the lateral direction of FIG. 1, and the Y-axis moving table EX13b2 is a moving table that horizontally moves the semiconductor wafer 1w in the front-rear direction of FIG. The X-axis moving table EX13b1 and the Y-axis moving table EX13b2 are mechanically connected to the drive units EX14b and EX14c, respectively, so that the moving operation is performed.

  The drive units EX14a to EX14c are electrically connected to the main control unit EX15, respectively, and their operations are controlled by the main control unit EX15. The main controller EX15 is a component for controlling the overall operation of the exposure apparatus EX.

  Next, a method for manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

First, as shown in FIG. 23, p ^- is subjected to thermal oxidation treatment to the surface of the semiconductor substrate 1s made of form Si single crystal, after forming an insulating film 16 made of, for example, SiO ₂ having a thickness of about 135A, the top surface Further, for example, an insulating film 17 made of silicon nitride having a thickness of about 1400 mm is deposited by a CVD method or the like.

  Subsequently, the insulating film 17 is patterned by removing a portion of the insulating film 17 located in the element isolation region by a photolithography technique and a dry etching technique. In this photolithography process, the mask PM1 shown in FIG. 8 is used.

Thereafter, a selective oxidation process is performed using the patterned insulating film 17 as a mask to form a field insulating film 2 for element isolation on the main surface of the semiconductor substrate 1s as shown in FIG. The field insulating film 2 is made of, for example, SiO ₂ and has a thickness of about 4000 mm.

  Note that FIG. 3 is a plan view of the memory cell region M after this processing.

  Next, after removing the insulating film 17 with a hot phosphoric acid solution or the like, using the photoresist as a mask, for example, p-type impurity boron is introduced into a predetermined position of the semiconductor substrate 1s by ion implantation, and the photoresist is removed. Then, a p-well 3p is formed by performing a thermal diffusion process on the semiconductor substrate 1s.

  Further, using a photoresist as a mask, for example, n-type impurity phosphorus is introduced into a predetermined position of the semiconductor substrate 1s by ion implantation, and after removing the photoresist, the semiconductor substrate 1s is subjected to a thermal diffusion process to thereby form an n-well. 3n is formed.

Next, after the insulating film 16 on the surface of the semiconductor substrate 1s is removed by etching with a hydrofluoric acid solution, an insulating film (not shown) made of SiO _{2 having a} thickness of, for example, about 100 mm is formed on the surface of the semiconductor substrate 1s.

  Thereafter, a predetermined impurity is ion-implanted into the main surface of the active region in order to obtain the threshold voltage of each MOS by optimizing the impurity concentration in the channel region.

  Next, as shown in FIG. 25, after the insulating film on the surface of the semiconductor substrate 1s is removed by etching with a hydrofluoric acid solution, the gate insulating film 4c of the selection MOS and the gate insulation of the MOS constituting the peripheral circuit are formed on the surface of the semiconductor substrate 1s. Films 14c and 15c are formed. The gate insulating film 4c is formed by, for example, a thermal oxidation method and has a thickness of about 90 mm.

Subsequently, as shown in FIG. 26, the upper surface of the semiconductor substrate 1, for example, phosphorus is sequentially deposited conductor film 18d2 made of a conductor film 18d1 and WSi ₂ made of low-resistance poly-silicon introduced. The conductor films 18d1 and 18d2 are formed by, for example, the CVD method, and the film thicknesses thereof are, for example, 700 mm and 1500 mm, respectively.

Thereafter, an insulating film 6a made of, for example, SiO ₂ and a cap insulating film 7a made of silicon nitride are sequentially deposited on the upper conductor film 18d2. The insulating film 6a and the cap insulating film 7a are formed by, for example, a CVD method.

  The insulating film 6a is a film for preventing the inside of the film forming apparatus from being contaminated with the constituent metal of the conductor film 18d2 when the cap insulating film 7a is formed, and relaxing the stress applied to the cap insulating film 7a during heat treatment or the like. The thickness is, for example, about 100 to 500 mm.

  The cap insulating film 7a is a film that functions as an etching stopper in a connection hole forming step described later, and has a thickness of, for example, about 2000 mm.

  Next, as shown in FIG. 27, by using the photoresist as a mask, the cap insulating film 7a, the insulating film 6a, and the conductor films 18d2 and 18d1 exposed from the photoresist are sequentially removed by etching, so that the memory cell region M and the peripheral area are removed. Gate electrodes 4d (word lines WL), 14d, and 15d are formed in the circuit region P.

  In the photolithography process, the photomask PM2 shown in FIG. 10 is used. Note that FIG. 4 is a plan view of the memory cell region M after this processing.

Subsequently, after removing the above-described photoresist, a thin insulating film 6b made of, for example, SiO ₂ is formed on the side surfaces of the gate electrodes 4d, 14d, and 15d by performing a thermal oxidation process on the semiconductor substrate 1s.

  Thereafter, as shown in FIG. 28, n-type impurity phosphorus and p-type impurity boron are ion-implanted into the nMOS formation region and the pMOS formation region in the peripheral circuit region P, respectively, using the gate electrodes 14d and 15d as masks. Semiconductor regions 14a1, 14b1, 15a1, 15b1 having impurity concentrations are formed.

  Next, phosphorus of an n-type impurity is ion-implanted into the selection MOS formation region of the memory cell region M using the gate electrode 4d as a mask, and the source region and the drain region of the selection MOS 4 are configured by extending and diffusing the n-type impurity. Semiconductor regions 4a and 4b are formed. Bit lines and capacitors are connected to semiconductor regions 4a and 4b, respectively.

  Subsequently, after an insulating film made of, for example, silicon nitride is deposited on the semiconductor substrate 1s by a CVD method, the insulating film is etched back by an anisotropic dry etching method such as RIE (Reactive Ion Etching). A sidewall 7b is formed on the side surface of the gate electrode 4d of the selection MOS 4.

  After such a sidewall 7b is formed, arsenic (As) is ion-implanted into the main surface of the p-well 3p at a higher concentration than the n-type impurity phosphorus described above, so that the source region of the selection MOS 4 and The drain region may have an LDD (Lightly Doped Drain) structure.

  After that, by implanting n-type impurity phosphorus and p-type impurity boron into the nMOS formation region and pMOS formation region of the peripheral circuit region P using the sidewall 7b as a mask, respectively, the semiconductor regions 14a2, 14b2, high impurity concentration 15a2 and 15b2 are formed. As a result, the nMOS 14 in the peripheral circuit region P and the semiconductor regions 14a, 14b, 15a, 15b of the pMOS 15 are formed.

Next, as shown in FIG. 29, after an interlayer insulating film 8a made of, for example, SiO _{2 is} deposited on the semiconductor substrate 1s by a CVD method or the like, an interlayer insulating film 8b made of, for example, BPSG or the like is formed on the interlayer insulating film 8a. Is deposited by CVD or the like.

  Subsequently, after the upper surface of the interlayer insulating film 8b is planarized by a chemical mechanical polishing (CMP) method, a mask made of low-resistance polysilicon into which, for example, phosphorus is introduced on the interlayer insulating film 8b. A film (first mask film) 10a is deposited by a CVD method or the like.

  Thereafter, by using the photoresist as a mask, the mask film 10a is patterned by a dry etching method or the like, thereby forming a pattern of the mask film 10a that opens above one semiconductor region 4b of the selection MOS 4.

  At this time, in the first embodiment, since the upper surface of the interlayer insulating film 8b underlying the mask film 10a is flattened, a sufficient photolithography margin can be ensured and good pattern transfer can be achieved. . In this photolithography process, the photomask PM5 shown in FIG. 18 is used. In the peripheral circuit region P, the entire upper surface of the interlayer insulating film 8b is covered with the mask film 10a.

  Here, the reason why the low resistance polysilicon is used as the mask film 10a is as follows. First, the etching selectivity with the silicon nitride film can be increased in the connection hole forming step for the capacitor 5 described later. Second, after the conductor film is buried in the connection hole, the lower mask film 10a can be removed at the same time when the conductor film is etched back.

  However, the constituent material of the mask film 10a is not limited to polysilicon, and can be variously changed. For example, silicon nitride may be used.

  Next, using the mask film 10a as an etching mask, the interlayer insulating films 8a and 8b exposed from the mask film 10a are removed by, for example, dry etching, thereby exposing the semiconductor region 4b of the selection MOS 4 as shown in FIG. Such a connection hole (first capacitor connection hole) 9b1 is formed. The diameter of the connection hole 9b1 is, for example, about 0.36 μm.

  At this time, in the first embodiment, since the cap insulating film 7a and the sidewall 7b are formed of silicon nitride, the cap insulating film 7a and the side wall 7b can be formed by setting a high selection ratio with respect to silicon nitride in the dry etching process. The sidewall 7b serves as an etching stopper, and the fine connection hole 9b1 can be formed with high alignment accuracy in a self-aligning manner.

  For example, even if the position of the opening of the mask film 10a is slightly shifted in the width direction of the word line WL (left and right direction in FIG. 30), the cap insulating film 7a and the sidewall 7b are made of silicon nitride so as to function as an etching stopper. Therefore, a part of the word line WL is not exposed from the connection hole formed using the mask film as an etching mask.

  Further, even if the position of the opening of the mask film 10a is shifted in the extending direction of the word line WL, in that case, the thickness of the lower field insulating film 2 is sufficiently thick, so that the mask film is used as an etching mask. The formed connection hole does not reach the top of the semiconductor substrate 1s.

  Therefore, in the first embodiment, since the alignment margin of the connection hole 9b1 that has been secured by taking into account the misalignment can be reduced, the area of the memory cell region M can be reduced. It has become.

The dry etching conditions at this time are as follows, for example. The selection ratio is, for example, 10-15. The reaction gas is, for example, C ₄ F ₈ / CF ₄ / CO / Ar gas, which is about 3/5/200/550 sccm, for example. The pressure is about 100 mTorr, for example, and the high frequency power (RF Power) is about 1000 watts, for example. The processing temperature is, for example, about 20/60 / −10 degrees for each of the upper electrode / wall surface / lower electrode.

  Subsequently, as shown in FIG. 31, after depositing a conductor film 13 made of, for example, low-resistance polysilicon into which phosphorus is introduced on the semiconductor substrate 1s by a CVD method or the like, the conductor film 13 is formed by a dry etching method or the like. By etching back, as shown in FIG. 32, the conductor film 13 is embedded only in the connection hole 9b1. During this etch-back process, the underlying mask film 10a (see FIG. 31) is also removed.

Thereafter, as shown in FIG. 33, an interlayer insulating film 8c made of, for example, SiO ₂ is deposited on the semiconductor substrate 1s by a CVD method or the like. The thickness of this interlayer insulating film 8c is, for example, about 500 to 1000 mm.

  Next, a mask film 10b made of, for example, low-resistance polysilicon is deposited on the interlayer insulating film 8c by the CVD method or the like. The thickness of the mask film 10b is, for example, about 3000 to 6000 mm.

  Subsequently, using the photoresist as a mask, the mask film 10b is patterned by dry etching. As a mask used in this photolithography process, the photomask PM3 shown in FIG. 13 is used.

  By this process, after opening the upper part of the semiconductor region 4a in the mask film 10b, the interlayer insulating films 8a to 8c in the region exposed from the opening are removed by dry etching.

  Thereby, as shown in FIG. 34, a connection hole 9a1 is formed so that the semiconductor region 4a of the selection MOS 4 is exposed. The diameter of the connection hole 9a1 is, for example, about 0.36 μm.

  At this time, in the first embodiment, since the cap insulating film 7a and the sidewall 7b are formed of silicon nitride, the cap insulating film 7a and the side wall 7b can be formed by setting a high selection ratio with respect to silicon nitride in the dry etching process. The sidewall 7b serves as an etching stopper, and the fine connection hole 9a1 can be formed with high alignment accuracy in a self-aligning manner.

  For example, even if the position of the opening of the mask film 10b is slightly shifted in the width direction of the word line WL (left and right direction in FIG. 34), the cap insulating film 7a and the sidewall 7b are made of silicon nitride so as to function as an etching stopper. Therefore, a part of the word line WL is not exposed from the connection hole formed using the mask film as an etching mask.

  Further, even if the position of the opening of the mask film 10b is shifted in the extending direction of the word line WL, in that case, the thickness of the field insulating film 2 below is sufficiently thick, so that the mask film is used as an etching mask. The formed connection hole does not reach the top of the semiconductor substrate 1s.

  Therefore, in the first embodiment, the alignment margin of the connection hole 9a1 that has been secured by taking into account the misalignment can be reduced, so that the area of the memory cell region M can be reduced. It has become.

The dry etching process conditions at this time are as follows, for example. The selection ratio is, for example, 10-15. The reaction gas is, for example, C ₄ F ₈ / CF ₄ / CO / Ar gas, which is about 3/5/200/550 sccm, for example. The pressure is about 100 mTorr, for example, and the high frequency power (RF Power) is about 1000 watts, for example. The processing temperature is, for example, about 20/60 / −10 degrees for each of the upper electrode / wall surface / lower electrode.

Thereafter, as shown in FIG. 35, on the resulting semiconductor substrate 1s, for example, a conductor film BL2 made of a conductor film BL1 and WSi ₂ phosphorus made of low-resistance poly-silicon introduced sequentially deposited by CVD method or the like, followed by An insulating film 6c made of SiO ₂ and a cap insulating film 11a made of silicon nitride are sequentially deposited on the conductor film BL2 by a CVD method or the like. The cap insulating film 11a has a thickness of about 2000 mm, for example.

  Next, a photoresist 19a is formed on the cap insulating film 11a so as to cover the bit line formation region. The mask used in this photolithography process is the photomask PM4 shown in FIG.

  Subsequently, using the photoresist 19a as an etching mask, the cap insulating film 11a, the insulating film 6c, the conductor films BL2 and BL1, and the mask film 10b exposed from the mask are sequentially removed by etching.

  As a result, as shown in FIG. 36, the bit line BL including the conductor films BL1 and BL2 and the mask film 10b is formed. The bit line BL is electrically connected to one semiconductor region 4a of the selection MOS 4 through the connection hole 9a1. The plan view in the memory cell region M after this processing is shown in FIG.

Subsequently, after removing the photoresist 19a (see FIG. 35), the semiconductor substrate 1 is subjected to a thermal oxidation process, so that the conductor films BL1, BL2 constituting the bit line BL as shown in FIG. A thin insulating film 6d made of, for example, SiO ₂ is formed on the side surface of the mask film 10b.

  Thereafter, an insulating film made of, for example, silicon nitride is deposited on the semiconductor substrate 1s by a CVD method, and then the insulating film is etched away by an anisotropic dry etching method such as RIE, so that the side surface of the bit line BL is formed on the side surface. A wall 11b is formed.

  Next, an insulating film 12 made of, for example, silicon nitride having a thickness of about 100 to 500 mm, preferably about 250 mm, is deposited on the semiconductor substrate 1s by a CVD method. This insulating film 12 has a function as an etching stopper in a wet etching removing process of the base insulating film after the capacitor forming process described later.

Subsequently, as shown in FIG. 38, an insulating film 20 made of, for example, SiO ₂ is deposited on the semiconductor substrate 1s by the CVD method, and then the upper surface of the insulating film 20 is planarized by, for example, the CMP method.

  Thereafter, a mask film 10c made of, for example, low-resistance polysilicon into which phosphorus is introduced is deposited on the semiconductor substrate 1s by a CVD method. In this case, the thickness of the mask film 10c is, for example, about 500 to 2000 mm.

  Next, a capacitor connection part formation region is opened in the mask film 10c by a photolithography technique and a dry etching technique. The mask used at this time is the photomask PM5 shown in FIG.

  Subsequently, by using the mask film 10c as an etching mask, the insulating film 20, the insulating film 12, and the interlayer insulating film 8b in the regions exposed from the mask film 10c are removed by etching, thereby forming the conductor film 13 as shown in FIG. A connection hole 9b2 is formed so as to reach. The diameter of the connection hole 9a2 is, for example, about 0.36 μm.

  At this time, in the first embodiment, since the cap insulating film 11a and the sidewall 11b covering the bit line BL are formed of silicon nitride, the selection ratio with respect to silicon nitride in the dry etching process is set high. The cap insulating film 11a and the sidewall 11b serve as an etching stopper, and a fine connection hole (second capacitor connection hole) 9b2 can be formed in a self-aligning manner with high alignment accuracy.

  Here, FIG. 40 shows a plan view of the main part of the memory cell region M at this stage, and FIGS. 41 and 42 show cross-sectional views taken along lines XXXXI-XXXXI and XXXXII-XXXXII.

  In the case of the first embodiment, for example, even if the position of the opening of the mask film 10c is slightly shifted in the width direction of the bit line BL (up and down direction in FIG. 40), as can be seen from FIG. Since the sidewall 11b is made of silicon nitride and functions as an etching stopper, a part of the bit line BL is not exposed from a connection hole formed using the mask film as an etching mask.

  Further, even if the position of the opening of the mask film 10c is shifted in the extending direction of the bit line BL (left and right direction in FIG. 40), in that case, as shown in FIG. 41, the lower word line WL is covered. Since the cap insulating film 7a and the sidewall 7b to be formed are made of silicon nitride and function as an etching stopper, the word line WL is not exposed from the connection hole formed using the mask film as an etching mask.

  That is, in the first embodiment, as shown in FIG. 40, the capacitor connection holes 9b1 and 9b2 (see FIG. 39) are positioned within the region A surrounded by the word line WL and the bit line BL. To be formed. Note that a region B in FIG. 40 shows the formation range of the connection holes 9b1 and 9b2 in consideration of other alignment margins such as an alignment margin range in consideration of alignment with the element isolation region.

The dry etching process conditions at this time are as follows, for example. The selection ratio is, for example, 10-15. The reaction gas is, for example, C ₄ F ₈ / CF ₄ / CO / Ar gas, which is about 3/5/200/550 sccm, for example. The pressure is about 100 mTorr, for example, and the high frequency power (RF Power) is about 1000 watts, for example. The processing temperature is, for example, about 20/60 / −10 degrees for each of the upper electrode / wall surface / lower electrode.

Next, after depositing a conductive film having a thickness of about 500 to 1000 mm made of, for example, low-resistance polysilicon into which phosphorus is introduced on the mask film 10c, an upper surface having a thickness of about 3000 to 6000 mm made of, for example, SiO ₂ is deposited. An insulating film is deposited by a plasma CVD method or the like.

  The conductor film is also deposited in the connection holes 9b1 and 9b2, and is electrically connected to the other semiconductor region 4b of the selection MOS 4 through the conductor film 13.

  In addition, the insulating film on the conductor film is formed of an insulating film having a higher etch rate in the wet etching process than the insulating film 20 made of the lower BPSG. This is because, when the etching rate of the insulating film is lower than that of the insulating film 20, when the insulating film and the insulating film 20 are removed at the same time in a later step, the insulating film becomes a narrow depression at the center of the first electrode 5a. This is because the insulating film 20 is removed before the insulating film is sufficiently removed, which may adversely affect the underlying elements.

  Subsequently, in the insulating film, the conductor film, and the mask film 10c, a portion exposed from the photoresist is etched away by a dry etching method or the like, so that a lower portion 5a1 of the first electrode 5a of the capacitor and An insulating film 21 is formed.

  Then, after depositing a conductor film made of low-resistance polysilicon on the semiconductor substrate 1s by the CVD method, the conductor film is etched back by an anisotropic dry etching method such as RIE, as shown in FIG. Then, the side portion 5a2 of the first electrode 5a of the capacitor is formed on the side surface of the insulating film 21.

  Next, the insulating films 20 and 21 are removed by wet etching using, for example, a hydrofluoric acid solution, thereby forming the first electrode 5a of the cylindrical capacitor as shown in FIG. At this time, since the insulating film 12 formed on the interlayer insulating film 8c functions as a wet etching stopper, the underlying interlayer insulating film 8c is not removed.

Subsequently, after a silicon nitride film (not shown) is deposited on the semiconductor substrate 1s by a CVD method, the silicon nitride film is subjected to an oxidation treatment, thereby forming the surface of the silicon nitride film as shown in FIG. forming a SiO ₂ film to form a capacitor insulating film 5b made of a silicon film and a SiO ₂ film nitride.

  Thereafter, a conductive film made of, for example, low-resistance polysilicon is deposited on the semiconductor substrate 1s by the CVD method, and the conductive film is etched using the photoresist as a mask to form the second electrode 5c of the capacitor 5, Capacitor 5 is formed.

Then, on the resulting semiconductor substrate 1s, for example, after an interlayer insulating film 8d1 made of SiO ₂ is deposited by CVD method or the like, deposited thereon the interlayer insulating film 8d1, for example an interlayer insulating film 8d2 made of BPSG or the like, the interlayer insulating The upper surface of the film 8d2 is planarized by, eg, CMP.

  Then, it transfers to a wiring formation process. This wiring formation process will be described with reference to FIGS. 47 to 50 are cross-sectional views of the main part of the same DRAM, although a cross section of a portion different from that of FIGS. 23 to 46 is shown to explain the wiring forming process.

First, as shown in FIG. 47, an interlayer insulating film 8e made of, for example, SiO ₂ is deposited on the semiconductor substrate 1s by a CVD method or the like. Thereby, the capacitor 5 is covered.

  Subsequently, a connection hole 22a is formed in the interlayer insulating film 8e using the photoresist as a mask so that the pad portion of the second electrode 5c of the capacitor 5 is exposed, and one of the MOS / FETs 23 in the peripheral circuit region P is formed. A connection hole 22b that exposes the semiconductor region 23a is formed by dry etching.

  Thereafter, a conductor film made of, for example, titanium (Ti) is deposited on the semiconductor substrate 1s by a sputtering method or the like, and then a conductor film made of, for example, tungsten or the like is deposited on the upper surface by a CVD method or the like. For example, a conductive film made of titanium nitride (TiN) or the like is deposited by a sputtering method or the like.

  Next, the multilayer conductor film is patterned by a dry etching method or the like using a photoresist as a mask, thereby forming a first layer wiring 24a as shown in FIG.

Subsequently, an interlayer insulating film 8f made of, for example, SiO _{2 is} deposited on the semiconductor substrate 1s by a CVD method or the like to cover the first layer wiring 24a, and then the interlayer insulating film 8f is dry-etched using a photoresist as a mask. By performing the processing, a connection hole 22c is formed so that a part of the first layer wiring 24a is exposed.

  Thereafter, as shown in FIG. 49, the second layer wiring 24b is formed on the interlayer insulating film 8f. The second layer wiring 24b is formed as follows, for example.

  First, after depositing a conductor film made of tungsten or the like by a CVD method or the like, a conductor film made of aluminum (Al) or the like is deposited on the upper surface by a sputtering method, and further on the upper surface, for example made of TiN or the like. A conductor film is deposited by sputtering. Thereafter, the laminated conductor film is formed by patterning similarly to the first layer wiring 24a.

Next, an interlayer insulating film 8g made of, for example, SiO _{2 is} deposited on the interlayer insulating film 8f by a CVD method or the like to cover the second layer wiring 24b, and then dry etching is performed on the interlayer insulating film 8g using a photoresist as a mask. By performing the treatment, a connection hole 22d is formed so that the second layer wiring 24b is exposed.

  Subsequently, as shown in FIG. 50, a third layer wiring 24c is formed on the interlayer insulating film 8g. The third layer wiring 24c is formed of the same material and the same method as the second layer wiring 24b.

Finally, a surface protection film 25 made of, for example, SiO _{2 is} deposited on the semiconductor substrate 1s by a CVD method or the like, and the third layer wiring 24c is covered, thereby completing the wafer process of the DRAM of the first embodiment. .

Thus, according to the first embodiment, the following effects can be obtained.
(1). By making the interval between the light transmission regions P2 for transferring word lines adjacent to each other constant in each interval line, the phase difference operation of the light transmitted through the light transmission regions P2 adjacent to each other is performed. It is possible to perform as well as designed (including errors) in the entire region between the two light transmission regions P2. As a result, the shape and dimensions of the transfer pattern (word line WL) can be formed as designed (including errors).
(2). The phase difference operability of the light transmitted through the light transmission regions P2 adjacent to each other by equalizing the interval between the light transmission regions P2 for transferring word lines adjacent to each other and the width of the narrow portion of the light transmission region P2 Therefore, the fidelity of the shape and dimensions of the transfer pattern (word line WL) can be improved.
(3) A fine light-shielding region S1 is arranged in the wide region of each light transmission region P4 for bit line formation, and the boundary region between the wide region and the narrow region of the light transmission region P4 in the surrounding light-shielding region By arranging the auxiliary pattern PA2 in the vicinity of the light transmission region P4, it is possible to suppress a large variation in the transmitted light due to the difference in the area ratio between the wide region and the narrow region of the light transmission region P4. It is possible to transfer the wide area and the narrow area as well (including errors) as designed. As a result, the shape and dimensions of the transfer pattern (bit line BL) can be formed as designed (including errors).
(4) Depending on the arrangement state of the light transmission region P5 for forming the connection hole for the capacitor 5, the auxiliary patterns PA3a to PA3d arranged on the four sides are shared or the dimensions are changed, which is useless. It is possible to transfer the light transmission region P4 satisfactorily without transferring the pattern. As a result, the shape and dimensions of the connection holes 9b1 and 9b2 for the capacitor 5 can be formed as designed (including errors).
(5) By the above (1) to (4), the alignment margin between the predetermined layers can be reduced, so that the dimensions of the semiconductor chip constituting the semiconductor integrated circuit device can be reduced.
(6) Since the alignment accuracy between the predetermined layers can be improved by the above (1) to (4), the yield and reliability of the semiconductor integrated circuit device can be improved.

(Embodiment 2)
FIG. 51 is a fragmentary cross-sectional view of a memory cell region of a semiconductor integrated circuit device according to another embodiment of the present invention.

  The semiconductor integrated circuit device of the second embodiment shown in FIG. 51 shows a case where the burying conductor film shown in the first embodiment is not provided in the connection hole 9b1 for the capacitor 5.

  The connection hole 9b1 in this case is formed as follows, for example. First, as in the first embodiment, the bit line BL, the insulating films 6c and 6d covering the bit line BL, the cap insulating film 11a, the sidewall 11b, and the insulating film 12 are formed.

  Subsequently, after depositing an insulating film on the insulating film 12, the upper surface of the insulating film is planarized. Thereafter, a mask film 10b made of, for example, low-resistance polysilicon is deposited on the insulating film.

  Thereafter, the mask film 10b is patterned in the same manner as in the first embodiment. The photomask used in this case is the photomask PM5 shown in FIG.

  Next, by using the patterned mask film 10b as a mask, a connection hole 9b1 through which the semiconductor region 4b on the semiconductor substrate 1s is exposed is formed by dry etching in the insulating film, the insulating film 12, and the interlayer insulating films 8a to 8c. Perforate.

  At this time, also in the second embodiment, the cap insulating film 7a and the sidewall 7b covering the word line WL, and the cap insulating film 11a and the sidewall 11b covering the bit line BL are formed of silicon nitride. The connection hole 9b1 can be formed in a self-aligning manner.

  Such a method of manufacturing a semiconductor integrated circuit device according to the second embodiment can obtain the same effects as those of the first embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the first and second embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first and second embodiments, the case where the step-and-repeat type exposure apparatus is used has been described. However, the present invention is not limited to this. It is also possible to use a so-called step-and-scan type exposure apparatus in which the mask (reticle) and the exposure stage are exposed (scanned) while moving at a predetermined speed ratio after being moved (stepped) downward.

  In the first and second embodiments, the case where the capacitor of the memory cell is cylindrical has been described. However, the present invention is not limited to this and can be variously modified. For example, a fin shape may be used.

  In the first and second embodiments, the case where the bit line is formed by providing the silicide layer on the low resistance polysilicon has been described. However, the present invention is not limited to this. For example, the bit line is formed only by the silicide layer. May be. In this case, the bit line BL can be thinned.

  In the above description, the case where the invention made mainly by the present inventor is applied to a DRAM having a COB structure which is a field of use as a background thereof has been described. However, the present invention is not limited thereto, and various applications are possible. Ordinary DRAM, SRAM (Static RAM), ROM (Read Only Memory) provided with a capacitor below the bit line, logic circuit or other semiconductor integrated circuit device provided with a semiconductor memory circuit and a logic circuit on the same semiconductor substrate Applicable to etc.

  The present invention can be applied to the manufacturing industry of semiconductor integrated circuit devices.

1 is a circuit block diagram showing a configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a fragmentary cross-sectional view of a memory cell region of the semiconductor integrated circuit device of FIG. 1. FIG. 3 is a plan view of a principal part in an active region layer of the memory cell region of FIG. 2. FIG. 3 is a plan view of a main part in a word line layer in the memory cell region of FIG. 2. FIG. 3 is a plan view of a main part in a bit line layer in the memory cell region of FIG. 2. FIG. 3 is a plan view of a main part in a capacitor first electrode layer in the memory cell region of FIG. 2. FIG. 2 is a fragmentary cross-sectional view of a peripheral circuit region of the semiconductor integrated circuit device of FIG. 1. FIG. 2 is a plan view of a principal part of a photomask used in an exposure process that is a manufacturing process of the semiconductor integrated circuit device of FIG. 1. It is a top view of the pattern transcribe | transferred with the photomask of FIG. FIG. 2 is a plan view of a principal part of a photomask used for transferring a word line pattern in an exposure process which is a manufacturing process of the semiconductor integrated circuit device of FIG. 1. It is sectional drawing of the XI-XI line of FIG. It is a top view of the pattern transcribe | transferred with the photomask of FIG. FIG. 2 is a plan view of a main part of a photomask used when transferring a connection hole pattern for a bit line in an exposure process which is a manufacturing process of the semiconductor integrated circuit device of FIG. 1. It is a top view of the pattern transcribe | transferred with the photomask of FIG. FIG. 2 is a plan view of a principal part of a photomask used for transferring a bit line pattern in an exposure process which is a manufacturing process of the semiconductor integrated circuit device of FIG. 1. (A) is sectional drawing of the XVIa-XVIa line | wire of FIG. 15, (b) is sectional drawing of the XVIb-XVIb line | wire of FIG. It is explanatory drawing explaining distribution of the transmitted light at the time of using the photomask of FIG. It is a top view of the pattern transcribe | transferred with the photomask of FIG. FIG. 2 is a plan view of a main part of a photomask used for transferring a capacitor connection hole pattern in an exposure process which is a manufacturing process of the semiconductor integrated circuit device of FIG. 1. It is sectional drawing of the XIX-XIX line | wire of FIG. FIG. 20 is a plan view of a pattern transferred by the photomask of FIG. 19. FIG. 2 is an explanatory diagram of a configuration of an exposure apparatus used in an exposure process that is a manufacturing process of the semiconductor integrated circuit device of FIG. 1. FIG. 2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during the manufacturing process thereof. FIG. 24 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 23; FIG. 25 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 24; FIG. 26 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 25; FIG. 27 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 26; FIG. 28 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 27; FIG. 29 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during the manufacturing process following that of FIG. 28; FIG. 30 is a main-portion cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during the manufacturing process following that of FIG. 29; FIG. 31 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step subsequent to FIG. 30; FIG. 32 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 31; FIG. 33 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during the manufacturing process following that of FIG. 32; FIG. 34 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 33; FIG. 35 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 34; FIG. 36 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 35; FIG. 37 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 36; FIG. 38 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 37; FIG. 39 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 38; FIG. 40 is a substantial part plan view of the semiconductor integrated circuit device of FIG. 1 during the manufacturing process of FIG. 39; It is sectional drawing of the XXXXI-XXXXI line | wire of FIG. It is sectional drawing of the XXXXII-XXXXII line | wire of FIG. FIG. 40 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 39; 44 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 43; FIG. FIG. 45 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 44; FIG. 46 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 45; FIG. 47 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 46; FIG. 48 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 47; FIG. 49 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 48; FIG. 50 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 49; It is principal part sectional drawing of the memory cell area | region of the semiconductor integrated circuit device which is the other Example of this invention.

Explanation of symbols

1s semiconductor substrate 1w semiconductor wafer 2 field insulating film 3p p well 3n n well 4 memory cell selection MOS / FET
4a, 4b Semiconductor region 4c Gate insulating film 4d Gate electrode 4d1, 4d2 Conductor film 5 Capacitor 5a First electrode (third conductor film)
5b Capacitor insulating film 5c Second electrodes 6a to 6d Insulating film 7a Cap insulating film (first cap insulating film)
7b Side wall (first side wall insulating film)
8a-8g Interlayer insulating film 8d1, 8d2 Insulating film 9a1 Connection hole 9b1 Connection hole (first capacitor connection hole)
9b2 connection hole (second capacitor connection hole)
10a Mask film (first mask film)
10b Mask film (second mask film)
10c Mask film (third mask film)
11a Cap insulating film (second cap insulating film)
11b Side wall (second side wall insulating film)
12 Insulating film 13 Conductor film (first conductor film)
14 n-channel MOS FET
14a, 14b Semiconductor region 14c Gate insulating film 14d Gate electrodes 14d1, 14d2 Conductor film 15 P channel type MOS-FET
15a, 15b Semiconductor region 15c Gate insulating film 15d Gate electrodes 15d1, 15d2 Conductor film 16 Insulating film 17 Insulating films 18d1, 18d2 Conductor film 19a Photoresist 20 Insulating film 21 Insulating films 22a-22d Connection hole 23 MOS / FET
23a Semiconductor region 24a First layer wiring 24b Second layer wiring 24c Third layer wiring M Memory cell region P Peripheral circuit region A Active region MC Memory cell Qs Memory cell selection MOS / FET
C capacitor WL word line BL bit line BL1, BL2 conductor film (second conductor film)
SA sense amplifier circuit CD column decoder circuit I / O data input / output signal wiring DOL data output signal wiring YSL column selection signal wiring DOB data output buffer circuit Dout output terminal VDD power supply voltage P1 to P5 light transmission region PM, PM1 to PM5 photomask PS1 to PS5 Phase shifters PR1 to PR5 Photoresist films PA1, PA2, PA3a to PA3d Auxiliary pattern S1 Light-shielding area EX Exposure device EX1 Exposure light source EX2 Condensing mirror EX3a First plane reflector EX3b Second plane reflector EX4 Shutter EX5 Fly eye Lens EX6 Aperture EX7 Shortcut filter EX8 Mask blind EX9 Condenser lens EX10 Reduction projection lens (projection optical system)
EX11 Mask mounting table EX12 Wafer suction table EX13a Z-axis moving table EX13b XY stage EX13b1 X-axis moving table EX13b2 Y-axis moving table EX14a to EX14c Drive unit EX15 Main control unit

Claims (5)

A method for manufacturing a semiconductor integrated circuit device comprising a wiring having a wide region and a narrow region on a semiconductor substrate, the method comprising the following steps:
(A) a step of depositing a conductive film for wiring formation on the semiconductor substrate and then depositing a photoresist film on the conductive film;
(B) A photomask provided for transferring the wiring and having a light transmission region having a wide region and a narrow region, wherein a light shielding region is formed in a part of the wide region of the light transmission region. And in the light shielding area surrounding the light transmission area, light having a phase opposite to that of the light transmitted through the light transmission area is formed in the vicinity of the boundary area between the wide area and the narrow area of the light transmission area. A step of preparing a photomask having an auxiliary pattern made of such a fine light transmission region,
(C) transferring the pattern of the wiring by irradiating the photoresist film with exposure light through the photomask;
(D) forming the wiring by patterning the wiring forming conductor film using the wiring pattern transferred to the photoresist film as a mask; A DRAM comprising a word line constituting a gate electrode of a memory cell selection MISFET on a semiconductor substrate, and a bit line which is arranged on the upper layer of the word line so as to be orthogonal to the extending direction of the word line A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) depositing a conductor film for forming a bit line on the semiconductor substrate and then depositing a photoresist film on the conductor film;
(B) A function that is provided for transferring the bit line, includes a plurality of light transmission regions having a wide region and a narrow region, and the light transmitted through the light transmission regions adjacent to each other has a reverse phase. A photomask having a light shielding region disposed in a part of the wide region of the light transmission region, and a boundary between the wide region of the light transmission region and the narrow region in the light shielding region surrounding the light transmission region A step of preparing a photomask in which an auxiliary pattern composed of a fine light transmission region that forms light having a phase opposite to that of light transmitted through the light transmission region is disposed in the vicinity of the region;
(C) irradiating the photoresist film with exposure light through the photomask, thereby transferring the bit line pattern;
(D) forming the bit line by patterning the bit line forming conductor film using the bit line pattern transferred to the photoresist film as a mask; A word line that constitutes a gate electrode of a memory cell selection MISFET formed on a semiconductor substrate; and a bit line that is disposed on the upper layer of the word line so as to be orthogonal to the extending direction of the word line. A method of manufacturing a semiconductor integrated circuit device having a DRAM having a memory cell having a capacitor over bit line structure in which a capacitor for storing information is provided on an upper layer of the bit line, comprising the following steps: Manufacturing method of semiconductor integrated circuit device characterized by:
(A) forming a word line by patterning the conductive film after depositing a conductive film for forming a word line on the semiconductor substrate;
(B) a step of covering the upper surface and side surfaces of the word line with a first cap insulating film and a first sidewall insulating film made of silicon nitride;
(C) forming a first insulating film having a flat upper surface made of a material having an etching rate higher than that of the silicon nitride on the semiconductor substrate, and covering the first cap insulating film and the first sidewall insulating film; ,
(D) After depositing a second mask film made of a material having an etching rate slower than that of the first insulating film on the upper surface of the first insulating film, between the adjacent word lines in the second mask film. Opening a formation region of the bit line connection hole located;
(E) A bit line connection hole that exposes one semiconductor region of the memory cell selection MISFET by etching away the first insulating film portion exposed from the opening region of the second mask film. Drilling in a state defined in a self-aligned manner by one cap insulating film and a first sidewall insulating film;
(F) depositing a second conductive film on the semiconductor substrate after forming the bit line connection hole, and then depositing a photoresist film on the second conductive film;
(G) A function that is provided for transferring the bit line, includes a plurality of light transmission regions having a wide region and a narrow region, and the light transmitted through the light transmission regions adjacent to each other has a reverse phase. A photomask having a light shielding region disposed in a part of the wide region of the light transmission region, and a boundary between the wide region of the light transmission region and the narrow region in the light shielding region surrounding the light transmission region A step of preparing a photomask in which an auxiliary pattern composed of a fine light transmission region that forms light having a phase opposite to that of light transmitted through the wide region is disposed in the vicinity of the region;
(H) transferring the pattern of the bit line by irradiating the photoresist film with exposure light through the photomask;
(I) A step of forming the bit line by patterning the second conductor film using the bit line pattern transferred to the photoresist film as a mask. A word line that constitutes a gate electrode of a memory cell selection MISFET formed on a semiconductor substrate; and a bit line that is disposed on the upper layer of the word line so as to be orthogonal to the extending direction of the word line. A method of manufacturing a semiconductor integrated circuit device having a DRAM having a memory cell having a capacitor over bit line structure in which a capacitor for storing information is provided on an upper layer of the bit line, comprising the following steps: Manufacturing method of semiconductor integrated circuit device characterized by:
(A) depositing a conductor film for forming word lines on the semiconductor substrate, and then depositing a first photoresist film on the conductor film;
(B) Provided with a plurality of light transmission regions extending in parallel to each other provided to transfer the word line pattern, and the light transmitted through the light transmission regions adjacent to each other is in reverse phase A first photomask having a function, wherein a first light-shielding region is provided between the adjacent light-transmitting regions so as to always form a constant interval along the extending direction of the light-transmitting regions. Preparing a photomask,
(C) transferring the word line pattern to the first photoresist film by irradiating exposure light through the first photomask;
(D) forming a word line by patterning the conductive film for word line formation using the pattern of the word line transferred to the first photoresist film as a mask;
(E) a step of covering the upper surface and side surfaces of the word line with a first cap insulating film and a first sidewall insulating film made of silicon nitride;
(F) forming a first insulating film having a flat upper surface made of a material having an etching rate higher than that of the silicon nitride on the semiconductor substrate, and covering the first cap insulating film and the first sidewall insulating film; ,
(G) After depositing a second mask film made of a material whose etching rate is slower than that of the first insulating film on the upper surface of the first insulating film, between the adjacent word lines in the second mask film. Opening a formation region of a bit line connection hole located;
(H) A bit line connection hole that exposes one semiconductor region of the memory cell selection MISFET by etching away the first insulating film portion exposed from the opening region of the second mask film. Drilling in a state defined in a self-aligned manner by one cap insulating film and a first sidewall insulating film;
(I) depositing a second photoresist film on the second conductor film after depositing a second conductor film on the semiconductor substrate after forming the bit line connection hole;
(J) A function that is provided for transferring the bit line, includes a plurality of light transmission regions having a wide region and a narrow region, and the light transmitted through the light transmission regions adjacent to each other has a reverse phase. A second photomask having a light shielding region disposed in a part of the wide region of the light transmissive region, and in the light shielding region surrounding the light transmissive region, a wide region and a narrow region of the light transmissive region; A step of preparing a second photomask in which an auxiliary pattern including a fine light transmission region is arranged in the vicinity of the boundary region of
(K) transferring the bit line pattern to the second photoresist film by irradiating exposure light through the second photomask;
(L) forming the bit line by patterning the second conductor film using the bit line pattern transferred to the second photoresist film as a mask; A word line that constitutes a gate electrode of a memory cell selection MISFET formed on a semiconductor substrate; and a bit line that is disposed on the upper layer of the word line so as to be orthogonal to the extending direction of the word line. A method of manufacturing a semiconductor integrated circuit device having a DRAM having a memory cell having a capacitor over bit line structure in which a capacitor for storing information is provided on an upper layer of the bit line, comprising the following steps: Manufacturing method of semiconductor integrated circuit device characterized by:
(A) depositing a word line forming conductor film on the semiconductor substrate and then depositing a photoresist film on the conductor film;
(B) Provided with a plurality of light transmission regions extending in parallel to each other provided to transfer the word line pattern, and the light transmitted through the light transmission regions adjacent to each other is in reverse phase A photomask having a function, wherein a light-shielding region is provided between the adjacent light-transmitting regions so as to always form a constant interval along the extending direction of the light-transmitting regions. The process of
(C) transferring the word line pattern to the photoresist film by irradiating exposure light through the photomask;
(D) forming a word line by patterning the word line forming conductor film using a pattern of the word line transferred to the photoresist film as a mask;
(E) a step of covering the upper surface and side surfaces of the word line with a first cap insulating film and a first sidewall insulating film made of silicon nitride;
(F) forming a first insulating film having a flat upper surface made of a material having an etching rate higher than that of the silicon nitride on the semiconductor substrate, and covering the first cap insulating film and the first sidewall insulating film; ,
(G) After depositing a first mask film made of a material whose etching rate is slower than that of the first insulating film on the upper surface of the first insulating film, between the adjacent word lines in the first mask film. Opening a first capacitor connection hole forming region located;
(H) A first capacitor connection hole that exposes one semiconductor region of the memory cell selection MISFET by etching away the first insulating film portion exposed from the opening region of the first mask film, Drilling in a state defined in a self-aligned manner by the first cap insulating film and the first sidewall insulating film;
(I) A first conductor film is deposited on the semiconductor substrate after the first capacitor connection hole is formed, and then the first conductor film is etched back so that the first capacitor connection hole is formed in the first capacitor connection hole. Embedding a first conductor film;
(J) a step of depositing a second insulating film on the first insulating film after the step of filling the first conductive film;
(K) After depositing a second mask film made of a material having an etching rate slower than that of the first insulating film and the second insulating film on the second insulating film, the second mask films are adjacent to each other. Opening a bit line connection hole forming region located between word lines to be
(L) A bit line connection hole in which the other semiconductor region of the memory cell selection MISFET is exposed by etching away the second insulating film and the first insulating film exposed from the opening region of the second mask film. Piercing in a state defined in a self-aligned manner by the first cap insulating film and the first sidewall insulating film,
(M) depositing a second conductor film on the second conductor film after depositing a second conductor film on the semiconductor substrate after forming the bit line connection hole;
(N) A function that is provided for transferring the bit line, includes a plurality of light transmission regions having a wide region and a narrow region, and the light transmitted through the light transmission regions adjacent to each other has a reverse phase. A second photomask having a light shielding region disposed in a part of the wide region of the light transmissive region, and in the light shielding region surrounding the light transmissive region, a wide region and a narrow region of the light transmissive region; A step of preparing a second photomask in which an auxiliary pattern including a fine light transmission region is arranged in the vicinity of the boundary region of
(O) a step of transferring the bit line pattern by irradiating the second photoresist film with exposure light through the second photomask;
(P) forming the bit line by patterning the second conductor film using the bit line pattern transferred to the second photoresist film as a mask;

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