JP2001230250A - Semiconductor device and manufacturing method therefor as well as method for forming mask pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To apply an OPC to a large scale logic circuit by reducing a DA treating time in the case of OPC treating a random pattern such as the logic circuit or the like. SOLUTION: A dummy pattern 16 is disposed on a periphery of a wiring 15 having an isolated patterning (e.g. a penetrating through hole pattern). In the case of applying the OPC to the penetrating through hole part or a line end of the wiring 15, a predetermined rule is applied without considering the state of a peripheral pattern, and a hammer head 17 is added.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor device having a pattern layer in which a dense line pattern and an isolated pattern coexist.

[0002]

2. Description of the Related Art In an optical lithography technique, an optical proximity effect (OPE: Optical Proximity Ef
effect) appears, and the optical proximity effect correction (O
PC: Optical Proximity Correction) is required. In particular, when the pattern size is about the exposure wavelength or less, the effect of the optical proximity effect becomes remarkable, and the OPC
The need for application increases. The optical proximity correction is described in, for example, “Semiconductor Process Technology”, published on November 30, 1998 by Baifukan Co., Ltd., pp. 92-93.

A pattern formed in a memory cell or the like of a DRAM is a periodic pattern. When OPC is applied to such a periodic pattern, a simulation or experiment is performed, and based on the result, a basic cell (memory cell) is obtained. )
OPC needs to be performed only for. That is, if an optimal OPC correction amount and correction shape can be obtained for one basic cell, it is sufficient to apply OPC uniformly to almost all cells, and OPC is individually performed for all cells. No need. As described above, it is relatively easy to apply O
Since PC can be applied, OPC has been introduced for the periodic pattern from an early stage.

[0004]

However, the pattern applied to the logic circuit is random. In the case of these random patterns, the pattern size, the distance from the peripheral pattern, the shape, and the like are random, and if an optimal OPC correction is to be applied to each of the random patterns, the correction shape, the correction amount, and the like are changed one by one. You have to calculate. If a large-scale OPC including a peripheral pattern is applied to a random pattern, a large-scale and complicated OPC process is required. Due to the problem of DA processing time, rule-based OPC is generally used for logic patterns. However, if the rules are complicated, the DA processing time becomes enormous, and it becomes difficult to apply OPC.

Since the pattern size correction by OPC basically corrects the dimensions at the time of best focus, when patterns having different defocus characteristics coexist, it is difficult to improve the dimensional accuracy if consideration is given to the time of defocus. It is.

For example, in the case of a through hole pattern in a logic wiring layer, a dense line pattern and an isolated through hole pattern coexist on the same mask. In such a case, application of OPC is essential. However, since the OPC correction amount depends on the peripheral pattern, the correction shape, the correction amount, and the like must be determined in consideration of the peripheral pattern. However, the shape of the peripheral pattern is random, and a complicated OPC rule is required. As a result, an enormous DA processing time is required. In addition, when only the through hole size is corrected, it is possible to correct the dimension at the time of best focus.However, the defocus characteristics are different between the isolated through hole pattern and the dense line portion. It is difficult to improve the dimensional accuracy in consideration of time.

A description will be given of a logic wiring layer with reference to FIG. FIGS. 14A to 14C are plan views showing an example of a pattern layout in which a through-hole pattern TH and a fine wiring pattern LN coexist in a logic wiring layer. FIG. 14A shows an example in which the through-hole pattern TH and the fine wiring pattern LN are isolated, and FIG. 14B shows a through-hole in which one side is open and the other side is a dense part. Pattern TH and fine wiring pattern L
14C shows an example in which the through-hole pattern TH and the fine wiring pattern LN are densely packed.

For example, in the case where ordinary illumination is used at an exposure wavelength of 0.248 μm and a numerical aperture of a stepper NA = 0.6, if optical proximity correction (OPC) is not performed, 0.25 μm
According to the experimental results of the present inventors, the amount of contraction at the end of the line is about 60 nm in an isolated part and about 30 nm in a dense part.
Similarly, according to the experimental results of the present inventors, the through-hole pattern is 80 nm in the isolated portion and 50 nm in the dense portion.
A certain amount of correction is required. For this reason, as shown in FIGS. 14A to 14C, a hammer head HH corresponding to the peripheral pattern must be added to the end of the line. Dimensional correction is needed accordingly. However, in FIG. 14, only the addition of the hammer head HH at the end of the line and the dimensional correction of the through-hole portion are performed by the rule-based
The example applied according to C is shown. The rule becomes more complicated as the target area of the peripheral pattern that affects the size becomes wider, and the time of DA processing becomes enormous. Further, in the general rule-based OPC, in the case of the pattern layout as shown in FIG. 15, the pattern P1 located at the center is determined as an isolated portion, and the same correction as that of the isolated portion is performed.
For this reason, the wiring short margin at the location indicated by the arrow A shown in FIG. 15 is reduced.

An object of the present invention is to improve the resolution of a pattern such as a wiring including an isolated pattern or a pattern having no other pattern in an adjacent region.

It is another object of the present invention to improve the resolution of a pattern in which an isolated pattern and a repetitive pattern such as a line pattern are mixed, that is, a pattern in which patterns having different defocus characteristics are mixed.

It is a further object of the present invention to provide a method for accurately performing optical proximity correction of a pattern in which an isolated pattern and a dense pattern are mixed within a practical correction calculation range.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the method of manufacturing a semiconductor device of the present invention, an insulating film is formed on any layer on a semiconductor substrate on which a semiconductor element is formed, and a lower layer wiring or a connection member connected to the semiconductor element is formed on the insulating film. Forming a wiring layer by forming a conductive film on the connection member and patterning the conductive film. The patterning of the conductive film includes a mask including a wiring pattern functioning as a wiring and a dummy pattern. The wiring pattern includes an adjacent pattern non-existing portion where no adjacent pattern exists, and a dummy pattern is arranged around the non-adjacent pattern non-existing portion.

In such a method of manufacturing a semiconductor device, since the dummy pattern is arranged around the adjacent pattern non-existing portion, the pattern interval between the adjacent pattern non-existing portion (typically, an isolated pattern) and the dense pattern is set. Are virtually equivalent to each other, and a similar optical proximity effect occurs.
Therefore, it is possible to apply the optical proximity effect correction to all the patterns under the same conditions, and it is not necessary to individually perform the correction calculation in consideration of the shape, the distance, and the like of the adjacent pattern for each pattern. As a result, the calculation of the optical proximity effect correction is simplified, and the calculation load can be reduced. On the other hand, since accurate optical proximity correction can be performed on all patterns, the pattern resolution can be maintained sufficiently high.

The dummy pattern is formed of a square pattern formed with the same size as the isolated pattern included in the wiring pattern, and is arranged at a position surrounding the isolated pattern and close to the isolated pattern. ,
When the square pattern is arranged at the position of the wiring pattern, the square pattern may not be arranged.

Further, the optical proximity effect correction for each pattern constituting the wiring pattern can be performed by applying the same rule without depending on the patterns arranged in the periphery.

Further, as illumination conditions for exposure used for patterning, annular illumination and other modified illumination suitable for line and space patterns and other repetitive patterns can be applied. That is, since the dummy pattern is arranged, the isolated pattern is no longer an isolated pattern in terms of defocus characteristics, but has the same defocus characteristics as a repetitive pattern like line and space. For this reason, deformed illumination suitable for a repetitive pattern such as annular illumination can be applied, and the defocus characteristics can be optimized, and the resolution can be further improved.

A semiconductor device according to the present invention includes a semiconductor substrate on which a semiconductor element is formed, an insulating film formed on any layer on the semiconductor substrate, a connecting member formed on the insulating film, The wiring layer includes a wiring pattern that functions as a wiring and a dummy pattern that does not function as a wiring. The wiring pattern includes a dense pattern and an isolated pattern. Is a pattern newly formed as an isolated pattern at a position surrounding the isolated pattern, or a dummy pattern is disposed around an adjacent pattern non-existing portion included in the wiring pattern. Such a semiconductor device is manufactured by the above-described semiconductor device manufacturing method.

Further, the mask pattern generating method of the present invention is a method of generating a mask pattern having both a wiring pattern and a dummy pattern, wherein the wiring pattern includes an adjacent pattern non-existing portion where no adjacent pattern exists. Therefore, a first method of arranging a dummy pattern around an adjacent pattern non-existing portion, generating a wiring pattern, arranging a dummy pattern around an adjacent pattern non-existing portion, and overlapping the wiring pattern and the dummy pattern Method of removing the dummy pattern portion formed by combining the dummy pattern and the wiring pattern, generating the wiring pattern and the isolated pattern included in the wiring pattern in separate layout layers, and A third method of arranging a dummy pattern on the substrate and synthesizing the wiring pattern with the isolated pattern and the dummy pattern; Others, the isolated pattern included in the wiring pattern wiring patterns generated by different layout layer, and a dummy pattern around the isolated pattern,
A fourth method of removing the isolated pattern and the dummy pattern formed by overlapping the isolated pattern and the dummy pattern with the wiring pattern, and combining the wiring pattern with the isolated pattern and the dummy pattern. The correction of the optical proximity effect on the individual patterns constituting the wiring pattern is performed by applying the same rule without depending on the patterns arranged in the periphery. With such a mask pattern generation method, a mask used in the manufacturing method can be generated.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIGS. 1 to 12 (excluding FIGS. 8 and 9) are sectional views or plan views showing an example of a manufacturing process of a semiconductor device according to an embodiment of the present invention in the order of steps. 8 and 9 are conceptual diagrams illustrating a method of generating a mask pattern used in the manufacturing method according to the present embodiment.

First, as shown in FIG. 1, an element isolation region 2 is formed on a main surface of a semiconductor substrate 1, and an n-type well 3 and a p-type well 4 are formed.

For example, a semiconductor substrate 1 made of p-type single crystal silicon having a specific resistance of about 10 Ωcm is prepared, and a thin silicon oxide film (not shown) having a thickness of about 10 nm formed by wet oxidation at about 850 ° C. And for example C
A silicon nitride film (not shown) having a thickness of about 140 nm formed by a VD (Chemical Vapor Deposition) method is deposited on the semiconductor substrate 1. Thereafter, the semiconductor substrate 1 is dry-etched using the photoresist film as a mask, so that the semiconductor substrate 1 in the element isolation region has a depth of 300 to 400.
A groove 5 of about nm is formed. Then, for example, ozone (O
₃ ) A silicon oxide film (not shown) deposited by plasma CVD using tetraethoxysilane (TEOS) as a source gas to a thickness of about 300 to 400 nm, and this silicon oxide film is deposited by CMP. Polished by groove 5
The silicon oxide film in the other region is removed, and the element isolation region 2 is formed leaving the silicon oxide film inside the trench 5.

Next, the silicon nitride film remaining on the surface of the semiconductor substrate 1 is removed by, for example, wet etching using hot phosphoric acid, and a sacrificial oxide film is formed. And a p-type well 4 is formed.
Note that, following this ion implantation, ion implantation for adjusting the threshold voltage of the MISFET may be performed.

Next, as shown in FIG. 2, a gate insulating film 6 is formed on the surface of the semiconductor substrate 1. Gate insulating film 6
Is formed, for example, by the CVD method, and the film thickness is, for example, 7
nm. Thereafter, a polycrystalline silicon film (not shown) serving as a gate electrode is formed on the gate insulating film 6, and the polycrystalline silicon film is patterned into a predetermined pattern to form a gate electrode 7. Thereafter, ion implantation is performed in the presence of the gate electrode 7 to form an impurity semiconductor region 8 serving as a source / drain region of the MISFET. The impurity semiconductor region 8 is formed in a self-aligned manner with respect to the gate electrode 7, and is formed such that a p-type impurity is introduced into the n-type well and an n-type impurity is introduced into the p-type well. Further, a low-concentration impurity is introduced into the impurity semiconductor region 8.

Next, as shown in FIG. 3, a side wall spacer 9 is formed on the side wall of the gate electrode 7. The sidewall spacers 9 are formed, for example, by forming a silicon nitride film on the entire surface of the semiconductor substrate 1 by using, for example, the CVD method, anisotropically etching the silicon nitride film, and remaining only on the side walls of the gate electrode 7. Formed. The silicon nitride film can be replaced with a silicon oxide film. Thereafter, ion implantation is performed in the presence of the sidewall spacer 9 and the gate electrode 7 to form a high-concentration impurity semiconductor region 10. The impurity semiconductor region 10 is formed so as to be self-aligned with the sidewall spacer 9, and is formed such that a p-type impurity is introduced into the n-type well and an n-type impurity is introduced into the p-type well. Further, the impurity semiconductor region 1
At 0, a high concentration of impurities is introduced. Thus, an LDD (Lightly Doped Drain) is formed by the high-concentration impurity semiconductor region 10 and the low-concentration impurity semiconductor region 8. After that, a silicide layer 11 is formed. For example, the silicide layer 11 is formed by depositing a metal film such as tungsten, titanium, or cobalt on the entire surface of the semiconductor substrate 1 and then performing a heat treatment to cause a silicide reaction in a portion where the metal film contacts silicon. Thereafter, the unreacted metal film is selectively removed. That is, it can be formed using a so-called salicide method. Thus, the silicide layer 1
By forming 1, the resistance of the gate electrode 7 can be reduced, and the contact resistance of the source / drain regions can be reduced.

Next, as shown in FIG.
3 is formed, and a plug 14 as a connecting member is formed.

As the insulating film 12, for example, a silicon nitride film formed by a CVD method can be used.

As the insulating film 13, for example, a silicon oxide film formed by a CVD method using TEOS and ozone can be used. Further, an insulating film having high fluidity such as SOG (Spin On Glass) may be used. Further, the surface of the insulating film 13 can be planarized by the CMP method.

The plug 14 is formed in a connection hole opened in the insulating film 13. For example, after the insulating film 13 is etched by the first etching in which the silicon oxide film is easily etched and the silicon nitride film is hardly etched, the insulating film 12 is etched by the second etching in which the silicon nitride film is etched. May be. in this case,
In the first etching, the insulating film 12 made of the silicon nitride film functions as an etching stopper, and the semiconductor substrate 1
(Element isolation region 2) can be prevented from being excessively etched.
After forming the connection hole, a conductive film filling the connection hole is deposited. For example, a polycrystalline silicon film can be applied to the conductive film. Instead of the polycrystalline silicon film, a stacked film of a titanium nitride film and a tungsten film can be used. After forming these conductive films, the conductive films are polished by applying a CMP method,
Alternatively, the conductive film on the insulating film 13 is etched by an etch-back method so that the conductive film remains only inside the connection hole. Thus, the plug 14 is formed.

The plug 14 is formed in a layout as shown in the plan view of FIG.

Next, as shown in FIG. 5, a wiring 15 and a dummy pattern 16 are formed. The wiring 15 and the dummy pattern 16 can be formed by depositing a conductive film on the entire surface of the semiconductor substrate 1 (insulating film 13) after forming the plug 14, and patterning the conductive film. As the conductive film, for example, a tungsten film or a stacked film of a titanium nitride film and a tungsten film can be used.

The wiring includes an isolated pattern.
In the case shown in (a), the wiring 15 (through-hole portion) formed only on the plug 14 corresponds to an isolated pattern. In addition, the wiring 15 is not formed only on the plug 14 but has no wiring pattern around (see FIG. 1).
In FIG. 5A, the wiring 15) on the right side is also included in the isolated pattern. A dummy pattern 16 is formed around the wiring 15 where no wiring pattern exists around such a periphery.

The dummy pattern 16 has no function as a wiring, and is formed in a square having the same size as the isolated pattern as shown in the figure, and each square pattern is formed so as to surround the isolated pattern. With such a dummy pattern 16, the peripheral condition of the pattern (wiring 15) to be subjected to OPC is made substantially constant.

A hammer head 17 is added to a portion of the wiring 15 where OPC is required. The hammer head 17 compensates for a reduction in the pattern area due to the optical proximity effect. A mask is formed in a state where the hammer head 17 is added to the wiring 15 and photolithography is applied to the hammer head 17 so that the hammer head 17 has an appropriate shape. The pattern is developed. In the present embodiment, since the dummy pattern 16 is arranged, the pattern situation around the wiring 15 is constant.
Can reduce the computational load required for.

Next, a method of arranging the dummy pattern 16 will be described with reference to FIGS. First, a dummy pattern 16 having a fixed shape as shown in the figure is added to the periphery of the end B of the line and the through-hole C of the wiring 15. The dummy pattern 16 includes eight rectangular patterns, and each rectangular pattern is disposed so as to surround the through-hole C.

Next, if necessary, the portion D where the dummy pattern overlaps with the wiring pattern can be processed by a conventional DA tool having no OPC function, such as taking out a common part of the wiring pattern and the dummy pattern. A DA process is performed to erase the dummy pattern. In the case of the dense pattern shown in FIG. 7, there is a case where no dummy pattern is arranged at all due to the erasure of the dummy pattern. As a result, it is possible to make the situation of the peripheral pattern of the portion requiring the OPC process almost constant, and to obtain the same effect as the case where the OPC process is individually performed by adding a fixed hammer head or by correcting the size without depending on the peripheral pattern. Can be. In this case, the OPC process does not need to consider the situation of the peripheral pattern, and the speed of the DA process can be increased. Further, the most unfavorable situation as shown in FIG. 15 can be avoided.

FIG. 8 is a conceptual diagram showing a procedure for generating a dummy pattern. FIG. 9 is a conceptual diagram of a computer system used for pattern generation. The pattern is generated using a workstation 31 connected to the server 30 as shown in FIG. The server 30 stores a pattern database 32. As shown in FIG. 8, first, design pattern data is stored in the design pattern database 20. After that, hierarchical design pattern data is generated and stored in the hierarchical pattern database 21. A pattern to which a dummy pattern is to be added is extracted from the hierarchical pattern data (step 22). This step is unnecessary if the target pattern has already been hierarchized and defined in another layer. Next, a dummy pattern is generated around the target pattern according to the rule (step 23), and then the pattern overlap is extracted with reference to the design pattern in the design pattern database 20 and deleted (step 24). Then, this data is stored in the corrected database 25 as corrected data. Thereafter, a mask pattern is generated by performing a certain rule, that is, OPC that does not consider the situation of the peripheral pattern.

Here, the pattern generation method in which the dummy pattern and the through-hole pattern are overlapped after the formation of the wiring pattern to erase the overlapped portion has been described.
A dummy pattern may be arranged without separating the through-hole pattern from the wiring pattern. Also, after the dummy pattern is arranged, the dummy pattern and the wiring pattern may be formed so as to overlap without erasing the superimposed portion. In this case, it is preferable that the width of the dummy pattern is smaller than or equal to the width of the wiring pattern. Further, a dummy pattern may be arranged so as not to overlap with the wiring pattern.

Further, the processing for adding the dummy pattern 16 and the processing for adding the hammer head 17 are not separately performed.
One design cell may be used so that the dummy pattern is added simultaneously with the addition of the hammer head, and the dummy pattern overlapping with the wiring pattern may be erased last. The wiring pattern that requires high-precision processing is where the upper or lower layer of the through-hole pattern connects. To place the dummy pattern only in this area, place a dummy pattern around each through-hole pattern. May be combined with the wiring layer. Also in this case, if necessary, a dummy pattern overlapping the wiring pattern can be replaced with a simple DA signal.
It is possible to delete by processing.

If the processing rules can be achieved only with the dummy pattern arrangement when the processing rules are relatively loose,
OPC is not required for the wiring pattern.

Further, particularly when deformed illumination such as annular illumination is used, the focus margin can be greatly improved by arranging the dummy patterns. FIG.
The simulation results of the focus margin in the case of the line-and-space (E) having the m width and the peripheral dummy pattern of the isolated through-hole pattern (F) and in the absence of the peripheral dummy pattern (G) are shown. It can be seen that when annular illumination is used, the focus margin can be expanded by adding a peripheral dummy pattern. In addition, compared to the case of simply correcting the dimension of the through-hole pattern, the dimensional change at the time of defocus can be made closer to the line-and-space defocus characteristic, and the dimensional accuracy can be improved by taking into account even the time of defocus. Becomes possible.

Although the dummy pattern 16 is arranged around the position where the hammer head 17 is formed, the dummy pattern 16 may be arranged on the line pattern L side as shown in FIG. good.

Next, as shown in FIG. 12, an insulating film 40 covering the wiring 15 and the dummy pattern 16 is formed, and the plug 4
Form one. The insulating film 40 is the same as the insulating film 13,
Plug 41 is similar to plug 14.

Further, the wiring 42 and the dummy pattern 4
3 is formed as shown in FIG. The wiring 42 and the dummy pattern 43 correspond to the wiring 15 and the dummy pattern 1.
Same as 6. Furthermore, an upper layer wiring can be formed in the same manner, but detailed description is omitted.

According to this embodiment, the dummy pattern is arranged around an isolated pattern (for example, a through-hole pattern) in which no other wiring exists around the wiring pattern. Can be the same as the area. As a result, the OPC can be easily applied to a circuit in which an isolated pattern and a dense pattern are mixed, for example, a semiconductor device such as a logic circuit. In other words, even in the case of an isolated pattern, a pattern peripheral situation similar to that of a dense pattern can be realized.
When applying OPC, it is possible to set a certain optimal rule without considering the situation of the peripheral pattern. For this reason, OP
The calculation load on C can be reduced to shorten the calculation time, or OPC can be applied to a large-scale circuit, and the accuracy of wiring patterning can be improved. In addition, modified illumination suitable for resolving a line and space pattern such as annular illumination can be used, and the resolution can be improved by increasing the depth of focus of photolithography.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the embodiment, a general MISFET circuit such as a logic circuit has been described.
It can be applied to AM, system LSI, flash memory, and the like.

[0050]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) The resolution of a pattern such as a wiring including an isolated pattern or a pattern having no other pattern in an adjacent region can be improved.

(2) The resolution of a pattern in which an isolated pattern and a repetitive pattern such as a line pattern are mixed, that is, a pattern in which patterns having different defocus characteristics are mixed can be improved.

(3) The optical proximity correction of a pattern in which an isolated pattern and a dense pattern are mixed can be accurately performed within the range of a realistic correction calculation.

That is, it is possible to reduce the DA processing time when OPC processing is performed on a random pattern such as a logic circuit, and to apply OPC to a large-scale logic circuit. As a result, the processing accuracy of a semiconductor integrated circuit device, particularly, a logic circuit or the like can be improved, and the pattern can be miniaturized.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device of the embodiment in the order of steps;

FIG. 3 is a cross-sectional view showing one example of a method for manufacturing a semiconductor device of the embodiment in the order of steps;

4A to 4C show an example of a method of manufacturing a semiconductor device according to an embodiment in the order of steps, wherein FIG. 4A is a plan view and FIG. 4B is a cross-sectional view.

5A and 5B show an example of a method of manufacturing a semiconductor device according to an embodiment in the order of steps, wherein FIG. 5A is a plan view and FIG. 5B is a cross-sectional view.

FIGS. 6A and 6B are plan views showing other regions at the stage of FIG. 5;

FIG. 7 is a plan view showing still another area at the stage of FIG. 5;

FIG. 8 is a conceptual diagram illustrating a method for generating a mask used in the method for manufacturing a semiconductor device according to the embodiment;

FIG. 9 is a conceptual diagram showing a computer system used for generating a mask pattern.

FIGS. 10A and 10B are plan views showing another example of the semiconductor device shown in FIG. 5;

FIG. 11 is a graph showing a difference in depth of focus depending on illumination conditions.

12A to 12C show an example of a method of manufacturing a semiconductor device according to an embodiment in the order of steps, wherein FIG. 12A is a plan view and FIG. 12B is a cross-sectional view.

13A to 13C show an example of a method of manufacturing a semiconductor device according to an embodiment in the order of steps, wherein FIG. 13A is a plan view and FIG. 13B is a cross-sectional view.

FIGS. 14A to 14C are plan views illustrating the problems of the present invention.

FIG. 15 is a plan view showing an object of the present invention.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 element isolation region 3 n-type well 4 p-type well 5 groove 6 gate insulating film 7 gate electrode 8 impurity semiconductor region 9 sidewall spacer 10 impurity semiconductor region 11 silicide layer 12 insulating film 13 insulating film 14 plug 15 wiring 16 Dummy pattern 17 Hammerhead 20 Design pattern database 21 Hierarchical pattern database 25 Corrected database 30 Server 31 Workstation 32 Pattern database 40 Insulating film 41 Plug 42 Wiring 43 Dummy pattern

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hideo Aoki 6-16-16 Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. (72) Kazutaka Mori 6-16-16 Shinmachi, Ome-shi, Tokyo 3 Hitachi, Ltd. Device Development Center (72) Inventor Norio Hasegawa 6-16, Shinmachi, Ome-shi, Tokyo 3 F-term in Hitachi Device Development Center (Reference) 5F033 QQ01 QQ08 QQ37 QQ48 UU01 VV01 5F048 AC03 BE03 BF00 5F064 EE15

Claims (5)

[Claims] A step of forming an insulating film in any layer on a semiconductor substrate on which a semiconductor element is formed, and forming a lower layer wiring or a connecting member connected to the semiconductor element on the insulating film; Forming a conductive layer on the conductive film and patterning the conductive film to form a wiring layer, wherein the conductive film is patterned by forming a wiring pattern functioning as a wiring and a dummy pattern. The wiring pattern includes an adjacent pattern non-existing portion where no adjacent pattern exists, and the dummy pattern is arranged around the adjacent pattern non-existing portion. The optical proximity correction for the individual patterns that constitutes is performed by applying the same rule without depending on the patterns arranged in the periphery. Method of manufacturing a semiconductor device that. 2. A step of forming an insulating film in any layer on a semiconductor substrate on which a semiconductor element is formed, and forming a lower layer wiring or a connecting member connected to the semiconductor element on the insulating film; Forming a conductive layer on the conductive film and patterning the conductive film to form a wiring layer, wherein the conductive film is patterned by forming a wiring pattern functioning as a wiring and a dummy pattern. The wiring pattern includes an adjacent pattern non-existing portion where no adjacent pattern exists, and the dummy pattern is arranged around the adjacent pattern non-existing portion. The optical proximity effect correction for each of the patterns constituting the dummy pattern is performed by applying the same rule without depending on the patterns arranged in the periphery. The square is formed of a square pattern formed with the same size as the isolated pattern included in the wiring pattern, and the square pattern is arranged at a position surrounding the isolated pattern and close to the isolated pattern. A method for manufacturing a semiconductor device, wherein when the square pattern of the dummy pattern is arranged at the position of the wiring pattern, the square pattern is not arranged. 3. A step of forming an insulating film in any layer on a semiconductor substrate on which a semiconductor element is formed, and forming a lower layer wiring or a connecting member connected to the semiconductor element on the insulating film; Forming a conductive layer on the conductive film and patterning the conductive film to form a wiring layer, wherein the conductive film is patterned by forming a wiring pattern functioning as a wiring and a dummy pattern. The wiring pattern includes an adjacent pattern non-existing portion where no adjacent pattern exists, and the dummy pattern is arranged around the adjacent pattern non-existing portion. The optical proximity effect correction for each pattern constituting the pattern is performed by applying the same rule without depending on the pattern arranged around, The illumination conditions of the exposure used in the grayed, line-and-space pattern suitable for other repeating patterns, a method of manufacturing a semiconductor device, which comprises applying the other modified illumination annular illumination. 4. A semiconductor substrate on which a semiconductor element is formed;
An insulating film formed on any layer on the semiconductor substrate,
A semiconductor device including a connection member formed on the insulating film and a wiring layer formed on the insulating film, wherein the wiring layer has a wiring pattern functioning as a wiring,
A dummy pattern that does not function as a wiring is included; the wiring pattern includes a dense pattern and an isolated pattern; and the dummy pattern is newly formed at a position surrounding the isolated pattern. Wherein the dummy pattern has one of the following two configurations: a first configuration, and a second configuration, wherein the dummy pattern is arranged around an adjacent pattern non-existence portion included in the wiring pattern. 5. A method of generating a mask pattern having both a wiring pattern and a dummy pattern, wherein the wiring pattern includes an adjacent pattern non-existing portion in which no adjacent pattern exists. A first method of arranging the dummy pattern around a portion, generating the wiring pattern, arranging the dummy pattern around an adjacent pattern absent portion, and overlapping the wiring pattern and the dummy pattern; A second method of removing the portion of the dummy pattern to be formed and synthesizing the dummy pattern and the wiring pattern, generating the wiring pattern and an isolated pattern included in the wiring pattern in separate layout layers, The dummy pattern is arranged around the isolated pattern, and the wiring pattern, the isolated pattern and the dummy A third method of synthesizing the isolated pattern, or generating the wiring pattern and an isolated pattern included in the wiring pattern in separate layout layers, arranging the dummy pattern around the isolated pattern, And removing a portion of the isolated pattern and the dummy pattern formed by overlapping the dummy pattern and the wiring pattern, and combining the wiring pattern with the isolated pattern and the dummy pattern.
The method according to any one of the above, wherein the optical proximity effect correction for each pattern constituting the wiring pattern is performed by applying the same rule without depending on a pattern arranged in the periphery. Method of generating a mask pattern to be used.