JP3728056B2 - Capacitance circuit - Google Patents

Description

なお、（３），（４）式における（Ｓｅｔ）及び（Ｓｃｔ）は、電流制御回路２１，２２中の各スイッチの投入状態を示す値であり、投入されたスイッチの場合には“１”、投入されていないスイッチの場合には“０”の値をとる。後述する数式でも、これと同様の記号は同様の内容を示す。
【００２０】
図１の回路において、入力端子ＩＮ₁ の電位が上昇すると、演算増幅器２３，２４によって電流制御回路２１，２２の制御端子ＣＣの電位が降下すると共に、トランジスタ２５，２６のエミッタの電位が上昇する。これによって、電流制御回路２１及びトランジスタ２５がオフ状態になり、電流制御回路２２及びトランジスタ２６がオン状態になる。そのため、入力端子ＩＮ₁ から電流制御回路２２へ電荷（電流）が入力され、その電荷の電流増幅率倍分の１に減衰された電荷が電流制御回路２２の電流流入端子ＯＵＴ２に流入する。また、トランジスタ２６によって電流増幅率倍分の１に減衰された電荷が、該トランジスタ２６のベースからコンデンサ１の他方の電極に流れ込む。これにより、コンデンサ１が充電される。
【００２１】
入力端子ＩＮ₁ の電位が降下すると、演算増幅器２３，２４によって電流制御回路２１，２２の制御端子ＣＣの電位が上昇すると共に、トランジスタ２５，２６のエミッタの電位が下降する。これによって、電流制御回路２１及びトランジスタ２５がオン状態になり、電流制御回路２２及びトランジスタ２６がオフ状態になる。そのため、電流制御回路２１から入力端子ＩＮ₁ へ電荷が出力され、その電荷の電流増幅率倍分の１に減衰された電荷が電流制御回路２１の電流流出端子ＯＵＴ１から流出される。また、トランジスタ２５によって電流増幅率倍分の１に減衰された電荷が、該トランジスタ２５のベースにコンデンサ１の他方の電極から流れ込む。これにより、コンデンサ１が放電する。
以上のように、この第１の実施形態の容量回路では、電流制御回路２１，２２を有する充放電電流生成回路２０とコンデンサ１とで容量回路を構成したので、各ＮＰＮトランジスタの電流増幅率をｈ_fen 、各ＰＮＰ型トランジスタの電流増幅率をｈ_fep 、コンデンサ１の容量をＣ₁ とすると、電荷を充電する場合には次の（５）式で示される容量Ｃを持つコンデンサと同等に働き、電荷を放電する場合には、（６）式で示される容量Ｃを持つコンデンサと同等に働く。
【００２２】
【数２】

従って、この容量回路では、Ｋ，Ｌ，Ｍ，Ｎの値の設定によって、容量の調節できる範囲を決定できると共に、各電流制御回路２１，２２中の複数のスイッチによってその範囲で細かな調整と変更が可能になっている。さらに、各Ｋ，Ｌ，Ｍ，Ｎの値の設定によっては、見掛上の容量の増幅が可能であり、集積回路における集積度が向上する。
【００２３】
［第２の実施形態］
図５は、本発明の第２の実施形態を示す容量回路の回路図であり、図１中の要素と共通する要素には、共通の符号が付されている。
この容量回路は、一方の電極がグランドＧＮＤに接続された第１の実施形態と同様のコンデンサ１と、充放電電流生成回路１０，２０とは異なる充放電電流生成回路３０とで構成されている。
充放電電流生成回路３０は、充放電電流生成回路２０における電流制御回路２１，２２を、第１の電流制御回路３１（第４の発明）対と第２の電流制御回路３２（第５の発明）に置換したものであり、他は充放電電流生成回路２０と同様の構成になっている。
図６は、図５中の電流制御回路３１の具体的回路を示す回路図である。
【００２４】
電流制御回路３１は、入力端子ＩＮ₁ に第９制御電極であるベースが接続されると共に第１７導通電極であるコレクタが電流流出端子ＯＵＴ１に接続された第９のトランジスタであるＰＮＰ型トランジスタ３１ａと、入力端子ＩＮ₁ に第１９導通電極であるコレクタが接続されると共に、第１８導通電極であるトランジスタ３１ａのエミッタが第１０制御電極であるベースに接続された第１０のトランジスタのＰＮＰ型トランジスタ３１ｂと、トランジスタ３１ａのエミッタが第２１導通電極のコレクタに接続されると共に第１１制御電極のベースに接続された第１１のトランジスタであるＰＮＰ型トランジスタ３１ｃとを、備えている。
トランジスタ３１ｂは、Ｋ＋１個のエミッタを有し、該各エミッタがＫ＋１個の第５のスイッチ３１ｄ₀ 〜３１ｄ_K を介して制御端子ＣＣに接続されている。トランジスタ３１ｃは、Ｌ＋１個のエミッタを有し、該各エミッタがＬ＋１個の第６のスイッチ３１ｅ₀ 〜３１ｅ_L を介して制御端子ＣＣに接続されている。トランジスタ３１ｂの各エミッタの面積は、例えば、２⁰ ，２¹ ，…，２^k になっている。トランジスタ３１ｃの各エミッタの面積は、２⁰ ，２¹ ，…，２^L になっている。
【００２５】
図７は、図５中の電流制御回路３２の具体的回路を示す回路図である。
電流制御回路３２は、入力端子ＩＮ₁ に第１２制御電極であるベースが接続されると共に、第２３導通電極であるコレクタが電流流入端子ＯＵＴ２に接続された第１２のトランジスタであるＮＰＮ型トランジスタ３２ａと、入力端子ＩＮ₁ に第２５導通電極であるコレクタが接続されると共に、第２４導通電極であるトランジスタ３２ａのエミッタが第１３制御電極であるベースに接続された第１３のトランジスタのＮＰＮ型トランジスタ３２ｂと、トランジスタ３２ａのエミッタが第２７導通電極であるコレクタに接続されると共に第１４制御電極であるベースに接続された第１３のトランジスタのＮＰＮ型トランジスタ３２ｃとを、備えている。
【００２６】
トランジスタ３２ｂは、第２６導通電極であるＭ＋１個のエミッタを有し、該各エミッタがＭ＋１個の第７のスイッチ３２ｄ₀ 〜３２ｄ_M を介して制御端子ＣＣに接続されている。トランジスタ３２ｃは、第２８導通電極であるＮ＋１個のエミッタを有し、該各エミッタがＮ＋１個の第８のスイッチ３２ｅ₀ 〜３２ｅ_N を介して制御端子ＣＣに接続されている。トランジスタ３２ｂの各エミッタの面積は、例えば、２⁰ ，２¹ ，…，２^M になっている。トランジスタ３２ｃの各エミッタの面積は、例えば２⁰ ，２¹ ，…，２^N になっている。
図６及び図７の電流制御回路３１，３２を有する図５の容量回路では、各電流制御回路３１，３２が、電流制御回路２１，２２と同様の動作を行うので、図１の第１の実施形態と同様の動作を行う。
従って、第１の実施形態と同様の効果が期待できる。
【００２７】
［第３の実施形態］
図８は、本発明の第３の実施形態を示す容量回路の回路図であり、図２中の要素と共通する要素には、共通の符号が付されている。
この容量回路は、一方の電極がグランドＧＮＤに接続された参考例と同様のコンデンサ１と、参考例における充放電電流生成回路１０とは異なる充放電電流生成回路４０（第６の発明）とで構成されている。
充放電電流生成回路４０は、入力端子ＩＮ₁ に接続された第１の電流制御回路４１（第７の発明）及び第２の電流制御回路４２（第８の発明）と、該入力端子ＩＮ₁ が非反転入力端子（＋）に接続された演算増幅器４３とを備えている。
電流制御回路４１は、入力端子ＩＮ₁ へ電流を出力するが、その電流に対応した値の電流を電流流入端子ＯＵＴ３から流入するものであり、その流入電流の値が可変に設定できるようになっている。電流制御回路４１の電流流入端子ＯＵＴ３は、第１のトランジスタであるＰＮＰ型トランジスタ４４の第１導通電極のコレクタに接続されている。そして、第２導通電極であるトランジスタ４４のエミッタが第１の電源電位Ｖｃｃに接続されると共に、第１制御電極であるトランジスタ４４のベースが、第２のトランジスタであるＮＰＮ型トランジスタ４５の第３導通電極のコレクタに接続されている。即ち、トランジスタ４４とトランジスタ４５とは、ダーリントン接続になっている。第２制御電極であるトランジスタ４５のベースがコンデンサ１の他方の電極に接続されている。
【００２８】
電流制御回路４２は、入力端子ＩＮ₁ から電流を入力するが、その電流に対応した値の電流を電流流出端子ＯＵＴ４から流出するものであり、流出電流の値は可変に設定できるようになっている。電流制御回路４２の電流流出端子ＯＵＴ４は、第３のトランジスタであるＮＰＮ型トランジスタ４６の第５導通電極のコレクタに接続されている。第６導通電極であるトランジスタ４６のエミッタがグランドＧＮＤに接続されると共に、第３制御電極であるトランジスタ４６のベースが、第４のトランジスタであるＰＮＰ型トランジスタ４７の第７導通電極のコレクタに接続されている。即ち、トランジスタ４６とトランジスタ４７とは、ダーリントン接続になっている。第４制御電極であるトランジスタ４７のベースが、コンデンサ１の他方の電極に接続されている。
第４導通電極であるトランジスタ４５のエミッタと第８導通電極であるトランジスタ４７のエミッタとが、演算増幅器４３の出力端子に接続され、コンデンサ１の他方の電極が、演算増幅器４３の反転入力端子（−）に接続されている。また、電流制御回路４１の電源端子ＣＣは、電源電位Ｖｃｃに接続され、電流制御回路４２の電源端子ＣＣが、グランドＧＮＤに接続されている。
【００２９】
図９は、図８中の電流制御回路４１の具体的回路を示す回路図である。
この電流制御回路４２は、電源端子ＣＣに第９導通電極であるコレクタが接続された第５のトランジスタであるＫ＋１個のＮＰＮ型トランジスタ４１ａ₀ 〜４１ａ_K を備えている。第１０導通電極である各トランジスタ４１ａ₀ 〜４１ａ_K のエミッタは、Ｋ＋１個の第１のスイッチ４１ｂ₀ 〜４１ｂ_K を介して入力端子ＩＮ₁ に接続されている。第５制御電極であるトランジスタ４１ａ₀ 〜４１ａ_K のベースは、電流流入端子ＯＵＴ３に共通に接続されている。この電流流入端子ＯＵＴ３には、第６のトランジスタであるＬ＋１個のＮＰＮ型トランジスタ４１ｃ₀ 〜４１ｃ_L の第６制御電極のベースが接続されると共に、第１１導通電極である各トランジスタ４１ｃ₀ 〜４１ｃ_L のコレクタが接続されている。第１２導通電極である各トランジスタ４１ｃ₀ 〜４１ｃ_L のエミッタが、Ｌ＋１個の第２のスイッチ４１ｄ₀ 〜４１ｄ_L を介して入力端子ＩＮ₁ に接続されている。トランジスタ４１ａ₀ 〜４１ａ_K のエミッタの面積は、例えば、２⁰ ，２¹ ，…，２^k になっている。トランジスタ４１ｃ₀ 〜４１ｃ_L のエミッタの面積は、例えば、２⁰ ，２¹ ，…，２^L になっている。
【００３０】
図１０は、図８中の電流制御回路４２の具体的回路を示す回路図である。
この電流制御回路４２は、電源端子ＣＣに第１３導通電極であるコレクタがそれぞれ接続されたＭ＋１個の第７のトランジスタであるＰＮＰ型トランジスタに４２ａ₀ 〜４２ａ_M を備えている。第１４電極である各トランジスタ４２ａ₀ 〜４２ａ_M のエミッタは、Ｍ＋１個の第３のスイッチ４２ｂ₀ 〜４２ｂ_M を介して入力端子ＩＮ₁ に共通に接続されている。第７制御電極である各トランジスタ４２ａ₀ 〜４２ａ_M のベースが、電流流出端子ＯＵＴ４に共通に接続されている。この電流流出端子ＯＵＴ４には、第８のトランジスタであるＮ＋１個のＰＮＰ型トランジスタ４２ｃ₀ 〜４２ｃ_N の第７制御電極のベースが接続されると共に、第１５導通電極である各トランジスタ４２ｃ₀ 〜４２ｃ_N のコレクタが共通に接続されている。第１６導通電極である各トランジスタ４２ｃ₀ 〜４２ｃ_N のエミッタが、Ｎ＋１個の第４のスイッチ４２ｄ₀ 〜４２ｄ_N を介して入力端子ＩＮ₁ に共通に接続されている。トランジスタ４２ａ₀ 〜４２ａ_M のエミッタの面積は、例えば、２⁰ ，２¹ ，…，２^M になっている。トランジスタ４２ｃ₀ 〜４２ｃ_N のエミッタの面積は、例えば、２⁰ ，２¹ ，…，２^N になっている。
【００３１】
次に、この容量回路の動作を説明する。
電流制御回路４１では、電源端子ＣＣが“Ｈ”レベルに保たれた状態で、入力端子ＩＮ₁ の電位が降下すると、各トランジスタ４１ａ₀ 〜４１ａ_K ，４１ｃ₀ 〜４１ｃ_L がオンし、スイッチ４１ｂ₀ 〜４１ｂ_K ，４１ｄ₀ 〜４１ｄ_L の投入状態に応じた値の電荷が、電流流入端子ＯＵＴ３から流入する。電流流入端子ＯＵＴ３から流入する電荷及びスイッチ４１ｂ₀ 〜４１ｂ_K ，４１ｄ₀ 〜４１ｄ_L の投入状態によって決まる値の電荷が、入力端子ＩＮ₁ へ出力される。
同様に、電流制御回路４２では、電源端子ＣＣが“Ｌ”に保たれた状態で、入力端子ＩＮ₁ の電位が上昇すると、各トランジスタ４２ａ₀ 〜４２ａ_M ，４２ｃ₀ 〜４２ｃ_N がオンし、スイッチ４２ｂ₀ 〜４２ｂ_M ，４２ｄ₀ 〜４２ｄ_N の投入状態に応じた値の電荷が、電流流出端子ＯＵＴ４から流出する。電流流出端子ＯＵＴ４から流出する電荷及びスイッチ４２ｂ₀ 〜４２ｂ_M ，４２ｄ₀ 〜４２ｄ_N の投入状態によって決まる値の電荷が、入力端子ＩＮ₁ から入力される。各電流制御回路４１，４２は、それぞれカレントミラー構成になっているので、電流制御回路４１，４２における入力電流Ｉinと出力電流Ｉout の関係は、次の（７），（８）式のようになる。
【００３２】
【数３】

電流制御回路４１，４２を有する図８の容量回路では、入力端子ＩＮ₁ が上昇すると、演算増幅器４３によってトランジスタ４５，４７のエミッタの電位が上昇する。よって、トランジスタ４４，４５がオフ状態になると共に、電流制御回路４１もオフ状態になる。一方、トランジスタ４６，４７がオン状態になって電流制御回路４２もオン状態になる。このときには、電流制御回路４２に入力端子ＩＮ₁ から入力された電荷が、電流増幅率倍されて電流制御回路４２の電流流出端子ＯＵＴ４から流出する。この電荷が、トランジスタ４６，４７で、これらの電流増幅率分の１に減衰されてコンデンサ１に与えられる。これで、コンデンサ１が充電される。
【００３３】
入力端子ＩＮ₁ の電位が降下すると、演算増幅器４３によってトランジスタ４５，４７のエミッタの電位が降下する。よって、トランジスタ４４，４５がオン状態になり、電流制御回路４１もオン状態になる。一方、トランジスタ４６，４７がオフ状態になり、電流制御回路４２がオフ状態になる。この状態では、電流制御回路４１から入力端子ＩＮ₁ へ流出した電荷を電流増幅率倍した電荷が、電流制御回路４１の電流流入端子ＯＵＴ３に流入する。トランジスタ４４，４５は、その電荷を電流増幅率分の１に減衰させた値の電荷をコンデンサ１から吸収する。これで、コンデンサ１が放電される。
以上のように、この第３の実施形態の容量回路では、電流制御回路４１，４２を有する充放電電流生成回路４０とコンデンサ１とで容量回路を構成したので、ＮＰＮトランジスタ４５，４６の電流増幅率をｈ_fen 、各ＰＮＰ型トランジスタ４４，４７の電流増幅率をｈ_fep 、コンデンサ１の容量をＣ₁ とすると、電荷を充電する場合には次の（９）式で示される容量Ｃを持つコンデンサと同等に働き、電荷を放電する場合には、（１０）式で示される容量Ｃを持つコンデンサと同等に働く。
【００３４】
【数４】

よって、この容量回路では、Ｋ，Ｌ，Ｍ，Ｎの値の設定によって、容量の調節できる範囲を決定できると共に、各電流制御回路４１，４２中の複数のスイッチによってその範囲で細かな調整と変更が可能になっている。また、充電と放電における増幅率の値が、電流増幅率ｈ_fen とｈ_fep の値によらずバランスがとれるので、調整が容易である。そのうえ、トランジスタ４４と４５、及びトランジスタ４６と４７を、それぞれダーリントン接続にしたので、これらによって電流増幅率が高まり、コンデンサ１における見掛上の容量をさらに大きくできる。従って、集積回路における集積度が向上する。
【００３５】
［第４の実施形態］
図１１は、本発明の第４の実施形態を示す容量回路の回路図であり、図８中の要素と共通する要素には、共通の符号が付されている。
この容量回路は、一方の電極がグランドＧＮＤに接続された第３の実施形態と同様のコンデンサ１と、第３の実施形態における充放電電流生成回路４０とは異なる充放電電流生成回路５０とで構成されている。
充放電電流生成回路５０は、充放電電流生成回路４０における電流制御回路４１，４２を、第１の電流制御回路５１（第９の発明）及び第２の電流制御回路，５２（第１０の発明）に置換したものであり、他は充放電電流生成回路４０と同様の構成になっている。
【００３６】
図１２は、図１１中の電流制御回路５１の具体的回路を示す回路図である。
この電流制御回路５１は、電源端子ＣＣに第１７導通電極であるコレクタが接続された第９のトランジスタであるＮＰＮ型トランジスタ５１ａを備えている。トランジスタ５１ａは、第１８導通電極であるＫ＋１個のエミッタを有している。トランジスタ５１ａの各エミッタの面積は、例えば、２⁰ ，２¹ ，…，２^k になっており、該各エミッタがＫ＋１個の第５のスイッチ５１ｂ₀ 〜５１ｂ_K を介して入力端子ＩＮ₁ に共通に接続されている。第９制御電極であるトランジスタ５１ａのベースは、電流流入端子ＯＵＴ３に接続されている。この電流流入端子ＯＵＴ３には、第１０のトランジスタであるＮＰＮ型トランジスタ５１ｃの第１０制御電極であるベースに接続されると共に、第１９導通電極である該トランジスタ５１ｃのコレクタに接続されている。トランジスタ５１ｃは、Ｌ＋１個の第２０導通電極であるエミッタを有している。トランジスタ５１ｃの各エミッタの面積は、例えば、２⁰ ，２¹ ，…，２^L になっており、該各エミッタがＬ＋１個の第６のスイッチ５１ｄ₀ 〜５１ｄ_L を介して入力端子ＩＮ₁ に共通に接続されている。
【００３７】
図１３は、図１１中の電流制御回路５２の具体的回路を示す回路図である。
この電流制御回路５２は、電源端子ＣＣに第２１導通電極であるコレクタが接続された第１１のトランジスタであるＰＮＰ型トランジスタ５２ａを備えている。トランジスタ５２ａは、第２２導通電極であるＭ＋１個のエミッタを有している。トランジスタ５２ａの各エミッタの面積は、例えば、２⁰ ，２¹ ，…，２^M になっており、該各エミッタがＭ＋１個の第７のスイッチ５２ｂ₀ 〜５２ｂ_M を介して入力端子ＩＮ₁ に共通に接続されている。第１１制御電極であるトランジスタ５２ａのベースは、電流流出端子ＯＵＴ４に接続されている。この電流流出端子ＯＵＴ４には、第１２のトランジスタであるＰＮＰ型トランジスタ５２ｃの第１２制御電極であるベースに接続されると共に、第２３導通電極である該トランジスタ５２ｃのコレクタに接続されている。トランジスタ５２ｃは、Ｎ＋１個の第２４導通電極であるエミッタを有している。トランジスタ５２ｃの各エミッタの面積は、例えば、２⁰ ，２¹ ，…，２^N になっており、該各エミッタがＮ＋１個の第８のスイッチ５２ｄ⁰ 〜５２ｄ_N を介して入力端子ＩＮ₁ に共通に接続されている。
図１２及び図１３の電流制御回路５１，５２を有する図１１の容量回路では、各電流制御回路５１，５２が、電流制御回路４１，４２と同様の動作を行うので、図８の第３の実施形態と同様の動作を行う。従って、第３の実施形態と同様の効果が期待できる。
【００３８】
［第５の実施形態］
図１４は、本発明の第５の実施形態を示す容量回路の回路図であり、図２中の要素と共通する要素には、共通の符号が付されている。
この容量回路は、一方の電極がグランドＧＮＤに接続された参考例と同様のコンデンサ１と、参考例における充放電電流生成回路１０とは異なる充放電電流生成回路６０（第１１の発明）とで構成されている。
充放電電流生成回路６０は、入力端子ＩＮに接続された第１の電流制御回路６１及び第２の電流制御回路６２と、該入力端子ＩＮが反転入力端子（−）に接続された第１の演算増幅器６３と、該入力端子ＩＮが非反転入力端子（＋）に接続された第２の演算増幅器６４とを備えている。
電流制御回路６１は、入力端子ＩＮへ電流を出力するが、その電流に対応した値の電流を電流流出端子ＯＵＴ５から流出するものであり、その流出電流は可変に設定できるようになっている。電流制御回路６１の電流流出端子ＯＵＴ５に第３の電流制御回路６５が接続されている。電流制御回路６５は、電流制御回路６１から電流を入力するが、その電流に対応した値の電流を電流流入端子ＯＵＴ６から流入するものであり、その流入電流の値は任意に設定できるようになっている。
【００３９】
電流制御回路６２は、入力端子ＩＮから電流を入力するが、その電流に対応した値の電流を電流流入端子ＯＵＴ７から流入するものであり、その流入電流は可変に設定できるようになっている。電流制御回路６２の電流流入端子ＯＵＴ７に第４の電流制御回路６６が接続されている。電流制御回路６６は、電流制御回路６２へ電流を出力するが、その電流に対応した値の電流を電流流入端子ＯＵＴ８から流出するものであり、その流出電流の値は可変に設定できるようになっている。
電流制御回路６１及び電流制御回路６２の制御端子ＣＣは、演算増幅器６３の出力端子に接続されている。電流制御回路６５及び電流制御回路６６の制御端子ＣＣは、演算増幅器６４の出力端子に接続されている。電流制御回路６５の電流流入端子ＯＵＴ６び電流制御回路６６の電流流出端子ＯＵＴ８が、コンデンサ１の他方に接続されている。
各電流制御回路６１及び電流制御回路６６は、図３と同様の電流制御回路でそれぞれ構成され（第１２，１３の発明）、電流制御回路６２及び電流制御回路６５（第１４，１５の発明）は、図４と同様の電流制御回路でそれぞれ構成されている。
【００４０】
次に、この容量回路の動作を説明する。
電流制御回路６１及び電流制御回路６６は、制御端子ＣＣの電位に応じて第２の実施形態の電流制御回路２１と同様の動作を行う。電流制御回路６２及び電流制御回路６５は、制御端子ＣＣの電位に応じて電流制御回路２２と同様の動作を行う。
これら電流制御回路６１，６２，６５，６６を有する図１４の容量回路では、入力端子ＩＮ₁ の電位が上昇すると、演算増幅器６３により、電流制御回路６１，６２の制御端子ＣＣに第１の制御電圧が与えられてその電位が降下し、演算増幅器６４により、電流制御回路６３，６４の制御端子ＣＣに第１の制御電圧が与えられてその電位が上昇する。これにより、電流制御回路６１，６５がオフ状態になると共に、電流制御回路６２，６６がオン状態になる。そのため、入力端子ＩＮ₁ から電流制御回路６２に電荷が入力され、電流制御回路６２における電流増幅率倍された電荷が電流制御回路６６から出力されて該電流制御回路６２の電流流入端子ＯＵＴ７に流入する。その電流制御回路６６から出力された電荷が電流制御回路６６の電流増幅率倍された電荷が、該電流制御回路６６の電流流出端子ＯＵＴ８からコンデンサ１に流出される。これにより、コンデンサ１が充電される。
【００４１】
次に、入力端子ＩＮ₁ の電位が降下すると、演算増幅器６３により、電流制御回路６１，６２の制御端子ＣＣの電位が上昇し、演算増幅器６４により、電流制御回路６３，６４の制御端子ＣＣの電位が降下する。これにより、電流制御回路６１，６５がオン状態になると共に、電流制御回路６２，６６がオフ状態になる。このとき、入力端子ＩＮ₁ へ電流制御回路６１から電荷が出力され、電流制御回路６１における電流増幅率倍された電荷が該電流制御回路６１の電流流出端子ＯＵＴ５から電流制御回路６５へ流出する。その電流制御回路６１から出力された電荷が電流制御回路６５の電流増幅率倍された電荷が、コンデンサ１から該電流制御回路６５の電流流入端子ＯＵＴ６に流入する。これにより、コンデンサ１が放電される。
以上のように、この第５の実施形態の容量回路では、充放電電流生成回路６０に、電流制御回路６１，６２，６５，６６を設け、電流制御回路６２，６６の電流増幅率を利用してコンデンサ１の充電電流を生成し、電流制御回路６１，６５の電流増幅率を利用して放電電流を生成している。そのため、コンデンサ１を充電するときには、コンデンサ１が次の（１１）式にような容量Ｃを持つコンデンサと同等に働き、放電するときには（１２）式のような容量Ｃを持つコンデンサとして働く。
【００４２】
【数５】

ここで、（１１）式のＫ，Ｌは、電流制御回路６２における値であり、Ｍ，Ｎは電流制御回路６６における値である。また、（１２）式のＫ，Ｌは、電流制御回路６５における値であり、Ｍ，Ｎは電流制御回路６１における値を示している。
（１１），（１２）式から分かるように、この実施形態の容量回路では、各Ｋ，Ｌ，Ｍ，Ｎの値を調節することによって、容量Ｃの値が調整できると共にその範囲が決定できる。また、各スイッチの投入状態によって、その範囲で容量Ｃの細かな調整と変更とが可能になる。そして、この容量回路ではトランジスタの増幅率そのものが、（１１），（１２）に含まれないので、容量Ｃがより正確に設定できる。また、２段の電流制御回路６１，６５と電流制御回路６２，６５で、容量を設定できるので、各Ｋ，Ｌ，Ｍ，Ｎの値によって、見掛上の容量の増幅が第２の実施形態よりも容易になり、集積回路における集積度が向上する。
【００４３】
［第６の実施形態］
図１５は、本発明の第６の実施形態を示す容量回路の回路図であり、図１４中の要素と共通する要素には、共通の符号がふされている。
この容量回路は、一方の電極がグランドＧＮＤに接続された第５の実施形態と同様のコンデンサ１と、第５の実施形態における充放電電流生成回路６０とは異なる充放電電流生成回路７０とで構成されている。
充放電電流生成回路７０は、充放電電流生成回路６０における電流制御回路６１，６２を、電流制御回路７１，７２に置換し、電流制御回路６５，６６を、電流制御回路７３，７４に置換したのである。充放電電流生成回路７０の他の構成は、充放電電流生成回路６０と同様の構成になっている。
各電流制御回路７１及び電流制御回路７４は、図６と同様の電流制御回路でそれぞれ構成され、電流制御回路７２及び電流制御回路７３は、図７と同様の電流制御回路でそれぞれ構成されている。
電流制御回路７１〜７４を有する図１５の容量回路では、各電流制御回路７１，７３が、電流制御回路６１，６５とそれぞれ同様の動作を行い、各電流制御回路７２，７４が、電流制御回路６２，６６とそれぞれ同様の動作を行うので、図１４の第５の実施形態と同様の動作を行う。従って、第５の実施形態と同様の効果が期待できる。
【００４４】
［第７の実施形態］
図１６は、本発明の第７の実施形態を示す容量回路の回路図である。
第１〜第６の実施形態の容量回路では、一方の電極がグランドＧＮＤに接地されたコンデンサを用いた容量回路であったが、この第７の実施形態の容量回路は、いずれの両電極も固定電位に固定されないコンデンサ８０を備えている（第１６の発明）。コンデンサ８０の一方の電極は、第１の入力端子ＩＮ₁ に接続された充放電電流生成回路８０Ａの出力端子に接続されている。コンデンサ８０の他方の電極は、第２の入力端子ＩＮ₂ に接続された充放電電流生成回路８０Ｂの出力端子に接続されている。
図１７は、図１６中の充放電電流生成回路８０Ａ，８０Ｂの構成例（その１）を示す回路図である。
この充放電電流生成回路は、第１導通電極であるコレクタが入力端子ＩＮ₁ またはＩＮ₂ に接続されると共に第２導通電極であるエミッタが電源電位Ｖｃｃに接続された第１の導電型の第１のトランジスタであるＰＮＰトランジスタ８１と、第３導通電極であるコレクタが入力端子ＩＮ₁ またはＩＮ₂ に接続されると共に第４導通電極のエミッタがグランドＧＮＤに接地された第２の導電型の第２のトランジスタであるＮＰＮ型トランジスタ８２とを、備えている。
【００４５】
第１制御電極であるトランジスタ８１のベースは、第３のトランジスタであるＮＰＮ型トランジスタ８３の第５導通電極のコレクタに接続されている。一方、第２制御電極であるトランジスタ８２のベースは、第４のトランジスタであるＰＮＰ型トランジスタ８４の第７導通電極のコレクタに接続されている。第６導通電極であるトランジスタ８３のエミッタは、第８導通電極であるトランジスタ８４のエミッタと共に、入力端子ＩＮ₁ またはＩＮ₂ に接続されている。第３制御電極であるトランジスタ８３のベースと、第４制御電極であるトランジスタ８４のベースとが、コンデンサ８０のいずれかの電極に共通に接続されている。
次に、図１７の回路でそれぞれ構成した充放電電流生成回路８０Ａ，８０Ｂをコンデンサ８０の両電極に接続した容量回路の動作を説明する。
例えば、入力端子ＩＮ₁ の電位が上昇すると、トランジスタ８３，８４のエミッタの電位が上昇し、トランジスタ８２，８４がオン状態になり、トランジスタ８１，８３がオフ状態になる。そのため、入力端子ＩＮ₁ から充放電電流生成回路８０Ａに電荷が入力される。そして、トランジスタ８２及び８４で構成されるダーリントン接続における電流増幅率分の１の電荷が、充放電電流生成回路８０Ａの出力端子からコンデンサ８０へ流れる。そして、コンデンサ８０は充放電電流生成回路８０Ａからの電荷と同じ値の電荷を、充放電電流生成回路８０Ｂ側に押し出す。これにより、充放電電流生成回路８０Ｂにおけるトランジスタ８３とトランジスタ８１がオン状態になり、コンデンサ８０に引き込まれた電荷をトランジスタ８３，８１で構成されたダーリントン接続の電流増幅率倍した電荷が、入力端子ＩＮ₂ を介して流出される。
【００４６】
図１８は、図１６中の充放電電流生成回路８０Ａ，８０Ｂの構成例（その２）を示す回路図である。
充放電電流８０Ａ，８０Ｂは、参考例で用いた充放電電流生成回路１０でそれぞれ構成することができる。図１７の充放電電流生成回路を用いた場合には、例えば入力端子ＩＮ₁ の電位とコンデンサ８０の電極との間の電位差がトランジスタ８４がオンする電圧ＶBEに至らないと、回路全体が動作しないということが想定されるが、図１８のように、演算増幅器１３を設けることで、入力端子ＩＮ₁ の電位とコンデンサ８０の電極との間の電位差が小さくても、動作するようになる。なお、充放電電流８０Ａ，８０Ｂのうちの一方が、図１７の回路、他方が図１８の回路で構成することも可能である。
以上のように、この第７の実施形態では、コンデンサ８０の両電極と入力端子ＩＮ₁ ，ＩＮ₂ との間に、それぞれ充放電電流生成回路８０Ａ，８０Ｂを設けている。よって、入力端子ＩＮ₁ から大電流を流出入して入力端子ＩＮ₂ からそれと同じ大きさの電流を流出入するので、大きな容量を持つ回路を構成しているが、コンデンサ８０には、その大電流をダーリントン接続の電流増幅率分の１の微弱電流しか流出入しない。つまり、容量の小さなコンデンサ８０で大きな容量値を持つ回路を構成でき、集積回路における集積度が向上する。
【００４７】
［第８の実施形態］
図１９は、本発明の第８の実施形態を示す容量回路の回路図である。
この容量回路は、複数のコンデンサ１００ｍ（ｍは２以上の任意の整数）が、直列或は並列に接続され組み合わされたコンデンサ複合回路１００を有している。このコンデンサ複合回路１００における複数の入力端子ＩＮに、充放電電流生成回路１１０ｍが接続されている（第１７の発明）。充放電電流生成回路１１０ｍは、図１７の充放電電流生成回路或いは図１８の充放電電流生成回路で構成されている。
この容量回路では、各入力端子ＩＮから入力された電荷が、充放電電流生成回路１１０ｍで電流増幅率分の１に減衰されてコンデンサ複合回路１００中の各コンデンサ１００ｍにそれぞれ供給される。そして、コンデンサ複合回路１００中で演算された電荷が、電流増幅率倍されて各入力端子ＩＮからそれぞれ出力される。
以上のように、この第８の実施形態の容量回路では、複数のコンデンサ１００ｍで構成されたコンデンサ複合回路１００の各入力端子ＩＮに、充放電電流生成回路１１０ｍをそれぞれ設け、電流増幅率分の１に減衰した電流をコンデンサ複合回路１００に与え、電流増幅率倍した電流を各入力端子ＩＮから出力するようにでき、すべてのコンデンサ１００ｍを電流増幅率倍の容量を持つコンデンサとして使用することができ、集積回路の集積度を向上できる。そのうえ、一つ一つのコンデンサ１００ｍの両電極に充放電電流生成回路１１０ｍを接続するのではないので、第７の実施形態の容量回路を複合させる場合よりも、小型の集積回路が実現できる。
【００４８】
なお、本発明は、上記参考例や実施形態に限定されず種々の変形が可能である。その変形例としては、例えば次のようなものがある。
（１） 参考例や第１〜第６の実施形態では、エミッタ面積が２のべき乗の複数のトランジスタ２１ｂ₀ 〜２１ｂ_k ，２１ｄ₀ 〜２１ｄ_L ，２２ｂ₀ 〜２２ｂ_M ，２２ｄ₀ 〜２２ｄ_N 、４１ａ₀ 〜４１ａ_k ，４１ｃ₀ 〜４１ｃ_L ，４２ａ₀ 〜４２ａ_M ，４２ｃ₀ 〜４２ｃ_N と、面積が２のべき乗の複数のエミッタを持つトランジスタ３１ｂ，３１ｃ、５１ａ，５１ｃ，５２ａ，５２ｃを用いているが、これらは、Ｋ＋１ビット幅、Ｌ＋１ビット幅、Ｍ＋１ビット幅、及びＮ＋１ビット幅の信号によって複数のスイッチを投入することで、その信号の値に対応して電流増幅率を制御できるようにしたものであり、各面積はべき乗に限定しなくてもよい。例えば、同一のエミッタ面積としてもよい。
（２） 第７，８の実施形態では、充放電電流生成回路を図１７の回路及び参考例の充放電電流生成回路１０を用いた例を説明しているが、他の第１〜第５の実施形態のいずれの充放電流生成回路２０〜７０を用いても、第７，８の実施形態と同様の効果が得られる。
（３） 第５の実施形態では、電流制御回路６１，６６に図３の回路を用いているが、いずれか一方を図６の回路で構成しても、同様に動作し同様の効果が得られる。また、電流制御回路６２，６５に図４の回路を用いているが、いずれか一方を図７の回路で構成しても、同様に動作し同様の効果が得られる。
【００４９】
【発明の効果】
以上詳細に説明したように、第１〜第１５の発明によれば、一方の電極が固定電位に接続されたコンデンサと、入力端子と前記コンデンサとの間に接続され、入力端子から電流を入出力し該入出力電流を可変な比で減衰させた値の電流をそのコンデンサの他方の電極に与えて該コンデンサを充放電する充放電電流生成回路とで容量回路を構成したので、コンデンサの充放電電流を少なくするとともに、その充放電電流を可変に設定できる。よっ て、小さなコンデンサで集積回路を形成することができ、集積度が向上する。
【００５０】
第１６の発明によれば、コンデンサと第１及び第２の入力端子との間に、第１及び第２の充放電電流生成回路を設けたので、２端子のコンデンサの充放電電流が少なくなり、小さなコンデンサで集積回路を形成することができ、集積度が向上する。
第１７の発明によれば、コンデンサ複合回路と該コンデンサ複合回路に対する複数の入力端子との間に複数の充放電電流生成回路を設けたので、コンデンサ複合回路の各コンデンサに対する充放電電流が少なくなり、小さいコンデンサで集積回路を形成でき、集積度が向上する。
【図面の簡単な説明】
【図１】 本発明の第１の実施形態を示す容量回路の回路図である。
【図２】 本発明の第１の実施形態の参考例を示す容量回路の回路図である。
【図３】 図１中の電流制御回路２１の具体的回路を示す回路図である。
【図４】 図１中の電流制御回路２２の具体的回路を示す回路図である。
【図５】 本発明の第２の実施形態を示す容量回路の回路図である。
【図６】 図５中の電流制御回路３１の具体的回路を示す回路図である。
【図７】 図５中の電流制御回路３２の具体的回路を示す回路図である。
【図８】 本発明の第３の実施形態を示す容量回路の回路図である。
【図９】 図８中の電流制御回路４１の具体的回路を示す回路図である。
【図１０】 図８中の電流制御回路４２の具体的回路を示す回路図である。
【図１１】 本発明の第４の実施形態を示す容量回路の回路図である。
【図１２】 図１１中の電流制御回路５１の具体的回路を示す回路図である。
【図１３】 図１１中の電流制御回路５２の具体的回路を示す回路図である。
【図１４】 本発明の第５の実施形態を示す容量回路の回路図である。
【図１５】 本発明の第６の実施形態を示す容量回路の回路図である。
【図１６】 本発明の第７の実施形態を示す容量回路の回路図である。
【図１７】 図１６中の充放電電流生成回路８０Ａ，８０Ｂの構成例（その１）を示す回路図である。
【図１８】 図１６中の充放電電流生成回路８０Ａ，８０Ｂの構成例（その２）を示す回路図である。
【図１９】 本発明の第８の実施形態を示す容量回路の回路図である。
【符号の説明】
１，８０，１００ｍ
コンデンサ
１０，２０，３０，４０，５０，６０，７０，８０Ａ，８０Ｂ，１１０ｍ
充放電電流生成回路
２１，３１，４１，５１，６１
第１の電流制御回路
２２，３２，４２，５２，６２
第２の電流制御回路
６５，７３
第３の電流制御回路
６６，７４
第４の電流制御回路
ＩＮ₁ ，ＩＮ₂ ，ＩＮ
入力端子[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a capacitor circuit that is used in a semiconductor integrated circuit or the like and is charged / discharged by an input / output current.
[0002]
[Prior art]
  In a conventional integrated circuit, a large-capacity capacitor is built into an LSI chip to form a chip with a large area. When a capacitor cannot be incorporated, a large-capacity capacitor is externally attached to the chip.
[0003]
[Problems to be solved by the invention]
  However, the conventional integrated circuit has the following problems.
  When a large-capacity capacitor is required, if it is incorporated into an LSI chip, there is a problem that the chip area increases. Further, if the large-capacity capacitor is externally attached, there is a problem that it is naturally impossible to make a single chip and the entire apparatus is enlarged.
[0004]
[Means for Solving the Problems]
  In order to solve the above-mentioned problems,In the first to fifteenth inventions, in the capacitor circuit, a capacitor having two electrodes, one of which is connected to a fixed potential, and the potential of the other electrode is changed by charging and discharging, an input terminal, a capacitor, A charge / discharge current generation circuit that is connected between the input terminals and inputs / outputs current from the input terminal, and charges / discharges the input / output current by attenuating the input / output current with a variable ratio to the other electrode of the capacitor. are doing.
[0005]
  According to the first to fifteenth inventions, the charge / discharge current generation circuit weakens the charge / discharge current for other capacitors with respect to the current input / output from the input terminal, but the level is variable.
[0006]
  According to a sixteenth aspect of the present invention, in the capacitor circuit, a capacitor having two electrodes, and one of the electrodes of the capacitor connected between the first input terminal and the current input / output from the first input terminal are attenuated. A first charge / discharge current generation circuit that inputs / outputs to / from the capacitor, and is connected between the other electrode of the capacitor and the second input terminal, and attenuates current input / output from the second input terminal to the capacitor. A second charge / discharge current generation circuit for inputting and outputting is used.
  Thus, according to the sixteenth aspect, currents input / output from the first and second input terminals are attenuated by the first and second charge / discharge current generation circuits and flow into or out of the capacitor. Also in this case, the charge / discharge current for the capacitor becomes weak.
[0007]
  In a seventeenth aspect of the present invention, a capacitor composite circuit configured by combining a plurality of capacitors in series or in parallel and a plurality of input terminals connected to the capacitor composite circuit are connected. A capacitance circuit is composed of a plurality of charge / discharge current generation circuits which are attenuated by using the amplification factor and input / output to / from the capacitor.
  Thus, according to the seventeenth aspect, a weak input / output current is applied to the capacitors in the capacitor composite circuit by the plurality of charge / discharge current generation circuits.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
  An embodiment of a capacitor circuit in which the actual capacitance can be reduced by apparently increasing the capacitance of the capacitor is as follows.Reference examples and1st to 1st8The embodiment will be described. In addition,Reference examples andFirst1~6The embodiment of the first1~15The invention7The embodiment of the first16The invention and8The embodiment of the first17This corresponds to each of the inventions.
[First embodiment]
  Figure2The first embodiment of the present inventionReference exampleFIG.
  This capacity timesRoadA capacitor having one electrode connected to a ground GND having a fixed potential, and an input terminal IN₁And a charging / discharging current generation circuit 10 for applying a charging / discharging current to the capacitor 1.
[0009]
  The charge / discharge current generation circuit 10 is a circuit in which a PNP transistor that is a first conductivity type transistor and an NPN transistor that is a second conductivity type transistor are combined, and a collector that is a first conduction electrode is connected to an input terminal IN.₁And a PNP transistor 11 as a first transistor having an emitter as a second conduction electrode connected to the first power supply potential Vcc and a collector as a third conduction electrode as an input terminal IN.₁And an NPN transistor 12 which is a second transistor whose fourth conduction electrode has its emitter grounded to the ground GND, and its input terminal IN₁And an operational amplifier 13 having a non-inverting input terminal (+) connected thereto.
  The base of the transistor 11 serving as the first control electrode is connected to the collector of the fifth conduction electrode of the NPN transistor 14 serving as the third transistor, and the emitter of the transistor 14 serving as the sixth conduction electrode is connected to the operational amplifier 13. Connected to the output terminal. On the other hand, the base of the transistor 12 as the second control electrode is connected to the collector of the seventh conduction electrode of the PNP transistor 15 as the fourth transistor, and the emitter of the transistor 15 as the eighth conduction electrode is an operational amplifier. 13 output terminals.
[0010]
  The base of the transistor 14 that is the third control electrode and the base of the transistor 15 that is the fourth control electrode are connected to the other electrode of the capacitor 1 at the node a, and the inverting input terminal (−) of the operational amplifier 13. It is connected to the.
  Next, the operation of this capacitance circuit will be described.
  Input terminal IN₁When the potential inputted to the transistor rises and exceeds the potential of the node a, the operational amplifier 13 raises the potentials of the emitters of the transistors 14 and 15. The transistors 11 and 14 are in a Darlington connection, and the transistors 12 and 15 are also in a Darlington connection. Therefore, the transistor 12 and the transistor 15 are turned on, and the transistor 11 and the transistor 14 are turned off.
  The base current of the transistor 15 is the input terminal IN₁The collector current of the transistor 12 output to 1 becomes a value of 1 / the current amplification factor in the transistors 12 and 15 and flows out toward the capacitor 1. The base current of the transistor 15 at this time is the charging current Ij of the capacitor 1₁Thus, the capacitor 1 is charged.
[0011]
  Input terminal IN₁And the node a have the same potential, the base current Ij of the transistor 15₁Becomes 0. Input terminal IN₁Is lower than the potential of the node a, the operational amplifier 13 lowers the potentials of the emitters of the transistors 14 and 15. Therefore, the transistors 12 and 15 are turned off, and the transistors 11 and 14 are turned on. The base current of the transistor 14 has a value that is one-half the current amplification factor in the transistors 11 and 14 with respect to the collector current of the transistor 11 and flows out of the capacitor 1. The base current of the transistor 14 at this time is the discharge current Ih of the capacitor 1.₁Thus, the capacitor 1 is discharged. Input terminal IN₁And the node a have the same potential, the base current Ih of the transistor 14₁Becomes 0.
  As above, thisReference exampleThen, the transistors 11 and 14 connected in Darlington, the transistors 12 and 15 connected in Darlington, and the operational amplifier 13 which is connected in feedback and inputs the potential of the node a to the inverting input terminal (−) are generated. The charge / discharge current Ij that constitutes the circuit 10 and is input / output by the charge / discharge current generation circuit 10₁, Ih₁Thus, the capacitor 1 is charged and discharged.
[0012]
  Therefore, the charge / discharge current Ij of the capacitor 1₁, Ih₁Is the current gain of the transistors 11 and 15 h_fe11, H_fe15, The current amplification factor of the transistors 12 and 14 is h_fe12, H_fe14When the charge / discharge current generation circuit 10 is not provided, the input terminal IN₁If the charging / discharging currents of the capacitor 1 passing through Ij and Ih are respectively expressed by the following equations (1) and (2), they are sufficiently weakened.
        Ij₁= Ij / (h_fe12× h_fe15(1)
        Ih₁= Ih / (h_fe11× h_fe14(2)
  That is, the capacitor 1 is h_fe11× h_fe14Double or h_fe12× h_fe15The same movement as a capacitor having a double capacitance value can be made. Therefore, the degree of integration in the semiconductor integrated circuit can be improved.
  Further, the operational amplifier 3 to which the feedback is applied is connected to the potential of the node a and the input terminal IN.₁Output voltage that eliminates the difference in potential between the node a and the input terminal IN.₁Even if the potential difference between them is small, the corresponding charge / discharge current Ij₁, Ih₁Can be generated.
  On the other hand, for example, the input terminal IN₁Is directly connected to the emitters of the transistors 14 and 15, there is a possibility that the base-emitter voltage VBE is low and the transistors 14 and 15 may not be turned on. Input terminal IN₁And operate reliably even if the potential difference between the node a and the node a is small.
[0013]
FIG.Of the present invention1It is a circuit diagram of a capacitor circuit showing an embodiment of the2Elements common to the elements inside are given common reference numerals.
  This capacitance circuit (first1Invention)), one electrode was connected to the ground GNDReference exampleA capacitor 1 similar toReference exampleThe charge / discharge current generation circuit 10 is different from the charge / discharge current generation circuit 10 in FIG.
  The charge / discharge current generation circuit 20 has an input terminal IN₁Connected to the first current control circuit 21 (first2Invention) and second current control circuit 22 (second)3And the input terminal IN₁Is connected to the inverting input terminal (−), the first operational amplifier 23, and the input terminal IN₁Includes a second operational amplifier 24 connected to the non-inverting input terminal (+).
  The current control circuit 21 has an input terminal IN₁A current having a value corresponding to the current flows out from the current outflow terminal OUT1, and the outflow current can be set variably. The output terminal of the current control circuit 21 is connected to the collector of the first conduction electrode of the NPN transistor 25 that is the first transistor. The base of the transistor 25 as the first control electrode is connected to the other electrode of the capacitor 1.
[0014]
  The current control circuit 22 has an input terminal IN₁A current having a value corresponding to the current flows in from the current inflow terminal OUT2, and the value of the inflow current can be set variably. The current inflow terminal OUT2 of the current control circuit 22 is connected to the collector of the third conduction electrode of the PNP transistor 26 that is the second transistor. The emitter of the transistor 25, which is the second conduction electrode, and the emitter of the transistor 26, which is the fourth conduction electrode, are connected. The base of the transistor 26 that is the second control electrode is connected to the other electrode of the capacitor 1.
  The output terminal of the operational amplifier 24 is connected to the emitter of the transistor 25 and the emitter of the transistor 26. Each current control circuit 21, 22 has a first control terminal CC, which are connected in common to the output terminal of the operational amplifier 23. The non-inverting input terminal (+) of the operational amplifier 23 and the inverting input terminal (−) of the operational amplifier 24 are connected to the other electrode of the capacitor 1.
  Figure 31It is a circuit diagram which shows the specific circuit of the current control circuit 21 in it.
[0015]
  The current control circuit 21 has an input terminal IN₁Are connected to the base which is the third control electrode, and the PNP transistor 21a which is the third transistor having the collector which is the fifth conduction electrode connected to the current outflow terminal OUT1, and the input terminal IN.₁P + 1 type transistors 21b which are K + 1 (K is an integer of 0 or more) fourth transistors, to which collectors which are seventh conduction electrodes are respectively connected.₀~ 21b_KAnd has. Each transistor 21b as the fourth control electrode₀~ 21b_KAre commonly connected to the emitter of the transistor 21a, which is the sixth conduction electrode. Transistor 21b as the eighth conduction electrode₀~ 21b_KAre the K + 1 first switches 21c.₀~ 21c_KTo the control terminal CC. These transistors 21b₀~ 21b_KFor example, the emitter area is 2⁰, 2¹, ..., 2^kIt has become.
[0016]
  The emitter of the transistor 21a includes L + 1 (L is an integer of 0 or more) fifth PNP transistors 21d.₀~ 21d_LThe collector which is the ninth conduction electrode is connected together with the base which is the fifth control electrode. Each transistor 21d which is the tenth conducting electrode₀~ 21d_LOf the L + 1 second switch 21e.₀~ 21e_LTo the control terminal CC. These transistors 21d₀~ 21d_LFor example, the emitter area is 2⁰, 2¹, ..., 2^LIt has become.
  FIG.1It is a circuit diagram which shows the specific circuit of the current control circuit 22 in an inside.
  The current control circuit 22 has an input terminal IN₁Are connected to the base as the sixth control electrode and the NPN transistor 22a as the sixth transistor with the collector as the eleventh conduction electrode connected to the current inflow terminal OUT2, and the input terminal IN.₁N + 1 transistors 22b, which are M + 1 (M is an integer of 0 or more) seventh transistors, to which collectors that are thirteenth conductive electrodes are respectively connected.₀~ 22b_MAnd has. Each transistor 22b which is the seventh control electrode₀~ 22b_MAre commonly connected to the emitter of the transistor 22a, which is the twelfth conducting electrode. Each transistor 22b which is the 14th conductive electrode₀~ 22b_MOf the M + 1 third switches 22c₀~ 22c_MTo the control terminal CC. These transistors 22b₀~ 22b_MFor example, the emitter area is 2⁰, 2¹, ..., 2^MIt has become.
[0017]
  The emitter of the transistor 22a has N + 1 (N is an integer of 0 or more) eighth transistors, which are NPN transistors 22d.₀~ 22d_NThe collector which is the fifteenth conductive electrode is connected together with the base which is the eighth control electrode. Transistor 22d as the sixteenth conducting electrode₀~ 22d_NAre N + 1 fourth switches 22e.₀~ 22e_NTo the control terminal CC. These transistors 22d₀~ 22d_NFor example, the emitter area is 2⁰, 2¹, ..., 2^NIt has become.
[0018]
  Next, figure1The operation of the capacitor circuit will be described.
  In the current control circuit 22, when the potential of the control terminal CC drops, the transistor 22a is turned on and the transistor 22b₀~ 22b_MAnd transistor 22d₀~ 22d_NTurns on. As a result, the input terminal IN₁From the current inflow terminal OUT2 and current Iin from the current inflow terminal OUT2. The value of the input current Iin is the value of M and the switch 22c.₀~ 22c_MThe current Iout is the value of N and the switch 22e.₀~ 22e_NIt is determined by the input state. In the current control circuit 21, when the potential of the control terminal CC rises, the transistor 21a is turned on and the transistor 21b₀~ 21b_KAnd transistor 21d₀~ 21d_LTurns on. As a result, the input terminal IN₁Current Iin is output from the current output terminal, and current Iout is output from the current output terminal OUT1. The value of the input current Iin is the value of K and the switch 21c.₀~ 21c_MThe current Iout is L and the switch 21e.₀~ 21e_LIt is determined by the input state. That is, since each current control circuit 21, 22 has a current mirror configuration, the current Iin and current Iout in the current control circuit 21 are expressed by the following equation (3) and the current Iin in the current control circuit 22. And the current Iout are in the relationship of equation (4).
[0019]
[Expression 1]

  Note that (Set) and (Sct) in the equations (3) and (4) are values indicating the ON state of each switch in the current control circuits 21 and 22, and “1” in the case of the ON switch. In the case of a switch that is not turned on, it takes a value of “0”. In the mathematical formulas to be described later, the same symbols indicate the same contents.
[0020]
  Figure1In this circuit, the input terminal IN₁Is increased by the operational amplifiers 23 and 24, the potentials of the control terminals CC of the current control circuits 21 and 22 are decreased, and the potentials of the emitters of the transistors 25 and 26 are increased. As a result, the current control circuit 21 and the transistor 25 are turned off, and the current control circuit 22 and the transistor 26 are turned on. Therefore, input terminal IN₁The charge (current) is input from the current control circuit 22 to the current control circuit 22, and the charge attenuated to 1 / multiple of the current amplification factor of the charge flows into the current inflow terminal OUT2 of the current control circuit 22. In addition, the charge attenuated by the current amplification factor of 1 by the transistor 26 flows from the base of the transistor 26 to the other electrode of the capacitor 1. Thereby, the capacitor 1 is charged.
[0021]
  Input terminal IN₁Is lowered by the operational amplifiers 23 and 24, the potentials of the control terminals CC of the current control circuits 21 and 22 are raised, and the potentials of the emitters of the transistors 25 and 26 are lowered. As a result, the current control circuit 21 and the transistor 25 are turned on, and the current control circuit 22 and the transistor 26 are turned off. Therefore, from the current control circuit 21 to the input terminal IN₁The charge is output from the current outflow terminal OUT1 of the current control circuit 21. In addition, the charge attenuated by a factor of 1 by the transistor 25 flows into the base of the transistor 25 from the other electrode of the capacitor 1. As a result, the capacitor 1 is discharged.
  As above, this number1In the capacitor circuit of the embodiment, the charge / discharge current generating circuit 20 having the current control circuits 21 and 22 and the capacitor 1 constitute the capacitor circuit, so that the current amplification factor of each NPN transistor is set to h_fen, The current amplification factor of each PNP transistor_fep, The capacity of the capacitor 1 is C₁Then, when charging the electric charge, it works in the same manner as a capacitor having the capacity C shown by the following equation (5), and when discharging the electric charge, the capacitor having the capacitance C shown by the equation (6) Work equally.
[0022]
[Expression 2]

  Therefore, in this capacity circuit, the range in which the capacity can be adjusted can be determined by setting the values of K, L, M, and N, and fine adjustment within the range can be performed by a plurality of switches in each of the current control circuits 21 and 22. It can be changed. Furthermore, depending on the setting of the values of K, L, M, and N, apparent capacitance can be amplified, and the degree of integration in the integrated circuit is improved.
[0023]
[First2Embodiment of]
  FIG. 5 shows the first aspect of the present invention.2It is a circuit diagram of a capacitor circuit showing an embodiment of the1Elements common to the elements inside are given common reference numerals.
  This capacitor circuit has a first electrode in which one electrode is connected to the ground GND.1The capacitor 1 is the same as that of the first embodiment, and the charge / discharge current generation circuit 30 is different from the charge / discharge current generation circuits 10 and 20.
  The charge / discharge current generation circuit 30 replaces the current control circuits 21 and 22 in the charge / discharge current generation circuit 20 with the first current control circuit 31 (first4The second current control circuit 32 (second)5The rest of the configuration is the same as that of the charge / discharge current generation circuit 20.
  FIG. 6 is a circuit diagram showing a specific circuit of the current control circuit 31 in FIG.
[0024]
  The current control circuit 31 has an input terminal IN₁Are connected to the base which is the ninth control electrode and the collector which is the seventeenth conducting electrode is connected to the current outflow terminal OUT1, the PNP transistor 31a which is the ninth transistor and the input terminal IN.₁Are connected to the collector which is the nineteenth conduction electrode, and the PNP transistor 31b of the tenth transistor in which the emitter of the transistor 31a which is the eighteenth conduction electrode is connected to the base which is the tenth control electrode; A PNP transistor 31c which is an eleventh transistor having an emitter connected to the collector of the twenty-first conductive electrode and a base of the eleventh control electrode.
  The transistor 31b has K + 1 emitters, and each emitter has K + 1 fifth switches 31d.₀~ 31d_KTo the control terminal CC. The transistor 31c has L + 1 emitters, and each emitter has L + 1 sixth switches 31e.₀~ 31e_LTo the control terminal CC. The area of each emitter of the transistor 31b is, for example, 2⁰, 2¹, ..., 2^kIt has become. The area of each emitter of the transistor 31c is 2⁰, 2¹, ..., 2^LIt has become.
[0025]
  FIG. 7 is a circuit diagram showing a specific circuit of the current control circuit 32 in FIG.
  The current control circuit 32 has an input terminal IN₁Are connected to the base which is the twelfth control electrode and the NPN transistor 32a which is the twelfth transistor having the collector which is the twenty-third conduction electrode connected to the current inflow terminal OUT2, and the input terminal IN.₁Are connected to the collector which is the 25th conduction electrode, and the NPN transistor 32b of the 13th transistor in which the emitter of the transistor 32a which is the 24th conduction electrode is connected to the base which is the 13th control electrode; And an NPN transistor 32c of a thirteenth transistor having an emitter connected to a collector which is a twenty-seventh conduction electrode and a base which is a fourteenth control electrode.
[0026]
  The transistor 32b has M + 1 emitters that are 26th conducting electrodes, and each emitter has M + 1 seventh switches 32d.₀~ 32d_MTo the control terminal CC. The transistor 32c has N + 1 emitters that are 28th conduction electrodes, and each emitter has N + 1 eighth switches 32e.₀~ 32e_NTo the control terminal CC. The area of each emitter of the transistor 32b is, for example, 2⁰, 2¹, ..., 2^MIt has become. The area of each emitter of the transistor 32c is, for example, 2⁰, 2¹, ..., 2^NIt has become.
  In the capacity circuit of FIG. 5 having the current control circuits 31 and 32 of FIGS. 6 and 7, the current control circuits 31 and 32 perform the same operation as the current control circuits 21 and 22, respectively.1The first1The same operation as in the embodiment is performed.
  Therefore, the second1The same effect as that of the embodiment can be expected.
[0027]
[First3Embodiment of]
  FIG.3It is a circuit diagram of a capacitor circuit showing an embodiment of the2Elements common to the elements inside are given common reference numerals.
  This capacitor circuit has one electrode connected to the ground GND.Reference exampleA capacitor 1 similar toReference exampleIs different from the charge / discharge current generation circuit 10 in FIG.6Invention).
  The charge / discharge current generation circuit 40 is connected to the input terminal IN.₁Is connected to the first current control circuit 41 (first7Invention) and the second current control circuit 42 (second)8And the input terminal IN₁Is provided with an operational amplifier 43 connected to the non-inverting input terminal (+).
  The current control circuit 41 has an input terminal IN₁Is output from the current inflow terminal OUT3, and the value of the inflow current can be set variably. The current inflow terminal OUT3 of the current control circuit 41 is connected to the collector of the first conduction electrode of the PNP transistor 44 that is the first transistor. The emitter of the transistor 44 that is the second conduction electrode is connected to the first power supply potential Vcc, and the base of the transistor 44 that is the first control electrode is the third transistor of the NPN transistor 45 that is the second transistor. Connected to the collector of the conducting electrode. That is, the transistor 44 and the transistor 45 are in a Darlington connection. The base of the transistor 45 that is the second control electrode is connected to the other electrode of the capacitor 1.
[0028]
  The current control circuit 42 has an input terminal IN₁Is supplied from the current outflow terminal OUT4, and the value of the outflow current can be set variably. The current outflow terminal OUT4 of the current control circuit 42 is connected to the collector of the fifth conduction electrode of the NPN transistor 46 that is the third transistor. The emitter of the transistor 46 which is the sixth conduction electrode is connected to the ground GND, and the base of the transistor 46 which is the third control electrode is connected to the collector of the seventh conduction electrode of the PNP transistor 47 which is the fourth transistor. Has been. That is, the transistor 46 and the transistor 47 are in a Darlington connection. The base of the transistor 47 that is the fourth control electrode is connected to the other electrode of the capacitor 1.
  The emitter of the transistor 45, which is the fourth conduction electrode, and the emitter of the transistor 47, which is the eighth conduction electrode, are connected to the output terminal of the operational amplifier 43, and the other electrode of the capacitor 1 is connected to the inverting input terminal ( -) Is connected. The power supply terminal CC of the current control circuit 41 is connected to the power supply potential Vcc, and the power supply terminal CC of the current control circuit 42 is connected to the ground GND.
[0029]
  FIG. 9 is a circuit diagram showing a specific circuit of the current control circuit 41 in FIG.
  This current control circuit 42 includes K + 1 NPN transistors 41a which are fifth transistors in which a collector which is a ninth conduction electrode is connected to the power supply terminal CC.₀~ 41a_KIt has. Each transistor 41a which is the tenth conducting electrode₀~ 41a_KThe emitters of the K + 1 first switches 41b₀~ 41b_KThrough the input terminal IN₁It is connected to the. Transistor 41a as the fifth control electrode₀~ 41a_KAre commonly connected to the current inflow terminal OUT3. The current inflow terminal OUT3 has L + 1 NPN transistors 41c, which are sixth transistors.₀~ 41c_LThe base of the sixth control electrode is connected, and each transistor 41c which is the eleventh conduction electrode₀~ 41c_LCollectors are connected. Each transistor 41c which is the twelfth conducting electrode₀~ 41c_LOf the L + 1 second switch 41d₀~ 41d_LThrough the input terminal IN₁It is connected to the. Transistor 41a₀~ 41a_KFor example, the emitter area is 2⁰, 2¹, ..., 2^kIt has become. Transistor 41c₀~ 41c_LFor example, the emitter area is 2⁰, 2¹, ..., 2^LIt has become.
[0030]
  FIG. 10 is a circuit diagram showing a specific circuit of current control circuit 42 in FIG.
  This current control circuit 42 includes a PNP transistor 42a, which is an M + 1 seventh transistor in which a collector, which is a thirteenth conduction electrode, is connected to the power supply terminal CC.₀~ 42a_MIt has. Each transistor 42a which is the 14th electrode₀~ 42a_MOf the M + 1 third switches 42b₀~ 42b_MThrough the input terminal IN₁Connected in common. Each transistor 42a which is the seventh control electrode₀~ 42a_MAre commonly connected to the current outflow terminal OUT4. The current outflow terminal OUT4 has N + 1 PNP transistors 42c as the eighth transistor.₀~ 42c_NThe base of the seventh control electrode is connected, and each transistor 42c which is the fifteenth conduction electrode₀~ 42c_NCollectors are connected in common. Each transistor 42c which is the sixteenth conducting electrode₀~ 42c_NAre N + 1 fourth switches 42d.₀~ 42d_NThrough the input terminal IN₁Connected in common. Transistor 42a₀~ 42a_MFor example, the emitter area is 2⁰, 2¹, ..., 2^MIt has become. Transistor 42c₀~ 42c_NFor example, the emitter area is 2⁰, 2¹, ..., 2^NIt has become.
[0031]
  Next, the operation of this capacitance circuit will be described.
  In the current control circuit 41, the input terminal IN with the power supply terminal CC kept at the “H” level.₁When the potential of the transistor 41a drops, each transistor 41a₀~ 41a_K, 41c₀~ 41c_LTurns on and switch 41b₀~ 41b_K, 41d₀~ 41d_LThe charge having a value corresponding to the input state of flows in from the current inflow terminal OUT3. Charge flowing in from the current inflow terminal OUT3 and the switch 41b₀~ 41b_K, 41d₀~ 41d_LThe charge determined by the input state of the input terminal IN₁Is output.
  Similarly, in the current control circuit 42, the input terminal IN with the power supply terminal CC kept at “L”.₁When the potential of the transistor 42a rises, each transistor 42a₀~ 42a_M42c₀~ 42c_NTurns on and switch 42b₀~ 42b_M42d₀~ 42d_NThe charge having a value corresponding to the input state of flows out from the current outflow terminal OUT4. Charge flowing out from the current outflow terminal OUT4 and the switch 42b₀~ 42b_M42d₀~ 42d_NThe charge determined by the input state of the input terminal IN₁It is input from. Since each of the current control circuits 41 and 42 has a current mirror configuration, the relationship between the input current Iin and the output current Iout in the current control circuits 41 and 42 is expressed by the following equations (7) and (8). Become.
[0032]
[Equation 3]

  In the capacitor circuit of FIG. 8 having the current control circuits 41 and 42, the input terminal IN₁Rises, the operational amplifier 43 raises the potentials of the emitters of the transistors 45 and 47. Therefore, the transistors 44 and 45 are turned off, and the current control circuit 41 is also turned off. On the other hand, the transistors 46 and 47 are turned on, and the current control circuit 42 is also turned on. At this time, the current control circuit 42 is connected to the input terminal IN.₁From the current control circuit 42 is multiplied by the current amplification factor and flows out from the current outflow terminal OUT4. This electric charge is attenuated by a factor of these current amplification factors by the transistors 46 and 47 and applied to the capacitor 1. Thus, the capacitor 1 is charged.
[0033]
  Input terminal IN₁, The operational amplifier 43 causes the emitter potentials of the transistors 45 and 47 to drop. Therefore, the transistors 44 and 45 are turned on, and the current control circuit 41 is also turned on. On the other hand, the transistors 46 and 47 are turned off, and the current control circuit 42 is turned off. In this state, the current control circuit 41 inputs the input terminal IN.₁A charge obtained by multiplying the charge flowing out by the current amplification factor flows into the current inflow terminal OUT3 of the current control circuit 41. The transistors 44 and 45 absorb from the capacitor 1 a charge whose value has been attenuated to 1 / current amplification factor. Thereby, the capacitor 1 is discharged.
  As above, this number3In the capacitor circuit of the embodiment, the charge / discharge current generating circuit 40 having the current control circuits 41 and 42 and the capacitor 1 constitute the capacitor circuit, so that the current amplification factors of the NPN transistors 45 and 46 are set to h._fen, The current amplification factor of each PNP transistor 44, 47 is h_fep, The capacity of the capacitor 1 is C₁Then, when charging the charge, it works in the same way as a capacitor having the capacity C shown by the following equation (9), and when discharging the charge, the capacitor having the capacity C shown by the equation (10) Work equally.
[0034]
[Expression 4]

  Therefore, in this capacity circuit, the range in which the capacity can be adjusted can be determined by setting the values of K, L, M, and N, and fine adjustment within the range can be performed by a plurality of switches in each of the current control circuits 41 and 42. It can be changed. In addition, the value of the gain in charging and discharging is the current gain h_fenAnd h_fepAdjustment is easy because a balance can be achieved regardless of the value of. In addition, since the transistors 44 and 45 and the transistors 46 and 47 are Darlington connected, respectively, the current amplification factor is increased, and the apparent capacity of the capacitor 1 can be further increased. Therefore, the degree of integration in the integrated circuit is improved.
[0035]
[First4Embodiment of]
  FIG. 11 shows the first of the present invention.4FIG. 9 is a circuit diagram of a capacitor circuit showing the embodiment, and elements common to those in FIG. 8 are denoted by common reference numerals.
  This capacitor circuit has a first electrode in which one electrode is connected to the ground GND.3A capacitor 1 similar to that of the first embodiment,3The charge / discharge current generating circuit 50 is different from the charge / discharge current generating circuit 40 in the embodiment.
  The charge / discharge current generation circuit 50 replaces the current control circuits 41 and 42 in the charge / discharge current generation circuit 40 with the first current control circuit 51 (first step).9Invention) and a second current control circuit, 52 (second10The rest of the configuration is the same as that of the charge / discharge current generating circuit 40.
[0036]
  FIG. 12 is a circuit diagram showing a specific circuit of current control circuit 51 in FIG.
  The current control circuit 51 includes an NPN transistor 51a that is a ninth transistor in which a collector that is a seventeenth conduction electrode is connected to the power supply terminal CC. The transistor 51a has (K + 1) emitters that are the eighteenth conducting electrodes. The area of each emitter of the transistor 51a is, for example, 2⁰, 2¹, ..., 2^kAnd each emitter has K + 1 fifth switches 51b.₀~ 51b_KThrough the input terminal IN₁Connected in common. The base of the transistor 51a, which is the ninth control electrode, is connected to the current inflow terminal OUT3. The current inflow terminal OUT3 is connected to the base which is the tenth control electrode of the NPN transistor 51c which is the tenth transistor and to the collector of the transistor 51c which is the nineteenth conduction electrode. The transistor 51c has an emitter that is L + 1 20th conducting electrodes. The area of each emitter of the transistor 51c is, for example, 2⁰, 2¹, ..., 2^LEach emitter has L + 1 sixth switches 51d.₀~ 51d_LThrough the input terminal IN₁Connected in common.
[0037]
  FIG. 13 is a circuit diagram showing a specific circuit of current control circuit 52 in FIG.
  The current control circuit 52 includes a PNP transistor 52a that is an eleventh transistor having a collector that is a twenty-first conductive electrode connected to a power supply terminal CC. The transistor 52a has M + 1 emitters which are 22nd conduction electrodes. The area of each emitter of the transistor 52a is, for example, 2⁰, 2¹, ..., 2^MAnd each emitter has M + 1 seventh switches 52b.₀~ 52b_MThrough the input terminal IN₁Connected in common. The base of the transistor 52a as the eleventh control electrode is connected to the current outflow terminal OUT4. The current outflow terminal OUT4 is connected to the base which is the twelfth control electrode of the PNP transistor 52c, which is the twelfth transistor, and to the collector of the transistor 52c, which is the twenty-third conduction electrode. The transistor 52c has N + 1 emitters that are 24th conductive electrodes. The area of each emitter of the transistor 52c is, for example, 2⁰, 2¹, ..., 2^NAnd each emitter has N + 1 eighth switches 52d.⁰~ 52d_NThrough the input terminal IN₁Connected in common.
  In the capacity circuit of FIG. 11 having the current control circuits 51 and 52 of FIGS. 12 and 13, the current control circuits 51 and 52 perform the same operation as the current control circuits 41 and 42.8The first3The same operation as in the embodiment is performed. Therefore, the second3The same effect as that of the embodiment can be expected.
[0038]
[First5Embodiment of]
  FIG. 14 shows the first of the present invention.5It is a circuit diagram of a capacitor circuit showing an embodiment of the2Elements common to the elements inside are given common reference numerals.
  This capacitor circuit has one electrode connected to the ground GND.Reference exampleA capacitor 1 similar toReference exampleThe charge / discharge current generation circuit 60 (first) is different from the charge / discharge current generation circuit 10 in FIG.11Invention).
  The charge / discharge current generation circuit 60 includes a first current control circuit 61 and a second current control circuit 62 connected to the input terminal IN, and a first current control circuit in which the input terminal IN is connected to the inverting input terminal (−). An operational amplifier 63 and a second operational amplifier 64 whose input terminal IN is connected to the non-inverting input terminal (+) are provided.
  The current control circuit 61 outputs a current to the input terminal IN, but a current having a value corresponding to the current flows out from the current outflow terminal OUT5, and the outflow current can be set variably. A third current control circuit 65 is connected to the current outflow terminal OUT5 of the current control circuit 61. The current control circuit 65 receives a current from the current control circuit 61, and flows a current having a value corresponding to the current from the current inflow terminal OUT6. The value of the inflow current can be arbitrarily set. ing.
[0039]
  The current control circuit 62 inputs a current from the input terminal IN, and flows a current having a value corresponding to the current from the current inflow terminal OUT7. The inflow current can be variably set. A fourth current control circuit 66 is connected to the current inflow terminal OUT7 of the current control circuit 62. The current control circuit 66 outputs a current to the current control circuit 62. The current control circuit 66 outputs a current having a value corresponding to the current from the current inflow terminal OUT8, and the value of the outflow current can be set variably. ing.
  Control terminals CC of the current control circuit 61 and the current control circuit 62 are connected to the output terminal of the operational amplifier 63. The control terminals CC of the current control circuit 65 and the current control circuit 66 are connected to the output terminal of the operational amplifier 64. The current inflow terminal OUT6 of the current control circuit 65 and the current outflow terminal OUT8 of the current control circuit 66 are connected to the other side of the capacitor 1.
  Each current control circuit 61 and current control circuit 66 are configured by current control circuits similar to those in FIG.12,13Invention), current control circuit 62 and current control circuit 65 (first)14,15The present invention comprises a current control circuit similar to that shown in FIG.
[0040]
  Next, the operation of this capacitance circuit will be described.
  The current control circuit 61 and the current control circuit 66 perform the same operation as the current control circuit 21 of the second embodiment according to the potential of the control terminal CC. The current control circuit 62 and the current control circuit 65 perform the same operation as the current control circuit 22 according to the potential of the control terminal CC.
  In the capacitor circuit of FIG. 14 having these current control circuits 61, 62, 65, 66, the input terminal IN₁Is increased, the first control voltage is applied to the control terminals CC of the current control circuits 61 and 62 by the operational amplifier 63 to decrease the potential, and the operational amplifier 64 controls the current control circuits 63 and 64. When the first control voltage is applied to the terminal CC, the potential rises. Thereby, the current control circuits 61 and 65 are turned off, and the current control circuits 62 and 66 are turned on. Therefore, input terminal IN₁Is input to the current control circuit 62, and the charge multiplied by the current amplification factor in the current control circuit 62 is output from the current control circuit 66 and flows into the current inflow terminal OUT7 of the current control circuit 62. A charge obtained by multiplying the charge output from the current control circuit 66 by the current amplification factor of the current control circuit 66 flows out from the current outflow terminal OUT8 of the current control circuit 66 to the capacitor 1. Thereby, the capacitor 1 is charged.
[0041]
  Next, input terminal IN₁Is lowered by the operational amplifier 63, and the potential of the control terminal CC of the current control circuits 63 and 64 is lowered by the operational amplifier 64. Thereby, the current control circuits 61 and 65 are turned on, and the current control circuits 62 and 66 are turned off. At this time, the input terminal IN₁The electric charge is output from the current control circuit 61, and the electric charge multiplied by the current amplification factor in the current control circuit 61 flows out from the current outflow terminal OUT5 of the current control circuit 61 to the current control circuit 65. A charge obtained by multiplying the charge output from the current control circuit 61 by the current amplification factor of the current control circuit 65 flows from the capacitor 1 into the current inflow terminal OUT6 of the current control circuit 65. As a result, the capacitor 1 is discharged.
  As above, this number5In the capacitor circuit of the embodiment, the charge / discharge current generation circuit 60 is provided with current control circuits 61, 62, 65, 66, and the charging current of the capacitor 1 is generated using the current amplification factor of the current control circuits 62, 66. The discharge current is generated using the current amplification factors of the current control circuits 61 and 65. Therefore, when the capacitor 1 is charged, the capacitor 1 works in the same way as a capacitor having a capacity C as shown in the following equation (11), and when discharged, it works as a capacitor having a capacity C as shown in the equation (12).
[0042]
[Equation 5]

  Here, K and L in the equation (11) are values in the current control circuit 62, and M and N are values in the current control circuit 66. In the equation (12), K and L are values in the current control circuit 65, and M and N indicate values in the current control circuit 61.
  As can be seen from the equations (11) and (12), in the capacitor circuit of this embodiment, by adjusting the values of K, L, M, and N, the value of the capacitor C can be adjusted and its range can be determined. . In addition, depending on the switch-on state, the capacity C can be finely adjusted and changed within that range. In this capacity circuit, the transistor amplification factor itself is not included in (11) and (12), so that the capacity C can be set more accurately. Further, since the capacity can be set by the two-stage current control circuits 61 and 65 and the current control circuits 62 and 65, the apparent capacity is amplified by the values of K, L, M, and N in the second embodiment. It becomes easier than the form, and the degree of integration in the integrated circuit is improved.
[0043]
[First6Embodiment of]
  FIG. 15 shows the first of the present invention.6FIG. 15 is a circuit diagram of a capacitor circuit showing the embodiment, and elements common to elements in FIG. 14 are denoted by common reference numerals.
  This capacitor circuit has a first electrode in which one electrode is connected to the ground GND.5A capacitor 1 similar to that of the first embodiment,5The charge / discharge current generation circuit 60 is different from the charge / discharge current generation circuit 60 in the embodiment.
  In the charge / discharge current generation circuit 70, the current control circuits 61 and 62 in the charge / discharge current generation circuit 60 are replaced with current control circuits 71 and 72, and the current control circuits 65 and 66 are replaced with current control circuits 73 and 74. It is. Other configurations of the charge / discharge current generation circuit 70 are the same as those of the charge / discharge current generation circuit 60.
  Each current control circuit 71 and current control circuit 74 are each configured by a current control circuit similar to FIG. 6, and the current control circuit 72 and the current control circuit 73 are each configured by a current control circuit similar to FIG. .
  In the capacitor circuit of FIG. 15 having the current control circuits 71 to 74, the current control circuits 71 and 73 perform the same operations as the current control circuits 61 and 65, respectively, and the current control circuits 72 and 74 are the current control circuits. 14 and 66, the same operation is performed.5The same operation as in the embodiment is performed. Therefore, the second5The same effect as that of the embodiment can be expected.
[0044]
[First7Embodiment of]
  FIG. 16 shows the first of the present invention.7It is a circuit diagram of the capacitor circuit showing the embodiment.
  1st to 1st6In the capacitive circuit according to the embodiment, the capacitive circuit using the capacitor having one electrode grounded to the ground GND is used.7The capacitive circuit of this embodiment includes a capacitor 80 in which neither of the electrodes is fixed at a fixed potential (first16Invention). One electrode of the capacitor 80 is connected to the first input terminal IN.₁Is connected to the output terminal of the charge / discharge current generating circuit 80A. The other electrode of the capacitor 80 is connected to the second input terminal IN.₂Connected to the output terminal of the charge / discharge current generating circuit 80B connected toThe
  FIG. 17 is a circuit diagram showing a configuration example (No. 1) of the charge / discharge current generation circuits 80A and 80B in FIG.
  In this charge / discharge current generation circuit, the collector which is the first conduction electrode is connected to the input terminal IN.₁Or IN₂And a PNP transistor 81 as a first transistor of the first conductivity type whose emitter as a second conduction electrode is connected to the power supply potential Vcc, and a collector as a third conduction electrode as an input terminal IN₁Or IN₂And an NPN transistor 82, which is a second transistor of the second conductivity type, whose emitter is connected to the ground GND and grounded to the ground GND.
[0045]
  The base of the transistor 81 that is the first control electrode is connected to the collector of the fifth conduction electrode of the NPN transistor 83 that is the third transistor. On the other hand, the base of the transistor 82 as the second control electrode is connected to the collector of the seventh conduction electrode of the PNP transistor 84 as the fourth transistor. The emitter of the transistor 83 which is the sixth conduction electrode has the input terminal IN together with the emitter of the transistor 84 which is the eighth conduction electrode.₁Or IN₂It is connected to the. The base of the transistor 83 that is the third control electrode and the base of the transistor 84 that is the fourth control electrode are connected in common to any electrode of the capacitor 80.Thising.
  Next, the operation of the capacitance circuit in which the charge / discharge current generation circuits 80A and 80B each configured by the circuit of FIG. 17 are connected to both electrodes of the capacitor 80 will be described.
  For example, input terminal IN₁Rises, the potentials of the emitters of the transistors 83 and 84 rise, the transistors 82 and 84 are turned on, and the transistors 81 and 83 are turned off. Therefore, input terminal IN₁The charge is input to the charge / discharge current generation circuit 80A. Then, a charge corresponding to a current amplification factor in the Darlington connection constituted by the transistors 82 and 84 flows from the output terminal of the charge / discharge current generation circuit 80A to the capacitor 80. Then, the capacitor 80 pushes out charges having the same value as the charge from the charge / discharge current generation circuit 80A to the charge / discharge current generation circuit 80B side. As a result, the transistor 83 and the transistor 81 in the charge / discharge current generation circuit 80B are turned on, and the charge obtained by multiplying the charge drawn into the capacitor 80 by the current amplification factor of the Darlington connection configured by the transistors 83 and 81 becomes the input terminal. IN₂Spilled through.
[0046]
  FIG. 18 is a circuit diagram showing a configuration example (No. 2) of the charge / discharge current generation circuits 80A and 80B in FIG.
  The charge / discharge currents 80A and 80B are:Reference exampleThe charge / discharge current generation circuit 10 used in the above can be configured respectively.TheWhen the charge / discharge current generation circuit of FIG. 17 is used, for example, the input terminal IN₁It is assumed that the entire circuit does not operate unless the potential difference between the potential of the capacitor 80 and the electrode of the capacitor 80 reaches the voltage VBE at which the transistor 84 is turned on, but the operational amplifier 13 is provided as shown in FIG. And input terminal IN₁Even if the potential difference between the potential of the capacitor and the electrode of the capacitor 80 is small, the operation becomes possible. Note that one of the charge / discharge currents 80A and 80B can be configured by the circuit of FIG. 17 and the other by the circuit of FIG.
  As above, this number7In this embodiment, both electrodes of the capacitor 80 and the input terminal IN₁, IN₂Are provided with charge / discharge current generation circuits 80A and 80B, respectively. Therefore, the input terminal IN₁A large current from the input terminal IN₂Since a current having the same magnitude as that flows in and out, a circuit having a large capacity is formed. However, the capacitor 80 flows only a weak current that is a fraction of the current amplification factor of the Darlington connection. . That is, a circuit having a large capacitance value can be configured with the capacitor 80 having a small capacitance, and the degree of integration in the integrated circuit is improved.
[0047]
[First8Embodiment of]
  FIG. 19 shows the first of the present invention.8It is a circuit diagram of the capacitor circuit showing the embodiment.
  This capacitance circuit has a capacitor composite circuit 100 in which a plurality of capacitors 100m (m is an arbitrary integer of 2 or more) are connected in series or in parallel. A charge / discharge current generation circuit 110m is connected to a plurality of input terminals IN in the capacitor composite circuit 100 (first).17Invention). The charge / discharge current generation circuit 110m includes the charge / discharge current generation circuit of FIG. 17 or the charge / discharge current generation circuit of FIG.
  In this capacitance circuit, the charge input from each input terminal IN is attenuated by a current amplification factor by the charge / discharge current generation circuit 110 m and supplied to each capacitor 100 m in the capacitor composite circuit 100. Then, the electric charge calculated in the capacitor composite circuit 100 is multiplied by the current amplification factor and output from each input terminal IN.
  As above, this number8In the capacitor circuit of this embodiment, the charge / discharge current generation circuit 110m is provided at each input terminal IN of the capacitor composite circuit 100 composed of a plurality of capacitors 100m, and the current attenuated to 1 / the current amplification factor is combined with the capacitor composite. A current multiplied by the current amplification factor can be supplied to the circuit 100 and output from each input terminal IN, and all the capacitors 100m can be used as capacitors having a capacity that is double the current amplification factor. Can be improved. In addition, the charge / discharge current generation circuit 110m is not connected to both electrodes of each capacitor 100m.7A smaller integrated circuit can be realized as compared with the case where the capacitive circuit of the embodiment is combined.
[0048]
  In the present invention, the aboveReference examples andVarious modifications are possible without being limited to the embodiments. Examples of such modifications include the following.
  (1)Reference examples and1st to 1st6In this embodiment, the plurality of transistors 21b whose emitter area is a power of 2₀~ 21b_k, 21d₀~ 21d_L, 22b₀~ 22b_M, 22d₀~ 22d_N41a₀~ 41a_k, 41c₀~ 41c_L42a₀~ 42a_M42c₀~ 42c_NTransistors 31b, 31c, 51a, 51c, 52a, 52c having a power of 2 are used, which are K + 1 bit width, L + 1 bit width, M + 1 bit width, and N + 1 bit width. By turning on a plurality of switches according to the signal, the current amplification factor can be controlled according to the value of the signal, and each area does not have to be limited to a power. For example, the same emitter area may be used.
  (2) No.7,8In the embodiment, the charge / discharge current generation circuit is replaced with the circuit of FIG.Reference exampleAlthough an example using the charge / discharge current generation circuit 10 is described,1~5Even if any of the charge / discharge current generation circuits 20 to 70 of the embodiment is used,7,8The same effect as in the embodiment can be obtained.
  (3) No.5In the present embodiment, the circuit of FIG. 3 is used for the current control circuits 61 and 66. However, even if one of them is configured by the circuit of FIG. Further, although the circuit of FIG. 4 is used for the current control circuits 62 and 65, even if one of them is configured by the circuit of FIG.
[0049]
【The invention's effect】
  As explained in detail above,According to the first to fifteenth inventions, one electrode is connected between a fixed potential and an input terminal and the capacitor, current is input / output from the input terminal, and the input / output current is variable. Since the capacitor circuit is configured with a charge / discharge current generation circuit that charges and discharges the capacitor by applying a current of a value attenuated at a certain ratio to the other electrode of the capacitor, the charge / discharge current of the capacitor is reduced, and Charging / discharging current can be set variably. By Thus, an integrated circuit can be formed with a small capacitor, and the degree of integration is improved.
[0050]
  According to the sixteenth aspect, since the first and second charge / discharge current generation circuits are provided between the capacitor and the first and second input terminals, the charge / discharge current of the two-terminal capacitor is reduced. An integrated circuit can be formed with a small capacitor, and the degree of integration is improved.
  According to the seventeenth aspect, since the plurality of charge / discharge current generation circuits are provided between the capacitor composite circuit and the plurality of input terminals for the capacitor composite circuit, the charge / discharge current for each capacitor of the capacitor composite circuit is reduced. An integrated circuit can be formed with a small capacitor, and the degree of integration is improved.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a capacitor circuit showing a first embodiment of the present invention.
FIG. 2 shows the first aspect of the present invention.1Embodiment ofReference exampleFIG.
FIG. 31It is a circuit diagram which shows the specific circuit of the current control circuit 21 in it.
FIG. 41It is a circuit diagram which shows the specific circuit of the current control circuit 22 in an inside.
FIG. 5 shows the first of the present invention.2It is a circuit diagram of the capacitor circuit showing the embodiment.
6 is a circuit diagram showing a specific circuit of the current control circuit 31 in FIG. 5. FIG.
7 is a circuit diagram showing a specific circuit of the current control circuit 32 in FIG. 5. FIG.
FIG. 8 shows the first of the present invention.3It is a circuit diagram of the capacitor circuit showing the embodiment.
9 is a circuit diagram showing a specific circuit of the current control circuit 41 in FIG. 8. FIG.
10 is a circuit diagram showing a specific circuit of the current control circuit 42 in FIG. 8. FIG.
FIG. 11 shows the first of the present invention.4It is a circuit diagram of the capacitor circuit showing the embodiment.
12 is a circuit diagram showing a specific circuit of the current control circuit 51 in FIG. 11. FIG.
13 is a circuit diagram showing a specific circuit of current control circuit 52 in FIG. 11. FIG.
FIG. 14 shows the first of the present invention.5It is a circuit diagram of the capacitor circuit showing the embodiment.
FIG. 15 shows the first of the present invention.6It is a circuit diagram of the capacitor circuit showing the embodiment.
FIG. 16 shows the first of the present invention.7It is a circuit diagram of the capacitor circuit showing the embodiment.
17 is a circuit diagram showing a configuration example (No. 1) of charge / discharge current generation circuits 80A and 80B in FIG. 16;
18 is a circuit diagram showing a configuration example (No. 2) of the charge / discharge current generation circuits 80A and 80B in FIG. 16;
FIG. 19 shows the first of the present invention.8It is a circuit diagram of the capacitor circuit showing the embodiment.
[Explanation of symbols]
  1,80,100m
          Capacitor
  10, 20, 30, 40, 50, 60, 70, 80A, 80B, 110m
          Charge / discharge current generation circuit
  21, 31, 41, 51, 61
          First current control circuit
  22, 32, 42, 52, 62
          Second current control circuit
  65,73
          Third current control circuit
  66, 74
          Fourth current control circuit
  IN₁, IN₂, IN
          Input terminal

Claims (17)

A capacitor having two electrodes, one of which is connected to a fixed potential, and the potential of the other electrode is changed by charging and discharging;
The capacitor is connected between the input terminal and the capacitor, and current is input / output from the input terminal and a current obtained by attenuating the input / output current with a variable ratio is applied to the other electrode of the capacitor to fill the capacitor. A charge / discharge current generating circuit for discharging;
A capacitance circuit comprising:
The charge / discharge current generation circuit
It is connected to the input terminal and has a variable current amplification factor, and is turned on / off based on a given control voltage. In the ON state, a current is output to the input terminal and the current value is multiplied by the current amplification factor. A first current control circuit for draining the generated current;
It is connected to the input terminal and has a variable current amplification factor, and is turned on / off in a complementary manner with the first current control circuit based on the control voltage, and current is input from the input terminal in the on state. And a second current control circuit for flowing a current obtained by multiplying the current value by the current amplification factor,
The conduction state between the first conduction electrode is controlled by the first conduction electrode connected to the first current control circuit, the first control electrode connected to the other electrode of the capacitor, and the first control electrode. And is turned on based on a potential difference between the first control electrode and the second conduction electrode, and the outflow current of the first current control circuit is input to the first conduction electrode. And a first transistor of the second conductivity type that receives a current having a value attenuated from the other electrode of the capacitor;
A conductive state between the third conductive electrode connected to the second current control circuit, the second control electrode connected to the other electrode of the capacitor, and the potential of the second control electrode A fourth conduction electrode that is controlled, and is turned on based on a potential difference between the second control electrode and the fourth conduction electrode, and outputs a current from the third conduction electrode to the first current control circuit. And a second transistor of the first conductivity type that is complementary to the second conductivity type that flows a current having a value attenuated to the other electrode of the capacitor;
A non-inverting input terminal and an inverting input terminal, wherein the non-inverting input terminal is connected to the other electrode of the capacitor and the inverting input terminal is connected to the input terminal; the other electrode of the capacitor and the input A first operational amplifier that amplifies a potential difference with respect to the terminal to generate the control voltage;
A non-inverting input terminal; an inverting input terminal; and an output terminal, the non-inverting input terminal connected to the input terminal, the inverting input terminal connected to the other electrode of the capacitor, and the output terminal connected to the second conduction A second operational amplifier connected to the electrode and the fourth conductive electrode, and amplifying a potential difference between the other electrode of the capacitor and the input terminal and supplying the amplified potential difference to the second conductive electrode and the fourth conductive electrode. ,
The capacitor is configured to charge and discharge with an inflow current of the first control electrode and an outflow current of the second control electrode.   The first current control circuit includes:
A third control electrode connected to the input terminal, a fifth conduction electrode connected to the current outflow terminal, and a sixth conduction electrode in which the conduction state between the fifth conduction electrode is controlled by the third control electrode; A third transistor of the first conductivity type comprising:
A fourth control electrode and a seventh conduction electrode and an eighth conduction electrode, the conduction state of which is controlled by the fourth control electrode, respectively. The seventh conduction electrode is commonly connected to the input terminal and A plurality of fourth transistors of the first conductivity type, wherein a fourth control electrode is commonly connected to the sixth conduction electrode;
A plurality of first conductors connected between each of the eighth conduction electrodes and a first control terminal to which the control voltage is applied, and each of the eighth conduction electrodes is connected to the first control terminal in the on state. And the switch
Each of the ninth conduction electrode and each of the fifth control electrodes has the sixth conduction electrode, and each of the ninth conduction electrode and each of the fifth control electrodes has the sixth conduction electrode. A plurality of fifth transistors of the first conductivity type commonly connected to electrodes;
A plurality of second switches that are connected between the tenth conductive electrodes and the first control terminal and that connect the tenth conductive electrodes to the first control terminal when in the on state; ,
The variable current amplification factor is set in a state where the plurality of first switches and the plurality of second switches are turned on, and a current multiplied by the current amplification factor is flowed out from the current outflow terminal. The capacitor circuit according to claim 1, wherein: The second current control circuit includes:
A sixth control electrode connected to the input terminal, an eleventh conduction electrode connected to the current inflow terminal, and a twelfth conduction electrode in which a conduction state between the eleventh conduction electrode is controlled by the sixth control electrode; A sixth transistor of the second conductivity type having
A seventh conductive electrode and a thirteenth conductive electrode whose conductive state is controlled by the seventh control electrode, respectively, and the thirteenth conductive electrode is commonly connected to the input terminal and A plurality of seventh transistors of the second conductivity type in which a seventh control electrode is commonly connected to the twelfth conduction electrode;
A plurality of third electrodes are connected between each of the fourteenth conductive electrodes and a second control terminal to which the control voltage is applied, and each of the fourteenth conductive electrodes is connected to the second control terminal in the on state. And the switch
Each of the fifteenth conduction electrode and the sixteenth conduction electrode has an eighth control electrode and a fifteenth conduction electrode whose conduction state is controlled by the eighth control electrode, and each of the fifteenth conduction electrode and each of the eighth control electrodes is the twelfth conduction electrode. A plurality of eighth transistors of the second conductivity type commonly connected to electrodes;
A plurality of fourth switches connected between each of the sixteenth conductive electrodes and the second control terminal and respectively connecting the sixteenth conductive electrodes to the second control terminal in the on state; ,
The variable current amplification factor is set when the plurality of third switches and the plurality of fourth switches are turned on, and a current multiplied by the current amplification factor is introduced from the current inflow terminal. The capacitor circuit according to claim 1, wherein: The first current control circuit includes:
A ninth control electrode connected to the input terminal, a seventeenth conduction electrode connected to the current outflow terminal, and an eighteenth conduction electrode whose conduction state is controlled by the ninth control electrode; A ninth transistor of the first conductivity type having:
A tenth control electrode; a nineteenth conduction electrode whose conduction state is controlled by the tenth control electrode; and a plurality of twentieth conduction electrodes, the nineteenth conduction electrode being connected to the input terminal and the tenth conduction electrode A tenth transistor of the first conductivity type with a control electrode connected to the eighteenth conducting electrode;
A plurality of twentieth conductive electrodes connected to the first control terminal to which the control voltage is applied, and a plurality of twentieth conductive electrodes connected to the first control terminal in the on state, respectively. 5 switches,
An eleventh control electrode, a twenty-first conduction electrode and a plurality of twenty-second conduction electrodes whose conduction state is controlled by the eleventh control electrode, wherein the twenty-first conduction electrode and the eleventh control electrode are the eighteenth conduction electrode An eleventh transistor of the first conductivity type commonly connected to
A plurality of sixth switches which are connected between the respective twenty-second conductive electrodes and the first control terminal and which connect the respective twenty-second conductive electrodes to the first control terminal when in the on state; ,
The variable current amplification factor is set in a state in which the plurality of fifth switches and the plurality of sixth switches are turned on, and a current multiplied by the current amplification factor is flowed out from the current outflow terminal. The capacitor circuit according to claim 1, wherein: The second current control circuit includes:
A twelfth control electrode connected to the input terminal, a twenty-third conduction electrode connected to the current inflow terminal, and a twenty-fourth conduction electrode whose conduction state is controlled by the twelfth control electrode; A twelfth transistor of the second conductivity type having:
A thirteenth control electrode; a twenty-fifth conduction electrode whose conduction state is controlled by the thirteenth control electrode; and a plurality of twenty-sixth conduction electrodes. The twenty-fifth conduction electrode is connected to the input terminal and the thirteenth conduction electrode. A thirteenth transistor of the second conductivity type having a control electrode connected to the twenty-fourth conducting electrode;
A plurality of seventh conductive electrodes are connected between each of the twenty-sixth conductive electrodes and a second control terminal to which the control voltage is applied, and each of the twenty-sixth conductive electrodes is connected to the second control terminal in the on state. And the switch
  A fourteenth control electrode, a twenty-seventh conduction electrode controlled by the fourteenth control electrode and a plurality of twenty-eight conduction electrodes, wherein the twenty-seventh conduction electrode and the fourteenth control electrode are the twenty-fourth conduction electrode; A plurality of fourteenth transistors of the second conductivity type connected in common to each other;
A plurality of eighth switches connected between each of the twenty-eighth conductive electrodes and the second control terminal and connecting each of the twenty-eighth conductive electrodes to the second control terminal when in the on state; ,
The variable current amplification factor is set when the plurality of seventh switches and the plurality of eighth switches are turned on, and a current multiplied by the current amplification factor is introduced from the current inflow terminal. The capacitor circuit according to claim 1, wherein: A capacitor having two electrodes, one of which is connected to a fixed potential, and the potential of the other electrode is changed by charging and discharging;
The capacitor is connected between the input terminal and the capacitor, and current is input / output from the input terminal and a current obtained by attenuating the input / output current with a variable ratio is applied to the other electrode of the capacitor to fill the capacitor. A charge / discharge current generating circuit for discharging;
A capacitance circuit comprising:
The charge / discharge current generation circuit
It is connected to the input terminal and has a variable current amplification factor, is turned on / off based on the potential of the input terminal, outputs a current to the input terminal in the on state, and multiplies the current value by the current amplification factor. A first current control circuit for flowing in
It is connected to the input terminal and has a variable current amplification factor, and is turned on / off in a complementary manner to the first current control circuit based on the potential of the input terminal, and current is supplied from the input terminal in the on state. A second current control circuit that inputs and flows out a current obtained by multiplying the current value by the current amplification factor;
A first conduction electrode connected to the first current control circuit, a second conduction electrode connected to a first power supply potential, and a first state for controlling a conduction state between the first conduction electrode and the second conduction electrode. A control electrode, which is turned on in accordance with a potential difference between the first control electrode and the second conduction electrode, and outputs the inflow current in the first current control circuit from the first conduction electrode, and the current A first transistor of a first conductivity type that drains a current of attenuated value from the first control electrode;
The conduction state between the third conduction electrode is controlled by the third conduction electrode connected to the first control electrode, the second control electrode connected to the other electrode of the capacitor, and the second control electrode. A fourth conduction electrode, which is turned on based on a potential difference between the second control electrode and the fourth conduction electrode, and inputs an outflow current from the first control electrode to the third conduction electrode. A second transistor of a second conductivity type that is complementary to the first conductivity type and that flows a current having a value attenuated from the other electrode of the capacitor;
A fifth conduction electrode connected to the second current control circuit; a sixth conduction electrode connected to a second power supply potential; and a fifth state for controlling a conduction state between the fifth conduction electrode and the sixth conduction electrode. The third control electrode, and is turned on according to the potential difference between the third control electrode and the sixth conduction electrode, and inputs the outflow current in the second current control circuit from the fifth conduction electrode and A third transistor of the second conductivity type that flows a current attenuated from the third control electrode;
The conduction state between the seventh conduction electrode is controlled by the seventh conduction electrode connected to the third control electrode, the fourth control electrode connected to the other electrode of the capacitor, and the fourth control electrode. An eighth conduction electrode, which is turned on based on a potential difference between the fourth control electrode and the eighth conduction electrode, and outputs an inflow current in the third control electrode from the seventh conduction electrode, and the current A fourth transistor of the first conductivity type that flows a current of a value attenuated to the other electrode of the capacitor;
A non-inverting input terminal; an inverting input terminal; and an output terminal. The non-inverting input terminal is connected to the input terminal, the inverting input terminal is connected to the other electrode of the capacitor, and the output terminal is the fourth continuity. An operational amplifier connected to the electrode and the eighth conduction electrode, and amplifying a potential difference between the other electrode of the capacitor and the input terminal and applying the amplified potential difference to the fourth conduction electrode and the eighth conduction electrode;
The capacitor is configured to charge and discharge with an inflow current of the second control electrode and an outflow current of the fourth control electrode. The first current control circuit includes:
A fifth conduction electrode and a ninth conduction electrode and a tenth conduction electrode, the conduction state of which is controlled by the fifth control electrode, respectively, and each of the ninth conduction electrodes is commonly connected to the first power supply potential, and A plurality of fifth transistors of the second conductivity type, wherein each fifth control electrode is commonly connected to a current inflow terminal through which current flows from the first transistor;
A plurality of first switches connected between each of the ten conduction electrodes and the input terminal and respectively connecting the tenth conduction electrode to the input terminal when in the on state;
Each of the eleventh conductive electrode and the twelfth conductive electrode is controlled by the sixth control electrode and the sixth control electrode, and each of the eleventh conductive electrode and each of the sixth control electrodes is the current inflow terminal. A plurality of sixth transistors of the second conductivity type commonly connected to each other;
A plurality of second switches connected between each of the twelfth conductive electrodes and the input terminal and respectively connecting the twelfth conductive electrode to the input terminal when in the on state;
The variable current amplification factor is set when the plurality of first switches and the plurality of second switches are turned on, and a current multiplied by the current amplification factor is introduced from the current inflow terminal. The capacitor circuit according to claim 6, wherein: The second current control circuit includes:
A seventh control electrode and a thirteenth conduction electrode and a fourteenth conduction electrode, the conduction state of which is controlled by the seventh control electrode, respectively, and each of the thirteenth conduction electrodes is commonly connected to the second power supply potential, A plurality of seventh transistors of the first conductivity type, wherein each seventh control electrode is commonly connected to a current outflow terminal through which current flows out to the third transistor;
A plurality of third switches connected between each of the fourteenth conducting electrodes and the input terminal and respectively connecting the fourteenth conducting electrodes to the input terminal when in the on state;
Each of the fifteenth conduction electrode and the sixteenth conduction electrode is controlled by the eighth control electrode and the eighth control electrode, and each of the fifteenth conduction electrode and each of the eighth control electrodes is the current outflow terminal. A plurality of eighth transistors of the first conductivity type commonly connected to each other;
A plurality of fourth switches connected between each of the sixteenth conducting electrodes and the input terminal and respectively connecting the sixteenth conducting electrodes to the input terminal when in the on state;
The variable current amplification factor is set when the plurality of third switches and the plurality of fourth switches are turned on, and a current multiplied by the current amplification factor is flowed out from the current outflow terminal. The capacitor circuit according to claim 6, wherein: The first current control circuit includes:
A ninth control electrode; a seventeenth conductive electrode whose conduction state is controlled by the ninth control electrode; and a plurality of eighteenth conductive electrodes, wherein the seventeenth conductive electrode is connected to the first power supply potential and A ninth control electrode connected to a current inflow terminal through which current flows from the first transistor; a ninth transistor of the second conductivity type;
A plurality of fifth switches connected between each of the eighteenth conducting electrodes and the input terminal and respectively connecting each of the eighteenth conducting electrodes to the input terminal when in the on state;
A tenth control electrode and a nineteenth conduction electrode and a plurality of twentieth conduction electrodes whose conduction state is controlled by the tenth control electrode, wherein the nineteenth conduction electrode and the tenth control electrode serve as the current inflow terminal; A tenth transistor of the second conductivity type connected in common;
A plurality of sixth switches that are connected between the twentieth conduction electrodes and the input terminals and that connect the twentieth conduction electrodes to the input terminals when in the on state;
The variable current amplification factor is a value calculated by the plurality of fifth switches and the plurality of sixth switches. 7. The capacitance circuit according to claim 6, wherein the capacitance circuit is set in an on state and is configured to receive a current multiplied by the current amplification factor from the current inflow terminal. The second current control circuit includes:
An eleventh control electrode, and a twenty-first conduction electrode and a plurality of twenty-second conduction electrodes, the conduction state of which is controlled by the eleventh control electrode, and each of the twenty-first conduction electrodes is connected to the second power supply potential, An eleventh transistor of the first conductivity type having an eleventh control electrode connected to a current outflow terminal through which current flows out to the third transistor;
A plurality of seventh switches connected between each of the twenty-second conductive electrodes and the input terminal, and each of the twenty-second conductive electrodes connected to the input terminal when in the on state;
A twelfth control electrode and a twenty-fourth conductive electrode controlled by the twelfth control electrode; and the twenty-third conductive electrode and the twelfth control electrode serve as the current outflow terminal. A twelfth transistor of the first conductivity type connected in common;
A plurality of eighth switches that are connected between the 24th conductive electrodes and the input terminals and connect the 24th conductive electrodes to the input terminals when in the on state;
The variable current amplification factor is set when the plurality of seventh switches and the plurality of eighth switches are turned on, and a current multiplied by the current amplification factor is flowed out from the current outflow terminal. The capacitor circuit according to claim 6, wherein: A capacitor having two electrodes, one of which is connected to a fixed potential, and the potential of the other electrode is changed by charging and discharging;
The capacitor is connected between the input terminal and the capacitor, and current is input / output from the input terminal and a current obtained by attenuating the input / output current with a variable ratio is applied to the other electrode of the capacitor to fill the capacitor. A charge / discharge current generating circuit for discharging;
A capacitance circuit comprising:
The charge / discharge current generation circuit
It is connected to the input terminal and has a variable current amplification factor, and is turned on / off based on a given first control voltage. In the on state, a current is output to the input terminal and the current value is converted to the current A first current control circuit for discharging a current multiplied by an amplification factor;
The input terminal is connected to the input terminal and has a variable current amplification factor. The input terminal is turned on and off in a complementary manner with respect to the first current control circuit based on a given first control voltage. A second current control circuit that inputs a current from the current and flows a current obtained by multiplying the current value by the current amplification factor;
Connected to the first current control circuit, has a variable current amplification factor, and is turned on / off based on a given second control voltage, and outputs current to the first current control circuit in the on state. And a third current control circuit for flowing a current multiplied by the current amplification factor from the other electrode of the capacitor;
The second current control circuit is connected to the second current control circuit and has a variable current amplification factor. The third current control circuit is complementarily turned on / off based on a given second control voltage, and the on-state A fourth current control circuit that outputs a current to the second current control circuit and outputs a current multiplied by the current amplification factor to the other electrode of the capacitor;
A non-inverting input terminal and an inverting input terminal, wherein the non-inverting input terminal is connected to the other electrode of the capacitor and the inverting input terminal is connected to the input terminal; the other electrode of the capacitor and the input A first operational amplifier that amplifies a potential difference with the terminal to generate the first control voltage;
A non-inverting input terminal and an inverting input terminal, the non-inverting input terminal is connected to the input terminal, the inverting input terminal is connected to the other electrode of the capacitor, the other electrode of the capacitor and the input terminal; And a second operational amplifier that amplifies the potential difference between the two and generates the second control voltage. The first current control circuit according to claim 11 comprises:
The third control electrode and the seventh conduction electrode are connected to the input terminal, the current outflow terminal is connected to the third current control circuit, and the first control voltage is applied to the first control terminal. 3. The first current control circuit according to claim 2, wherein the ninth control electrode and the nineteenth conduction electrode are connected to the input terminal, and the current outflow terminal is connected to the third current control circuit. A capacitor circuit comprising the first current control circuit according to claim 4, wherein the first control terminal is connected so that the first control voltage is applied to the first control terminal. The fourth current control circuit according to claim 11 is:
12. The second control circuit according to claim 11, wherein the third control electrode and the seventh conduction electrode are connected, the current outflow terminal is connected to the other electrode of the capacitor, and the first control terminal is connected to the first current control circuit. 12. The first current control circuit according to claim 2 connected so as to be supplied with a second control voltage, or the ninth control electrode and the nineteenth conduction electrode in the second current control circuit according to claim 11. The first current control according to claim 4, wherein the current outflow terminal is connected to the other electrode of the capacitor and the second control voltage is applied to the first control terminal. A capacitor circuit characterized by comprising a circuit. The second current control circuit according to claim 11 comprises:
The sixth control electrode and the thirteenth conduction electrode are connected to the input terminal, the current inflow terminal is connected to the fourth current control circuit, and the first control voltage is applied to the second control terminal. 4. The second current control circuit according to claim 3, wherein the twelfth control electrode and the twenty-fifth conduction electrode are connected to the input terminal, and the current inflow terminal is connected to the fourth current control circuit. A capacitor circuit comprising the second current control circuit according to claim 5, wherein the second control terminal is connected so that the first control voltage is applied to the second control terminal. The third current control circuit according to claim 11 comprises:
12. The first current control circuit according to claim 11, wherein the sixth control electrode and the thirteenth conduction electrode are connected, the current inflow terminal is connected to the other electrode of the capacitor, and the second control terminal is connected to the second current control circuit. 12. The second current control circuit according to claim 3, which is connected to be supplied with a second control voltage, or the twelfth control electrode and the 25th conduction electrode in the first current control circuit according to claim 11. The second current control according to claim 5, wherein the current inflow terminal is connected to the other electrode of the capacitor, and the second control terminal is connected to the second control voltage. A capacitor circuit characterized by comprising a circuit. A capacitor having two electrodes;
The first input terminal is connected between one electrode of the capacitor and the first input terminal, and the current input / output from the first input terminal is attenuated using a variable current amplification factor and input / output to / from the capacitor. 1 charge / discharge current generation circuit;
The second input terminal is connected between the other electrode of the capacitor and the second input terminal, and the current input / output from the second input terminal is attenuated using a variable current amplification factor and input / output to / from the capacitor. Two charge / discharge current generation circuits;
A capacitance circuit comprising:
The first current according to claim 2, 3, 4, or 5, wherein the first charge / discharge current generation circuit, the second charge / discharge current generation circuit, or the first and second charge / discharge current generation circuits are the same. 11. A charge / discharge current generation circuit according to claim 1, further comprising a control circuit or a second current control circuit, and a first current control circuit or a second current control circuit according to claim 7, 8, 9 or 10. A charge / discharge current generation selected from the charge / discharge current circuit according to claim 6 and the charge / discharge generation circuit according to claim 11 having the first to fourth current control circuits according to claim 12, 13, 14 or 15. Capacitor circuit characterized by comprising each circuit. A capacitor composite circuit constructed by combining a plurality of capacitors in series or in parallel;
A plurality of charge / discharge current generation circuits connected to a plurality of input terminals for the capacitor composite circuit, and attenuating currents input / output from the input terminals using a variable current amplification factor to input / output to / from the capacitors;
A capacitance circuit comprising:
Each of the charge / discharge current generation circuits is a first current control circuit according to claim 2, 3, 4 or 5, or 11. A charge / discharge current generation circuit according to claim 1 having a second current control circuit, or a first current control circuit or a second current control circuit according to claim 7, 8, 9 or 10. The charge / discharge current generation circuit selected from the charge / discharge generation circuit according to claim 11, and the charge / discharge generation circuit according to claim 11, comprising the first to fourth current control circuits according to claim 12, 13, 14 or 15. Capacitor circuit characterized by comprising each.

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