JP3726694B2 - Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, a manufacturing method thereof, a circuit board, and an electronic device.
[0002]
[Background]
In a semiconductor chip, a semiconductor device having a structure in which a solder ball is provided at a position shifted from an Al pad has been developed. Such a semiconductor device can be applied to a CSP (Chip Scale / Size Package).
[0003]
In this structure, when the semiconductor chip is mounted on the circuit board, stress is applied due to the difference in thermal expansion coefficient between the semiconductor chip and the circuit board, and the solder ball may be cracked.
[0004]
The present invention is for solving this problem, and its purpose is to relieve the stress applied to the solder balls during mounting, and to prevent the wiring from being broken, and to provide a semiconductor device with high connection reliability, a manufacturing method thereof, and a circuit It is to provide a substrate and an electronic device.
[0005]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes a semiconductor element having an electrode,
A wiring layer provided on the surface of the semiconductor element on which the electrode is formed and electrically connected to the electrode;
Providing a first insulating layer in a region excluding an area where the electrode is formed in the wiring layer, forming a first through hole in the first insulating layer;
A second insulating layer is provided on the area where the electrode of the wiring layer is formed and the first insulating layer,
Communicating with the first through-hole of the second insulating layer, providing a second through-hole with a diameter larger than the first through-hole,
Providing a conductive layer filled inside the first through hole and the second through hole;
Solder balls formed with a diameter smaller than the diameter of the second through hole are disposed in a state of being embedded in the second through hole,
The solder balls is characterized by comprising electrically conductive and the wiring layer through the conductive layer which is filled in the through hole.
[0006]
According to the present invention, since the wiring is formed linearly in the cross section of the semiconductor device, a highly reliable semiconductor device can be obtained without disconnecting the wiring. In addition, when the semiconductor element is mounted on the circuit board, a part of the solder ball is embedded in the insulating layer, so that the stress applied to the solder ball can be relieved by the insulating layer. Further, since the solder ball is embedded in the through hole, the solder ball can be formed by self-alignment.
[0007]
In the present invention, the semiconductor element includes not only a semiconductor chip but also individual elements of a semiconductor wafer before dicing.
[0008]
In this semiconductor device, the width of the first through hole is narrower than the width of the solder ball .
[0009]
According to this, since the solder ball is supported by the resin underneath, the stress applied to the solder ball can be relieved by the insulating layer when the semiconductor element is mounted on the circuit board.
[0010]
(3) In this semiconductor device, the wiring layer may be formed so as to be disposed on a passivation film formed on a semiconductor element having an electrode.
[0011]
(4) In this semiconductor device, the second insulating layer may use a solder resist.
[0012]
In this semiconductor device, the wiring layer may be nickel, the conductive layer filling the through hole may be nickel , and either gold, copper, or tin may be formed on the outermost surface.
[0013]
In this semiconductor device, the wiring layer is two layers of nickel and gold, the conductive layer filling the inside of the through hole is nickel , and gold, copper, or tin is formed on the outermost surface. Also good.
By so doing, the wiring layer, the conductive layer filled in the through hole and the solder ball can be formed with good adhesion, leading to improved reliability.
[0014]
(7) A circuit board according to the present invention is equipped with the semiconductor device.
[0015]
(8) An electronic device according to the present invention includes the semiconductor device.
[0016]
A method for manufacturing a semiconductor device according to the present invention includes a first step of providing a wiring layer electrically connected to the electrode on the surface of the semiconductor element on which the electrode is formed;
A second step of providing a first insulating layer in a region excluding the area where the electrode is formed in the wiring layer ;
A third step of forming a first through hole in the first insulating layer;
A fourth step of providing a second insulating layer on the area of the wiring layer where the electrode is formed and on the first insulating layer;
A fifth step of communicating with the first through hole of the second insulating layer and providing a second through hole with a larger diameter than the first through hole;
A sixth step of providing a conductive layer filled in the first through hole and the second through hole;
A seventh step of disposing a solder ball formed with a diameter smaller than the diameter of the second through hole in a state of being embedded in the second through hole;
It is characterized by having .
[0017]
According to the present invention, since the wiring is formed linearly in the cross section of the semiconductor device, the wiring can be easily formed without disconnection. In addition, since the solder ball is embedded in the through hole formed in the insulating layer, the solder ball can be formed by self-alignment.
[0018]
In the present invention, the semiconductor element includes not only a semiconductor chip but also individual elements of a semiconductor wafer before dicing.
[0020]
(11) In this method of manufacturing a semiconductor device, the diameter of the first through hole may be formed to be smaller than the diameter of the solder ball.
[0021]
(12) In this method of manufacturing a semiconductor device, the wiring layer formed in the first step may be formed so as to be disposed on a passivation film formed on a semiconductor element having an electrode.
[0022]
(13) In this method of manufacturing a semiconductor device, the second insulating layer may be formed using a solder resist.
[0023]
(14) In this method of manufacturing a semiconductor device, the wiring layer is formed by electroless nickel plating, the conductive layer filling the through hole is formed by electroless nickel plating, and the outermost surface thereof is electroless gold plated or non-electrolyzed. It may be formed by either electrolytic copper plating or electroless tin plating.
[0024]
(15) In this method of manufacturing a semiconductor device, the wiring layer is formed by electroless nickel plating, the outermost surface thereof is formed by electroless gold plating, and the conductive layer filling the inside of the through hole is formed by electroless nickel plating. In addition, the outermost surface may be formed by any one of electroless gold plating, electroless copper plating, and electroless tin plating.
[0025]
According to this, the conductive layer filled in the wiring layer, the through hole, and the solder ball can be formed with good adhesion, leading to improved reliability.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiments. The present invention can be applied to a CSP (Chip Size / Scale Package) which is an embodiment of a semiconductor device.
[0027]
(First embodiment)
FIG. 1A to FIG. 5 are diagrams showing an embodiment of a method of manufacturing a semiconductor device according to the present invention along the process. In the present embodiment, the first step (FIGS. 1A to 2B) for forming the wiring layer 14 above the semiconductor chip 1, the first insulating layer 15 is formed, and the first insulating layer 15 has the first step. The second step of forming the through hole 20 (FIGS. 2C to 3A), the second insulating layer 16 is formed in the region excluding the first through hole 20, and the conductive layer 17 and the surface conductive layer 18 are formed in the first step. A third step (FIGS. 3B to 4B) for embedding in the through hole 20 and a fourth step (FIG. 3) for forming the external electrode terminal 19 on the surface conductive layer 18 and in the second through hole 21 of the second insulating layer. 5).
[0028]
As shown in FIG. 1A, the semiconductor chip 1 has a plurality of electrodes (or pads) 10 on its main surface. The electrode 10 may be arranged at the end of the main surface of the semiconductor chip 1 or may be arranged at the center of the main surface of the semiconductor chip 1. Further, the electrodes 10 may be arranged along two parallel end portions of the main surface of the semiconductor chip 1 when the semiconductor chip 1 is rectangular, or may be arranged in four side end portions. Each electrode 10 is often formed thin and flat on the main surface of the semiconductor chip 1, but the shape of the side surface or the longitudinal section is not limited, and may be flush with the surface of the semiconductor chip 1. . The electrode 10 is made of, for example, aluminum. Further, the planar shape of the electrode 10 is not particularly limited, and may be circular or rectangular. A passivation film 11 having an opening on the electrode 10 is often formed on the main surface of the semiconductor chip 1. The passivation film 11 is an insulating layer. The passivation film 11 can be formed of, for example, SiO ₂ , SiN, polyimide resin, or the like.
[0029]
Next, a conductive layer 12 is formed on the electrode 10 as shown in FIG. The conductive layer 12 may be a single layer or a plurality of layers. In the example shown in the figure, the conductive layer 12 formed on the electrode 10 is made of only nickel, but the conductive layer 12 is a first layer (lower layer) and a second layer (upper layer or surface layer) laminated thereon. ) And may be formed. In this case, the first layer is made of nickel, for example, and the second layer is made of gold, for example.
[0030]
As a method for forming the nickel layer constituting at least a part of the conductive layer 12, the electrode 10 is subjected to a zincate treatment to replace the surface on the aluminum with zinc, and then immersed in an electroless nickel plating solution. Nickel may be deposited through the above substitution reaction. Alternatively, aluminum may be immersed in a palladium solution that selectively adsorbs only on aluminum, and then immersed in an electroless nickel plating solution to deposit nickel using palladium as a nucleus.
[0031]
In order to form a gold layer on the nickel layer, it is further immersed in an electroless gold plating solution to further form gold on the nickel surface. By forming gold, the electrical connection with the wiring layer 14 can be further ensured. In general, since nickel can be deposited in a shorter time than gold, the first layer (lower layer) is formed of nickel and the second layer (upper layer or The surface layer is preferably formed of gold. It is preferable to block light while the semiconductor chip 10 is immersed in the solution. This is a matter common to all the embodiments. By these, the potential change between the electrodes in the solution caused by immersing the semiconductor chip 10 in the solution can be prevented.
[0032]
Next, as shown in FIG. 1C, a resist 13 for forming a wiring from the conductive layer 12 is formed. This uses a general photolithography method. In this example, a general positive resist (OFPR800 manufactured by Tokyo Ohka) was used. However, although not shown in the figure, between FIG. 1 (B) and FIG. 1 (C), for surface roughening, a step of immersing in alkali (5% KOH), and immersing in a palladium solution for passivation. Forming a nucleus for plating on the film 11;
[0033]
By immersing in an electroless nickel plating solution with the resist 13 formed, a nickel wiring layer 14 is formed in a region other than the region covered with the resist, as shown in FIG. In this embodiment, the nickel-phosphorus type is used, but the nickel-boron type has a lower specific resistance, and a film more suitable as a wiring can be obtained. In this embodiment, the wiring layer 14 is a film having a thickness of about 2 μm.
[0034]
Next, by removing the resist, the nickel wiring layer 14 can be formed. A state in which the nickel wiring layer 14 is formed is shown in FIG.
[0035]
Next, the first insulating layer 15 is formed. The first insulating layer 15 is insulative with respect to the wiring layer 14. The first insulating layer 15 preferably protects the semiconductor chip 1 and also has heat resistance when melting solder at the time of mounting. The first insulating layer 15 has a Young's modulus that is low enough to relieve stress caused by a difference in thermal expansion coefficient between the semiconductor chip and the mounted circuit board when the semiconductor device is mounted on the circuit board. preferable. For this purpose, the insulating layer 15 may be formed of, for example, a polyimide resin. Further, the thickness of the first insulating layer 15 can be freely determined as necessary. FIG. 2C shows a state where the first insulating layer is formed. In this embodiment, photosensitive polyimide is used and formed using photolithography, but in order to form at a lower cost, a method using a non-photosensitive polyimide resin and printing using a printing method is desirable.
[0036]
As shown in FIG. 3A, the first insulating layer 15 is provided with a first through hole 20 that exposes at least a part of the wiring layer 14 that becomes each electrode of the semiconductor chip 1. Therefore, the first through hole 20 may be formed on the wiring layer 14 and formed according to the total number of the electrodes 10. The first through hole 20 may be formed with an inner wall surface perpendicular to the main surface of the semiconductor element, and the first through hole 20 may be tapered.
[0037]
In the present embodiment, the first through hole 20 covers the wiring 14 and forms the first insulating layer 15 and is formed by applying a photolithography technique, and avoids the peripheral region where the electrode 10 is located by a printing method. A method of forming the first through hole 20 by irradiating a laser after forming the first insulating layer 15 can be formed more simply and at low cost, and is optimal for mass production. Although the diameter of the first through hole 20 is made with a diameter of 100 μm, it may be smaller or larger and can be arbitrarily selected, but it is formed as an external electrode terminal in the final process. It is desirable that the diameter is smaller than the diameter of the solder ball. This is because, when a semiconductor device is mounted on a circuit board, the Young's modulus is low under the solder balls in order to relieve stress caused by the difference in thermal expansion coefficient between the semiconductor chip and the circuit board to be mounted. This is because it is desirable to support the material. More preferably, the diameter of the first through hole 20 is smaller than 2/3 of the diameter of the solder ball.
[0038]
Next, the second insulating layer 16 is formed in a region excluding the first through hole 20. In the present embodiment, a solder paste is applied to the entire surface as the second insulating layer 16, and the second through hole having a diameter larger than that of the first through hole 20 is formed on the upper portion of the first through hole 20 using a photolithography method. Hole 21 was provided. Here, it was 350 μm.
[0039]
As the second insulating layer 16, any material having insulating properties with respect to the wiring layer 14 may be used. The first insulating layer 15 may be made of the same material or different material, and the second insulating layer 16 may protect the semiconductor chip 1 and have heat resistance when melting solder at the time of mounting. It ’s fine.
[0040]
Furthermore, the second insulating layer may be photosensitive or non-photosensitive. In the case of non-photosensitive, the laser is irradiated to form an opening as in the case of the first insulating layer. It is also possible to do. In this case, it is also possible to open the first insulating layer and the second insulating layer all together. However, considering the formation of solder balls, it is desirable to use a solder resist for the second insulating layer 16.
[0041]
FIG. 3B shows a state where the second through hole 21 is formed in the second insulating layer 16. Here, the size of the second through hole has a larger area than the first through hole 20 in a plan view, that is, the diameter of the solder ball formed in a later process overlapping therewith. Larger is desirable.
[0042]
FIG. 4A shows the conductive layer 17 filled partway through the first through hole 20 and the second through hole 21. As a result, the wiring layer 14 and the conductive layer 17 are electrically connected. Therefore, the electrode 10 to the conductive layer 17 are electrically connected. The conductive layer 17 does not necessarily need to completely fill the first through hole 20 with the conductive layer 17, and is formed along the inner wall of the first through hole 20, as long as it is electrically conductive. .
[0043]
In this embodiment, the conductive layer 17 is formed by first forming the first through hole 20 in the first insulating layer 15 and immersing it in the palladium solution in the state shown in FIG. The insulating layer 16 is formed. When immersed in an electroless nickel plating solution in the state of FIG. 3B, a nickel film can be uniformly formed on the inner surface of the first through hole 20. By adjusting the plating time, the conductive layer 17 can be filled in the first through hole 20 or can be formed only on the inner wall of the first through hole 20. In this embodiment, nickel is used. However, any material that can conduct electroless plating can be used. For example, copper, gold, tin, or the like can be used.
[0044]
Next, as shown in FIG. 4B, a surface conductive layer 18 is formed on the surface of the conductive layer 17 exposed at the upper part of the first through hole 20. This is for the purpose of preventing the oxidation of nickel in the conductive layer 17 and improving the bondability between the solder and the conductive layer formed in the subsequent process. Further, as the material of the surface conductive layer 18, electroless substitution gold plating is used in this embodiment, but other than that, copper or tin, or a laminate of copper and tin, a laminate of gold and copper, gold, copper and tin are used. Various combinations such as lamination are conceivable, but any combination is possible as long as it satisfies the above purpose. The film thickness is sufficient if it covers the surface, and may be a thin film such as displacement plating of gold or tin.
[0045]
Finally, as shown in FIG. 5, external electrode terminals 19 are formed on the surface conductive layer 18. As the external electrode terminals, solder balls are usually used, but the solder balls are formed by a method such as printing. Also in this example, solder balls were formed as the external electrode terminals 19 by printing. Further, the position of the external electrode terminal may be formed in accordance with the position of the opening of the solder resist formed previously.
[0046]
In this example, after the solder balls were printed, the external electrode terminals 19 could be formed by passing through a reflow furnace, and the semiconductor device 100 was obtained. The semiconductor device 100 includes a semiconductor chip 1 having a plurality of electrodes 10, a first insulating layer 15 in which a first through hole 20 is formed, a conductive layer 12 and a wiring layer 14 provided on the electrode 10, A second insulating layer 16 formed on the first insulating layer 15; a conductive layer 17 and a surface conductive layer 18 filled in the first through holes 20 formed in the first insulating layer 15; And the external electrode terminal 19 formed in the second through hole 21 of the second insulating layer 16.
[0047]
In the present embodiment, each process is performed on the semiconductor chip 1. However, this process may be performed on each semiconductor element of the semiconductor wafer (an element that becomes a semiconductor chip when diced). In that case, the semiconductor chip may be replaced with the semiconductor element of the semiconductor wafer in the above description. Further, the step of providing the external terminal may be performed on the semiconductor wafer. Thereafter, the semiconductor wafer can be diced to obtain individual semiconductor devices. This can also be applied to the following embodiments.
[0048]
In this embodiment mode, the first insulating layer is not formed over the electrode, but may be formed over the entire surface of the semiconductor element. Furthermore, in this embodiment, the stepped insulating layer is formed through the two-step process as formed by the first and second insulating layers, but may be formed in a single-step process. That is, after forming an insulating film having a necessary thickness in advance, a through hole may be formed so as to form a stepped portion.
[0049]
FIG. 6 shows a circuit board 100 on which the semiconductor device 2 according to the present embodiment is mounted. The circuit board 100 is generally an organic substrate such as a glass epoxy substrate. The circuit board 100 is formed with a wiring pattern made of, for example, copper or the like so as to form a desired circuit. The wiring pattern and the external terminal of the semiconductor device 2 are mechanically connected to electrically connect them. Plan.
[0050]
As an electronic apparatus having the semiconductor device 1 to which the present invention is applied, a notebook personal computer 200 is shown in FIG. 7, and a mobile phone 300 is shown in FIG.
[Brief description of the drawings]
FIG. 1A to FIG. 1C are diagrams showing a method for manufacturing a semiconductor device according to a first embodiment to which the present invention is applied.
FIGS. 2A to 2C are views showing a method for manufacturing a semiconductor device according to a first embodiment to which the present invention is applied.
FIGS. 3A and 3B are views showing a method of manufacturing a semiconductor device according to the first embodiment to which the present invention is applied.
FIGS. 4A and 4B are views showing a method of manufacturing a semiconductor device according to the first embodiment to which the present invention is applied.
FIG. 5 is a diagram showing a method for manufacturing the semiconductor device according to the first embodiment to which the present invention is applied;
FIG. 6 is a diagram showing a circuit board on which the semiconductor device according to the present embodiment is mounted.
FIG. 7 is a diagram illustrating an electronic apparatus including the semiconductor device according to the present embodiment.
FIG. 8 is a diagram illustrating an electronic apparatus including the semiconductor device according to the present embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Semiconductor device 10 Electrode 11 Passivation film 12 Conductive layer 13 Resist 14 Wiring layer 15 1st insulating layer 16 2nd insulating layer 17 Conductive layer 18 Surface conductive layer 19 External electrode terminal 20 1st through-hole 21 1st Two through holes 100 Circuit board 200 Notebook personal computer 300 Mobile phone

Claims (14)

A semiconductor element having an electrode;
A wiring layer provided on the surface of the semiconductor element on which the electrode is formed and electrically connected to the electrode;
Providing a first insulating layer in a region excluding an area where the electrode is formed in the wiring layer, forming a first through hole in the first insulating layer;
A second insulating layer is provided on the area where the electrode of the wiring layer is formed and the first insulating layer,
Communicating with the first through hole of the second insulating layer, providing a second through hole with a diameter larger than the first through hole;
Providing a conductive layer filled inside the first through hole and the second through hole;
Solder balls formed with a diameter smaller than the diameter of the second through hole are disposed in a state of being embedded in the second through hole,
The solder balls semiconductor device characterized by comprising been said wiring layer and electrically connected via the conductive layer which is filled in the through hole. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein a width of the first through hole is narrower than a width of the solder ball. The semiconductor device according to claim 1 or 2,
A semiconductor device, wherein the wiring layer is formed on a passivation film formed on a semiconductor element having an electrode. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device, wherein the second insulating layer is made of a solder resist. The semiconductor device according to any one of claims 1 to 4,
The wiring layer is nickel, and the conductive layer filling the through hole is nickel ,
One of gold, copper, and tin is formed on the outermost surface, and the semiconductor device is characterized. The semiconductor device according to any one of claims 1 to 4,
The wiring layer is composed of two layers of nickel and gold, the conductive layer filling the inside of the through hole is nickel , and the semiconductor is characterized in that either gold, copper or tin is formed on the outermost surface. apparatus.   A circuit board on which the semiconductor device according to claim 1 is mounted.   An electronic apparatus comprising the semiconductor device according to claim 1. A first step of providing a wiring layer electrically connected to the electrode on the surface of the semiconductor element on which the electrode is formed;
A second step of providing a first insulating layer in a region excluding the area where the electrode is formed in the wiring layer ;
A third step of forming a first through hole in the first insulating layer;
A fourth step of providing a second insulating layer on the area of the wiring layer where the electrode is formed and on the first insulating layer;
A fifth step of communicating with the first through hole of the second insulating layer and providing a second through hole with a larger diameter than the first through hole;
A sixth step of providing a conductive layer filled in the first through hole and the second through hole;
A seventh step of disposing a solder ball formed with a diameter smaller than the diameter of the second through hole in a state of being embedded in the second through hole;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 9,
A method of manufacturing a semiconductor device, wherein the diameter of the first through hole is formed to be smaller than the diameter of a solder ball. In the manufacturing method of the semiconductor device according to claim 9 or 10 ,
A method of manufacturing a semiconductor device, wherein the wiring layer formed in the first step is formed so as to be disposed on a passivation film formed on a semiconductor element having an electrode. The method of manufacturing a semiconductor device according to any one of claims 9 to 11,
The method for manufacturing a semiconductor device, wherein the second insulating layer is formed using a solder resist. The method of manufacturing a semiconductor device according to any one of claims 9 to 12,
The wiring layer is formed by electroless nickel plating, the conductive layer filling the first and second through holes is formed by electroless nickel plating, and the outermost surface thereof is electroless gold plated or electroless copper plated or A method of manufacturing a semiconductor device, wherein the semiconductor device is formed by any one of electroless tin plating. The method of manufacturing a semiconductor device according to any one of claims 9 to 13,
The wiring layer is formed by electroless nickel plating, and the outermost surface thereof is formed by electroless gold plating, the conductive layer filling the through hole is formed by electroless nickel plating, and the outermost surface is electroless gold plated or A method of manufacturing a semiconductor device, wherein the semiconductor device is formed by either electroless copper plating or electroless tin plating.

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