JP3722692B2 - Layout design change device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a layout design change technology for a semiconductor device, and more particularly to a layout design change device that can reduce the number of relocation wirings as much as possible and can perform timing adjustment with a short TAT.
[0002]
[Prior art]
A conventional rearrangement wiring flow for timing adjustment will be described with reference to FIG. Referring to FIG. 10, in the prior art, first, placement and routing are performed (step S101). As a result, if there is a timing error (Y in step S102), or if circuit correction has not been completed (in step S108). N) The block replacement determination is executed (step S103), and if it is determined that the block replacement is necessary (Y in step S103), circuit correction is performed on the block on the passing path causing the timing error. Therefore, a process of replacing with a block having a different operation speed or driving capability (step S104) and a process of deleting a block on a passing path causing a timing error (for example, deleting a useless buffer) (step S107) are performed. Execute and return to the determination in step S108 to correct the circuit and adjust the timing. Cormorant.
[0003]
When it is determined that the block replacement is not necessary (N in step S103), the block addition determination is executed (step S105). When it is determined that the block needs to be added (Y in step S105), the block is added (for example, , High drive buffer insertion, delay block insertion, etc.) processing (step S106) and block deletion on the passing path causing the timing error (for example, useless buffer deletion) processing (step S107). ) And return to the determination in step S108 to correct the circuit and perform timing adjustment.
[0004]
Further, when it is determined that the addition of the block is unnecessary (N in Step S105), a process (Step S107) of deleting a block on the passing path causing the timing error (for example, deleting a useless buffer) is executed. By returning to the determination in step S108, the circuit is corrected and the timing is adjusted.
[0005]
When the circuit correction is completed (Y in step S108), the process from step S101 to step S102 is performed. If there is no timing error (N in step S102), the process ends.
[0006]
For example, first, when it is determined that there is a timing error in step S102 as a result of the placement and routing (step S101), in step S103 and step S104, the block is replaced with a block having a different operation speed or driving capability, or step S105. In step S106, the high drive buffer is inserted, and the process (step S107) for deleting the block on the passing path causing the timing error (for example, deleting the useless buffer) is executed, and the process returns to step S101 and changed. Perform relocation wiring for only the location. If the timing error still remains, the high drive buffer is further inserted in step S105 and step S106, and the process of deleting the block on the passing path causing the timing error (for example, deleting the useless buffer) (step S107) is executed, and the process returns to step S101 again to perform rearrangement wiring. As a result, even if a buffer is inserted, a good effect in terms of timing cannot be obtained, and if the adverse effect is adversely affected, a useless buffer is deleted in step S107, and rearrangement is performed again in step S101. Perform wiring. Thereafter, the circuit correction in step S103 to step S107 and the placement and routing in step S101 are repeated until there is no timing error.
[0007]
[Problems to be solved by the invention]
However, in the conventional relocation wiring process for timing adjustment, the appropriateness of timing adjustment cannot be determined without performing layout wiring. Therefore, if the circuit correction accuracy is poor, the layout wiring is repeated many times. Therefore, there is a problem that it takes a lot of TAT (Turn Around Time: time required from LSI specification determination to commercialization).
[0008]
The present invention has been made in view of such a problem, and an object of the present invention is to provide a layout design change device capable of reducing the number of relocation wirings as much as possible and performing timing adjustment with a short TAT. There is in point to do.
[0009]
[Means for Solving the Problems]
The layout design change device of the present invention inputs a placement and routing means, a path delay constraint value, calculates a path delay value of the circuit of the semiconductor device after placement and routing, and verifies whether the path delay constraint value is satisfied Timing verification means for performing a verification and outputting a timing verification result including a path delay, and when there is a path having a timing error in the timing verification result, an input capacity of each block constituting a circuit of the semiconductor device, The path before the circuit correction obtained from the timing verification result based on the library including at least information on the gate delay value and the delay coefficient, the timing verification result, and the circuit correction information for the path having the timing error. delay and, before and after circuit modification included in the circuit correction information for the path which becomes the timing error block , Re-gate delay time of the blocks obtained from the library, the information of the delay factor, and the input capacitance, estimate the load capacity of the block after circuit modification, the path delay value of the path becomes and the timing error A recalculating means for performing calculation, and a circuit for correcting an actual circuit according to the circuit correction information when the circuit correction information for timing adjustment is valid as a result of recalculation by the recalculating means Correction means, and the placement and routing is performed by the placement and routing means only on the corrected portion corrected by the circuit correction means.
If the recalculation result of the recalculation means does not satisfy the path delay constraint value, new circuit correction information is input to the recalculation means, and the path delay value is recalculated for the timing verification result. And repeating means until the path delay constraint value is satisfied.
The recalculation means may output the recalculation result in accordance with the output format of the timing verification result.
In addition, when the designer corrects the actual circuit before creating the circuit correction proposal, the designer includes an extraction unit that extracts a difference between the circuit information before the correction and the circuit information after the correction. The circuit correction information can be created by means.
The circuit correction information may include data for replacement with a block having a different operation speed and driving capability, and data for addition and deletion of a buffer.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
The present invention provides means for directly reflecting the contents of circuit correction for timing adjustment in the original timing verification result in the relocation wiring processing flow particularly when a timing error occurs in an ASIC (dedicated LSI for a specific customer). It has the characteristics.
[0011]
As a result, the path delay can be recalculated from the circuit correction information for timing adjustment and the original timing verification result, and the validity of the circuit correction plan for timing adjustment can be confirmed before relocation wiring. As a result, the number of relocation wirings can be reduced as much as possible, and TAT (Turn Around Time: time required from LSI specification determination to commercialization) can be shortened. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0012]
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is an explanatory diagram of a rearrangement wiring flow for timing adjustment in the layout design changing method according to the first embodiment of the present invention.
[0013]
Referring to FIG. 1, in the present embodiment, placement and routing are first performed in step S11. Step S12 is executed, and timing verification is performed based on the input path delay constraint value. Thereafter, it is determined whether or not a timing error has occurred (step S13).
[0014]
If it is determined in step S13 that a timing error has occurred (Y in step S13), step S14 (circuit correction plan input processing) is executed, and the timing verification result obtained in step S12 and the circuit for timing adjustment are executed. The correction plan is input, and the path delay constraint value input from step S12 is stored. If it is determined in step S13 that a timing error has not occurred (N in step S13), the process ends.
[0015]
Here, the circuit modification proposal includes data for replacement with blocks having different operation speeds and driving capabilities, and addition and deletion of buffers, and is created on the designer side.
[0016]
Subsequently, step S15 (processing for recalculating the path delay value with reference to the library based on the circuit correction plan) is executed, and the path verification is performed on the timing verification result obtained from step S12 based on the circuit correction plan. Recalculate the delay value. At this time, in step S15, a library related to each block is referred to. This library describes the input capacity, gate delay value, and delay coefficient of each block. Details regarding step S15 will be described later with reference to FIG.
[0017]
If the result of the recalculation in step S15 does not satisfy the path delay constraint value, that is, if the circuit correction proposal for timing adjustment is not valid (N in step S16), the process returns to step S14 again, and the path delay constraint value is set. A series of loop processing from step S14 to step S16 is repeated until satisfied.
[0018]
When the path delay constraint value is satisfied, it is determined that the circuit correction proposal for timing adjustment is appropriate (Y in step S16), and the actual circuit is corrected according to the circuit correction proposal (step S17: Thereafter, the placement and routing of only the corrected portion (step S11) is performed again, and this operation is completed through the processing of step S12 and step S13 (step S11 → step S12 → step). N → End of S13).
[0019]
FIG. 2 is an explanatory diagram of a detailed flow of step S15 shown in FIG. 3 to 6 are specific examples of the inter-gate delay. Referring to FIG. 2, in step S15 (processing for recalculating the path delay value by referring to the library based on the circuit modification proposal) in this embodiment, the delay value is recalculated in blocks having different operation speeds and driving capabilities. Basically, it is assumed that the original wiring path (wiring capacity) does not change, although it differs somewhat depending on each process such as replacement with, addition and deletion of blocks. The calculations performed in step S15 all use the following general simple delay calculation formula.
[0020]
For example, the delay value t _AB between the gate A and the gate B in FIG. 3 is as follows.
[0021]
Delay value t _AB = gate delay value of gate A + load capacity of gate A × additional capacity of delay coefficient gate A of gate A = wiring capacity + input capacity of all blocks driven by gate A (= input capacity of gate B) )
[0022]
Step S22 (replacement delay value recalculation process) executed when it is determined in step S21 that the block is replaced (Y in step S21) is a recalculation process at the time of block replacement. For example, when the gate B shown in FIG. 4A is replaced with the gate B ′ shown in FIG. 4B, the input capacitance of the gate B is replaced with the input capacitance of the gate B ′ according to the above simple calculation formula, and the delay of the gate B The value t _AB , the delay value t _BC , the wiring length L _AB , the wiring length L _BC , the delay coefficient, the delay value t _{AB ′} of the gate B _′ , the delay value t _B′C , the wiring length L _{AB ′} , and the wiring length L _{B 'C} , replace with delay factor and recalculate.
[0023]
Step S24 (deletion delay value recalculation process) executed when it is determined in step S21 that the block is not replaced (N in step S21) and it is determined in step S23 that the block is deleted (Y in step S23). Is a recalculation process when a block is deleted. For example, when the gate B shown in FIG. 5 is deleted, as shown in FIG. 5A, the value of the wiring capacitance + the input capacitance of the gate B is extracted based on the delay value t _AB , and the delay value t _BC is _calculated . Based on this, the value of the input capacitance of the wiring capacitance + C is extracted, and the delay value t _AC shown in FIG. 5B is recalculated using the value obtained by subtracting the input capacitance of the gate B from the sum of the two.
[0024]
If it is determined in step S23 that the block is not deleted (N in step S23), and it is determined that a gate has been added immediately after the previous stage (Y in step S25), step S26 (first additional delay value re-estimation) is executed. Step S28 (second time calculation) is executed when it is determined that the block is not deleted in Step S23 (N in Step S23) and it is determined that a gate is added immediately before the subsequent stage (Y in Step S27). In step S23, it is determined that the block is not deleted (N in step S23), it is determined that no gate is added immediately after the previous stage (N in step S25), and immediately before the subsequent stage. If it is determined that no gate has been added (N in Step S27), Step S29 is executed (the third additional delay value is reset). Processing of calculation), respectively, a re-calculation process when additional blocks. For example, when adding the gate X shown in FIG. 6B between the gate A and the gate B shown in FIG. 6A, the delay value differs depending on the position where the gate X is added.
[0025]
Specifically, when the gate X is added immediately after the gate A, recalculation is performed assuming that the wiring length L _AX = 0 and the wiring length L _XB = the wiring length L _AB . If it is added immediately before the gate B, recalculation is performed assuming that the wiring length L _AX = wiring length L _AB and the wiring length L _XB = 0. Further, as shown in FIG. 6B, if added between the gate A and the gate B, recalculation is performed assuming that the wiring length L _AX = wiring length L _XB = wiring length L _AB / 2.
[0026]
In step S31 (path delay recalculation process) executed when it is determined in step S30 that all circuit correction proposals have been recalculated (Y in step S30), all blocks included in the circuit correction proposal are processed. When the delay value recalculation is completed, the path is recalculated. If it is determined that all circuit correction proposals have not been recalculated (N in step S30), the process returns to step S21.
[0027]
Next, the path delay recalculation operation of FIG. 2 will be described using the timing verification result shown in FIG. 7 and the circuit correction proposal shown in FIG. The parameters of the timing verification result shown in FIG. 7 will be described. STEP is the number of blocks existing in the path between FFs (flip-flops), TOTAL is a delay value from the start point to each block, and IPIN (for example, H03F) is a block. Input pin, OPIN (eg, N01F) is an output pin of the block, INTRCON, IOPATH are inter-block delay components, BLK (eg, SEL611NW or F434NC) is a block name, and INSTANCE (eg, A) is an instance name of the block. .
[0028]
In this embodiment, the inter-block delay is described separately as components such as an inter-block delay component INTRCON and an inter-block delay component IOPATH, and recalculation is performed using the sum of the two as the inter-block delay. The timing verification result shown here is merely an example, and the present invention is not limited to this format.
[0029]
Now, in step S14 shown in FIG. 1, it is assumed that the timing verification result shown in FIG. 7 is input and the path delay constraint value is 12 ns. Further, in order to satisfy the above-described path delay constraint value, a circuit correction plan (FIG. 8) for replacing the inverter F101 shown in FIG. 8 with the high drive inverter F145 is created by the designer and is similarly input to step S14 shown in FIG. Assuming that The above circuit correction proposal is for knowing which block is to be changed and how to change it, and is not limited to the format shown here.
[0030]
Next, step S15 shown in FIG. 1 is executed, and inter-block and path delay values are recalculated for the timing verification result in accordance with the input circuit correction plan. In step S15, since the circuit correction plan is block replacement, block delay is recalculated in step S22.
[0031]
By replacing the block type of instance name E (INSTANCE E) shown in the above circuit modification proposal, the delay value of instance name D (INSTANCE D) to instance name E (INSTANCE E) and the instance name E (INSTANCE E) to instance name Since the delay value of F (INSTANCE F) is affected, it is necessary to recalculate the delay value between each block.
[0032]
When recalculating the delay value of the instance name E (INSTANCE D) from the instance name D (INSTANCE D), first, the gate delay value (= 0.2 ns) of the instance name D (INSTANCE D) and the delay coefficient (= 0.6) and the delay value of E (= 0.22 ns) is extracted from the instance name D (INSTANCE D) from the timing verification result, and the instance name D (INSTANCE C) is calculated from the above general simple delay calculation formula. D) The load capacitance (= 0.03 pF) is extracted.
[0033]
When the instance name E (INSTANCE E) is replaced, only the input capacity of the instance name E (INSTANCE E) affects the delay value from the instance name D (INSTANCE D) to the instance name E (INSTANCE E). Therefore, the input capacity (= inverter F101: 0.02 pF, high drive inverter F145: 0.10 pF) before and after replacement of the instance name E (INSTANCE E) is extracted from the library, and the instance name D (INSTANCE E) is extracted. Replacement is performed for the load capacity (= 0.11 pF) of D). When the recalculation is performed using the simple delay calculation formula using the load capacity obtained here, a delay value of 0.27 ns is obtained.
[0034]
When the delay value of the instance name F (INSTANCE F) is recalculated from the instance name E (INSTANCE E), first, the gate delay value (= 0.04 ns) of the instance name E (INSTANCE E) before the change from the library. The delay coefficient (= 1.5) is extracted, and the delay value (= 3.29 ns) of the instance name F (INSTANCE F) is extracted from the instance name E (INSTANCE E) from the timing verification result, and the simple delay is extracted. The load capacity (= 2.17 pF) of the instance name E (INSTANCE E) is extracted using the calculation formula.
[0035]
When the instance name E (INSTANCE E) is replaced, the gate delay value of the instance name E (INSTANCE E) affects the delay value of the instance name F (INSTANCE E) to the instance name F (INSTANCE F). Therefore, the gate delay value (= 0.05 ns) and the delay coefficient (= 0.10) of the block high drive inverter F145 that replaces the instance name E (INSTANCE E) are extracted from the library, and these are extracted. When recalculation is performed using the above simple delay calculation formula, a delay value of 0.27 ns is obtained.
[0036]
As a matter of course, a slight error occurs between the delay value obtained by recalculation and the delay value obtained by actually performing the relocation wiring. However, it is possible to obtain a calculation result with relatively high accuracy by performing recalculation using the wiring capacity of the actual wiring result on the premise that the original wiring route does not change.
[0037]
FIG. 9 is a chart showing the result of recalculating the path delay in step S31 of FIG. When the delay value recalculation of all the blocks described in the circuit correction proposal is completed, the path delay is recalculated in step S11. The result is shown in FIG. In FIG. 9, since the total delay value (= TOTAL delay) is 11.53 ns, which satisfies the path delay constraint value (= 12 ns), it is determined that the circuit correction plan is appropriate.
[0038]
As described above, the present embodiment relates to the relocation and wiring process for timing adjustment, based on the timing verification result in which the timing error has occurred and the actual wiring capacity before the relocation and wiring are executed. By recalculating the delay value according to the circuit correction proposal to be created with relatively high accuracy and confirming the validity of the circuit correction proposal in advance, the number of relocation wirings can be reduced as much as possible, and a large TAT There is an effect that shortening is possible.
[0039]
(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described in detail with reference to the drawings. Note that the same parts as those already described in the above embodiment are denoted by the same reference numerals, and redundant description is omitted. FIG. 11 is an explanatory diagram of a rearrangement wiring flow for timing adjustment in the layout design changing method according to the second embodiment of the present invention.
[0040]
The basic configuration of the second embodiment of the present invention is the same as that of the first embodiment, but step S14 (circuit correction plan input processing) shown in FIG. 1 is further devised.
[0041]
That is, in the present embodiment, the circuit correction plan created on the designer side is input as in step S14 shown in FIG. 1. However, if the designer creates an actual circuit before creating the circuit correction plan, If it has been corrected (step S114: circuit correction processing), the difference between the circuit information before correction (net list) and the circuit information after correction (net list) is extracted (step S115), and based on this, the above-described difference is extracted. Steps S14 to S17 are executed, and the circuit correction plan can be automatically created.
[0042]
(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described in detail with reference to the drawings. Note that the same parts as those already described in the above embodiment are denoted by the same reference numerals, and redundant description is omitted. 12 to 14 are specific examples of the inter-gate delay.
[0043]
As shown in FIG. 12, there are cases where there are a plurality of pin pairs of the gate A, and the arrangement positions of the subsequent blocks driven by the gate A are separated from each other. In such a case, generally, as shown in FIG. 13, in order to reduce the load on the gate A, a delay is improved by adding a buffer for each path of a plurality of pin pairs and performing isolation. However, as shown in FIG. 14, when the gate A and the gate C are arranged very close to each other, even if a buffer is added between the two (gate A and gate C) by the isolation method, the gate A to the gate The path delay value of C is not always improved, and a useless buffer may be inserted.
[0044]
In this embodiment, it is possible to cope with such an isolation method, and as shown in FIG. 14, it is impossible to determine the arrangement position of the subsequent block group driven by the gate A, and the gate A and the gate C shown in FIG. When a large error occurs in the result of delay value recalculation when a useless buffer is inserted between the gate A and the gate A, the delay between the gate A and the gate B and the delay between the gate A and the gate C are branched as shown in FIG. It is characterized in that a means for dividing the point P is provided.
[0045]
As a result, it is possible to estimate the delay with high accuracy, and as a result, it is possible to improve the accuracy of the circuit correction validity determination.
[0046]
Note that the present invention is not limited to the above-described embodiments, and it is obvious that the above-described embodiments can be appropriately changed within the scope of the technical idea of the present invention. In addition, the number, position, shape, and the like of the constituent members are not limited to the above embodiments, and can be set to a number, position, shape, and the like that are suitable for carrying out the present invention. Moreover, in each figure, the same code | symbol is attached | subjected to the same component.
[0047]
【The invention's effect】
As described above, according to the present invention, a designer creates a rearrangement wiring process for timing adjustment based on a timing verification result in which a timing error has occurred and an actual wiring capacity before executing the rearrangement wiring. By recalculating the delay value according to the circuit correction proposal with relatively high accuracy and confirming the validity of the circuit correction proposal in advance, the number of relocation wiring can be reduced as much as possible, and TAT can be greatly shortened. The effect that becomes.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a rearrangement wiring flow for timing adjustment in a layout design changing method according to a first embodiment of the present invention;
FIG. 2 is an explanatory diagram of a detailed flow of step S15 shown in FIG.
FIG. 3 is a specific example of an inter-gate delay.
FIG. 4 is a specific example of an inter-gate delay.
FIG. 5 is a specific example of an inter-gate delay.
FIG. 6 is a specific example of an inter-gate delay.
FIG. 7 is a chart showing an example of a timing verification result.
FIG. 8 is a chart showing a circuit correction proposal.
FIG. 9 is a chart showing a result of recalculation of path delay in step S31 of FIG.
FIG. 10 is a rearrangement wiring flowchart for conventional timing adjustment.
FIG. 11 is an explanatory diagram of a rearrangement wiring flow for timing adjustment in the layout design changing method according to the second embodiment of the present invention;
FIG. 12 is a specific example of an inter-gate delay.
FIG. 13 is a specific example of an inter-gate delay.
FIG. 14 is a specific example of an inter-gate delay.
[Explanation of symbols]
A, B, B ', C, X ... Gate BLK ... Block name E ... Instance name F101 ... Inverter F145 ... High drive inverter INSTANCE ... Block instance name INTRCON ... Interblock delay component IOPATH ... Interblock delay component IPIN ... Block input pins _{L AB, L AB ', L} AX, L BC, L B'C, L XB ... number _{t AB} output pins P ... block in the path between the branch point STEP ... FF wiring lengths OPIN ... block, t _{AB '} , t _AC , t _BC , t _B'C ... Delay value TOTAL ... Delay value from the start point to each block

Claims (5)

Placement and routing means;
The path delay constraint value is input, the path delay value of the circuit of the semiconductor device after placement and routing is calculated, the timing verification is performed to verify whether the path delay constraint value is satisfied, and the timing verification result including the path delay is output. Timing verification means;
If there is a path that has a timing error in the timing verification result, a library including at least information on input capacitance, gate delay value, and delay coefficient of each block constituting a circuit of the semiconductor device, and the timing verification result And the circuit correction information for the path having the timing error,
A path delay before circuit correction obtained from the timing verification result;
Blocks before and after circuit correction included in the circuit correction information for the path having the timing error ,
Recalculate the path delay value of the path that caused the timing error by estimating the load capacity of the block after circuit correction from the gate delay time, delay coefficient, and input capacity information of the block obtained from the library Recalculation means for performing
As a result of recalculation by the recalculation means, when the circuit correction information for timing adjustment is appropriate, circuit correction means for correcting an actual circuit according to the circuit correction information, and
The layout design changing device, wherein the placement and routing unit performs placement and routing only on the corrected portion corrected by the circuit modification unit. If the recalculation result of the recalculation means does not satisfy the path delay constraint value, new circuit correction information is input to the recalculation means, and the path delay value is recalculated for the timing verification result. The layout design changing apparatus according to claim 1, further comprising a repeating unit that repeats until the path delay constraint value is satisfied. The layout design changing device according to claim 1, wherein the recalculation unit outputs a recalculation result in accordance with an output format of the timing verification result. An extraction means for extracting a difference between the circuit information before correction and the circuit information after correction when the designer has corrected the actual circuit before creating the circuit correction proposal ;
4. The layout design change device according to claim 1, wherein the circuit correction information is created by the extraction unit. 5. The layout design change device according to claim 1 , wherein the circuit correction information includes data for replacement with a block having a different operation speed and driving capability, and data for addition and deletion of a buffer. 6.

Images