JP3368859B2 - Scan path connection device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan path connecting device as an LSI test technique.

[0002]

2. Description of the Related Art Conventionally, a scan path connecting device is an LSI
The method of using a scan path is generally well known as a test technique of.

However, in the prior art of an LSI having a scan path structure, the wiring of the scan path path is the LSI.
However, there is a problem that the wiring accommodating ability of the above is impaired. In order to solve this, restrictions are placed on the arrangement positions of blocks connected to the scan path so that the wiring of the scan path does not become too long. For example, Japanese Patent Laid-Open No. 1-
As disclosed in Japanese Patent Laid-Open No. 302850, a method is adopted in which the scan path connection order is changed so that the scan path path becomes short after all blocks are arranged.

If all the blocks are arranged and then the replacement is performed so that the scan path path is shortened, it is not necessary to give a restriction to the arrangement position of the blocks.
In addition, it is possible to minimize the influence of the scan path on the wiring accommodability. However, the problem of hold time error in the scan path does not disappear.
The problem of hold time error is as follows.

In a normal LSI, in order to distribute a clock signal to each clock input element such as F / F, a clock tree structure or a clock mesh main line structure is used so that the clock signal arrives at each clock input element as much as possible. It has been devised so that there is no time difference (clock skew). However, with respect to the wirings and transistors that form the clock tree structure and the clock mesh main line structure, there are various factors such as the problem of complexity of delay calculation, the transistor film thickness, the wiring width, and the wiring height during the LSI manufacturing. The clock skew always occurs due to the problem that an error occurs in etc.

If the clock skew is large, the data input signal of the clock input element may change at an excessively fast timing before the clock input element operates by receiving the clock signal, and the clock input element may malfunction. Hold time error) will occur.

In order to avoid this, in the prior art, a delay buffer is inserted in the scan path manually or by a program so that this hold time error does not occur.

[0008]

However, in the above-mentioned conventional technique, by inserting the delay buffer, the wiring of the scan path route presses the wiring accommodating ability of the LSI, and the problem is caused in the scan path route. There is a problem that a hold time error occurs.

It is an object of the present invention to provide a scan path connecting device which reduces the occurrence of hold time error and minimizes the influence of scan path wiring on the wiring accommodability of an LSI.

[0010]

In order to achieve the above object, the scan path connecting device of the present invention constitutes a circuit.
And logical connection information / library information input means for inputting the physical library information necessary to perform the logical connection information and the LSI layout between blocks on the scan path connection, arrangement information input for inputting the information relating to the location of the said block Means and a block connected to the same clock net.
Grouping means for grouping the group
For the blocks grouped by
A group that optimizes the connection of scan paths within a group.
An intra-group scan path connection optimizing means and an inter-group scan path connection optimizing means for optimizing inter-group scan path connection . later, it is characterized by performing the optimization scan path connections between the groups by the group between the scan path connection optimization means.

Further, logical connection information between the blocks to be input by the above logical connection information / library information input means, in the layout design of the LSI, the scan for obtaining a wire results in less scan path generation of the hold time error Campus Of the logical connection relationship between blocks on the connection
As the information, the physical library information may be circuit configuration information necessary for laying out the LSI, such as the size of the LSI, the size of each type of logic element, the position of terminals, and the width of wiring.

Further, the above scan path connecting device is
A scan path connection result output means for outputting the connection result of the scan path constituted by the scan path connection device is provided, and further, the grouping means performs the grouping operation performed by the grouping means.
In the ping process, the target of the clock net connection is
The clock input element in the block is preferable.

Further, a clock buffer and a plurality of clock input elements are connected via a clock net, and a plurality of clock input elements connected to other clock buffers other than the clock buffer via a clock net. the state in which the bets are freely scan path connections, a plurality of clock input elements to each other which are connected each to each clock buffer as scan path length is the shortest path connected directly to the group in the scan path a connection optimization means, grouped between the groups scan path length between groups together each are then reconnect the scan path network as the shortest scan path connections optimized by the group within the scan path connected optimizing means Means, and the scan path connection optimization means in the group When, the group and other grayed
The scan path nets that are connected to the loop are
Form an output path and add the group to all the groups.
Performs processing by the scan path connection optimization means in the loop
If the clock input elements belonging to other groups are once freely connected, the inter-group scan path connection optimizing means is executed.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of a scan path connecting apparatus according to the present invention will be described in detail with reference to the accompanying drawings. 1 to 7, there is shown one embodiment of the scan path connecting device of the present invention.

FIG. 1 is a block diagram showing a configuration example of a scan path connection method of the present invention. In FIG. 1, the scan path connection device according to the present embodiment includes a control unit 1, a logical connection information / library information input unit 2, an arrangement information input unit 3, a grouping unit 4, an intra-group scan path connection optimization unit 5, and an inter-group. It comprises scan path connection optimization means 6 and scan path connection result output means 7. In addition, the scan path connection device of the present embodiment,
Logical connection information 8, physical library information 9, and block arrangement information 10 are input.

The control means 1 is a control unit for controlling the operation of the entire scan path connection apparatus of this embodiment.

Logical connection information / library information input means 2
Inputs the logical connection information 8 and the physical library information 9. That is, in the layout design of the LSI, the logical connection information 8 between the blocks forming the circuit, the size of the LSI, the size of each type of each logic element in order to obtain the wiring result of the scan path with less hold time error. It is an information input unit for inputting physical library information 9 necessary for laying out an LSI such as positions of terminals, widths of wirings, and the like.

The layout information input means 3 is a layout information input section for inputting the block layout position information 10.

The grouping means 4 is a processing unit for grouping blocks connected to the same clock net.

In-group scan path connection optimizing means 5
Is a processing unit that performs connection optimization of scan paths within a group for scan path connections within a group.

Inter-group scan path connection optimization means 6
Is a processing unit for optimizing scan path connections between groups.

The scan path connection result output means 7 is an output section for outputting the connection result of the scan path constituted by the present scan path connecting device.

(Explanation of Operation of Embodiment) FIG. 2 is a flowchart of a processing procedure showing an example of a processing procedure of an LSI layout design processing when the method of the present invention is applied.

First, step S1 is an information input step. In this step, logical connection information 8 and physical library information 9 which are information necessary for layout design are input. The logical connection information 8 is information on the logical connection relationship between the logic elements forming the circuit. The physical library information 9 refers to library information necessary for laying out the LSI, such as the size of the LSI to be designed, the size of each logic element, the terminal position, and the width of the wiring.

Since the hold time error is highly likely to occur when the difference in the arrival time of the clock signal to the clock input element (clock skew) is large, in the present embodiment, the logical connection information 8 of the clock signal is first set. Focus on it. FIG. 3 is an example showing only the connection relationship of the clock signals of the logical connection information 8. In an ordinary LSI, a clock trunk line or the like may be used on the way, but as a logical connection structure, the F / F of the F / F is finally passed through such a multi-stage clock signal relay buffer inserted in a tree shape. The clock signal reaches the clock input element.

Next, as shown in step S2, block layout position information is input. The layout position information input in step S2 is information 10 of layout position coordinates of each block obtained by using a conventional automatic layout method or manually designating the layout position of each block. Is. FIG. 4 shows a configuration example of the F / F clock input device and the clock buffer after the arrangement information of each block described in the clock logical connection information 8 shown in FIG. 3 is input. In FIG.
A clock signal is transmitted from the clock buffer 14 to the clock input elements 21, 22, 23 and 24 via the clock net 41.

Although the method and procedure for deciding the layout position of the blocks are affected to some extent, if the wiring length from the clock buffer to the clock input element is long, the delay value of the signal varies and the clock skew may increase. There is. Therefore, normally, in order to reduce the clock skew, as shown in FIG. 4, the clock buffer and the clock input element are arranged as close to each other as possible.

On the other hand, the connection relationship of the scan path signal is irrelevant to the connection relationship of the clock signal, and the scan path is used only during the operation test of the LSI. Therefore, the scan path signal net has no risk of causing a MAX timing error, and the scan path connection is not taken into consideration at the time of arrangement. Therefore, as a result of arranging the blocks, the scan path signal net is freely connected to another F / F like the scan path net (thick line arrow) in FIG.

After that, as shown in step S3, clock input elements connected to the same clock net are grouped. Specifically, the clock input elements 21 to 24, which are the final stage in the tree-shaped clock signal logical connection structure shown in FIG. 3, are grouped to form a group 31. For other elements (for example, the clock signal relay buffer 15), all clock input elements connected to the same clock buffer are grouped (for example, group 32). Further, blocks such as the hard macro block 35 in FIG. 3 to which the clock is supplied without passing through the clock buffer at the final stage are left as they are.

Next, as shown in step S4, the intra-group scan path nets are rearranged so that the scan path length becomes the shortest. An example of the result of replacement is shown in FIG. The shortest scanning method is to first find the placement position of each block from the placement information, use it to estimate the scan path wiring length, and replace the scan path logic so that the length is the shortest. Is possible.

Although there are various methods for estimating the scan path length, a method of using a half circumference of a rectangle surrounding the output terminal and the input terminal of the scan path can be considered. Regarding scan path nets connected to other groups, F / F410 to F / F411 and F / F412 in FIG.
Clock input elements belonging to another group, such as ~ F / F413, are connected to each other. Therefore, the input / output terminals of the scan path net are neither excessive nor insufficient. In addition, by performing this replacement for all the scan paths in the group, the scan path connection information is changed so that only one scan path input terminal and one output terminal in the group are connected to another group. be able to.

In the replacement of the scan paths, the buffers supplied with the clock signal from the same clock buffer are combined into one group to replace the scan paths, so that the clock input elements connected to the scan paths are the same. The clock signal will be supplied from the buffer. Therefore, clock skew is reduced. Further, since the clock input element is arranged near the clock buffer, the scan path length can be reduced.

After that, as shown in step S5, the scan path nets are replaced so that the scan path length between the groups becomes the shortest. Step S5 is different from step S4 only in that groups are replaced instead of blocks, and the optimum scan path replacement method is similar to step S4. FIG. 6 shows an example in which the scan path connection within the group is optimized but the connection between the groups is not optimized in step S4.

FIG. 7 shows a configuration example in which the inter-group connection is optimized in step S5. A clock that does not pass through the clock buffer at the final stage, such as the hard macro block 35, is also supplied. Therefore, even if there is a block that has not been grouped in step S4, the route is optimized including this block in step S5. Then, in step S6, the scan path connection result is output.

As described above, according to this hierarchical scan path replacement method according to the flow of a series of processing, the scan path length is sufficiently short, and the layout result of the scan paths in which the hold time error is hard to occur can be automatically realized. it can. The reason why the scan path length can be shortened is that the F / Fs connected to the same clock net / same clock buffer are arranged in the vicinity of the normal buffer as described above. Also, since the blocks connected to the same clock net are connected at the final stage of the clock tree hierarchy, the clock skew between the clock input elements connected to the scan path can be reduced, and the probability of a hold time error occurring can be reduced. It can be reduced. Also, one L
Even if there are multiple scan path routes in SI,
By repeating the procedure from step S1 to step S6 for each path, an optimum scan path layout result can be realized.

According to the above embodiment, the scan paths are hierarchically connected to reduce the occurrence of a hold time error and minimize the influence of the scan path wiring on the wiring accommodability of the LSI. Is possible.

The above-mentioned embodiment is an example of a preferred embodiment of the present invention. However, it is not limited to this,
Various modifications can be made without departing from the scope of the present invention.

[0038]

As is clear from the above description, the scan path connection device of the present invention inputs the logical connection information between the blocks constituting the circuit and the physical library information necessary for the layout of the LSI, By inputting the information of the block layout position, the blocks connected to the same clock net are grouped by optimizing the connection of the scan paths within the group, and the scan path connection between the groups is optimized. With this configuration, it is possible to obtain the scan path connecting device with less hold time error. This is because when the scan paths are replaced, the scan paths are replaced in consideration of clock connection so that clock skew is less likely to occur.

It is possible to obtain the scan path connection in which the influence of the scan path wiring on the wiring accommodation of the LSI is minimized. This is because the scan path wiring can be replaced so as to be the shortest. In the present invention, since the replacement is performed in consideration of the clock connection as compared with the conventional method of performing the replacement without considering the clock connection, it is considered that the degree of freedom at the time of replacement is reduced.
Clock input devices connected to the same clock net / same clock buffer are arranged close to each other. Therefore, an optimized replacement result can be obtained in comparison with the conventional replacement result that does not consider the clock connection.

Further, in order to prevent a hold time error from occurring, it is conventionally necessary to insert a buffer (delay buffer) that causes a delay time in a signal. However, in the present invention, the occurrence of hold time error is small. Therefore, the number of delay buffers to be inserted can be reduced, and the influence of the delay buffer on the wiring accommodability of the LSI can be minimized .
Lock input elements can be connected freely and then grouped
Since inter-scan path connection optimization is performed,
Scan path net while optimizing and optimizing between groups
There will be no excess or shortage of input / output terminals of.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a scan path connection device of the present invention.

FIG. 2 is a flowchart showing an example of a processing procedure.

FIG. 3 is a diagram showing a connection relationship of clock signals of logical connection information.

FIG. 4 shows a configuration example of a clock input element such as an F / F and a clock buffer after the arrangement information of each block described in the logical connection information of the clock shown in FIG. 3 is input.

FIG. 5 shows an example of a result of changing the intra-group scan path nets so that the scan path length becomes the shortest.

FIG. 6 shows an example in which scan path connections within a group have been optimized, but connections between groups have not been optimized.

FIG. 7 shows a configuration example in which connection between groups is optimized.

[Explanation of symbols]

1 control means 2 Logical connection information / library information input means 3 Placement information input means 4 Grouping means 5 Scan path connection optimization means within a group 6 Inter-group scan path connection optimization means 7 Scan campus connection result output means 8 logical connection information 9 Physical library information 10 block placement information 11-14 Clock buffer 15 Clock signal relay buffer 41 clock net 21, 22, 23, 24 Clock input element 31, 32 groups 35 hard macro blocks 401 Clock output terminal 410-413 F / F

Continuation of the front page (56) References JP 2000-137741 (JP, A) JP 2000-55986 (JP, A) Actual Kaihei 10-207921 (JP, U) Susumu Kobayashi, 1 person, multi-scan check In-optimization method, IPSJ research report, IPSJ, May 24, 1996, Vol. 96, No. 51 (96-DA-80), p. 37-44 Konno, Y. et al. , Scan Design Methodology for Large-Scale ASICs, NEC Research and Development, Vol. 38, No. 2, p. 181-188 (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 17/50 654 G01R 31/28

Claims (6)

(57) [Claims] 1. A logical connection information / library information input means for inputting logical connection information between blocks on a scan path connection forming a circuit and physical library information necessary for laying out an LSI. an arrangement information inputting means for inputting the information relating to the location of the said block, the block being connected to the same clock net group
Grouping means for grouping, and the blocks grouped by the grouping means.
Connection of scan paths within a group for
The intra-group scan path connection optimizing means, and the inter-group scan path connection optimizing means for optimizing the scan path connection between the groups. After the optimization , the scan path connection device between groups is optimized by the scan path connection optimization means between groups. 2. The logical connection information between blocks input by the logical connection information / library information input means is LS.
In the layout design of I, a scan path for obtaining scan path wiring results with less hold time error
2. The scan path connection device according to claim 1, wherein the information is information on a logical connection relationship between blocks on a scan path connection . 3. The physical library information input by the logical connection information / library information input means is an LSI layout such as the size of the LSI, the size of each logic element, the position of terminals, and the width of wiring. The scan path connection device according to claim 1 or 2, wherein the circuit configuration information is required above. 4. The scan path connection device further comprises scan path connection result output means for outputting a connection result of a scan path constituted by the scan path connection device. The scan path connecting device according to any one of claims. 5. A glue pin performed by the grouping means.
The target of connection of the clock net is
Characterized by a clock input element in the block
The scan path connection device according to claim 1.
Place 6. A plurality of clock input elements in which a clock buffer and a plurality of clock input elements are connected via a clock net and are connected to other clock buffers other than the clock buffer via a clock net. the state in which the bets are freely scan path connections, a plurality of clock input elements to each other which are connected each to each clock buffer as scan path length is the shortest path connected directly to the group in the scan path a connection optimization means, the group <br/>-loop scan path length to each other between the grouped respective groups in the group within the scan path connection optimization means reconnect the scan path network as the shortest Inter-scan path connection optimizing means, wherein the intra-group scan path connection optimizing means When, in the corresponding group and the other group is connected
Scan path nets form a set of input / output paths,
For all the groups,
Claim performs processing by connecting optimization means, after connecting the clock input elements to each other belonging to the other groups once freely, and executes a scan path connection optimizing means between said group 1 6. The scan path connecting device according to any one of 1 to 5 .