JP3715461B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a wet etching process.
[0002]
[Prior art]
Compound semiconductors typified by GaAs are light transition elements such as LEDs (Light Emission Diode), MESFETs (Metal-Semiconductor Field Effect Transistors), HEMTs (High Electron Mobility) due to their direct transition band structure and high electron mobility. Transistors) and HBTs (Hetero-junction Bipolar Transistors) are widely used today as high-speed operating elements. The processing techniques required to create these elements include lithography techniques and film deposition techniques such as CVD (Chemical Vapor Deposition). Among them, the etching technique is an important position in the formation of compound semiconductor elements. is occupying. This is because, unlike silicon-based semiconductors, the main method of forming compound semiconductor elements is to form elements by pre-stacking necessary layers on a substrate and then scraping off unnecessary portions. It comes from that. In other words, in forming a compound semiconductor device, it is important to accurately leave a necessary part and remove an unnecessary part.
[0003]
Conventional compound semiconductor etching techniques are roughly classified into a dry etching technique using plasma for etching and a wet etching technique mainly using an oxidation reaction by a solution.
[0004]
The dry etching technique has high processing accuracy such as high verticality, can be given selectivity by devising the type of gas used, and is widely used as an effective means. However, since plasma having high energy is used, the etched surface has a drawback that damage caused by plasma ions and contamination by gas species cannot be avoided. For this reason, there is a problem that post-processing such as a heat treatment for recovering the damage and a step for removing the damaged layer is necessary.
[0005]
On the other hand, wet etching technology is mainly scraped from the surface of the semiconductor layer using an oxidation reaction, so that a damage layer as seen in dry etching is not formed, a clean surface appears on the etched surface, etc. It can be said that this is an etching method suitable for the subsequent electrode forming step. However, although the etching form has anisotropy depending on the plane orientation, it is basically isotropic etching, and side etching in which the lower part of the mask material is scraped off is unavoidable. Therefore, it is necessary to anticipate a conversion difference between the mask pattern and the pattern actually formed by etching, and process management for controlling the side etching amount is required.
[0006]
Furthermore, as a mask material for etching, resists conventionally used for patterning and patterned SiO 2 ₂ Although a film is used, an adhesion failure is likely to occur due to a slight difference in conditions of pretreatment for mask material formation, and an unexpected result such as an etchant permeating the lower part of the mask may be caused. In that sense, it is necessary to ensure sufficient adhesion between the mask material and the semiconductor layer, but the mask material that has the conflicting properties of being easily removable and securely adhered after processing. Finding it is extremely difficult. In that sense, it is no exaggeration to say that the discovery of an ideal mask material is an eternal problem in wet etching technology.
[0007]
[Problems to be solved by the invention]
As described above, it is a wet etching technique that has the advantage that it can be processed without forming a damage layer on the semiconductor layer, but the pattern conversion difference due to the isotropic etching and the mask There was a problem such as the occurrence of defects due to poor adhesion with the material.
[0008]
An object of the present invention is to provide a mask material that suppresses side etching, which is a cause of a pattern conversion difference, and has excellent adhesion, and provides a highly controllable etching method that eliminates the drawbacks of conventional wet etching. It is to provide.
[0009]
[Means for Solving the Problems]
A first invention of the present application includes a mask forming step of forming a mask having a desired shape on a semiconductor layer, and a wet etching step of performing wet etching using the mask, and the mask is formed in the semiconductor layer. A process for producing a semiconductor device comprising an element having a standard electrode potential lower than a standard electrode potential of an element to be a cation atom.
[0010]
A second invention of the present application is the method for manufacturing a semiconductor element according to the first invention of the present application, wherein the semiconductor layer and the mask are in ohmic contact.
In a third invention of the present application, the semiconductor layer is an n-type In _x Ga _1-x The method for manufacturing a semiconductor device according to the first aspect of the present invention, wherein the method is an As layer, and the mask contains Ti.
[0011]
That is, the present invention relates to a material containing an element having a standard electrode potential lower than the standard electrode potential of an element corresponding to a cation (cation) atom constituting a semiconductor in a wet etching process of a semiconductor, particularly a compound semiconductor. The mask material is used to perform wet etching by a reaction involving an oxidation reaction.
[0012]
The standard electrode potential corresponds to the electrode potential when a metal or a compound thereof is immersed in a solution containing the ions, and the value of the standard hydrogen electrode is 0 V as the origin. Qualitatively, the more the metal tends to emit electrons and become ions, that is, the easier it is oxidized, the smaller the value of the standard electrode potential. According to this, the present invention is characterized in that a material containing an element that is more easily oxidized than an element corresponding to a cation atom constituting a compound semiconductor is used as a mask material.
[0013]
On the other hand, in etching using an oxidation reaction widely used in conventional wet etching processes of compound semiconductors, the {111} A plane, which is a plane composed only of cation atoms, usually has the slowest etching rate. It has been known. As a result, as shown in FIG. 8, when a concave groove is formed by etching, a {111} A surface 3 appears on the side surface of the groove, and a shape called a forward mesa or reverse mesa is formed. become. However, even in such a {111} A plane, the etching rate is only small, and there is no change in the situation where a pattern conversion difference occurs. On the other hand, by devising the mixing ratio of the oxidizer or by using a weak acid such as an organic acid as the acid that functions to remove the oxide of the compound semiconductor, it is different on the {111} A plane that is most difficult to oxidize. It has been reported that it has a direction. However, in such a conventional example, since the ability to remove oxides is basically reduced, there are other problems such as a low etching rate, a reaction sensitive to the mixing ratio of chemicals and poor reproducibility. there were.
[0014]
Considering why the etching rate of the {111} A plane is smaller than that of other crystal planes, assuming that the etching is performed using an oxidation reaction, {111} A composed only of cation atoms It can be considered that the surface is a crystal surface that is most hardly oxidized. However, it is still etched at a certain rate by an oxidizing agent such as H2O2 contained in the etching solution.
Ga → Ga ³⁺ + 3e ^- (Oxidation reaction) (1)
In → In ³⁺ + 3e ^- (1) '
H ₂ O ₂ + 2H ⁺ + 2e ^- → 2H ² O (Reduction reaction of oxidizing agent) (2)
This is because the cation atoms (Ga atoms and In atoms in this example) constituting the {111} A plane are oxidized and dissolved (here, the case of InGaAs etching is assumed). ). In other words, if this reaction can be inhibited, the {111} A plane remains without being etched. That is, since etching stops on the {111} A plane with respect to the mask, side etching does not occur, and the pattern conversion difference can be eliminated.
[0015]
A material containing an element having a standard electrode potential lower than the standard electrode potential of the element corresponding to the cation atom constituting the compound semiconductor that is a feature of the present invention is used as a mask material, that is, a {111} A plane is formed. In the case where a material containing an element that is more easily oxidized than the material being used is used as the mask material, the mask material is preferentially oxidized over the compound semiconductor as shown in FIG. As a result, an oxidation reaction is suppressed among chemical reactions occurring in etching on the semiconductor side. At this time, since the mask material acts as an electron supply source in the chemical reaction formula (2) mentioned above, the reaction of (1) and (1) ′, which is the original cation atom electron supply reaction, can be suppressed. is there. At this time, it is desirable that the mask material and the compound semiconductor are in ohmic connection so that electrons are smoothly supplied from the mask material to the compound semiconductor. However, a complete ohmic connection is not necessary as long as a local battery formed by the mask material and the {111} A surface allows sufficient electron movement. In this case, since the electromotive force of the formed battery roughly corresponds to the difference between the standard electrode potential of the material constituting the {111} A plane and the mask material, the connection allows sufficient current to flow at the corresponding potential difference. If it is in a state, it will be good.
[0016]
In addition, by using a material that is more easily oxidized as a mask material, in other words, a material rich in reactivity, the mask material and the natural oxide film formed on the surface of the compound semiconductor at the interface with the underlying compound semiconductor are used. A redox reaction occurs between them, and a chemical bond is generated. This is because, in the formation of the integrated circuit, in the wiring formation process, the adhesion is improved by inserting a highly reducing (easily oxidized) substance such as Ti between the gold wiring and the substrate. Is a well-known phenomenon. Since such a chemical bond also occurs between the compound semiconductor and the mask material, the adhesion between the compound semiconductor and the mask material is improved, and defects due to poor adhesion such as etchant permeation during wet etching are prevented. be able to.
[0017]
As described above, by performing wet etching using a material containing an element having a standard electrode potential lower than the standard electrode potential of the element corresponding to the cation atom constituting the compound semiconductor as a mask material, dimensions that do not cause side etching Not only etching with high accuracy is possible, but also wet etching with high reproducibility can be performed without causing the problem of poor adhesion.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 2 is a schematic view of wet etching according to the first embodiment.
The laminated structure of the compound semiconductor used here is obtained by laminating a desired device structure on a semi-insulating GaAs substrate, and then n ⁺ Type In _x Ga _1-x The As emitter contact layer 10 is laminated to 100 nm. In this case, x is gradually changed from 0 to 0.5, so that a large amount of transition can be prevented from occurring with the underlying GaAs layer, and ohmic electrode characteristics can be obtained directly with the metal. Yes. A Ti mask 9 is used as a mask material, and a pattern having a thickness of 150 nm is formed using a lift-off technique. The standard electrode potential of Ti is
Ti ²⁺ + 2e ^- → Ti
−1.63V, while In _x Ga _1-x The standard electrode potentials of In and Ga, which are As cation atoms, are
In ³⁺ + 3e ^- → In
Ga ³⁺ + 3e ^- → Ga
In this reaction, they are −0.3382 V and −0.53 V, respectively, and it can be seen that the standard electrode potential of Ti is significantly lower. When such a combination of materials is etched using a solution in which phosphoric acid, hydrogen peroxide solution, and pure water, which are widely used as GaAs etching solutions, are mixed at a ratio of 3: 1: 50, respectively. It can be seen that the end surface of the etched portion is composed of a {111} A surface starting from the end portion of the mask material, and no side etching occurs. Furthermore, by inserting a layer that cannot be etched with a mixed solution of phosphoric acid, hydrogen peroxide water, and pure water, such as an InGaP layer, as an etching stopper layer, a thickness direction can be easily controlled. In this case, since side etching does not occur, even if a sufficiently long etching is performed for a predetermined thickness (for example, about twice), there is no difference in pattern conversion, and it is absolutely necessary within the wafer surface. It is possible to perform a large amount of etching, which is effective for improving mass productivity.
[0019]
FIG. 3 is a schematic view of wet etching according to the second embodiment.
In this embodiment, the TiW mask 13 is used as a mask material for the compound semiconductor layer having the same stacked structure as that of the first embodiment. TiW is formed by a sputtering method, and patterning is performed by transferring a resist pattern formed by an optical exposure method to a TiW film by a RIE (Reactive Ion Etching) method. In this case, compared with the case where Ti alone is used as a mask material, there is a surface that is somewhat inferior in reactivity due to the presence of W. However, due to the presence of Ti, the oxidation reaction occurs preferentially in the mask material, and The effect of being suppressed is exhibited. As a result, the semiconductor layer can be patterned with little side etching.
[0020]
FIG. 4 is a schematic view of wet etching according to the third embodiment.
In this embodiment, unlike the above-described embodiment, the semiconductor layer is n-type GaAs. In this case, even if Ti is directly connected, ohmic connection is not obtained, and the impurity concentration of GaAs is 5 × 10 5. ¹⁸ cm ^-3 In such a case, since the Schottky connection formed does not result in a current flowing at an electromotive force between the semiconductor layer and the mask material, the effect of suppressing the oxidation reaction in the semiconductor layer does not appear. Become. Therefore, in this embodiment, an AuGe (5%) layer of 100 nm and a Ni layer of 1 nm are laminated on a base of Ti which is a mask material in order to make ohmic connection between the mask material and the semiconductor layer. Specifically, it can be realized by sequentially depositing AuGe, Ni, and Ti, performing patterning using a lift-off method, and annealing in nitrogen at 370 ° C. for 1 minute. With such a structure, the mask material and the semiconductor layer are ohmic-connected, and at the same time, an effect of suppressing the oxidation reaction due to Ti appears and etching with good controllability without side etching can be realized. As is clear from this example, it is not necessary to use an easily oxidizable substance such as Ti for all the materials constituting the mask, and it is important that there is an easily oxidized substance on the outermost surface. is there. In that sense 4 × 10 ¹⁹ cm ^-3 A similar effect can be obtained by sequentially stacking a Pt layer and Ti that can realize a good ohmic connection to p-type GaAs doped with impurities at a high concentration to the extent. In this case, by annealing at about 350 ° C., Pt and GaAs react to form a more stable interface, so that the problem of adhesion can be avoided.
[0021]
FIG. 5 is a schematic view of wet etching according to the fourth embodiment.
In this embodiment, the etching technique according to the present invention is applied to formation of a gate electrode of MESFET. The figure shows a cross-sectional view of the gate electrode portion of the element after the gate electrode 18 in which Mo (50 nm) and Au (500 nm) are sequentially stacked is formed by the lift-off method. The portion used in the present invention is a recess groove portion of the gate electrode forming portion, and is used when forming the V groove 21 having a side surface portion constituted by a {111} A plane.
[0022]
Specifically, first, Si is ion-implanted into a GaAs substrate, and then a channel portion and a source / drain region are formed by activation annealing, and AuGe (5%) (100 nm), Ni (1 nm) is formed in the source / drain region. ), And source / drain electrodes 19 and 20 in which Au (10 nm) is sequentially stacked. Next, the Ti mask 9 is formed so as to have an opening in the part where the recess groove of the gate electrode is formed. At that time, Ti is formed first because it is necessary to make ohmic contact with the conductive layer. It is formed so as to be electrically connected to the source / drain electrodes. Next, a lift-off pattern of the gate electrode is formed with a resist capable of forming a reverse tapered cross-sectional shape, and the recess groove is etched with an etching solution in which phosphoric acid, hydrogen peroxide solution, and pure water are mixed. At this time, since the etching stops at the {111} A surface of the end face of the Ti mask, the V groove 21 can be formed with in-plane uniformity and reproducibility. Thereafter, the gate electrode material is deposited and lifted off, and the Ti electrode is etched away with diluted hydrofluoric acid to complete the gate electrode. Thereafter, ion implantation is performed using the gate electrode as a mask for the purpose of reducing parasitic resistance, and a process of forming a passivation film (not shown) on the surface is continued, thereby completing the transistor.
[0023]
By making the gate electrode embedded in such a V-shaped recess groove, the effective gate length appears to be shorter than the actual gate length. As a result, high frequency characteristics such as an increase in cutoff frequency and an improvement in noise figure are improved.
[0024]
Next, a fifth embodiment of the present invention will be described.
In this embodiment, the case where the wet etching of the present invention is applied to a method for manufacturing a heterojunction bipolar transistor (HBT) will be described.
[0025]
The HBT tends to have a smaller element size recently in order to bring out its high-speed performance. Among them, the control of the emitter size has the greatest influence on the performance. Therefore, it is essential to form a small-sized emitter mesa with good controllability.
[0026]
However, the conventional emitter forming methods are mainly 1) a method in which an emitter mesa and an emitter electrode are formed in a non-self-aligned manner, and 2) a method in which an emitter mesa is formed by etching a W-based emitter electrode as a mask. In the method 1), the contact area of the emitter electrode is inevitably smaller than the area of the emitter mesa, and when the emitter size is reduced, an increase in the contact resistance of the emitter electrode becomes a problem (FIG. 9). In the method 2), since the emitter electrode is formed on the entire surface of the emitter mesa, the problem 1) does not occur, but the amount of side etching when the electrode is etched using the mask is not controlled. Another problem arises that control is not possible (FIG. 10).
[0027]
Thus, an emitter electrode material that has been formed on the entire surface of the emitter mesa and that does not undergo side etching during mesa etching has not been obtained yet.
The present embodiment has been made in view of the above points, and provides an HBT capable of forming an emitter mesa with good controllability without sacrificing the emitter electrode contact resistance as much as possible when the emitter size is reduced. The purpose is to do. In order to solve the above problems, the present embodiment uses an alloy of Ti and Pt as the emitter electrode material. The ionization tendency is in the order of Ti>Ga>In> Pt. When the ionization energy is based on the ionization energy of H, Ti → Ti ³⁺ Is -1.63 eV, Ga → Ga ³⁺ -0.56eV, In → In ³⁺ Is -0.34eV, Pt → Pt ²⁺ Is 1.12 eV. First, only Ti serves as an emitter electrode, and an emitter contact layer n ⁺ It is assumed that it is formed on the type InGaAs layer. Here, consider a case where etching is performed using a phosphoric acid / hydrogen peroxide-based etchant using the emitter electrode as a mask.
[0028]
Etching with this etchant proceeds by a mechanism of InGaAs oxidation → dissolution (ionization). Now, the Ti of the electrode is the semiconductor In
Since the ionization tendency is stronger than that of GaAs, Ti is ionized by the local battery effect and supplies electrons to the InGaAs side. As a result, the InGaAs directly under the electrode in direct contact with Ti is not etched. That is, InGaAs is not side-etched with respect to the electrode Ti which is a mask. In this way, an emitter mesa that is faithfully equal in size to Ti as a mask can be formed. However, since the surface of Ti is easily oxidized, if it is used as it is as an emitter electrode, poor electrical contact with the electrode will occur when the wiring is drawn out from it. In order to obtain electrical contact, after peeling off Ti, an emitter electrode is formed in a non-self-aligned manner, or a metal (eg, Pt or Au) that is difficult to oxidize is laminated on Ti. I have to leave. However, in the latter case, the exchange of electrons as described above is determined by the ionization tendency between the uppermost layer of Pt or Au and the semiconductor. In this case, since the ionization tendency of Ga and In is overwhelmingly large, a cycle occurs in which Ga and In are ionized and electrons are given to the etchant from Pt and Au having a low ionization tendency. In this way, etching of the semiconductor InGaAs is promoted, and so-called abnormal etching occurs.
[0029]
Therefore, according to the present embodiment, a structure using an alloy of Ti and Pt as the emitter electrode is proposed. Since Ti is in contact with both the semiconductor layer InGaAs and the etchant by using the alloy, exchange of electrons contributing to the reaction is performed through Ti. Moreover, even when wiring is extracted after the mesa is formed, even if an oxide film is formed on the Ti surface, electrical contact can be made with the Pt portion, so that there is no fear of causing poor contact of the electrode lead. Thus, the mesa size can be processed to be equal to the electrode size, and the mask at the time of mesa formation can be used as an electrode as it is, and the contact failure of the lead-out wiring from the electrode can be made compatible.
[0030]
FIG. 6 is a cross-sectional structure diagram of an InGaP / GaAs HBT according to the present embodiment. 31 is a compound semiconductor substrate, semi-insulating GaAs substrate, 32 is n ⁺ Type GaAs collector contact layer, 33 is an n type GaAs collector layer, and 34 is a heavily doped carbon p ⁺ Type GaAs base layer, 35 is an n type In0.5 Ga0.5 P emitter layer, and 36 is an n type ⁺ Type In _x Ga _1-x As (x = 0 → 0.5) emitter contact layers, which are sequentially stacked on the semi-insulating GaAs substrate 31. Where, for example, n ⁺ Type GaAs collector contact layer 32 is 500 nm, Si concentration 5 × 10 ¹⁸ cm ^-3 N-type GaAs collector layer 33 is 500 nm, Si concentration is 1 × 10 ¹⁶ cm ^-3 , P ⁺ Type GaAs base layer 34 is 50 nm, C concentration 5 × 10 ¹⁹ cm ^-3 , N-type In _0.5 Ga _0.5 P emitter layer 35 is 50 nm, Si concentration 5 × 10 ¹⁷ cm ^-3 , N ⁺ Type In _x Ga _1-x As layer 36 is 100 nm, Si concentration 3 × 10 ¹⁹ cm ^-3 And
[0031]
The steps up to the formation of the emitter mesa are shown in cross section in the order of FIG. First, the photoresist 50 is patterned so as to open the emitter electrode portion. Next, the TiPt alloy 51 is vacuum-deposited by sputtering or electron beam evaporation (FIG. 7a). Here, a film was formed by two-source simultaneous deposition of Ti and Pt using an electron beam deposition apparatus. This process can be performed by sputtering to form a film by simultaneous sputtering of two targets of Ti and Pt, by sputtering a TiPt alloy target, or by electron beam evaporation using a TiPt alloy source. Also good. Subsequently, an emitter electrode 37 is formed by a lift-off method (FIG. 7b). Etching is performed using the emitter electrode 37 as a mask to expose the base layer 34 (FIG. 7c). As the etchant, a mixed solution of phosphoric acid / hydrogen peroxide / water is used. The etchant is not limited to a mixed solution of phosphoric acid / hydrogen peroxide / water as long as it is an oxidant + acid system. The cross-sectional shape at this time is a shape in which side etching is not performed on the emitter electrode which is a mask, and is a mesa shape defined by the {111} A plane.
[0032]
In this state, the photoresist is patterned so as to protect the element region, and ion implantation is performed to increase the resistance of the region other than the element region 44. Subsequently, the entire surface is SiO ₂ A film 41 is deposited to 200 nm. Next, a base electrode pattern is formed with a photoresist, and SiO 2 ₂ The base electrode 38 is formed by etching the film 41 using ammonium fluoride and then depositing and lifting off the electrode metal. Further, a collector electrode pattern is formed with a photoresist, and a collector electrode 39 is formed by etching, vapor deposition, and lift-off. Next, in order to protect the entire surface of the device, a SiN passivation film 42 is deposited by plasma CVD.
[0033]
Finally, the entire element is flattened with a resin 43 such as polyimide, BCB (benzocyclobutene), or an olefin-based resin, a contact hole is opened on the electrode, and a wiring 40 is formed, whereby an HBT can be manufactured. .
[0034]
In the present embodiment, Ti is used as the metal having a low ionization energy of the emitter electrode and Pt is used as the large metal. However, the present invention is not limited to this. The same effect can be obtained by using a combination of one of Ti, Cr, and Al and one of Pt and W.
By the above method, it is possible to provide an HBT in which the emitter mesa size can be formed with good controllability and the emitter resistance can be reduced.
[0035]
【The invention's effect】
As described above, according to the present invention, by using a material containing an element that is more easily oxidized than an element corresponding to a cation atom constituting a compound semiconductor as a mask material, wet etching is performed by a reaction involving an oxidation reaction. Etching with good controllability that can suppress side etching can be performed. In addition, since a highly reactive substance is used for the mask material, the adhesiveness to the semiconductor layer is high, and etching with high reproducibility without trouble such as the penetration of the etching solution can be performed.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram illustrating the principle of the present invention.
FIG. 2 is a schematic view of wet etching according to the first embodiment of the present invention.
FIG. 3 is a schematic view of wet etching according to a second embodiment of the present invention.
FIG. 4 is a schematic view of wet etching according to a third embodiment of the present invention.
FIG. 5 is a schematic view of wet etching according to a fourth embodiment of the present invention.
FIG. 6 is a sectional structural view of an HBT according to a fifth embodiment of the present invention.
FIG. 7 is a view showing a method for manufacturing an HBT according to a fifth embodiment of the present invention.
FIG. 8 is a schematic diagram of conventional wet etching.
FIG. 9 is a cross-sectional structure diagram of an HBT of Conventional Example 1.
FIG. 10 is a cross-sectional structure diagram of an HBT of Conventional Example 2.
[Explanation of symbols]
1 Mask material containing material with low standard electrode potential
2 Compound semiconductor layer
3 {111} A surface
4. Etching reaction of compound semiconductor
5 Reaction of oxidizing agents
6 Reaction of mask material
7 Progress of etching
8 Electron transfer
9 Ti mask
10 n ⁺ Type InGaAs layer
11 InGaAs layer etching reaction
12 Ti oxidation reaction
13 TiW mask
14 TiW oxidation reaction of TiW
15 AuGe \ Ni \ Au layer
16 n-type GaAs layer
17 Etching reaction of GaAs layer
18 Gate electrode
19 Source electrode
20 Drain electrode
21 V-shaped recess groove
22 Source region
23 Drain region
24 channel region
25 GaAs substrate
26 resist mask
27 Side etching
31,111 Semi-insulating GaAs substrate
32,112 n ⁺ Type GaAs collector contact layer
33,113 n-type GaAs collector layer
34,114 p ⁺ Type GaAs base layer
35,115 n-type In _0.5 Ga _0.5 P emitter layer
36,116 n ⁺ Type In _x Ga _1-x As emitter contact layer
37,117 Emitter electrode
38,118 Base electrode
39,119 Collector electrode
40,120 Lead-out wiring
41, 121 SiO ₂ film
42,122 SiN film
43,123 Resin film such as BCB
High resistance region by ion implantation
50 photoresist
51 TiPt alloy
125 Emitter electrode

Claims (5)

N-type In _x on GaAs layer A mask forming step of forming a mask having a desired shape on the layer in which the Ga _1-x As layer is laminated ;
A wet etching step of performing wet etching using the mask,
The method of manufacturing a semiconductor device, wherein the mask contains Ti . The method according to claim 1, wherein the n-type In _x Ga _1-x As layer said mask and stacked layers on the GaAs layer is in ohmic contact. A collector contact layer of a first conductivity type;
A collector layer of a first conductivity type formed on the collector contact layer;
A base layer of a second conductivity type formed on the collector layer;
An emitter layer of a first conductivity type formed on the base layer;
An emitter contact layer formed on the emitter layer;
An emitter electrode formed on the emitter contact layer;
The emitter contact layer has a crystal structure of {111} plane, and the emitter electrode contains Ti. 4. The semiconductor element according to claim 3 , wherein the emitter contact layer is a GaAs compound semiconductor. The semiconductor device according to claim 4, wherein the GaAs compound semiconductor is n-type In _x Ga _1-x As.

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