JP3707987B2 - Semiconductor device and module mounted with the semiconductor device - Google Patents

Semiconductor device and module mounted with the semiconductor device Download PDF

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JP3707987B2
JP3707987B2 JP2000084457A JP2000084457A JP3707987B2 JP 3707987 B2 JP3707987 B2 JP 3707987B2 JP 2000084457 A JP2000084457 A JP 2000084457A JP 2000084457 A JP2000084457 A JP 2000084457A JP 3707987 B2 JP3707987 B2 JP 3707987B2
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semiconductor device
printed wiring
wiring board
semiconductor
bent
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JP2001274318A (en
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昌孝 西川
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Sharp Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップを搭載した半導体装置に関するものであり、特に、Ｄ−ＲＡＭ，Ｓ−ＲＡＭ，Ｍ−ＲＯＭやフラッシュメモリ等の半導体メモリ、これらの半導体メモリを混載して複合メモリ化した大容量型のモジュール、又は、複数の半導体チップ又はセルを選択するためのロジック半導体素子を混載した装置に利用可能な半導体装置に関する。
【０００２】
【従来の技術】
近年、情報携帯端末装置、ＩＣメモリカード、及び、電子スチルカメラ等に使用する半導体メモリの小型化及び大容量化が求められている。半導体メモリを含む一般的な半導体装置は、１枚の半導体チップを所定の形態の接続ピンを備えるリードフレームにボンディングした後に樹脂封止したものである。従来、半導体メモリの大容量化は、主基板（メインボード）上にＳＯＰ（Small Outline Package），ＣＳＰ等のパッケージ形態の小型の半導体メモリを平面状に複数並べて配置したり、ＣＳＰやＴＣＰなどのパッケージ形態の半導体メモリを高さ方向に累積搭載することにより、主基板の単位面積当たりに取り付けられている半導体メモリの数、即ち、単位面積当たりに搭載されている半導体チップの数を増やすことにより行っていた。
【０００３】
【発明が解決しようとする課題】
図７の（ａ）は、はんだボール１０１ａ，１０１ｂを備える表面実装型の半導体装置１００を示す。半導体装置１００は、はんだボール１０１ａ，１０１ｂの取り付けられている位置の直上の位置にはんだ取り付け部１０２ａ，１０２ｂを備える。図７の（ｂ）は、主基板１１０上のはんだ取り付け部１１１ａ，１１１ｂに上記半導体装置１００のはんだボール１０１ａ，１０１ｂを取り付けた後、更に、その上に同一構成の半導体装置１０３，１０６を実装した状態を示す。半導体装置１０３のはんだボール１０４ａ，１０４ｂは、半導体装置１００のはんだ取り付け部１０２ａ，１０２ｂにはんだ付けされる。半導体装置１０６のはんだボール１０７ａ，１０７ｂは、半導体装置１０３のはんだ取り付け部１０５ａ，１０５ｂにはんだ付けされる。
【０００４】
はんだ付けは、半導体装置１００を所定の位置に載置した主基板１１０を所定温度の雰囲気の炉内に置いてはんだボールを溶かして行う（いわゆるはんだリフロー処理）。半導体装置１００を主基板１１０にはんだ付けした後、半導体装置１００の上に半導体装置１０３を取り付ける際、再びはんだボール１０１ａ，１０１ｂのはんだを溶かすことなく、半導体装置１０３を半導体装置１００にはんだ付けし、更に、この後に、はんだボール１０１ａ，１０１ｂ，１０４ａ，１０４ｂのはんだを溶かすことなく、半導体装置１０６を半導体装置１０３にはんだ付けするには、各半導体装置の備えるはんだボール１０１ａ，１０１ｂ、１０４ａ，１０４ｂ、１０７ａ，１０７ｂは、順に融点の低いものを使用することが必要になる。このように、半導体装置１０１，１０２，１０３は、構成は同じであっても別々の融点のはんだボールを備えることが必要となり、製造コストが高くなる。
【０００５】
図８の（ａ）は、接続ピン２０１ａ，２０１ｂを備える半導体装置２００を示す図である。図８の（ｂ）は、基板２１０のはんだ取り付け部２１１ａ，２１１ｂに半導体装置２０１の接続ピン２０１ａ，２０１ｂを接続した後、更に、同一形態の半導体装置２０２，２０４を積み重ねるように実装し、各接続ピン２０３ａ，２０３ｂ、２０５ａ，２０５ｂを、各々はんだ取り付け部２１１ａ，２１１ｂにはんだ付けした状態を示す図である。図示するように、半導体装置２０２，２０４は、長さの異なる接続ピンを必要とする。このため、個々の半導体素子の生産性が低くなってしまう。
【０００６】
また、上記図７及び図８に示す何れの場合も、積み重ねて実装する各半導体装置のはんだボール又は接続ピンの位置が同じ場所であれば良いが、それぞれのピンの位置が異なる場合、ダミーの接続ピンを設ける必要が生じ、半導体装置の設計の自由度や生産性に問題が生じる。
【０００７】
上記の他、接続ピンをチップの片側に集めたパッケージ（例えば、ＳＩＰ）形態の半導体装置を利用し、半導体装置の取り付けに必要な主基板上の面積を小さくして単位面積当たりに搭載可能なチップの数を増やすことも考えられる。図９の（ａ）は、パッケージの一端に集めた接続ピン３０１を備える半導体装置３００を、主基板３１０のはんだ取り付け部３１１に取り付けた状態を示す図である。また、図９の（ｂ）は、半導体装置３００を基板３１０のはんだ取り付け部３１１に取り付けた後に、更にはんだ取り付け部３１２に半導体装置３０２の接続ピン３０３を接続し、はんだ取り付け部３１３に半導体装置３０４の接続ピン３０５を接続した状態を示す。当該手法では、各半導体装置３００，３０２，３０４の接続ピン３０１，３１２，３１３の配列及び形状を統一する必要が無いため、上記図７及び図８に示す半導体装置に比べて半導体装置の設計の自由度を向上することができる。しかし、全ての接続ピンをパッケージの一端に集めるため、パッケージ内での配線の引き回しが複雑化し、場合によってはチップからの配線長に起因する不具合が生じる場合もある。また、パッケージの２辺又は４辺全てに接続ピンを備える場合に比べて、接続端子を備える辺が長くなるといった不都合が生じる。
【０００８】
本発明は、上記従来の問題を解消し、設計の自由度を確保しつつも主基板の単位面積当たりに取り付ける半導体チップの数を増加した半導体装置、及び、当該半導体装置を取り付けたモジュールを提供することを目的とする。
【０００９】
【課題を解決するための手段】
請求項１記載の半導体装置は、複数の半導体チップを搭載し、主基板に電気的に接続される接続部を備えた、プリント配線基板、からなる半導体装置において、プリント配線基板が、九十九折り状に折り曲げられており、接続部が、折曲部に設けられており、折り曲げられてできた各面が、対向して近接しており、且つ、主基板に対して垂直になるように折り曲げた場合に比べ、主基板に接続した時の高さが低くなるように、主基板に対して一方向に傾いている、ことを特徴とする。
【００１０】
請求項２記載の半導体装置は、請求項１記載の半導体装置であって、折り曲げてできた各面が互いに平行に並んでいる、ことを特徴とする。
【００１１】
請求項３記載の半導体装置は、請求項１又は請求項２に記載の半導体装置であって、接続部が設けられていない折曲部の内、少なくとも１以上の折曲部に、プリント配線基板を主基板に固定するための固定部を備えている、ことを特徴とする。
【００１２】
請求項４記載の半導体装置は、請求項１乃至請求項３の何れかに記載の半導体装置であって、プリント配線基板の少なくとも折り曲げられている箇所が絶縁性のフィルム基板である、ことを特徴とする。
【００１３】
請求項５記載の半導体装置は、請求項１乃至請求項４の何れかに記載の半導体装置であって、プリント配線基板の両面に配線が施されている、ことを特徴とする。
【００１４】
請求項６記載の半導体装置は、請求項１乃至請求項５の何れかに記載の半導体装置であって、近接している面に、それぞれ搭載されている半導体チップが、絶縁シートを介して接している、ことを特徴とする。
【００１５】
請求項７記載の半導体装置は、請求項１乃至請求項６の何れかに記載の半導体装置であって、複数の半導体チップが、プリント配線基板に、ワイヤボンディング方式により搭載されている、ことを特徴とする。
【００１６】
請求項８記載の半導体装置は、請求項１乃至請求項６の何れかに記載の半導体装置であって、複数の半導体チップが、プリント配線基板に、フリップチップ方式により搭載されている、ことを特徴とする。
【００１７】
請求項９記載の半導体装置は、請求項１乃至請求項６の何れかに記載の半導体装置であって、複数の半導体チップが、プリント配線基板に、ワイヤボンディング方式又はフリップチップ方式により搭載されている、ことを特徴とする。
【００１８】
請求項１０記載の半導体装置は、請求項１乃至請求項９の何れかに記載の半導体装置であって、プリント配線基板が、半導体チップ以外の電子部品も搭載している、ことを特徴とする。
【００１９】
請求項１１記載のモジュールは、請求項１乃至請求項１０の何れかに記載の半導体装置が、接続されている主基板から成っている、ことを特徴とする。
【００２２】
【発明の実施の形態】
（１）発明の概要
本発明の半導体装置は、複数の半導体チップを搭載し、長手方向に沿って九十九折り状に折り曲げて縮めたプリント配線基板と、当該折り曲げることにより生じる略Ｕ字状の曲部（谷の部分）に主基板に実装するための接続部を備えることを特徴とする（図３を参照）。上記プリント配線基板を九十九折り状に折り曲げることにより装置の小型化が図られ、主基板上に取り付ける単位面積当たりの半導体チップの数を増やすことができる。また、略Ｕ字状の曲部を複数設けるように折り曲げ、かつ、主基板との接続部を複数設けることにより、プリント配線基板上での配線の引き回しの自由度を向上することができる。
以下、上記特徴を具備する発明の実施の形態に係る半導体装置、及び、当該半導体装置を取り付けたモジュールについて、添付の図面を用いて説明する。
【００２３】
（２）実施の形態
図１は、実施の形態にかかる半導体装置１で使用するプリント配線基板２と、当該プリント配線基板２の一部を拡大した断面を示す図である。プリント配線基板２は、絶縁性を有し、かつ屈曲可能な材料としてポリイミドを採用する。なお、ポリイミドの代わりに、ポリエステル等の薄いプリント配線基材を用いても良い。また、上記屈曲可能な材料は、折り曲げる位置のみに用いることとしても良い。
【００２４】
なお、本実施形態で使用するプリント配線基板２のサイズとしては、長手方向の長さ（以下、長さＬと表す）が短手方向の長さ（以下、幅Ｗと表す）よりも１．５倍以上の寸法であって、長さＬは、約２０ｍｍ〜２００ｍｍであり、幅Ｗは、約１０ｍｍ〜４０ｍｍであり、厚みＴは約０．０５ｍｍ〜０．２０ｍｍの程度のものを想定している。
【００２５】
プリント配線基板２は、厚さ１２μｍ又は１８μｍの銅箔が表裏に貼られた厚さ５０μｍのポリイミド基材３に対し、まず、バイアホールを形成する箇所をレーザにより削孔し、当該削孔箇所に厚さ約１０μｍの銅メッキ４を施した後に、基板２の表裏に所定の配線パターン５をエッチングにより形成し、上記削孔箇所にソルダーレジスト６を埋め込むと共に、チップや部品を接続する電極、及び、基板の折り曲げ箇所を除くはんだ付けしない箇所にソルダーレジスト６を約２０μｍ程度塗布して形成したものである。プリント配線基板２上の両面に配線パターンを有する箇所の厚みは、約７４μｍになる。上記削孔処理、銅メッキ処理、ソルダーレジスト６の埋め込み処理により表裏の配線を繋ぐバイアホールが形成される。
【００２６】
図２の（ａ）は、図１で説明したプリント配線基板２の上面に半導体チップ１０，１１，１２，１３，１４，１５…を搭載し、下面に表面実装型のチップ抵抗、コンデンサ、トランジスタ等の電子部品２１を取り付けた状態を示す断面図と、プリント配線基板２の一部を拡大した断面図を示す。各半導体チップ１０〜１５…は、プリント配線基板２にワイヤ（例えば、半導体チップ１２ではワイヤ２０）によりボンディングされている。プリント配線基板に半導体チップをワイヤボンディングにより取り付けることで、プリント配線基板の厚みの増加を抑制することができる。また、プリント配線基板に半導体チップ以外の電子部品も搭載することで、主基板への半導体チップ及び電子部品の実装点数を向上することができる。
【００２７】
プリント配線基板２は、矢印で示す方向に折り曲げられ、完全に折り曲げられた状態で固定される。当該固定方法としては、プリント配線基板２を折り曲げることによりできる各面の幅方向（プリント配線基板２の短手方向）の両端部分をそれぞれ棒状又は板状の固定部材（図示せず）に取り付けて固定することが考えられる。なお、プリント配線基板２を折り曲げる場合、屈曲部分の配線が断線するのを防止するため、曲率半径が０．５ｍｍ以上になるように直径１ｍｍの棒状の絶縁材をあてがいながら折り曲げる。基板の曲げに対する配線の強度に余裕がある場合には、曲率半径が０．５ｍｍ以下となるように折り曲げても良い。プリント配線基板２を折り曲げて固定したものが半導体装置１の完成品となる（後に説明する図３を参照）。
【００２８】
プリント配線基板２の上面に搭載された各半導体チップ１０〜１５は、折り曲げた面毎に樹脂１７，１８，１９，…により封止する。これにより、上記各半導体チップ１０〜１５を外部環境や機械的なストレスから保護する。上記樹脂封止した箇所１７，１８，１９の厚みは、約１．０ｍｍであり、プリント配線基板２の裏面に取り付けられる電子部品２１の幅を約１．０ｍｍとすると、この部分のプリント配線基板の厚みは、約２．１ｍｍになる。
【００２９】
図２の（ｂ）は、プリント配線基板２を折り曲げる途中の状態を示す図である。このようにプリント配線基板２を九十九折り状に折り曲げることで、半導体装置１の長手方向の長さを縮めることができる。プリント配線基板２の略Ｕ字状の曲部には、主基板（図示せず）との接続部１６ａ，１６ｂ，…を備える。なお、接続部１６ａ，１６ｂ，…は、ピン状であっても良いし、はんだボールを有する形状であっても良い。当該接続部１６ａ，１６ｂ，…については、以下に図３を参照しつつ説明する。
【００３０】
図３の（ａ）は、半導体装置１を実装したモジュールの一部を示す図である。該モジュールは、単位面積当たりの半導体チップ及び電子部品の数を増やすことができるため、小型化及び高集積化を図ることができる。半導体装置１のモジュールの主基板５０への実装は、接続部１６ａ，１６ｂを、主基板５０に備える接続部５１ａ，５１ｂにはんだ付けして行う。半導体装置１は、長さＬ＝４８ｍｍ、幅Ｗ＝３５ｍｍのサイズのプリント配線基板であって、当該プリント配線基板の両端から１２ｍｍの位置に接続部１６ａ，１６ｂを備えるプリント配線基板２を、前記接続部１６ａ，１６ｂの箇所が略Ｕ字状の谷になるように長手方向に１２ｍｍ単位で九十九折り状に折り曲げ、折り曲げた状態で固定したものである。図示するように、折り曲げられたプリント配線基板２の各面を互いに平行になるように折り曲げることで、プリント配線基板２を最も縮めることができる。また、左端に位置する下部の曲部から右隣に位置する上部の曲部までの距離と、当該上部の曲部から右隣に位置する下部の曲部までの距離が同じになるように折り曲げる。これにより、折り曲げられたプリント配線基板２の各面を主基板５０に対して垂直に設けることが可能となるため、当該半導体装置１の長さを最小にすることができる。本図に示す半導体装置１のサイズは、長さＬ１＝約１０．０ｍｍ（プリント配線基板の厚み２．１ｍｍ×４＋折り曲げたプリント配線基板同士にできる間隙約０．５ｍｍ×３として求めた）、高さＬ２＝約１２ｍｍ、幅（奥行き）Ｗ＝３５ｍｍとなる。このように、プリント配線基板２を折り曲げることにより装置の横幅を約８０％縮めることができる。
【００３１】
なお、プリント配線基板２を折り曲げることにより近接することになる半導体チップ同士の電気的な接触を防止するため、上記近接することになる半導体チップ同士の間に絶縁シートを挟むのが好ましい。以下に説明する各半導体装置１の変形例１〜３、半導体装置１’、半導体装置１’の変形例１，２において同じである。
【００３２】
図３の（ｂ）は、半導体装置１の変形例１を実装したモジュールの一部を示す図である。半導体装置１と同じ構成物には同じ参照番号を付して表す。当該半導体装置１の変形例１は、長さＬ＝１４４ｍｍ、幅Ｗ＝３５ｍｍのプリント配線基板２を使用し、当該プリント配線基板２の両端から１２ｍｍの位置に接続部１６ａ，１６ｂを備え、当該プリント配線基板２を、接続部１６ａ，１６ｂを設けた箇所が谷になるように長さ１２ｍｍ単位で九十九折り状に折り曲げて固定したものである。この場合、半導体装置１の変形例１のサイズは、長さＬ１’＝約３０．７ｍｍ（プリント配線基板の厚みを含めた半導体チップ搭載部の一折２．１ｍｍ×１２＋折り曲げたプリント配線基板同士にできる間隙約０．５ｍｍ×１１として求めた）、高さＬ２’＝１２ｍｍ、幅（奥行き）Ｗ＝３５ｍｍとなる。このように、プリント配線基板２を折り曲げることにより装置の長さを約８０％縮めることができる。
【００３３】
図示するように、半導体装置１の変形例１では、当該装置を安定して主基板５０に固定するため、６つある略Ｕ字状の曲部の内、両端に位置する曲部に主基板５０との接続部１６ａ，１６ｂを設ける。
【００３４】
なお、接続部を設ける位置及び数は、本例に限定されず、プリント配線基板２を安定して固定することができる場合には、接続部は、全部で６つある略Ｕ字状の曲部の内の１以上の曲部からなる組に設ければ良い。
【００３５】
図３の（ｃ）は、上記図３の（ｂ）の場合において、更に、半導体装置１の変形例１をモジュールの主基板５０により確実に固定するため、プリント配線基板２の残りの略Ｕ字状の曲部に固定部１６ｃを追加した半導体装置１の変形例２を示す図である。当該変形例２の備える固定部１６ｃに対応して、主基板５０は支持部５１ｃを備える。当該支持部５１ｃは、上記固定部１６ｃにはんだ付けされる。固定部１６ｃを設けることで、半導体装置１の確実な固定が可能になり、必要な接続部の数が少ない場合、例えば、接続部１６ａ１つで足りる場合に、不用な接続部（本例の場合、１６ｂ）を省くことができる。
なお、固定部を設ける位置及び数は、本例に限定されず、必要に応じて上記残りの略Ｕ字状の曲部の内の１以上の曲部からなる組に設ければ良い。
【００３６】
図４は、図１で説明したプリント配線基板２に半導体チップ３０，３１，３２，３３，３４，３５，…をフリップチップ方式により実装した状態を示す図である。プリント配線基板に半導体チップをフリップチップ方式により取り付けることで、基板上の配線と半導体チップ間の絶縁性を高めることができる。図２に示す実装状態図と同じ構成物には同じ参照番号を付し、ここでの説明を省く。図示するように、各半導体チップ３０〜３５，…は、突起状の接続ピン（例えば、半導体チップ３２ではピン３６）を備える。各半導体チップ３０〜３５，…は、上記接続ピンによりプリント配線基板２に接続されている。なお、半導体チップ３０〜３５，…とプリント配線基板２との間の一般にアンダーフィルと呼ぶ界面に樹脂３７，３８，３９，…を注入することにより、半導体チップの取り付け強度を向上することができる。
【００３７】
図５（ａ）〜（ｃ）は、図４を用いて説明したプリント配線基板２を所定の箇所で折り曲げてなる半導体装置１’並びにその変形例１及び２を実装したモジュールの一部を示す図である。
【００３８】
図５（ａ）は、プリント配線基板２が、２回谷折り、１回山折りできる長さの場合に形成される半導体装置１’を示す図である。図５の（ｂ）は、プリント配線基板２が、６回谷折り、５回山折りできる長さの場合に形成される半導体装置１’の変形例１を示す図である。図５の（ｃ）は、上記図５の（ｂ）の場合において、半導体装置１’の変形例１を主基板５０により確実に固定するため、プリント配線基板２の残りの略Ｕ字状の曲部に固定部１６ｃを追加した半導体装置１’の変形例２を示す図である。
【００３９】
本図において示す各半導体装置は、プリント配線基板２への半導体チップの取り付け方式が異なるだけで、接続部１６ａ，１６ｃ、固定部１６ｃの位置及び個数に関しては、上記図３を用いて既に説明した半導体装置１、半導体装置１の変形例１，２についてのものと同じであり、ここでの重複した説明は省く。
【００４０】
以下、主基板５０からの高さに制限がある場合について考察する。図６は、図３の（ｂ）に示したプリント配線基板２を用いて形成される半導体装置１の変形例３を示す図である。図示するように、半導体装置１の変形例３は、プリント配線基板２の略Ｕ字状の曲部の位置が所定量づつずれるように、下部の曲部から右隣に位置する上部の曲部までの距離に比べて、当該上部の曲部から右隣に位置する下部の曲部までの距離が所定量だけ短くなるようにプリント配線基板２を繰り返し折り曲げたものである。プリント配線基板２をこのように折り曲げることにより、半導体チップの取り付け面が主基板５０に対して角度θだけ傾き、主基板５０からの高さを低減することができる。なお、上記角度θは、半導体チップ及び電子部品を取り付けた状態のプリント配線基板２の厚みにもよるが約５°程度にまで傾けることができる。
なお、プリント配線基板２に半導体チップをフリップチップボンド方式により取り付けた場合であっても同様である。
半導体チップをワイヤボンド方式及びフリップチップ方式により取り付けることで、プリント配線基板の厚みの増加を抑制しつつ、基板上の配線と半導体チップ間の絶縁性を高めることができる。
【００４１】
【発明の効果】
請求項１記載の半導体装置は、折り曲げたプリント配線基板の各面を当該半導体装置を実装する主基板に対して傾けることで、主基板からの高さを低くすることができる。これにより、主基板からの高さに制限がある場合に対処することができる。
【００４２】
請求項２記載の半導体装置は、上記何れかの半導体装置において、折り曲げてできた各面を互いに平行に並べることにより、プリント配線基板の長さを縮めて半導体装置の小型化を図ることができる。
【００４３】
請求項３記載の半導体装置は、上記何れかの半導体装置において、接続部の設けられていない折曲部の内、少なくとも１以上の折曲部に、プリント配線基板を主基板に固定するための固定部を設けることにより、より確実に装置を主基板に固定することができる。
【００４４】
請求項４記載の半導体装置は、上記何れかの半導体装置において、上記プリント配線基板の内、少なくとも折り曲げられる箇所を絶縁性のフィルム基板とすることで、プリント配線基板に半導体チップを搭載した後に当該基板を折り曲げることを容易にすることができる。
【００４５】
請求項５記載の半導体装置は、上記何れかの半導体装置において、両面に配線を有するプリント配線基板を使用することで、半導体チップを含む電子部品の実装密度を向上することができる。
【００４６】
請求項６記載の半導体装置は、上記何れかの半導体装置において、上記プリント配線基板が曲部において折り曲げられていることによって近接している半導体チップの間に絶縁シートを備える。これにより、プリント配線基板の長さをより狭めて、半導体装置の小型化を図ることができる。
【００４７】
請求項７記載の半導体装置は、上記何れかの半導体装置において、プリント配線基板に半導体チップをワイヤボンディングにより取り付けることで、プリント配線基板の厚みの増加を抑制することができる。
【００４８】
請求項８記載の半導体装置は、請求項１乃至請求項６の何れかに記載の半導体装置において、プリント配線基板に半導体チップをフリップチップ方式により取り付けることで、基板上の配線と半導体チップ間の絶縁性を高めることができる。
【００４９】
請求項９記載の半導体装置は、請求項１乃至請求項６の何れかに記載の半導体装置において、必要に応じて、半導体チップをワイヤボンド方式及びフリップチップ方式により取り付けることで、プリント配線基板の厚みの増加を抑制しつつ、基板上の配線と半導体チップ間の絶縁性を高めることができる。
【００５０】
請求項１０記載の半導体装置は、上記何れかの半導体装置において、上記プリント配線基板に半導体チップ以外の電子部品も搭載することで、主基板への半導体チップ及び電子部品の実装点数を向上することができる。
【００５１】
請求項１１記載の半導体装置は、上記何れかの半導体装置を用いることで単位面積当たりの半導体チップ及び電子部品の数を増やすことができるため、小型化及び高集積化を図ることができる。
【図面の簡単な説明】
【図１】 実施の形態に係る半導体装置で用いるプリント配線基板の構成を示す図である。
【図２】 図１に示したプリント配線基板に半導体チップを搭載した状態を示す図である。
【図３】 図２に示すように半導体チップを搭載し、所定の箇所で折り曲げられたプリント配線基板を主基板に取り付けた状態を示す図である。
【図４】 図１で示したプリント配線基板に半導体チップを搭載した状態を示す図である。
【図５】 図４に示すように半導体チップを搭載し、所定の箇所で折り曲げられたプリント配線基板を主基板に取り付けた状態を示す図である。
【図６】 プリント配線基板の折り曲げ方の変形例について説明する図である。
【図７】 従来の半導体装置を主基板に高さ方向に積み上げて取り付けた場合を示す図である。
【図８】 従来の半導体装置を主基板に高さ方向に積み上げて取り付けた場合を示す図である。
【図９】 一端に接続ピンを備える従来の半導体装置を主基板に取り付けた状態を示す図である。
【符号の説明】
１，１’ 半導体装置、２ プリント配線基板、３ ポリイミド基材、４ 銅メッキ、５ 配線パターン、６ ソルダーレジスト、１０，１１，１２，１３，１４，１５，３０，３１，３２，３３，３４，３５ 半導体チップ、１６ａ，１６ｂ 接続部、１６ｃ 固定部、１７，１８，１９ 樹脂、２０ ワイヤ、２１ 電子部品、５０ 主基板。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device on which a semiconductor chip is mounted. In particular, the present invention relates to a semiconductor memory such as a D-RAM, S-RAM, M-ROM, flash memory, etc. The present invention relates to a semiconductor device that can be used for a device in which a capacitive module or a logic semiconductor element for selecting a plurality of semiconductor chips or cells is mixedly mounted.
[0002]
[Prior art]
In recent years, there has been a demand for downsizing and increasing the capacity of semiconductor memories used for portable information terminals, IC memory cards, electronic still cameras, and the like. A general semiconductor device including a semiconductor memory is obtained by bonding one semiconductor chip to a lead frame having a predetermined form of connection pins and then sealing with resin. Conventionally, the capacity of a semiconductor memory has been increased by arranging a plurality of small semiconductor memories in a package form such as SOP (Small Outline Package) and CSP on a main board (main board) in a plane, or by using CSP, TCP, etc. By accumulatively mounting package-type semiconductor memories in the height direction, by increasing the number of semiconductor memories attached per unit area of the main substrate, that is, by increasing the number of semiconductor chips mounted per unit area I was going.
[0003]
[Problems to be solved by the invention]
FIG. 7A shows a surface-mount semiconductor device 100 including solder balls 101a and 101b. The semiconductor device 100 includes solder attachment portions 102a and 102b at positions immediately above positions where the solder balls 101a and 101b are attached. In FIG. 7B, after the solder balls 101a and 101b of the semiconductor device 100 are attached to the solder attachment portions 111a and 111b on the main substrate 110, the semiconductor devices 103 and 106 having the same configuration are further mounted thereon. Shows the state. The solder balls 104 a and 104 b of the semiconductor device 103 are soldered to the solder mounting portions 102 a and 102 b of the semiconductor device 100. The solder balls 107 a and 107 b of the semiconductor device 106 are soldered to the solder mounting portions 105 a and 105 b of the semiconductor device 103.
[0004]
Soldering is performed by placing the main substrate 110 on which the semiconductor device 100 is placed at a predetermined position in a furnace having a predetermined temperature and melting the solder balls (so-called solder reflow process). After the semiconductor device 100 is soldered to the main substrate 110, when the semiconductor device 103 is mounted on the semiconductor device 100, the semiconductor device 103 is soldered to the semiconductor device 100 without melting the solder balls 101a and 101b again. Further, after this, in order to solder the semiconductor device 106 to the semiconductor device 103 without melting the solder of the solder balls 101a, 101b, 104a, and 104b, the solder balls 101a, 101b, 104a, and 104b included in each semiconductor device are used. 107a and 107b need to be used in the order of low melting points. As described above, the semiconductor devices 101, 102, and 103 need to be provided with solder balls having different melting points even if the configuration is the same, and the manufacturing cost increases.
[0005]
FIG. 8A shows a semiconductor device 200 including connection pins 201a and 201b. 8B, after connecting the connection pins 201a and 201b of the semiconductor device 201 to the solder mounting portions 211a and 211b of the substrate 210, the semiconductor devices 202 and 204 of the same form are further stacked and mounted. It is a figure which shows the state which soldered the connection pins 203a, 203b, 205a, 205b to the solder attachment parts 211a, 211b, respectively. As shown in the figure, the semiconductor devices 202 and 204 require connection pins having different lengths. For this reason, the productivity of each semiconductor element is lowered.
[0006]
Further, in any of the cases shown in FIG. 7 and FIG. 8, the positions of the solder balls or connection pins of the semiconductor devices stacked and mounted may be the same, but if the positions of the pins are different, There is a need to provide connection pins, which causes problems in the degree of freedom in design and productivity of the semiconductor device.
[0007]
In addition to the above, a package (for example, SIP) type semiconductor device in which connection pins are gathered on one side of the chip is used, and the area on the main substrate necessary for mounting the semiconductor device can be reduced and mounted per unit area. It is possible to increase the number of chips. FIG. 9A is a diagram illustrating a state in which the semiconductor device 300 including the connection pins 301 collected at one end of the package is attached to the solder attachment portion 311 of the main board 310. 9B, after the semiconductor device 300 is attached to the solder attachment portion 311 of the substrate 310, the connection pin 303 of the semiconductor device 302 is further connected to the solder attachment portion 312, and the semiconductor device is connected to the solder attachment portion 313. A state where the connection pins 305 of 304 are connected is shown. In this method, it is not necessary to unify the arrangement and shape of the connection pins 301, 312, and 313 of the semiconductor devices 300, 302, and 304, so that the design of the semiconductor device is higher than that of the semiconductor devices shown in FIGS. 7 and 8. The degree of freedom can be improved. However, since all the connection pins are gathered at one end of the package, the routing of the wiring within the package becomes complicated, and in some cases, a defect due to the wiring length from the chip may occur. Further, in comparison with the case where the connection pins are provided on all of the two sides or four sides of the package, there is a disadvantage that the sides provided with the connection terminals become longer.
[0008]
The present invention provides a semiconductor device in which the number of semiconductor chips to be attached per unit area of a main substrate is increased while eliminating the above-described conventional problems and ensuring a degree of design freedom, and a module to which the semiconductor device is attached. The purpose is to do.
[0009]
[Means for Solving the Problems]
The semiconductor device according to claim 1 is a semiconductor device comprising a printed wiring board on which a plurality of semiconductor chips are mounted and provided with a connection portion that is electrically connected to the main board. It is bent in a fold shape, the connecting portion is provided in the bent portion, and the surfaces formed by bending are close to each other and are perpendicular to the main substrate. It is characterized in that it is inclined in one direction with respect to the main substrate so that the height when it is connected to the main substrate is lower than when it is bent.
[0010]
A semiconductor device according to a second aspect is the semiconductor device according to the first aspect, wherein the bent surfaces are arranged in parallel to each other.
[0011]
The semiconductor device according to claim 3 is the semiconductor device according to claim 1 or 2, wherein at least one of the bent portions not provided with the connection portion is formed on a printed wiring board. It is characterized by having a fixing part for fixing the to the main board.
[0012]
A semiconductor device according to a fourth aspect is the semiconductor device according to any one of the first to third aspects, wherein at least a bent portion of the printed wiring board is an insulating film substrate. And
[0013]
A semiconductor device according to a fifth aspect is the semiconductor device according to any one of the first to fourth aspects, wherein wiring is provided on both surfaces of the printed wiring board.
[0014]
A semiconductor device according to a sixth aspect is the semiconductor device according to any one of the first to fifth aspects, wherein the semiconductor chips mounted on the adjacent surfaces are in contact with each other through an insulating sheet. It is characterized by that.
[0015]
A semiconductor device according to a seventh aspect is the semiconductor device according to any one of the first to sixth aspects, wherein a plurality of semiconductor chips are mounted on a printed wiring board by a wire bonding method. Features.
[0016]
The semiconductor device according to claim 8 is the semiconductor device according to any one of claims 1 to 6, wherein a plurality of semiconductor chips are mounted on a printed wiring board by a flip chip method. Features.
[0017]
A semiconductor device according to a ninth aspect is the semiconductor device according to any one of the first to sixth aspects, wherein a plurality of semiconductor chips are mounted on a printed wiring board by a wire bonding method or a flip chip method. It is characterized by that.
[0018]
A semiconductor device according to a tenth aspect is the semiconductor device according to any one of the first to ninth aspects, wherein the printed wiring board is mounted with an electronic component other than the semiconductor chip. .
[0019]
A module according to an eleventh aspect is characterized in that the semiconductor device according to any one of the first to tenth aspects comprises a connected main substrate.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
(1) Summary of the invention
A semiconductor device according to the present invention includes a printed wiring board on which a plurality of semiconductor chips are mounted, folded into a ninety-nine fold along the longitudinal direction, and a substantially U-shaped curved portion (valley of the valley) generated by the folding. And a connecting portion for mounting on the main board (see FIG. 3). By bending the printed wiring board into a 99-fold shape, the apparatus can be miniaturized, and the number of semiconductor chips per unit area to be mounted on the main board can be increased. Further, by bending so as to provide a plurality of substantially U-shaped curved portions and providing a plurality of connection portions with the main substrate, the degree of freedom in routing the wiring on the printed circuit board can be improved.
Hereinafter, a semiconductor device according to an embodiment of the invention having the above characteristics and a module to which the semiconductor device is attached will be described with reference to the accompanying drawings.
[0023]
(2) Embodiment
FIG. 1 is a diagram illustrating a printed wiring board 2 used in the semiconductor device 1 according to the embodiment and a cross-section in which a part of the printed wiring board 2 is enlarged. The printed wiring board 2 employs polyimide as an insulating and bendable material. A thin printed wiring substrate such as polyester may be used instead of polyimide. Further, the bendable material may be used only at a bending position.
[0024]
The size of the printed wiring board 2 used in the present embodiment is as follows: 1. The length in the longitudinal direction (hereinafter referred to as length L) is less than the length in the short direction (hereinafter referred to as width W). It is assumed that the dimension is 5 times or more, the length L is about 20 mm to 200 mm, the width W is about 10 mm to 40 mm, and the thickness T is about 0.05 mm to 0.20 mm. ing.
[0025]
The printed wiring board 2 is formed by first drilling a portion for forming a via hole with a laser on a polyimide base material 3 having a thickness of 12 μm or 18 μm and having a copper foil pasted on both sides thereof. After the copper plating 4 having a thickness of about 10 μm is applied, a predetermined wiring pattern 5 is formed by etching on the front and back of the substrate 2, and the solder resist 6 is embedded in the drilled portion, and electrodes for connecting chips and components, In addition, the solder resist 6 is formed by applying approximately 20 μm to a portion that is not soldered except for a bent portion of the substrate. The thickness of the portion having the wiring pattern on both surfaces of the printed wiring board 2 is about 74 μm. Via holes for connecting the front and back wirings are formed by the above-described drilling process, copper plating process, and solder resist 6 filling process.
[0026]
FIG. 2A shows a semiconductor chip 10, 11, 12, 13, 14, 15... Mounted on the upper surface of the printed wiring board 2 described in FIG. 1 and a surface-mounted chip resistor, capacitor, transistor on the lower surface. Sectional drawing which shows the state which attached electronic components 21, such as these, and sectional drawing which expanded a part of printed wiring board 2 are shown. The semiconductor chips 10 to 15 are bonded to the printed wiring board 2 with wires (for example, the wires 20 in the semiconductor chip 12). By attaching the semiconductor chip to the printed wiring board by wire bonding, an increase in the thickness of the printed wiring board can be suppressed. Also, by mounting electronic components other than semiconductor chips on the printed wiring board, the number of semiconductor chips and electronic components mounted on the main substrate can be improved.
[0027]
The printed wiring board 2 is bent in the direction indicated by the arrow and is fixed in a completely bent state. As the fixing method, both end portions in the width direction (short direction of the printed wiring board 2) of each surface that can be formed by bending the printed wiring board 2 are attached to a rod-like or plate-like fixing member (not shown). It may be fixed. When the printed wiring board 2 is bent, in order to prevent the wiring at the bent portion from being disconnected, the printed wiring board 2 is bent while applying a rod-shaped insulating material having a diameter of 1 mm so that the radius of curvature is 0.5 mm or more. When there is a margin in the strength of the wiring with respect to the bending of the substrate, the wiring may be bent so that the radius of curvature is 0.5 mm or less. A product obtained by bending and fixing the printed wiring board 2 is a completed product of the semiconductor device 1 (see FIG. 3 described later).
[0028]
Each semiconductor chip 10-15 mounted on the upper surface of the printed wiring board 2 is sealed with resin 17, 18, 19,... As a result, the semiconductor chips 10 to 15 are protected from the external environment and mechanical stress. The thickness of the resin-encapsulated portions 17, 18, and 19 is about 1.0 mm, and the width of the electronic component 21 attached to the back surface of the printed wiring board 2 is about 1.0 mm. The thickness of is about 2.1 mm.
[0029]
FIG. 2B is a diagram showing a state in the middle of bending the printed wiring board 2. In this way, the length of the semiconductor device 1 in the longitudinal direction can be reduced by bending the printed wiring board 2 into a ninety-nine fold. The substantially U-shaped curved portion of the printed wiring board 2 includes connection portions 16a, 16b,... With a main substrate (not shown). The connecting portions 16a, 16b,... May be pin-shaped or may have a shape having solder balls. The connection portions 16a, 16b,... Will be described below with reference to FIG.
[0030]
FIG. 3A shows a part of a module on which the semiconductor device 1 is mounted. Since the module can increase the number of semiconductor chips and electronic components per unit area, it can be downsized and highly integrated. The module of the semiconductor device 1 is mounted on the main substrate 50 by soldering the connection portions 16a and 16b to the connection portions 51a and 51b provided on the main substrate 50. The semiconductor device 1 is a printed wiring board having a length L = 48 mm and a width W = 35 mm, and includes the printed wiring board 2 provided with connection portions 16a and 16b at positions 12 mm from both ends of the printed wiring board. The connection portions 16a and 16b are bent in a ninety-nine fold shape in units of 12 mm in the longitudinal direction so that the locations of the connection portions 16a and 16b are substantially U-shaped valleys, and are fixed in a folded state. As shown in the figure, the printed wiring board 2 can be most contracted by bending the folded surfaces of the printed wiring board 2 so as to be parallel to each other. Also, bend so that the distance from the lower curved part located at the left end to the upper curved part located on the right side is the same as the distance from the upper curved part to the lower curved part located on the right side. . Thereby, each surface of the folded printed wiring board 2 can be provided perpendicularly to the main substrate 50, so that the length of the semiconductor device 1 can be minimized. The size of the semiconductor device 1 shown in this figure is the length L1 = about 10.0 mm (the thickness of the printed wiring board is 2.1 mm × 4 + the gap between the folded printed wiring boards is about 0.5 mm × 3), Height L2 = about 12 mm and width (depth) W = 35 mm. Thus, the width of the apparatus can be reduced by about 80% by bending the printed wiring board 2.
[0031]
In addition, in order to prevent electrical contact between semiconductor chips that come close to each other when the printed wiring board 2 is bent, it is preferable to sandwich an insulating sheet between the semiconductor chips that come close to each other. The same applies to Modifications 1 to 3 of each semiconductor device 1, semiconductor device 1 ′, and Modifications 1 and 2 of the semiconductor device 1 ′ described below.
[0032]
FIG. 3B is a diagram illustrating a part of a module on which the first modification of the semiconductor device 1 is mounted. The same components as those of the semiconductor device 1 are denoted by the same reference numerals. Modification 1 of the semiconductor device 1 uses a printed wiring board 2 having a length L = 144 mm and a width W = 35 mm, and includes connection portions 16 a and 16 b at positions 12 mm from both ends of the printed wiring board 2. The printed wiring board 2 is fixed by being folded into ninety nine folds in units of 12 mm in length so that the locations where the connecting portions 16a and 16b are provided are valleys. In this case, the size of the modification 1 of the semiconductor device 1 is as follows: length L1 ′ = about 30.7 mm (a part of the semiconductor chip mounting portion including the thickness of the printed wiring board is 2.1 mm × 12 + printed wiring boards The gap is about 0.5 mm × 11), the height L2 ′ = 12 mm, and the width (depth) W = 35 mm. Thus, the length of the apparatus can be reduced by about 80% by bending the printed wiring board 2.
[0033]
As shown in the figure, in Modification 1 of the semiconductor device 1, in order to stably fix the device to the main substrate 50, the main substrate is placed on the curved portions located at both ends of the six substantially U-shaped curved portions. 50 connecting portions 16a and 16b are provided.
[0034]
Note that the positions and the number of connecting portions are not limited to this example, and when the printed wiring board 2 can be stably fixed, the connecting portions include a total of six approximately U-shaped bends. What is necessary is just to provide in the group which consists of one or more music parts among the parts.
[0035]
FIG. 3C shows the remaining U of the printed wiring board 2 in order to securely fix the modification 1 of the semiconductor device 1 to the main board 50 of the module in the case of FIG. It is a figure which shows the modification 2 of the semiconductor device 1 which added the fixing | fixed part 16c to the character-shaped curved part. Corresponding to the fixing portion 16c included in the second modification, the main board 50 includes a support portion 51c. The support portion 51c is soldered to the fixed portion 16c. By providing the fixing portion 16c, the semiconductor device 1 can be reliably fixed, and when the number of necessary connection portions is small, for example, when only one connection portion 16a is sufficient, an unnecessary connection portion (in this example) 16b) can be omitted.
Note that the position and number of the fixing portions are not limited to this example, and may be provided in a group including one or more of the remaining substantially U-shaped bending portions as necessary.
[0036]
4 is a diagram showing a state in which the semiconductor chips 30, 31, 32, 33, 34, 35,... Are mounted on the printed wiring board 2 described in FIG. By attaching the semiconductor chip to the printed wiring board by the flip chip method, the insulation between the wiring on the board and the semiconductor chip can be improved. The same components as those in the mounting state diagram shown in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted here. As shown in the drawing, each of the semiconductor chips 30 to 35,... Has a protruding connection pin (for example, the pin 36 in the semiconductor chip 32). The semiconductor chips 30 to 35,... Are connected to the printed wiring board 2 by the connection pins. It is possible to improve the mounting strength of the semiconductor chip by injecting the resin 37, 38, 39,... Into the interface between the semiconductor chips 30 to 35,. .
[0037]
FIGS. 5A to 5C show a part of a module in which the semiconductor device 1 ′ formed by bending the printed wiring board 2 described with reference to FIG. 4 at a predetermined position and the modified examples 1 and 2 are mounted. FIG.
[0038]
FIG. 5A is a diagram showing a semiconductor device 1 ′ formed when the printed wiring board 2 has a length that allows two-fold valley folding and one-fold mountain folding. FIG. 5B is a diagram illustrating a first modification of the semiconductor device 1 ′ formed when the printed wiring board 2 has a length that can be folded 6 times and 5 times. FIG. 5C shows the remaining substantially U-shape of the printed wiring board 2 in order to securely fix the modification 1 of the semiconductor device 1 ′ to the main board 50 in the case of FIG. It is a figure which shows the modification 2 of semiconductor device 1 'which added the fixing | fixed part 16c to the curved part.
[0039]
Each semiconductor device shown in this figure is different only in the mounting method of the semiconductor chip to the printed wiring board 2, and the positions and the number of the connecting portions 16a and 16c and the fixing portion 16c have already been described with reference to FIG. This is the same as that of the semiconductor device 1 and the first and second modifications of the semiconductor device 1, and a duplicate description is omitted here.
[0040]
Hereinafter, a case where the height from the main substrate 50 is limited will be considered. FIG. 6 is a diagram showing a third modification of the semiconductor device 1 formed using the printed wiring board 2 shown in FIG. As shown in the drawing, the third modification of the semiconductor device 1 is such that the upper U-shaped curved portion located on the right side from the lower curved portion so that the position of the substantially U-shaped curved portion of the printed wiring board 2 is shifted by a predetermined amount. The printed wiring board 2 is repeatedly bent so that the distance from the upper curved portion to the lower curved portion located on the right is shortened by a predetermined amount compared to the distance up to. By bending the printed wiring board 2 in this way, the mounting surface of the semiconductor chip is inclined by an angle θ with respect to the main board 50, and the height from the main board 50 can be reduced. The angle θ can be tilted to about 5 ° depending on the thickness of the printed wiring board 2 with the semiconductor chip and the electronic component attached.
The same applies to the case where a semiconductor chip is attached to the printed wiring board 2 by the flip chip bonding method.
By attaching the semiconductor chip by the wire bond method and the flip chip method, it is possible to improve the insulation between the wiring on the substrate and the semiconductor chip while suppressing an increase in the thickness of the printed wiring substrate.
[0041]
【The invention's effect】
In the semiconductor device according to the first aspect, the height from the main substrate can be lowered by inclining each surface of the printed printed circuit board with respect to the main substrate on which the semiconductor device is mounted. Thereby, it is possible to cope with a case where the height from the main board is limited.
[0042]
According to a second aspect of the present invention, in the semiconductor device according to any one of the above, the lengths of the printed wiring board can be reduced and the semiconductor device can be miniaturized by arranging the bent surfaces in parallel with each other. .
[0043]
According to a third aspect of the present invention, there is provided the semiconductor device according to any one of the above semiconductor devices, wherein the printed wiring board is fixed to the main substrate in at least one of the bent portions not provided with the connection portion. By providing the fixing portion, the apparatus can be more securely fixed to the main board.
[0044]
The semiconductor device according to claim 4 is the semiconductor device according to any one of the above semiconductor devices, wherein at least a portion to be bent of the printed wiring board is an insulating film substrate, and the semiconductor chip is mounted on the printed wiring board. It is possible to easily bend the substrate.
[0045]
The semiconductor device according to claim 5 can improve the mounting density of electronic components including a semiconductor chip by using a printed wiring board having wirings on both sides in any of the above semiconductor devices.
[0046]
According to a sixth aspect of the present invention, in any one of the above semiconductor devices, an insulating sheet is provided between adjacent semiconductor chips by bending the printed wiring board at a curved portion. Thereby, the length of the printed wiring board can be further reduced, and the semiconductor device can be miniaturized.
[0047]
According to a seventh aspect of the present invention, in any of the above semiconductor devices, an increase in the thickness of the printed wiring board can be suppressed by attaching a semiconductor chip to the printed wiring board by wire bonding.
[0048]
The semiconductor device according to claim 8 is the semiconductor device according to any one of claims 1 to 6, wherein the semiconductor chip is attached to the printed wiring board by a flip chip method, so that the wiring on the substrate and the semiconductor chip are arranged. Insulation can be enhanced.
[0049]
A semiconductor device according to a ninth aspect is the semiconductor device according to any one of the first to sixth aspects, wherein a semiconductor chip is attached by a wire bond method and a flip chip method as necessary, so that the printed circuit board The insulation between the wiring on the substrate and the semiconductor chip can be enhanced while suppressing the increase in thickness.
[0050]
11. The semiconductor device according to claim 10, wherein in any one of the semiconductor devices described above, the mounting number of the semiconductor chip and the electronic component on the main substrate is improved by mounting an electronic component other than the semiconductor chip on the printed wiring board. Can do.
[0051]
In the semiconductor device according to the eleventh aspect, the number of semiconductor chips and electronic components per unit area can be increased by using any one of the semiconductor devices described above, and therefore, miniaturization and high integration can be achieved.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a printed wiring board used in a semiconductor device according to an embodiment.
2 is a view showing a state in which a semiconductor chip is mounted on the printed wiring board shown in FIG. 1;
FIG. 3 is a view showing a state where a printed wiring board mounted with a semiconductor chip and bent at a predetermined position is attached to a main board as shown in FIG. 2;
4 is a view showing a state in which a semiconductor chip is mounted on the printed wiring board shown in FIG. 1. FIG.
5 is a view showing a state in which a semiconductor chip is mounted as shown in FIG. 4 and a printed wiring board bent at a predetermined position is attached to a main board. FIG.
FIG. 6 is a diagram illustrating a modification example of a method of bending a printed wiring board.
FIG. 7 is a diagram showing a case where conventional semiconductor devices are stacked and attached to a main substrate in the height direction.
FIG. 8 is a diagram illustrating a case where conventional semiconductor devices are stacked and attached to a main substrate in a height direction.
FIG. 9 is a view showing a state in which a conventional semiconductor device having a connection pin at one end is attached to a main substrate.
[Explanation of symbols]
1,1 'semiconductor device, 2 printed wiring board, 3 polyimide substrate, 4 copper plating, 5 wiring pattern, 6 solder resist, 10, 11, 12, 13, 14, 15, 30, 31, 32, 33, 34 , 35 Semiconductor chip, 16a, 16b connection portion, 16c fixing portion, 17, 18, 19 resin, 20 wires, 21 electronic components, 50 main board.

Claims (11)

複数の半導体チップを搭載し、主基板に電気的に接続される接続部を備えた、プリント配線基板、からなる半導体装置において、
プリント配線基板が、九十九折り状に折り曲げられており、
接続部が、折曲部に設けられており、
折り曲げられてできた各面が、対向して近接しており、且つ、主基板に対して垂直になるように折り曲げた場合に比べ、主基板に接続した時の高さが低くなるように、主基板に対して一方向に傾いていることを特徴とする半導体装置。In a semiconductor device comprising a printed wiring board, which includes a plurality of semiconductor chips and includes a connection portion that is electrically connected to the main board.
The printed wiring board is folded into ninety-nine folds,
The connecting part is provided in the bent part,
Compared to the case where the bent surfaces are close to each other and are bent so as to be perpendicular to the main substrate, the height when connected to the main substrate is reduced. A semiconductor device, wherein the semiconductor device is inclined in one direction with respect to a main substrate. 折り曲げてできた各面が互いに平行に並んでいる、請求項１記載の半導体装置。  2. The semiconductor device according to claim 1, wherein the bent surfaces are arranged in parallel to each other. 接続部が設けられていない折曲部の内、少なくとも１以上の折曲部に、プリント配線基板を主基板に固定するための固定部を備えている、請求項１又は請求項２に記載の半導体装置。The fixing part for fixing a printed wiring board to a main board is provided in the at least 1 or more bending part among the bending parts in which the connection part is not provided, The claim 1 or Claim 2 Semiconductor device . プリント配線基板の少なくとも折り曲げられている箇所が絶縁性のフィルム基板である、請求項１乃至請求項３の何れかに記載の半導体装置。  4. The semiconductor device according to claim 1, wherein at least a bent portion of the printed wiring board is an insulating film substrate. プリント配線基板の両面に配線が施されている、請求項１乃至請求項４の何れかに記載の半導体装置。  The semiconductor device according to claim 1, wherein wiring is provided on both surfaces of the printed wiring board. 近接している面に、それぞれ搭載されている半導体チップが、絶縁シートを介して接している、請求項１乃至請求項５の何れかに記載の半導体装置。  The semiconductor device according to claim 1, wherein the semiconductor chips mounted on the adjacent surfaces are in contact with each other through an insulating sheet. 複数の半導体チップが、プリント配線基板に、ワイヤボンディング方式により搭載されている、請求項１乃至請求項６の何れかに記載の半導体装置。  The semiconductor device according to claim 1, wherein the plurality of semiconductor chips are mounted on the printed wiring board by a wire bonding method. 複数の半導体チップが、プリント配線基板に、フリップチップ方式により搭載されている、請求項１乃至請求項６の何れかに記載の半導体装置。  The semiconductor device according to claim 1, wherein a plurality of semiconductor chips are mounted on a printed wiring board by a flip chip method. 複数の半導体チップが、プリント配線基板に、ワイヤボンディング方式又はフリップチップ方式により搭載されている、請求項１乃至請求項６の何れかに記載の半導体装置。  The semiconductor device according to claim 1, wherein the plurality of semiconductor chips are mounted on the printed wiring board by a wire bonding method or a flip chip method. プリント配線基板が、半導体チップ以外の電子部品も搭載している、請求項１乃至請求項９の何れかに記載の半導体装置。  The semiconductor device according to claim 1, wherein the printed wiring board is mounted with an electronic component other than the semiconductor chip. 請求項１乃至請求項１０の何れかに記載の半導体装置が、接続されている主基板から成っているモジュール。  11. A module comprising the main substrate to which the semiconductor device according to claim 1 is connected.
JP2000084457A 2000-03-24 2000-03-24 Semiconductor device and module mounted with the semiconductor device Expired - Fee Related JP3707987B2 (en)

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