JP3707811B2 - Quantum effect device and manufacturing method thereof - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a quantum effect device using semiconductor quantum wires and quantum dots, and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, there has been an increasing interest in devices that confine electrons in fine lines or dot-like regions having a width of 100 nanometers (nm) or less and control the movement of electrons in the one-dimensional or zero-dimensional regions, so-called quantum effect devices. ing. In such a quantum effect device, a micro structure having the same size as the quantum mechanical wavelength of an electron is formed on a semiconductor substrate to control the wave nature of the electron, the tunnel effect, etc. Can be expected to become more and more multifunctional.
[0003]
Conventionally, microfabrication techniques such as the EB method and the RIE method are used to form quantum wires that confine electrons one-dimensionally and quantum dots that confine zero-dimensionally within a substrate surface. It is not easy to form fine lines or dots with intervals. In the III-V GaAs / AlGaAs system, which has been mainly used as a quantum wire and quantum dot material, a method of combining fine pattern drawing technology such as electron beam exposure and X-ray exposure with dry etching has been used. ing.
[0004]
However, in these methods, pattern transfer is subjected to processes such as exposure, development, etching, and resist stripping, so there is a concern that the controllability of the line width may be reduced. In addition, there is a problem such as substrate damage due to ion bombardment during etching, and a processing technique without an etching process is desired.
[0005]
Therefore, an FIB (Focused Ion Beam) method is cited as a promising candidate. The processing technique using FIB has a feature that a fine pattern can be formed by irradiating the substrate with a high-luminance ion beam, and has attracted attention as a fine pattern processing technique. In particular, a method is known in which FIB is used as ion implantation and a region irradiated with FIB is used as an impurity-doped conductive layer.
[0006]
[Problems to be solved by the invention]
When the quantum potential barrier layer is formed by increasing the resistance by impurity doping using the above-described FIB method, the ion energy is high (usually 20 KeV to 100 KeV), and therefore damage to the substrate is regarded as a problem.
[0007]
In addition, a method is known in which an electric potential layer such as a pn junction is locally formed by impurity doping, and this pn junction is used as a quantum potential barrier. Yes, the electron confinement effect is not sufficient to exhibit the quantum effect.
[0008]
Furthermore, since the height of the quantum potential barrier is gentle in the above method, it is extremely difficult to adjust the thickness and height of the barrier.
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a quantum effect device with high reliability by forming quantum wires and quantum dots on a substrate without damaging the substrate. And
[0009]
Another object of the present invention is to provide a quantum effect device including quantum wires and quantum dots having extremely steep quantum potential barriers.
A further object of the present invention is to provide a method of manufacturing a quantum effect device that is excellent in controllability of the thickness of quantum wires and quantum dots and that can freely control the height and width of a quantum potential barrier.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a quantum effect device according to the present invention provides: A plurality of cell regions having a substrate, a plurality of semiconductor regions selectively formed on the substrate and confining electrons, and a porous semiconductor region made of a porous semiconductor that separates the plurality of semiconductor regions; and A barrier layer that separates a plurality of cell regions and has a wider band gap than the porous semiconductor. Is.
[0012]
Also , The quantum effect device according to the present invention comprises: A plurality of n-type semiconductor regions formed so as to exhibit a quantum effect and a p-type semiconductor that separates the n-type semiconductor regions by doping the first conductivity-type semiconductor layer with a second conductivity-type impurity. A step of forming a superlattice according to a region, a step of converting a p-type semiconductor region into a porous semiconductor region by a selective porous treatment, and a porous oxidation region from a porous semiconductor region by a selective oxidation treatment Forming a semiconductor oxide region, and forming a semiconductor oxide film in an interface region between the n-type semiconductor region and the porous semiconductor oxide region. It is characterized by.
[0013]
More specifically, a region of the pn junction is first patterned to a size exhibiting a quantum effect by doping impurities into a semiconductor layer such as silicon by ion implantation such as FIB. Next, a porous semiconductor layer having a wide band gap is formed as a very fine potential barrier by selectively making the p-type region porous by anodic oxidation or the like. Thereby, a structure in which the n-type region is surrounded by the porous semiconductor layer having a wide band gap can be obtained. That is, a quantum wire or quantum dot structure in which electrons are confined in the n-type region can be formed.
[0014]
In addition, by bringing the quantum wires or quantum dots close to each other to such an extent that a physical interaction occurs, a very small potential barrier can be formed and a surface superlattice structure can be formed.
[0015]
Since the height of the barrier using a porous semiconductor is relatively lower than that of an insulator, the interaction between quantum wires or dots becomes more remarkable, and the surface superlattice characteristics can be observed more easily.
[0016]
Further, by selectively making the p-type region porous and then performing thermal oxidation or the like, the porous semiconductor is first oxidized, and if the oxidation continues, the n-type region in which electrons are confined begins to be oxidized from the interface. Therefore, an n-type region in which electrons are confined, a semiconductor oxide film surrounding the n-type region, and a porous semiconductor oxide film surrounding the semiconductor oxide film are formed. The band gap of the semiconductor oxide film is larger than that of the porous semiconductor oxide film, and forms a steeper quantum potential barrier, which improves the quantum confinement characteristics and makes stable quantum wires or quantum dots resistant to noise. Can be formed.
[0017]
Further, in the thermal oxidation, the semiconductor oxide film thickness can be controlled by adjusting the thermal oxidation time or the like, so that the size of the quantum wires or quantum dots can be controlled to a desired value. Accordingly, the height of the quantum potential barrier can be freely designed, and a quantum effect device having a wide application range can be provided.
[0018]
In this case, the semiconductor substrate refers to a substrate having a semiconductor layer formed at least on its surface, and the entire substrate may be made of a semiconductor material, or a semiconductor film may be formed on the surface of an insulating substrate.
[0019]
Preferred embodiments of the present invention include the following.
(1) As a substrate, a p-type semiconductor substrate or Al ₂ O _Three , SiO ₂ An insulating film substrate such as can be used. In the case of a p-type substrate, an n-type impurity such as P or As is doped by ion implantation, and the n-type region surrounded by the p-type region is drawn in a thin line shape or a dot shape with a size that exhibits a quantum effect. To do. In the case of an insulator substrate, a p-type (n-type) semiconductor layer is directly formed on the insulator substrate by a direct bonding technique or a lamination technique such as MOCVD, and this p-type (n-type) is formed. N-type (p-type) impurities are ion-implanted into the semiconductor layer to pattern fine lines and dots having a size that exhibits a quantum effect.
(2) As a method for patterning quantum wires or quantum dots, any technique that can form a pn junction by impurity doping can be used. Specifically, direct focused ion implantation by the FIB method or the like is preferable, but ion implantation technology by patterning and using a mask can also be used.
[0020]
The ion doping used in the present invention may have a relatively low energy and may be, for example, about 5 KeV to 20 KeV, so that damage to the substrate can be suppressed.
(3) The method for selectively making the p-type semiconductor layer porous can be used without limitation as long as it is a method in which a selective reaction occurs in addition to anodization. Specifically, an anodic oxidation method of electrochemical reaction, dry etching, or the like can be used.
(4) In the technique for forming a barrier layer made of an oxide film, it can be used without limitation as long as the porous semiconductor can be selectively insulated in addition to thermal oxidation. Specifically, wet oxidation etc. are mentioned instead of thermal oxidation. NH instead of oxide film _Three A porous semiconductor can be nitrided in an atmosphere, and a porous nitride film can be used as a barrier layer. CH _Four A porous semiconductor can be carbonized in an atmosphere and a SiC film can be used as a barrier layer.
[0021]
[Action]
A quantum effect device having a steep quantum potential barrier can be provided by forming a quantum wire or a quantum dot array using a porous semiconductor as a quantum potential barrier.
[0022]
Further, in the present invention, since the p region is selectively made porous to obtain a quantum potential barrier, the reduction in line width controllability due to pattern transfer, which is unavoidable with patterning techniques such as resists and masks, is solved. A stress and maskless patterning process can be realized, and the simplification of the process and the controllability of the line width can be greatly improved.
[0023]
Further, since a potential barrier made of an insulating film such as an oxide film formed at the interface between the n region and the porous semiconductor can be formed, a steeper quantum potential barrier can be realized. At this time, since the width of the oxide film can be easily controlled by thermal oxidation, the dimension of the quantum wire or quantum dot can be freely adjusted.
[0024]
【Example】
Embodiments of the present invention will be described below in detail with reference to the drawings.
(Example 1)
FIG. 1 shows a process diagram and a sectional structure diagram of a quantum wire array using porous silicon as a potential barrier according to Example 1 of the present invention. Hereinafter, the manufacturing process will be described with reference to FIG.
[0025]
First, as shown in FIG. 1A, a p-type impurity silicon (p-Si) substrate 1 (volume resistivity 10 cm · Ω) which is surface-treated by standard cleaning of a normal semiconductor wafer is prepared.
[0026]
Next, as shown in FIG. 1 (b), high concentration (10% by FIB ion implantation of low energy (≦ 20 KeV). ²⁰ cm ^-3 ) Is doped with phosphorus (P) impurities to form n-type region fine wires 2 in the p-type region. The beam diameter of the FIB is several nm, and the width of the formed n-type thin wire 2 is also approximately 10 nm. Moreover, the space | interval between a thin wire | line can be changed freely according to the objective.
[0027]
Next, as shown in FIG. 1 (c), the sample was treated with a hydrofluoric acid solution (HF: C ₂ H _Five OH = 2: 3), and photochemical conversion is performed by Xe lamp irradiation (intensity 1 mW).
In this way, the p-type region is selectively etched as an anode and transformed into the porous silicon layer 3 having a wide band gap. At this time, the n-type thin wire 2 is not etched and becomes a quantum wire, and the porous silicon layer 3 functions as a quantum confinement barrier (quantum potential barrier). When the p-type region is sufficiently thin, that is, when the interval between the n-type thin wires 2 is sufficiently small, a surface superlattice structure having a band diagram as shown in FIG. 2 is formed.
[0028]
According to the first embodiment, a quantum wire array with good line width controllability can be realized by a technique that does not use processes such as pattern transfer, exposure, and development. In addition, by forming porous silicon with a very small potential barrier layer, a surface superlattice structure characterized by the interaction between quantum wires can be realized. Since porous silicon is used as the quantum potential barrier, a steep potential barrier can be formed at the interface with the n-type region. For example, quantum effect devices such as quantum wire superlattices, quantum wire FETs, high electron mobility quantum wire devices, and quantum wire light-emitting devices can be formed using the substrate.
[0029]
Further, in this embodiment, since the FIB energy is low, damage to the substrate is small and a good quantum effect can be expected.
(Example 2)
In this example, quantum wires are formed in the same manner as in Example 1, but a substrate in which a semiconductor film is formed on an insulating substrate is used. The steps of this embodiment will be described with reference to FIG.
[0030]
First, as shown in FIG. ₂ O _Three An n-type silicon single crystal layer 5 having a thickness of about 10 nm is laminated on the substrate 4 by a CVD method. The condition at this time is SiH ₂ Cl ₂ Gas was used and the substrate temperature was 300 ° C.
[0031]
Next, as shown in FIG. 3B, boron (B) is doped by FIB ion implantation to form a p-type thin line 5 ′. The beam acceleration voltage was 20 KeV and the beam diameter was 10 nm.
[0032]
At this time, ion implantation is performed so that the width of the thin line 5 ′ in the p-type region and the width of the thin line 6 in the n-type region are both 10 nm.
Next, as shown in FIG. 3C, the p-type region is selectively made porous under the same conditions as in Example 1 to form a porous silicon layer 6 having a wide band gap. Thus, a quantum wire array in which the n-type silicon quantum wires 5 ′ are sandwiched between the porous silicon barriers 6 can be obtained. Since the quantum wire formed in this way can be controlled in the film thickness direction by the CVD method, it is more preferable that it can be controlled three-dimensionally when combined with the controllability in the in-plane direction of the present invention.
(Example 3)
In this embodiment, an array of quantum dots is formed using a process substantially similar to that of the second embodiment. The steps of this embodiment will be described with reference to FIG.
[0033]
First, as shown in FIG. 4A, the CVD method (SiH ₂ Cl ₂ Gas, substrate temperature 300 ° C) ₂ An n-type silicon thin film 8 (film thickness 10 nm) is laminated on the substrate 7.
[0034]
Next, as shown in FIG. 4B, under the same conditions as in Example 2, boron (B) is patterned by FIB ion implantation to form a p-type fine line pattern 9 in a matrix, and n-type dots 9 ′ are formed. Form. At this time, each side and interval of the n-type dot 9 ′ are 10 nm.
[0035]
Next, as shown in FIG. 4C, the p-type region is selectively made porous by anodization under the same conditions as in Example 1 to form a porous silicon layer 10 having a wide band gap.
[0036]
In this manner, a quantum dot array in which the porous silicon layer 10 is formed as a quantum potential barrier in the n-type silicon region 8 ′ is formed.
Here, SiO ₂ Although a substrate is used, an SOI substrate may be used.
(Example 4)
In this example, quantum wires obtained by subjecting the element structure shown in FIG. 3C described in Example 2 to further thermal oxidation were formed.
[0037]
First, the substrate shown in FIG. ₂ And N ₂ Mixed gas (O ₂ : 11 ml / min, N ₂ : 50 ml / min, 900 ° C., 10 minutes). Thereby, the porous silicon is selectively oxidized to form the porous silicon oxide layer 11, and at the same time, an extremely thin crystalline silicon oxide film 12 is formed at the interface between the n-type silicon layer and the porous oxide film. This crystalline silicon oxide film 12 is obtained by oxidizing a part of the n-type silicon layer 5, has a dense and stable structure, and the potential barrier layer formed thereby becomes more ideal. In this way, the material of the potential barrier is changed by oxidation, and a double barrier structure of a quantum wire 5 made of n-type crystalline silicon, a barrier layer 12 made of a crystalline silicon oxide film, and a barrier layer 11 made of a porous silicon oxide film in the plane. Quantum wires can be formed.
[0038]
The quantum wire structure thus obtained has a quantum potential barrier layer composed of a porous silicon oxide film and SiO 2 ₂ The double barrier structure of SiO ₂ As a result, interface characteristics are improved, carrier trapping and the like can be prevented, and stable element characteristics can be expected. The quantum wire substrate formed by this method is suitable for device applications such as a silicon ULSI integrated circuit because a flat structure can facilitate post-processes such as formation of an insulating film and formation of electrodes.
[0039]
The film thickness of the crystalline silicon oxide film 12 can be freely controlled by the thermal oxidation time, and a quantum effect device having a desired energy level can be provided. Further, since the quantum wire can be made thinner and thinner by the oxidation time, an ultimate fine structure that cannot be obtained by a mask process or a normal ion doping process can be formed.
(Example 5)
In this example, quantum dots obtained by subjecting the element structure shown in FIG. 4C described in Example 3 to further thermal oxidation were formed.
[0040]
The substrate shown in FIG. 4C is subjected to thermal oxidation under the same conditions as in Example 4 to form the quantum dot array shown in FIG. As a result, a porous silicon oxide layer 13 in which porous silicon is selectively oxidized is formed, and at the same time, an extremely thin crystalline silicon oxide film 14 is formed at the interface between the n-type crystalline silicon layer and the porous silicon oxide layer. Is done. In this way, a quantum dot having a double barrier structure of the quantum dot 5 made of n-type silicon, the barrier layer 14 made of a crystalline silicon oxide film, and the barrier layer 13 made of a porous silicon oxide film can be formed in the plane. .
[0041]
The quantum wire structure thus obtained is also characterized by a stable structure as in the fourth embodiment.
The size of the quantum dots can be further reduced by the oxide film, and the wavelength can be further shortened optically.
(Example 6)
In this example, quantum dots surrounded by potential barriers of different sizes will be described.
[0042]
First, the surface is oxidized and insulated ₂ An n-type silicon thin film is formed on the substrate 15 under the same conditions as in the second embodiment. Next, as shown in FIG. 7A, oxidation treatment is performed using a mask to form an n-type silicon region 17 and a silicon oxide film 16 on the substrate. As oxidation conditions, the substrate temperature is 1000 ° C., N ₂ 50 ml / min, O ₂ It was 5 hours in a 1 l / min atmosphere. An SOI substrate can also be used as the substrate.
[0043]
Next, as shown in FIG. 7B, the n-type silicon region 17 is doped with p-type impurities (B) using FIB under the same conditions as in the second embodiment, and the n-type quantum dots 18 and the p-type are doped. Region 19 is formed.
[0044]
Next, as shown in FIG. 7C, anodization is performed under the same conditions as in Example 1, and the p-type region 17 is selectively made porous to form a porous silicon layer 18.
In this way, the n-type quantum dot region 18 has a quantum dot structure surrounded by the barrier layer 19 made of porous silicon and the barrier layer 16 made of a silicon oxide film having a wider band gap than the porous silicon. .
[0045]
In FIG. 7C, when a portion 20 in which four quantum dots 18 are surrounded by a silicon oxide layer is used as a unit of one cell, between quantum dots separated by the porous silicon layer 19 in the cell 20, Electrons can move by the tunnel effect because of the relatively low potential barrier layer 19 made of porous silicon, but the tunnel effect does not occur because the electrons are moved between different cells because of the relatively high potential barrier layer 16 made of silicon oxide. There is no movement.
[0046]
On the other hand, electrons do not move due to the tunnel effect between different cells, but electrons are interacted by Coulomb interaction. By forming potential barriers of different sizes on the substrate in this way, a quantum effect device called a so-called QIC (Quantum Interconnecti-ons with Cellular architecture) can be formed.
[0047]
The element structure shown in FIGS. 8, 9, and 10 can be formed by the same process as in this embodiment. In addition, the same code | symbol is attached | subjected to the same part and the description is abbreviate | omitted.
When electrons are doped into the cells arranged in this way, the electrons are present at the positions indicated by the black dots shown in the figure. By combining these, it is possible to form quantum wires and logic circuits.
(Example 7)
In this example, a quantum light emitting element was formed using the quantum wire described in Example 1.
[0048]
FIG. 11 is a conceptual diagram of a light emitting device according to this example.
An Al electrode 21 is formed by vapor deposition on the lower surface of the substrate shown in FIG. 1C, and a transparent electrode 22 made of ITO or the like is formed on the upper surface. The quantum light emitting device thus obtained emits light by a heterojunction between the transparent electrode 22 and Si.
[0049]
Since a quantum wire of about 10 nm exhibits light emission characteristics due to the quantum effect, a silicon-based light-emitting element can be formed by applying a negative voltage to the Al electrode 21 and applying a positive voltage to the transparent electrode 22.
[0050]
Such a quantum light emitting device can be applied not only in the first embodiment but also in the second to fifth embodiments.
(Example 8)
In this example, a resonant tunneling effect device was formed using the quantum wire described in Example 1.
[0051]
FIG. 12 is a conceptual diagram of a resonant tunneling effect device using multiple quantum wires according to this embodiment.
Al electrodes 23 and 24 are vapor-deposited in a direction parallel to the quantum wires 2 of the substrate shown in FIG. 1C, and an ohmic contact is formed between the substrate and the electrodes. Thus, a mini-band is formed between multiple quantum wells formed by multiple quantum wires, and a one-dimensional resonance tunnel effect between the quantum wires 2 can be realized by applying a voltage between the electrodes 23 and 24.
[0052]
Such a quantum light emitting device can be applied not only in the first embodiment but also in the second to fifth embodiments.
Example 9
In this example, a quantum coupled field effect transistor was formed using the quantum wire described in Example 2.
[0053]
FIG. 13 is a conceptual diagram of a quantum coupled field effect transistor according to this example.
A source electrode 25 and a drain electrode 26 are formed by vapor-depositing Al on both ends of the quantum wire 5 ′ of the substrate shown in FIG.
[0054]
Next, the gate electrode 27 is formed by vapor-depositing Al on the quantum wire 5 ′. By applying a gate voltage to the quantum-coupled field effect transistor thus formed, the current between the source and drain can be controlled, and the quantum effect is observed in the IV characteristics.
[0055]
Such a quantum coupled field effect transistor can be applied not only in the second embodiment but also in the first and fourth embodiments.
(Example 10)
In this embodiment, a quantum MOSFET is formed in which an insulating film is interposed between the gate electrode 27 and the substrate in the transistor shown in the ninth embodiment.
[0056]
FIG. 14 is a conceptual diagram of a quantum MOSFET according to this embodiment.
A source electrode 25 and a drain electrode 26 are formed by vapor-depositing Al on both ends of the quantum wire 5 ′ of the substrate shown in FIG.
[0057]
Next, an SiO insulating film 28 is formed on this substrate by resistance vapor deposition.
Next, an Al electrode is formed as a gate electrode 27 on the SiO insulating film by vapor deposition. By applying a gate voltage to the quantum MOSFET thus formed, the current between the source and drain can be controlled, and a quantum effect is observed in the IV characteristic.
[0058]
Such a quantum MOSFET can be applied not only in the second embodiment but also in the first and fourth embodiments.
(Example 11)
In this example, a SET (Single Electron Tunneling) quantum effect device using silicon quantum dots was formed.
[0059]
FIG. 15 is a diagram for explaining a method of manufacturing a SET quantum effect device according to this embodiment.
First, as shown in FIG. ₂ O _Three An n-type silicon single crystal having a thickness of about 10 nm is formed on the substrate 4 by the CVD method under the same conditions as in the second embodiment, and p-type region 30 is formed by doping boron (B) by FIB ion implantation. An n-type quantum wire 31 is formed.
[0060]
Next, as shown in FIG. 15B, the p-type region 30 is selectively anodized under the same conditions as in Example 1 to form a porous silicon layer. The porous silicon layer thus formed is selectively thermally oxidized under the same conditions as in Example 4 to form a porous silicon oxide film 32.
[0061]
Next, as shown in FIG. 15C, the porous silicon oxide film 32 is selectively removed with a hydrofluoric acid solution to form an n-type silicon quantum wire 32 ′.
The selective etching is performed by using a 1:10 diluted hydrofluoric acid solution of hydrofluoric acid (HF 49%) for 2 seconds.
[0062]
Next, as shown in FIG. 15 (d), a potential barrier of porous silicon is formed by forming a p-type fine wire on the n-type silicon quantum wire 5 'by FIB under the same conditions as in Example 1 and performing anodization. Layer 33 (film thickness 3-5 nm) is formed. The n-type silicon region that is not simultaneously formed becomes the quantum dot 34. A SET quantum effect device can be formed by attaching a power source as shown in FIG. 15E to the SET1D array using the porous silicon formed as a barrier.
[0063]
Further, by subjecting the above element to further thermal oxidation, the interface of the quantum dots is made SiO 2 ₂ It is also possible to form a SET1D array using as a barrier layer.
(Example 12)
In this example, a zero-dimensional surface-emitting quantum dot array was formed using the quantum dots shown in FIG.
[0064]
FIG. 16 is a conceptual diagram of a zero-dimensional surface-emitting quantum dot array according to this example.
From the quantum dot array shown in FIG. 6, the porous silicon oxide layer 13 was removed with a hydrofluoric acid solution to form silicon zero-dimensional quantum dots 35.
[0065]
The size of the quantum dot is 10 nm or less and N ₂ When a laser (λ = 337 nm) is incident, photoluminescence in the visible light region can be obtained.
Such an element exhibits photoluminescence in all surface directions by photoexcitation. In this way, a zero-dimensional surface emitting quantum dot array can be formed.
[0066]
【The invention's effect】
INDUSTRIAL APPLICABILITY The present invention can provide a quantum effect device having a very fine quantum wire or quantum dot array and a method for manufacturing the same by utilizing selective anodization and wide gap characteristics of a porous semiconductor. In addition, since the quantum height of the present invention uses a porous semiconductor as a quantum potential barrier, the device has a very steep potential barrier. Also, a double barrier structure in which a quantum wire or dot of a substrate is surrounded by a quantum potential barrier made of an oxide film and a quantum potential barrier made of a porous conductive oxide film by selectively oxidizing the porous semiconductor layer is provided. Therefore, stable and dense quantum wires and quantum dots can be provided. Furthermore, since different barriers can be simultaneously produced in the plane, the tunneling probability can be controlled by different barrier heights, and a quantum effect device having a wide range of applications based on silicon can be provided.
[Brief description of the drawings]
FIG. 1 is a process diagram and schematic diagram of a quantum wire array according to Embodiment 1 of the present invention.
FIG. 2 is a band diagram of a surface superlattice according to Example 1 of the present invention.
FIG. 3 is a process diagram and schematic diagram of a quantum wire array according to Embodiment 2 of the present invention.
FIG. 4 is a process diagram and schematic diagram of a quantum dot array according to Example 3 of the present invention.
FIG. 5 is a schematic diagram of a quantum wire array in a planar direction according to a fourth embodiment of the present invention.
FIG. 6 is a schematic diagram of a quantum dot array according to Example 5 of the present invention.
FIGS. 7A and 7B are a process diagram and a schematic diagram of an element structure for simultaneously producing different potential barriers according to Example 6 of the invention. FIGS.
FIG. 8 is a schematic view of an element structure having different potential barriers according to Example 6 of the present invention.
FIG. 9 is a schematic view of an element structure having different potential barriers according to Example 6 of the present invention.
FIG. 10 is a schematic view of an element structure having different potential barriers according to Example 6 of the present invention.
FIG. 11 is a schematic diagram of a quantum light-emitting device according to Example 7 of the present invention.
FIG. 12 is a schematic view of a resonant tunneling effect device according to Embodiment 8 of the present invention.
FIG. 13 is a schematic diagram of a quantum coupled field effect transistor according to Example 9 of the invention.
14 is a schematic diagram of a quantum MOSFET according to Example 10 of the present invention. FIG.
FIG. 15 is a process diagram and schematic diagram of SET using silicon quantum dots according to Example 11 of the present invention.
FIG. 16 is a schematic view of a zero-dimensional surface-emitting quantum dot array according to Example 12 of the present invention.
[Explanation of symbols]
1 ... Semiconductor substrate
2 ... n-type thin wire region
3 ... Porous semiconductor layer
4 ... Insulator substrate
5 ... Semiconductor thin film
6 ... p-type thin wire region
8 '... n-type quantum dots
9 ... p-type semiconductor region
10: Porous semiconductor region

Claims (6)

A substrate,
A plurality of cell regions selectively formed on the substrate and having a plurality of semiconductor regions for confining electrons and a porous semiconductor region made of a porous semiconductor for separating the plurality of semiconductor regions;
Separating the plurality of cell regions, a barrier layer having a wider band gap than the porous semiconductor ,
A quantum effect device comprising: Electrons can move between the plurality of semiconductor regions separated by the porous semiconductor region by a tunnel effect,
2. The quantum effect device according to claim 1, wherein there is no movement of electrons due to a tunnel effect between the plurality of cell regions. The quantum effect device according to claim 1, wherein the semiconductor region is n-type. The quantum effect device according to claim 1, wherein the barrier layer is made of silicon oxide. A plurality of n-type semiconductor regions formed so as to exhibit a quantum effect and a p-type semiconductor that separates the n-type semiconductor regions by doping the first conductivity-type semiconductor layer with a second conductivity-type impurity. Forming a superlattice from the region;
Converting the p-type semiconductor region into a porous semiconductor region by selective porosification treatment;
Forming the porous semiconductor oxide region from the porous semiconductor region by selective oxidation treatment, and forming a semiconductor oxide film in an interface region of the n-type semiconductor region with the porous semiconductor oxide region; ,
A method of manufacturing a quantum effect device comprising: 6. The method of manufacturing a quantum effect device according to claim 5, further comprising the step of forming the first conductivity type semiconductor layer on an insulator substrate.

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