JP3697949B2 - Communication device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a communication technique, and more particularly, to a communication technique for synchronizing a plurality of communication apparatuses.
[0002]
[Prior art]
IEEE 1394 standard digital serial communication is spreading. In the IEEE 1394 standard, a network can be configured by connecting a plurality of communication nodes. For example, one receiving node can receive audio data from multiple transmitting nodes.
[0003]
Assume that the first and second transmitting nodes transmit data to one receiving node at the same time. In this case, the time at which the receiving node receives from the first transmitting node and the time from the second transmitting node are usually different due to the difference in distance between the nodes. For example, data is received from a first transmission node and then data is received from a second transmission node.
[0004]
Each of the transmitting node and the receiving node has its own cycle timer. Each cycle timer is not synchronized. It is difficult for the receiving node to synchronize the data received from the first transmitting node and the data received from the second transmitting node.
[0005]
In addition, one transmitting node may transmit the same data to the first and second receiving nodes almost simultaneously. However, as described above, normally, the time received by the first receiving node is different from the time received by the second receiving node. Since the first and second receiving nodes reproduce the received data according to their own cycle timers, the reproduction processing of the first and second receiving nodes is likely to be shifted.
[0006]
[Problems to be solved by the invention]
It is difficult for the receiving node to synchronize data transmitted from a plurality of transmitting nodes. Further, when the transmitting node transmits data to a plurality of receiving nodes, it is difficult to synchronize between the plurality of receiving nodes.
[0007]
An object of the present invention is to provide a communication device capable of synchronizing data communicated between a plurality of communication nodes.
[0008]
[Means for Solving the Problems]
According to an aspect of the present invention, a communication device forming one of a plurality of nodes connected to a network generates a time value synchronized with a time value output from a root node connected to the network. A cycle timer, sample count generation means for generating a count value for counting samples of audio data, and a synchronization time value for generating a synchronization time value in which a maximum delay amount is added to a time value corresponding to the synchronized time value Generating means; and a synchronization packet output means for generating a synchronization packet including the sample count value and the synchronization time value at a predetermined time interval and outputting the generated synchronization packet to the network.
[0009]
According to another aspect of the present invention, a communication device forming one of a plurality of nodes connected to a network has a time value synchronized with a time value output by a route node connected to the network. A clock timer for generating a word clock based on the synchronized time value and the received synchronization information, a receiving unit for receiving synchronization information from a word clock node connected to the network, and a clock generator for generating a word clock based on the synchronized time value and the received synchronization information Data sample supply means for sequentially supplying audio data samples based on the word clock; sample count supply means for supplying audio data sample count values based on the synchronization information; and maximum transfer delay to the count values Synchronous count generating means for generating a synchronous count value taking the amount into account, Communication apparatus having a transmitting means for transmitting to the receiving node to generate a data packet, which is connected generated data packet to the network including the supplied plurality of samples and the synchronization count.
[0010]
According to still another aspect of the present invention, a communication device forming one of a plurality of nodes connected to a network is synchronized with a time value output by a root node connected to the network. A cycle timer for generating a value, receiving means for receiving synchronization information from a word clock node connected to the network, and clock generation for generating a word clock based on the synchronized time value and the received synchronization information Means, data sample supply means for sequentially supplying audio data samples based on the word clock, and a synchronization time value generation means for generating a synchronization time value in which a maximum transfer delay amount is added to the synchronized time value. Generating a data packet including the supplied plurality of samples and the synchronization time value; And a transmitting means for transmitting a packet to the connected receiving node to the network.
[0011]
According to still another aspect of the present invention, a communication device forming one of a plurality of nodes connected to a network is synchronized with a time value output by a root node connected to the network. A cycle timer for generating a value, synchronization information receiving means for receiving synchronization information from a word clock node connected to the network, and generating a word clock based on the synchronized time value and the received synchronization information Clock generation means, data reception means for receiving a data packet including a plurality of samples and a synchronization count value associated with the plurality of samples from a transmission node connected to the network, the synchronization information and the synchronization count value And a plurality of samples included in the data packet at the timing based on And a sample output means for sequentially output one sample in accordance with the click.
[0012]
According to still another aspect of the present invention, a communication device forming one of a plurality of nodes connected to a network has a communication arrival delay time from a root node connected to the network to the communication device. Measuring means for measuring, a determining means for determining a correction value according to the arrival delay time measured by the measuring means, a time value receiving means for receiving the time value output by the root node, and the received time value Correction means for correcting according to the correction value, a cycle timer for generating a time value synchronized based on the corrected time value, and synchronization information for receiving synchronization information from a word clock node connected to the network Receiving means; and clock generating means for generating a word clock based on the synchronized time value and the received synchronization information
According to still another aspect of the present invention, a communication device forming one of a plurality of nodes connected to a network is synchronized with a time value output by a root node connected to the network. A cycle timer for generating a value, a measuring means for measuring an arrival delay time of communication from the root node to the communication device, a determining means for determining a correction value according to the arrival delay time measured by the measuring means, Synchronization information receiving means for receiving synchronization information from a word clock node connected to the network, correction means for correcting the received synchronization information according to the correction value, the synchronized time value and the corrected Clock generating means for generating a word clock based on the synchronization information.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing the configuration of a communication network according to the first embodiment of the present invention.
In this embodiment, it is possible to transfer packets in accordance with the “audio and music data transmission protocol” compliant with the IEEE 1394 standard. The packet transfer is preferably performed by the IEEE 1394 standard isochronous packet transfer.
[0014]
A word clock (WC) master node 1 and WC slave nodes 2 and 3 are connected to the IEEE 1394 bus 4. The WC slave node 2 is a transmission node (hereinafter referred to as a Tx node), and the WC slave node 3 is a reception node (hereinafter referred to as an Rx node). A plurality of Tx nodes 2 and / or a plurality of Rx nodes 3 may be connected to the bus 4.
[0015]
The WC master node 1 has a cycle timer 1a, the Tx node 2 has a cycle timer 2a, and the Rx node 3 has a cycle timer 3a. The cycle timers 1a, 2a and 3a are basically counters operating at about 25 MHz.
[0016]
The WC master node 1 transmits the WC packet 5 to the Tx node 2 and the Rx node 3 via the bus 4. The WC packet 5 is a packet for synchronization, and includes a system time 5a and a sample count 5b.
[0017]
The WC master node 1 sequentially transmits, for example, WC packets 5-24, 5-32, 5-40, and the like at predetermined intervals. The WC packet 5-24 is a packet for synchronizing the audio data of the 24th sample. The WC packets 5-32 and 5-40 are packets for synchronizing the audio data of the 32nd sample and the 40th sample, respectively.
[0018]
The Tx node 2 adjusts the timing according to the WC packet 5 received from the WC master node 1 and transmits the data packet 6 to the Rx node 3 via the bus 4. The data packet 6 includes a DBC 6a indicating a sample count and eight sample data 6b.
[0019]
The Tx node 2 sequentially transmits, for example, data packets 6-24, 6-32, 6-40 and the like to the Rx node 3 at predetermined intervals. The data packet 6-24 includes audio data 6b of 24th to 31st samples. The data packets 6-32 and 6-40 include audio data 6b of 32nd to 39th samples and 40th to 47th samples, respectively.
[0020]
The Rx node 3 adjusts timing according to the WC packet 5 received from the WC master node 1 and reproduces sample data (for example, audio data) 6b in the data packet 6 received from the Tx node 2.
[0021]
FIG. 2 is a timing chart for explaining the operation of the Tx node 2.
[0022]
First, a method for generating the data packet 6-24 (FIG. 1) will be described. The Tx node 2 generates eight data from the 24th sample data D24 to the 31st sample data D31 as one data packet 6b. The interval SYT_INTERVAL is a cycle for generating a packet.
[0023]
The cycle timer 2a increases the 32-bit cycle time value as time passes. Here, the cycle times of the 24th, 32nd, and 40th sample data D24, D32, D40 are CT24, CT32, and CT40, respectively.
[0024]
The system times SYT24, SYT32, and SYT40 are values of lower 16 bits of the cycle times CT24, CT32, and CT40, respectively.
[0025]
DBC 6a indicates the sample count. For example, since the head data of the data packet 6b is the 24th sample data D24, the value of the DBC 6a corresponding to the data packet 6b is 24.
[0026]
The data packet 6 (FIG. 1) includes a DBC 6a and a data packet 6b. The system time SYT24 may be included instead of the DBC 6a. As described above, the system time SYT24 indicates the timing of the first sample data D24 of the data packet 6b.
[0027]
The data packet 6-32 (FIG. 1) can also be generated in the same manner as described above. The Tx node 2 generates eight pieces of data from the 32nd sample data D32 to the 39th sample data D39 as one data packet 6b. Since the head data of the data packet 6b is the 32nd sample data D32, the value of the DBC 6a corresponding to the data packet 6b is 32. System time SYT32 may be used instead of DBC 6a.
The above DBC and system time (SYT) are the same as those defined in “audio and music data transmission protocol” conforming to the IEEE 1394 standard, and are included in the CIP header for isochronous packet transfer. Yes. DBC is 8 bits and SYT is 16 bits.
[0028]
FIG. 3 is a timing chart showing the operation between the nodes in FIG.
[0029]
The WC master node 1 sequentially transmits WC packets 5-24, 5-32, 5-40 and the like indicating the timing of the sample data 24, 32, 40, etc. to the Tx node 2 and the Rx node 3. The transmission interval of the WC packet 5 is an interval SYT_INTERVAL (see FIG. 2).
[0030]
The maximum communication time until the WC packet 5 reaches the Tx node 2 or the Rx node 3 from the WC master node 1 is SYT_OFFSET. The time SYT_OFFSET is a maximum delay time (transfer delay) determined by the IEEE 1394 standard, and is 352 μs. That is, when a packet is transmitted from one node to another, it is guaranteed that the packet will arrive within 352 μs at the latest.
[0031]
The WC packet 5 includes a maximum delay time SYT_OFFSET. That is, the WC packet 5-24 includes a sample count 5b indicating the 24th sample count, and a system time WC_SYT24 obtained by adding the maximum delay time SYT_OFFSET to the corresponding system time SYT24 (FIG. 2). System time WC_SYT24 = SYT24 + SYT_OFFSET. Similarly, the maximum delay time SYT_OFFSET is added to the WC packets 5-32 and 5-40.
[0032]
The vertical axis of the WC master node 1 in FIG. 3 indicates the value of the sample count 5b in the WC packet 5 transmitted by itself. Each vertical axis of the Tx node 2 and the Rx node 3 indicates the value of the sample count 5 b in the WC packet 5 received from the WC master node 1. The three nodes 1, 2, and 3 perform processing based on the sample count axis. The sample count axis corresponds to the time axis. The axes of the three nodes are different in absolute time but in the same relative time. The Tx node 2 and the Rx node 3 can be synchronized based on their sample count axes.
[0033]
For example, the WC master node 1 transmits a WC packet 5-32 to the Tx node 2 and the Rx node 3. The WC packet 5-32 includes a sample count 5b indicating the thirty-second sample count, and a system time WC_SYT32 obtained by adding the maximum delay time SYT_OFFSET (352 μs) to the system time SYT32 corresponding thereto.
[0034]
Upon receipt of the WC packet 5-32, the Tx node 2 transmits a data packet 6-49 including 49th (= 32 + 17) sample data obtained by adding an offset value SAMPLE_OFFSET (for example, 17 samples) to the 32nd sample count. . In the data packet 6-49, the DBC 6a is 49, and the sample data 6b is the 49th to 56th sample data.
[0035]
The addition of the offset value SAMPLE_OFFSET (for example, 17 samples) considers the maximum communication delay time of the data packet 6 from the Tx node 2 to the Rx node 3, and indicates that the sample data of 17 samples ahead is transmitted. means. That is, if the sample count 5b in the WC packet 5 is 32, the Tx node 2 transmits a data packet 6-49 having the sample data of the sample count value obtained by adding 17 samples to the value.
[0036]
It will be explained that the maximum communication delay time corresponds to 17 samples. As described above, the maximum communication delay time SYT_OFFSET is 352 μs. The sampling frequency of audio data is 48 kHz, for example.
[0037]
In this case, the number of samples is 48 kHz × 352 μs = 16.896. Therefore, the sample offset value must be greater than or equal to 16.896 samples. The sample offset value is preferably 17 samples as the smallest integer.
[0038]
The Rx node 3 has already received the data packet 6-49 from the Tx node 2 when the sample count is 49 at the latest. The total delay time of the above communication is T1 + T2. The delay time T1 is a communication time of the WC packet 5-32 from the WC master node 1 to the Tx node 2. The delay time T2 is a communication time of the data packet 6-49 from the Tx node 2 to the Rx node 3.
[0039]
The Rx node 3 stores the received data packet 6-49 in a first-in first-out buffer (FIFO). When the sample count reaches 49, the Rx node 3 starts reproduction processing of the data packet 6-49. The delay time T1 + T2 can be absorbed by storing the packet in the FIFO and waiting for processing until the sample count reaches 49.
[0040]
As described above, the WC packet 5-32 includes the system time WC_SYT32 in which the maximum delay time SYT_OFFSET is offset. The maximum delay time SYT_OFFSET is an offset value for absorbing the communication delay time T1.
[0041]
If the WC packet 5-32 is transmitted without offsetting the system time offset value SYT_OFFSET, when the Rx node 3 receives the WC packet 5-32, the system time corresponding to the sample count of 32 has already passed. It becomes impossible to process.
[0042]
The data packet 6-49 includes the DBC 6a to which the sample count offset value SAMPLE_OFFSET is offset. This offset value SAMPLE_OFFSET is an offset value for absorbing the communication delay time T2.
[0043]
If the data packet 6-32 is transmitted without offsetting the sample count offset value SAMPLE_OFFSET, when the Rx node 3 receives the data packet 6-32, the sample count of 32 has already passed and can be processed. It will disappear.
[0044]
FIG. 4 is a flowchart showing processing of the WC master node 1.
[0045]
In step SA1, a constant SYT_INTERVAL is added to the register sample count. The register sample count is a register for storing a count value of the number of samples of audio data. The constant SYT_INTERVAL is the number of samples in one packet, for example, 8. This register sample count corresponds to the sample count 5b in the WC packet 5 of FIG.
[0046]
Next, a value obtained by adding the offset value SYT_OFFSET to the system time SYT (FIG. 2) is stored in the register syt. The system time SYT is, for example, SYT 24 in FIG. The offset value SYT_OFFSET is a maximum delay time and is, for example, 352 μs. By adding the offset value SYT_OFFSET, the delay time T1 shown in FIG. 3 can be absorbed. This register syt corresponds to the system time 5a in the WC packet 5 of FIG.
[0047]
In step SA2, as shown in FIG. 1, the register sample count is set to the sample count 5b, the register syt is set to the system time 5a, and the WC packet 5 is generated and transmitted onto the bus 4.
[0048]
The above has shown the generation processing of one packet, but the WC master node 1 repeats the above processing at predetermined time intervals, and sequentially sends out, for example, WC packets 5-24, 5-32, 5-40, and the like.
[0049]
In the WC packet 5-24, the system time 5a is WC_SYT24 (= SYT24 + SYT_OFFSET), and the sample count 5b is 24. In the WC packet 5-32, the system time 5a is WC_SYT32 (= SYT32 + SYT_OFFSET), and the sample count 5b is 32.
[0050]
FIG. 5 is a block diagram illustrating a configuration example of the first Tx node 2.
[0051]
The Tx node 2 includes an IEEE 1394 interface system 11 and a node system 12.
[0052]
The WC packet 5 includes a system time 5a and a sample count 5b, and is a packet received from the WC master node 1. The sample count FIFO 13 stores the sample count 5b first in first out. The system time FIFO 14 stores the system time 5a in first-in first-out.
[0053]
The system time comparator 15 compares the system time 5a output from the FIFO 14 with the lower 16 bits of the cycle time output from the cycle timer 2a. The cycle time is 32 bits. The system time 5 a is a value obtained by adding the maximum delay time SYT_OFFSET (352 μs) to the lower 16 bits of the cycle time of the WC master node 1.
[0054]
Since the system time 5a is added by the maximum delay time SYT_OFFSET, it is longer than the cycle time of the cycle timer 2a. The cycle timer 2a sequentially increments the cycle time at about 25 MHz.
[0055]
Eventually, the cycle time and the system time 5a coincide. When the two match, the comparator 15 outputs a match signal. Processing shown later is awaited until the coincidence signal is output. By waiting for subsequent processing, the communication delay time T1 (FIG. 3) from the WC master node 1 to the Tx node 2 can be absorbed. When the WC packet 5 is transmitted from the WC master node 1 to the plurality of Tx nodes 2, the difference in the reception time of each Tx node 2 can be absorbed.
[0056]
The phase phase lock loop circuit (PLL) 16 generates an audio word clock WCK of 48 kHz, for example, in synchronization with the coincidence signal, and supplies it to the node system 12.
[0057]
The timing adjuster 17 outputs the sample count 5b in the FIFO 13 to the adder 18 when receiving the coincidence signal. The adder 18 adds an offset value SAMPLE_OFFSET (for example, 17 samples) to the sample count 5b, and outputs a sample count SCN. For example, when the sample count 5b is 32, the adder 18 outputs a sample count SCN = 32 + 17 = 49. By adding the offset value, preparation for absorbing the communication delay time T2 (FIG. 3) from the Tx node 2 to the Rx node 3 is completed. Absorption of the communication delay time T2 is performed at the Rx node 3 (FIG. 7) described later.
[0058]
In synchronization with the word clock WCK, the node system 12 reads eight sample data (for example, the 49th to 56th sample data) as data SDT in accordance with the sample count SCN (for example, 49), and first loads the data into the data FIFO 19. Store in-first-out.
[0059]
The DBC generator 20 generates a DBC according to the sample count SCN in synchronization with the word clock WCK.
[0060]
The DBC 6a is generated by the DBC generator 20. The sample data 6b is generated based on the sample data SDT in the FIFO 19.
[0061]
Data packet 6 is generated by packetizing DBC 6a and sample data 6b. The data packet 6 is transmitted from the Tx node 2 to the Rx node 3.
[0062]
The adder 18 is not limited to the case where the value SCN obtained by adding the offset value SAMPLE_OFFSET to the sample count 5b is supplied to the node system 12, and the sample count 5b may be directly supplied. In that case, the node system 12 needs to perform processing in consideration of the offset value SAMPLE_OFFSET.
[0063]
The sample count SCN is not limited to being supplied to the node system 12 every packet, but may be supplied every sample.
[0064]
FIG. 6 is a flowchart showing processing of the Tx node 2. The processes SB1 to SB8 on the left side of the flowchart indicate the process of the interface system 11, and the process SB9 on the right side indicates the process of the node system 12.
[0065]
In step SB1, the system time 5a and sample count 5b in the WC packet 5 are stored in the FIFOs 14 and 13, respectively.
[0066]
In step SB2, the comparator 15 compares the system time with the cycle time, and waits until they match. If they match, the process proceeds to step SB3.
[0067]
In step SB3, the next system time stored in the FIFO 14 is loaded into the comparator 15 to prepare for the next comparison.
[0068]
In step SB4, the PLL 16 generates a word clock WCK.
[0069]
In step SB5, the adder 18 adds the sample count 5b and the offset value SAMPLE_OFFSET, and outputs the added value SCN to the node system 12.
[0070]
Next, the interface system 11 processes step SB6, and the node system 12 processes step SB9.
[0071]
In step SB6, DBC is generated based on the generated sample count SCN. If necessary, the generated DBC is stored in the FIFO. Next, the process proceeds to step SB7.
[0072]
In step SB9, sample data SDT corresponding to the input sample count CNT is supplied to the interface system 11. Next, the process proceeds to step SB7.
[0073]
In step SB7, sample data SDT is received from the node system 12 described above.
[0074]
In step SB8, the sample data SDT and DBC are packetized, and the data packet 6 is sent to the Rx node 3.
[0075]
FIG. 7 is a block diagram illustrating a configuration example of the first Rx node 3.
[0076]
The Rx node 3 includes an IEEE 1394 interface system 31 and a node system 32.
[0077]
The WC packet 5 includes a system time 5a and a sample count 5b, and is a packet received from the WC master node 1. The sample count FIFO 33 stores the sample count 5b first in first out. The system time FIFO 34 stores the system time 5a first-in first-out.
[0078]
The system time comparator 35 compares the system time 5a output from the FIFO 34 with the lower 16 bits of the cycle time output from the cycle timer 3a. The system time 5a is a value obtained by adding the maximum delay time SYT_OFFSET (325 μs) to the lower 16 bits of the cycle time of the WC master node 1.
[0079]
When the cycle time and the system time 5a coincide, the comparator 35 outputs a coincidence signal. Processing shown later is awaited until the coincidence signal is output. By waiting for later processing, the communication delay time from the WC master node 1 to the Rx node 3 can be absorbed. When the WC packet 5 is transmitted from the WC master node 1 to a plurality of Rx nodes 3, differences in reception times of the Rx nodes 3 can be absorbed.
[0080]
The PLL 36 generates an audio word clock WCK of 48 kHz, for example, in synchronization with the coincidence signal and supplies it to the node system 32.
[0081]
When receiving the coincidence signal, the timing adjuster 37 supplies the sample count 5b in the FIFO 33 to the node system 32 as the sample count SCN.
[0082]
The data packet 6 includes a DBC 6a and sample data 6b, and is a packet received from the Tx node 2. The DBC-FIFO 40 stores the DBC 6a first-in first-out. The data FIFO 39 stores the sample data 6b first in first out.
[0083]
The DBC comparator 38 compares the sample count 5b output from the FIFO 33 with the DBC 6a output from the FIFO 40. The DBC 6a is a value obtained by adding an offset value SAMPLE_OFFSET (for example, 17) to the sample count 5b by the adder 18 of the Tx node 2 in FIG.
[0084]
Since the offset value is added to the DBC 6a, the DBC 6a is larger than the sample count 5b of the FIFO 33. The FIFO 33 outputs the value of the input sample count 5b, and then outputs a value obtained by sequentially incrementing the sample count.
[0085]
Eventually, the DBC and sample count will match. When the two match, the comparator 38 outputs a match signal. Until the coincidence signal is output, the data reading process in the data FIFO 39 is awaited. By waiting for the reading process, the communication delay time T2 (FIG. 3) from the Tx node 2 to the Rx node 3 can be absorbed. When the data packet 6 is transmitted from the Tx node 2 to the plurality of Rx nodes 3, the difference in the reception time of each Rx node 3 can be absorbed.
[0086]
The read pointer (address) of the data FIFO 39 and the DBC-FIFO 40 is controlled by the comparison result of the comparator 38.
[0087]
When the comparator 38 outputs a coincidence signal, the sample data is read from the data FIFO 39 and output to the timing adjuster 41, and the next DBC in the DBC-FIFO 40 is set in the comparator 38.
[0088]
The timing adjuster 41 supplies the data output from the FIFO 39 to the node system 32 as sample data SDT in synchronization with the word clock WCK.
[0089]
The node system 32 reproduces the sample data (audio data) SDT in accordance with the sample count SCN in synchronization with the word clock WCK and generates a sound from the speaker.
[0090]
The WC packet 5 may use DBC instead of the sample count 5b. In that case, the DBC is stored in the FIFO 33 and the comparator 38 compares the DBC in the FIFO 33 with the DBC in the FIFO 40.
[0091]
Further, when the Rx node 3 starts reception, it is necessary to control the read pointers of the data FIFO 39 and the DBC-FIFO 40 to predetermined values. Specifically, the head DBC value of the DBC-FIFO 40 is compared with the head sample count value of the sample count FIFO 33, and each read pointer of the data FIFO 39 and the DBC-FIFO 40 is controlled in units of samples. Thereby, the sample count SCN and the corresponding sample data SDT can be supplied to the node system 32 at a predetermined timing.
[0092]
According to the IEEE 1394 standard, data for a plurality of channels can be transferred in an isochronous packet. When there are a plurality of channels of data, a plurality of the read pointer controllers may be provided, or one channel may be controlled by switching one read pointer controller. When there are data for a plurality of channels, the data FIFO 39 is required for the number of channels.
[0093]
FIG. 8 is a flowchart showing processing of the Rx node 3.
[0094]
In step SC1, the system time 5a and sample count 5b in the received WC packet 5 are stored in the FIFOs 34 and 33, respectively.
[0095]
In step SC2, when the data packet 6 is received, the DBC 6a and the sample data 6b in the packet 6 are stored in the FIFOs 40 and 39, respectively.
[0096]
In step SC3, the comparator 35 compares the system time with the cycle time, and waits until they match. If they match, the process proceeds to step SC4.
[0097]
In step SC4, the next system time stored in the FIFO 34 is loaded into the comparator 35 to prepare for the next comparison.
[0098]
In step SC5, the PLL 36 generates a word clock WCK.
[0099]
In step SC6, the comparator 38 compares the sample count in the FIFO 33 with the DBC in the FIFO 40, and adjusts the read pointers of the FIFOs 39 and 40 according to the comparison result.
[0100]
In step SC 7, the sample data SDT is read from the FIFO 39 based on the adjusted pointer and supplied to the node system 32. Then, the sample count SCN in the FIFO 33 is read and supplied to the node system 32.
[0101]
In the first embodiment described above, as shown in FIG. 3, synchronization between nodes is achieved by using the sample count axis as a reference. A case where the first and second transmitting nodes 2 transmit the data packet 6 to one receiving node 3 will be described. The WC master node 1 transmits a WC packet 5 to the first and second transmission nodes 2 and the reception node 3. The first and second transmission nodes 2 each transmit a data packet 6 to the reception node 3 in response to the WC packet 5. For example, the first transmission node transmits the musical sound played at the first performance hall in real time as audio data, and the second transmission node transmits the musical sound played at the second performance hall in real time. . The receiving node can reproduce the audio data received from the first and second transmitting nodes in synchronization. Thereby, the joint performance in the 1st and 2nd performance halls is attained.
[0102]
Next, a second embodiment is shown. In the second embodiment, synchronization between nodes is established by using the system time axis as a reference instead of the sample count axis.
[0103]
FIG. 9 is a block diagram illustrating a configuration example of the second Tx node 2.
[0104]
In the second embodiment, as shown in FIG. 2, a system time 6c is used instead of the DBC 6a. That is, the data packet 6 includes a system time 6c and sample data 6b.
[0105]
The Tx node 2 includes an IEEE 1394 interface system 51 and a node system 52.
[0106]
The WC packet 5 includes a system time 5a and a sample count 5b. The sample count FIFO 53 stores the sample count 5b first in first out. The system time FIFO 54 stores the system time 5a first in first out.
[0107]
The system time comparator 55 compares the system time 5a output from the FIFO 54 with the lower 16 bits of the cycle time output from the cycle timer 2a. The system time 5 a is a value obtained by adding the maximum delay time SYT_OFFSET (352 μs) to the lower 16 bits of the cycle time of the WC master node 1.
[0108]
When the cycle time and the system time 5a coincide, the comparator 55 outputs a coincidence signal. Processing shown later is awaited until the coincidence signal is output. By waiting for subsequent processing, the communication delay time T1 (FIG. 3) from the WC master node 1 to the Tx node 2 can be absorbed.
[0109]
The PLL 56 generates, for example, a 48 kHz audio word clock WCK in synchronization with the coincidence signal, and supplies the audio word clock WCK to the node system 52.
[0110]
When receiving the coincidence signal, the timing adjuster 57 supplies the sample count 5b in the FIFO 53 to the node system 52 as the sample count SCN.
[0111]
In synchronization with the word clock WCK, the node system 52 reads eight sample data (for example, 49th to 56th sample data) as data SDT in accordance with the sample count SCN (for example, 49), and first loads the data into the data FIFO 59. Store in-first-out.
[0112]
The timing adjuster 100 supplies the value of the system time 5a output from the system time FIFO 54 as described above (the value matched by the comparator 55) to the adder 58 at the timing matched by the comparator 55. The adder 58 adds an offset value SYT_OFFSET (for example, a system time corresponding to 17 samples) to the system time 5a, and stores it in the system time FIFO 60 in first-in first-out. By adding the offset value, preparation for absorbing the communication delay time T2 (FIG. 3) from the Tx node 2 to the Rx node 3 is completed. Absorption of the communication delay time T2 is performed at the Rx node 3 (FIG. 11) described later.
[0113]
A data packet 6 is generated based on the system time 6a in the FIFO 60 and the sample data 6b in the FIFO 59. The data packet 6 is transmitted from the Tx node 2 to the Rx node 3.
[0114]
FIG. 10 is a flowchart showing the processing of the second Tx node 2 (FIG. 9). The processes SD1 to SD7 on the left side of the flowchart show the process of the interface system 51, and the process SD8 on the right side shows the process of the node system 52.
[0115]
In step SD1, the system time 5a and sample count 5b in the WC packet 5 are stored in the FIFOs 54 and 53, respectively.
[0116]
In step SD2, the comparator 55 compares the system time with the cycle time, and waits until they match. If they match, the process proceeds to step SD3.
[0117]
In step SD3, the next system time stored in the FIFO 54 is loaded into the comparator 55 to prepare for the next comparison.
[0118]
In step SD4, the PLL 66 generates the word clock WCK.
[0119]
In step SD5, the sample count SCN in the FIFO 53 is supplied to the node system 52.
[0120]
Next, the interface system 51 processes step SD6, and the node system 52 processes step SD8.
[0121]
In step SD6, the adder 58 adds the above-mentioned matched system time 5a and the offset value SYT_OFFSET, and stores the added value in the FIFO 60. Next, the process proceeds to step SD7.
[0122]
In step SD8, sample data SDT corresponding to the input sample count SCN is supplied to the interface system 51. Next, the process proceeds to step SD7.
[0123]
In step SD7, the sample data SDT and system time are packetized, and the data packet 6 is sent to the Rx node 3 via the bus 4.
[0124]
FIG. 11 is a block diagram illustrating a configuration example of the second Rx node 3.
[0125]
In the second embodiment, unlike the first embodiment (FIG. 7), the data packet 6 includes a system time 6c instead of the DBC 6a. The data packet 6 includes a system time 6c and sample data 6b.
[0126]
The Rx node 3 includes an IEEE 1394 interface system 71 and a node system 72.
[0127]
The received data packet 6 includes a system time 6c and sample data 6b. The system time FIFO 80 stores the system time 6c in first-in first-out. The data FIFO 79 stores the sample data 6b first in first out.
[0128]
The system time comparator 78 compares the system time 5c output from the FIFO 80 with the cycle time output from the cycle timer 3a. The system time 6c is a value obtained by adding the offset value SYT_OFFSET to the system time 5a by the adder 58 of the Tx node 2 in FIG.
[0129]
Since the offset value SYT_OFFSET is added to the system time 6c, the system time 6c is initially larger than the cycle time value of the cycle timer 3a. The cycle timer 3a sequentially increments the cycle time.
[0130]
When the system time 6c matches the cycle time, the comparator 78 outputs a coincidence signal. Until the coincidence signal is output, the data reading process in the data FIFO 79 is awaited. By this standby, the communication delay time T2 (FIG. 3) from the Tx node 2 to the Rx node 3 can be absorbed.
[0131]
When the timing adjuster 81 receives the coincidence signal from the comparator 78, the timing adjuster 81 reads the sample data from the data FIFO 79 and stores it in the data FIFO 73. When the comparator 78 outputs a coincidence signal, the next system time within the system time 80 is set in the comparator 78.
[0132]
The received WC packet 5 includes a system time 5a and a sample count 5b. The system time FIFO 74 stores the system time 5a first in first out. The sample count FIFO 82 stores the sample count 5b first in first out.
[0133]
The system time comparator 75 compares the system time 5a output from the FIFO 74 with the lower 16 bits of the cycle time output from the cycle timer 3a. The system time 5 a is a value obtained by adding the maximum delay time SYT_OFFSET (352 μs) to the lower 16 bits of the cycle time of the WC master node 1.
[0134]
When the cycle time and the system time 5a coincide, the comparator 75 outputs a coincidence signal. Since the process shown later is waited until the coincidence signal is output, the communication delay time from the WC master node 1 to the Rx node 3 can be absorbed.
[0135]
The PLL 76 generates, for example, a 48 kHz audio word clock WCK in synchronization with the coincidence signal, and supplies the audio word clock WCK to the node system 72.
[0136]
The timing adjuster 77 supplies the sample data 6b in the data FIFO 73 to the node system 72 as sample data SDT at the time when the coincidence signal is received.
[0137]
When the timing adjuster 83 receives the coincidence signal, the timing adjuster 83 supplies the sample count 5b in the sample count FIFO 82 to the node system 72 as the sample count SCN.
[0138]
The node system 72 can generate sound from the speaker by reproducing sample data (audio data) SDT in accordance with the sample count SCN in synchronization with the word clock WCK.
[0139]
As described above, according to the second embodiment, synchronization between nodes can be achieved by using the system time axis as a reference. The comparator 78 absorbs the communication delay time of the data packet 6 from the Tx node 2 to the Rx node 3, and the comparator 75 absorbs the communication delay time of the WC packet 5 from the WC master node 1 to the Rx node 3. be able to. By absorbing these communication delay times, synchronization between nodes can be achieved.
[0140]
FIG. 12 is a flowchart showing the processing of the second Rx node 3 (FIG. 11).
[0141]
In step SE1, the system time 5a and the sample count 5b in the received WC packet 5 are stored in the FIFOs 74 and 82, respectively.
[0142]
In step SE2, when data packet 6 is received, system time 6c and sample data 6b in packet 6 are stored in FIFOs 80 and 79, respectively.
[0143]
In step SE3, the comparator 78 compares the system time 6c in the FIFO 80 with the cycle time of the cycle timer 3a, and waits until they match. If they match, the process proceeds to step SE4.
[0144]
In step SE4, the next system time stored in the FIFO 80 is loaded into the comparator 78 to prepare for the next comparison.
[0145]
In step SE5, the sample data in the data FIFO 79 is stored in the data FIFO 73.
[0146]
In step SE6, the comparator 75 compares the system time 5a in the FIFO 74 with the cycle time of the cycle timer 3a, and waits until they match. If they match, the process proceeds to step SE7.
[0147]
In step SE7, the next system time stored in the FIFO 74 is loaded into the comparator 75 to prepare for the next comparison.
[0148]
In step SE8, the PLL 76 generates the word clock WCK.
[0149]
In step SE9, the sample count SCN in the FIFO 82 and the sample data SDT in the FIFO 73 are supplied to the node system.
[0159]
Next, a method of matching the phases of the cycle timers 1a, 2a, 3a (FIG. 1) of the WC master node 1, the Tx node 2, and the Rx node 3 will be described. The WC master node 1, the Tx node 2, and the Rx node 3 are all nodes connected to the IEEE 1394 bus. One of these nodes is determined as the root node. For example, an identification number is assigned to each node, and the node having the smallest or largest identification number becomes the root node. The configuration is as follows.
[0160]
FIG. 14 shows a network configuration expressing the network of FIG. 1 from another viewpoint.
[0161]
The root node RN is any one of the WC master node 1, the Tx node 2, and the Rx node 3. The first node N1 to the nth node Nn are nodes other than the root node.
[0162]
The root node RN sends the cycle time CT generated by its own cycle timer onto the bus. The nodes N1 to Nn receive the cycle time CT sent from the root node RN, and set the value of the cycle time CT in its own cycle timer.
[0163]
FIG. 15 is a flowchart illustrating processing performed by the root node RN.
[0164]
In step SF1, the self-cycle timer value CT is transmitted to another node, and the process ends. The root node RN broadcasts the cycle timer value CT on the bus at a predetermined cycle.
[0165]
FIG. 16 is a flowchart illustrating processing performed by the nodes N1 to Nn.
[0166]
In step SG1, the cycle timer value CT is received from the root node RN.
[0167]
In step SG2, the own cycle timer is updated to the cycle timer value CT received.
[0168]
This flowchart is performed every time the cycle timer value CT is received from the root node RN at a predetermined cycle.
[0169]
The cycle timer of each node can be synchronized by the above method. Here, consider the delay time for the root node RN to transmit the cycle time CT. Due to the difference in delay time, the times at which the nodes N1 to Nn receive the cycle time CT differ. Next, processing that takes communication delay time into consideration is shown.
[0170]
The nodes N1 to Nn transmit pin packets to the root node RN. When the root node RN receives the pin packet, it returns a response packet. The nodes N1 to Nn measure the time from when the pin packet is transmitted until the response packet is received. The time is a round-trip communication delay time from the nodes N1 to Nn to the root node RN. The nodes N1 to Nn advance their cycle timers by the one-way communication delay time, and match the phase of the cycle timer of the root node RN.
[0171]
For example, when the round-trip communication delay time is measured as 100 μs, the one-way communication delay time is 50 μs. The nodes N1 to Nn add their cycle timers by the one-way communication delay time (50 μs).
[0172]
By adding the cycle timer by the one-way communication delay time, the phase of the cycle timer of each node can be matched. Thereby, the plurality of Rx nodes can reproduce the audio data almost simultaneously. Next, the above process will be described with reference to a flowchart.
[0173]
FIG. 17 is a flowchart showing the process for determining the delay time correction value of the cycle timer. The processes SH1, SH4, SH5, and SH6 on the left side of the flowchart indicate the processes of the nodes N1 to Nn, and the processes SH2 and SH3 on the right side indicate the processes of the root node RN.
[0174]
In step SH1, the nodes N1 to Nn transmit pin packets to the root node RN and start time measurement.
[0175]
In step SH2, the root node RN receives the pin packet.
[0176]
In step SH3, the root node RN immediately transmits a response packet to the transmission source nodes N1 to Nn.
[0177]
In step SH4, the nodes N1 to Nn receive the response packet.
[0178]
In step SH5, a round-trip communication delay time from when the nodes N1 to Nn transmit the pin packet (step SH1) to when the response packet is received (step SH4) is calculated.
[0179]
In step SH6, a half value of the calculated round-trip communication delay time is calculated as a one-way communication delay time. Next, the correction value is determined by converting the value of the one-way communication delay time into a cycle time. In principle, the cycle time is a value counted at about 25 MHz.
[0180]
FIG. 18 is a flowchart showing the correction process performed by the nodes N1 to Nn, which replaces the flowchart of FIG.
[0181]
In step SI1, the cycle timer value CT transmitted from the root node RN in FIG. 15 is received.
[0182]
In step SI2, the correction value determined in FIG. 17 is added to the received cycle timer value CT.
[0183]
In step SI3, the self cycle timer is updated to the corrected cycle time value.
[0184]
By correcting the cycle time, the phase of the cycle timer of each node can be matched. For example, the first Tx node 2 (FIG. 5) corrects the value of the cycle timer 2a, and the first Rx node 3 (FIG. 7) corrects the value of the cycle timer 3a.
[0185]
Next, a method for correcting the system time instead of the cycle time will be described. In the first Tx node 2 (FIG. 5), the comparator 15 compares the value of the cycle timer 2a with the value of the system time FIFO 14. In the above description, the value of the cycle timer 2a is corrected. Instead, the value of the system time FIFO 14 is corrected and set in the comparator 15.
[0186]
Similarly, in the first Rx node 3 (FIG. 7), instead of correcting the value of the cycle timer 3a, the value of the system time FIFO 34 is corrected and set in the comparator 35.
[0187]
Similarly, in the second Tx node 2 (FIG. 9), instead of correcting the value of the cycle timer 2a, the value of the system time FIFO 54 is corrected and set in the comparator 55.
[0188]
Similarly, in the second Rx node 3 (FIG. 11), instead of correcting the value of the cycle timer 3a, the value of the system time FIFO 74 is corrected and set in the comparator 75, and the value of the system time FIFO 80 is corrected. And set in the comparator 78.
[0189]
FIG. 19 is a flowchart showing the system time correction process.
[0190]
In step SJ1, the system time value is extracted from the reception FIFOs 14, 34, 54, 74, and 80.
[0191]
In step SJ2, calculation is performed based on the extracted system timer value and the correction value determined in FIG. For example, the correction value is subtracted from the value of the system timer.
[0192]
In step SJ3, the above calculation values of the comparators 15, 35, 55, 75, 78 are set.
[0193]
Note that the second Tx node (FIG. 9) may transmit the data packet 6 after correcting the system time in the system time FIFO 60. In that case, it is not necessary to correct the value of the system FIFO 80 of the second Rx node (FIG. 11).
[0194]
As described above, the phase of the time axis of each node can be matched by correcting the cycle time or system time. By matching the phases, it is possible to match the phases of transmission timings of a plurality of Tx nodes or reproduction timings of a plurality of Rx nodes.
[0195]
According to the first and second embodiments, the WC master node 1 transmits the WC packet 5 to the Tx node 2 and the Rx node 3. The Tx node 2 transmits the data packet 6 to the Rx node 3. The data packet 6 has DBC 6a or system time 6c in addition to the sample data 6b.
[0196]
In the first embodiment, the DBC 6a can be used to synchronize the nodes based on the sample count axis. In the second embodiment, synchronization between nodes can be achieved based on the system time axis using the system time 6c.
[0197]
By synchronizing the nodes, when the same data is transmitted almost simultaneously from one Tx node to a plurality of Rx nodes, the data reproduction time can be adjusted between the plurality of Rx nodes. Each Rx node can reproduce a series of data without causing a timing shift.
[0198]
Further, by synchronizing between nodes, when data is transmitted from a plurality of Tx nodes to one Rx node, the timing of data transmitted from the plurality of Tx nodes can be matched in the Rx node.
[0199]
Note that the data in the packet is not limited to audio data, and may be image data or the like. Communication is not limited to IEEE 1394 digital serial communication, but may be other serial communication or parallel communication. For example, the Internet or a LAN may be used.
[0200]
FIG. 20 is a diagram showing a specific hardware configuration of the personal computer 12.
[0201]
The configuration of the personal computer 12 will be described. The bus 21 includes a CPU 22, a RAM 24, an external storage device 25, a MIDI interface 26 for transmitting / receiving MIDI data to / from the outside, a sound card 27, a ROM 28, a display device 29, input means 30 such as a keyboard, a switch, and a mouse, A communication interface 31 for connecting to the Internet is connected.
[0202]
The sound card 27 has a buffer 27a and a codec circuit 27b. The buffer 27a buffers data for input or output to the outside. The codec circuit 27b includes an A / D converter and a D / A converter, and can convert between an analog format and a digital format. Further, the codec circuit 27b includes a compression / decompression circuit, and can compress and decompress data.
[0203]
The external storage device 25 is, for example, a hard disk drive, a floppy disk drive, a CD-ROM drive, a magneto-optical disk drive, or the like, and can store MIDI data, audio data, image data, a computer program, or the like.
[0204]
The ROM 28 can store a computer program and various parameters. The RAM 24 has a working area such as a buffer and a register, and can copy and store the contents stored in the external storage device 25.
[0205]
The CPU 22 performs various calculations or processes according to the computer program stored in the ROM 28 or the RAM 24. The system clock 23 generates time information. The CPU 22 can obtain time information from the system clock 23 and perform timer interrupt processing.
[0206]
A communication interface 31 of the personal computer 12 is connected to the Internet line 32. The communication interface 31 is an interface for transmitting and receiving MIDI data, audio data, image data, computer programs, and the like over the Internet.
[0207]
The MIDI sound source 13 is connected to the MIDI interface 26, and the sound output device 14 is connected to the sound card 27. The CPU 22 receives MIDI data, audio data, image data, a computer program, and the like from the Internet line 32 via the communication interface 31.
[0208]
The communication interface 31 may be an Ethernet interface, an IEEE 1394 standard digital communication interface, or an RS-232C interface in addition to the Internet interface, and can be connected to various networks.
[0209]
The personal computer 12 stores a computer program for receiving and playing audio data. By storing a computer program, various parameters, and the like in the external storage device 25 and reading them into the RAM 24, it is possible to easily add or upgrade a computer program or the like.
[0210]
A CD-ROM (compact disk-read only memory) drive is a device that reads a computer program or the like stored in a CD-ROM. The read computer program or the like is stored in the hard disk. New installation and version upgrade of computer programs can be done easily.
[0211]
The communication interface 31 is connected to a communication network 32 such as a LAN (local area network), the Internet, or a telephone line, and is connected to the computer 33 via the communication network 32. When the above computer program or the like is not stored in the external storage device 25, the computer program or the like can be downloaded from the computer 33. The personal computer 12 transmits a command requesting download of a computer program or the like to the computer 33 via the communication interface 31 and the communication network 32. The computer 33 receives this command and distributes the requested computer program or the like to the personal computer 12 via the communication network 32. The personal computer 12 receives a computer program or the like via the communication interface 31 and stores it in the external storage device 25, whereby the download is completed.
[0212]
In addition, you may make it implement a present Example by the commercially available personal computer etc. which installed the computer program etc. corresponding to a present Example. In that case, the computer program or the like corresponding to the present embodiment may be provided to the user while being stored in a storage medium that can be read by the computer, such as a CD-ROM or a floppy disk. When the personal computer or the like is connected to a communication network such as LAN, the Internet, or a telephone line, a computer program or various data may be provided to the personal computer or the like via the communication network.
[0213]
Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
[0214]
【The invention's effect】
As described above, according to the present invention, data can be transmitted or processed in synchronization by communicating synchronization information between a plurality of communication devices.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a network according to an embodiment of the present invention.
FIG. 2 is a timing chart showing processing of a transmission node (Tx node).
FIG. 3 is a timing chart of each node shown in FIG. 1;
FIG. 4 is a flowchart showing processing of a WC master node.
FIG. 5 is a block diagram showing a configuration of a first Tx node.
FIG. 6 is a flowchart showing processing of a first Tx node.
FIG. 7 is a block diagram showing a configuration of a first receiving node (Rx node).
FIG. 8 is a flowchart showing processing of a first Rx node.
FIG. 9 is a block diagram showing a configuration of a second Tx node.
FIG. 10 is a flowchart showing processing of a second Tx node.
FIG. 11 is a block diagram showing a configuration of a second Rx node.
FIG. 12 is a flowchart showing processing of a second Rx node.
FIG. 13 is a block diagram showing a network configuration.
FIG. 14 is a flowchart showing processing of a root node.
FIG. 15 is a flowchart showing processing of a node other than the root node.
FIG. 16 is a flowchart showing processing for determining a delay time correction value for a cycle timer.
FIG. 17 is a flowchart showing first delay time correction processing;
FIG. 18 is a flowchart showing a second delay time correction process;
FIG. 19 is a diagram illustrating a specific hardware configuration of the personal computer 12;

Claims (6)

A communication device forming one of a plurality of nodes connected to a network,
A cycle timer for generating a time value synchronized with a time value output by a route node connected to the network;
Sample count generation means for generating a count value for counting samples of audio data;
A synchronization time value generating means for generating a synchronization time value in which a maximum delay amount is added to a time value corresponding to the synchronized time value;
A communication apparatus comprising: synchronization packet output means for generating a synchronization packet including the sample count value and the synchronization time value at a predetermined time interval and outputting the generated synchronization packet to the network. A communication device forming one of a plurality of nodes connected to a network,
A cycle timer for generating a time value synchronized with a time value output by a route node connected to the network;
Receiving means for receiving synchronization information from a word clock node connected to the network;
Clock generating means for generating a word clock based on the synchronized time value and the received synchronization information;
Data sample supply means for sequentially supplying samples of audio data based on the word clock;
Sample count supply means for supplying a sample count value of audio data based on the synchronization information;
Synchronization count generation means for generating a synchronization count value in which a transfer maximum delay amount is added to the count value;
A communication apparatus comprising: a transmission unit configured to generate a data packet including the plurality of supplied samples and the synchronization count value, and to transmit the generated data packet to a reception node connected to the network. A communication device forming one of a plurality of nodes connected to a network,
A cycle timer for generating a time value synchronized with a time value output by a route node connected to the network;
Receiving means for receiving synchronization information from a word clock node connected to the network;
Clock generating means for generating a word clock based on the synchronized time value and the received synchronization information;
Data sample supply means for sequentially supplying samples of audio data based on the word clock;
A synchronization time value generating means for generating a synchronization time value by adding a transfer maximum delay amount to the synchronized time value;
A communication apparatus comprising: a transmission unit configured to generate a data packet including the plurality of supplied samples and the synchronization time value, and to transmit the generated data packet to a reception node connected to the network. A communication device forming one of a plurality of nodes connected to a network,
A cycle timer for generating a time value synchronized with a time value output by a route node connected to the network;
Synchronization information receiving means for receiving synchronization information from a word clock node connected to the network;
Clock generating means for generating a word clock based on the synchronized time value and the received synchronization information;
Data receiving means for receiving a data packet including a plurality of samples and a synchronization count value associated with the plurality of samples from a transmission node connected to the network;
A communication apparatus comprising: sample output means for sequentially outputting a plurality of samples included in the data packet sample by sample according to the word clock at a timing based on the synchronization information and the synchronization count value. A communication device forming one of a plurality of nodes connected to a network,
Measuring means for measuring the arrival delay time of communication from the root node connected to the network to the communication device;
Determining means for determining a correction value according to the arrival delay time measured by the measuring means;
Time value receiving means for receiving a time value output from the root node;
Correction means for correcting the received time value according to the correction value;
A cycle timer that generates a synchronized time value based on the corrected time value;
Synchronization information receiving means for receiving synchronization information from a word clock node connected to the network;
A communication apparatus comprising: a clock generation means for generating a word clock based on the synchronized time value and the received synchronization information. A communication device forming one of a plurality of nodes connected to a network,
A cycle timer for generating a time value synchronized with a time value output by a route node connected to the network;
Measuring means for measuring the arrival delay time of communication from the root node to the communication device;
Determining means for determining a correction value according to the arrival delay time measured by the measuring means;
Synchronization information receiving means for receiving synchronization information from a word clock node connected to the network;
Correction means for correcting the received synchronization information according to the correction value;
A communication apparatus comprising: clock generation means for generating a word clock based on the synchronized time value and the corrected synchronization information.

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