JP3358581B2 - Packet transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a packet transfer apparatus for transmitting and receiving event sequence data such as audio data through a high-speed serial network to which a plurality of devices are connected.

[0002]

2. Description of the Related Art A plurality of electronic musical instruments and audio devices are sequentially connected by a cable to form an IEEE 1394 standard serial network, and audio data (voice, audio,
The technology for transmitting musical tones) and MIDI data is known as the "protocol for audio and music data transfer" (Audio
and Music Data Transmission Protocol, Version1.0,19
97-5, 1394 Trade Association).

FIG. 10 is an explanatory diagram showing a flow of a packet on a network. There are a plurality of nodes on the network, in this example, three transmitting nodes A101, transmitting nodes B102, transmitting nodes C103, and receiving nodes 104. In the illustrated example, a plurality of transmission nodes A10
At 1, B102, and C103, audio data input from an external device is reproduced by the external device at the receiving node. Sending nodes A101, B102, C10
3 transmits packets, the receiving node 104 receives packets transmitted from a plurality of transmitting nodes, and reproduces audio data included in packets from desired transmitting nodes at a predetermined sampling rate.
105a to 105d are packets transmitted from the transmission node A101, and 106a to 106c are transmission nodes B1
02, a packet transmitted from the transmission node C1 107
03 is a packet transmitted.

The entire network is time-controlled by a cycle master node. A cycle start packet is transmitted from the cycle master node to other nodes every 125 μsec. On other nodes,
Every time the cycle start packet is received, the time is adjusted by the cycle timer inside the node with the absolute time information in the packet, thereby synchronizing with the cycle master node.

[0005] Each of the transmitting nodes A101, B102, C10
In (3), a time stamp based on the time of a cycle timer (hereinafter, abbreviated as “syt” is used) is applied to audio data reproduced at a predetermined sampling clock by an external device connected to its own node, using an eight sampling clock (8). Data block).
Then, one or more channels of audio data are put in the data field and syt is put in the syt field, and a packet is created and transmitted. The playback time of the event sequence (audio channel) on the receiving side is specified by syt (time stamp). DBC (Da
ta Block Count) is a value of the total number of data blocks transmitted so far. The data block is usually composed of data of a plurality of event sequences generated by the same sampling clock.

FIG. 11 is an explanatory diagram of a packet format at the time of isochronous transfer. The isochronous transfer is a data transfer defined in the link layer of IEEE 1394, in which a transmission delay is guaranteed, and each node secures a “band” in advance. The packet format is isochronous header, CIP (Common i
sochronous packet format) header and data fields. 32 bits are a basic unit. The isochronous header includes fields of data length, tag, channel (isochronous transfer channel), "1010" bit string (tcode) representing isochronous data packet, synchronization (sync), and header CRC.

The CIP header contains various items necessary for reception, such as DBS (Data Block Size), DBC (Data Block Count), and syt (time stamp). Of the packet to which no syt is added
The value of no data is entered in the t field. The data field contains audio data, MIDI data, and the like. Although the illustration of the data format in the data field is omitted, (1) AM824: generic format,
(2) AM824: IEC958conformant, (3) AM824: Rawaudi
o, (4) AM824: MIDIconformant, (5) 32bit Data fo
rmat, (6) 24 * 4 Audio pack format.

FIG. 12 is a diagram for explaining the operation of isochronous transfer. This figure is for explaining the transfer control.
In FIG. 10 described above, syt is added for every 8 data blocks (8 sampling clocks), but in FIG. 12, syt is added for every 4 data blocks (4 sampling clocks), and the sampling frequency Fs
Is 26.7 kHz. The upper part is a transmitting side, which shows one event sequence (sampling data) included in the data block, and the middle part shows a packet. The lower side is a receiving side, and shows one event sequence (sampling data) included in each data block. In this example, sampling data reproduced at a predetermined sampling clock is input as an event sequence. The cycle timer of the transmitting node outputs a time value. The sending node has a nominal isochronous cycle (1
Once every 25 .mu.sec), a data block for the reserved band is created, and a packet is transmitted with a value of syt taking into account the transmission delay.

In the first packet, DBC = 3 (three data blocks have already been transmitted) and syt = R1 are put in the packet together with three data blocks. In the second packet, DBC = 6 (six data blocks have already been transmitted) and syt = R2 are put in predetermined fields together with four data blocks. Similarly, the third to fifth packets are transmitted. However, since the fourth packet does not include the data block of the sampling clock corresponding to the syt interval, syt
Is not added.

[0010] The packet is delayed in transmission and received by the receiving node. Then, a reproduction sampling clock is generated. In the figure, the index value indicates which number (0 to 3) of a plurality of data blocks included in a packet is sy.
This is a value indicating whether the data block corresponds to the time of the t interval, and is obtained by calculation from the DBC value and the syt interval.

Returning to FIG. 10, the description will be continued. In the packet 105a transmitted by the transmitting node A1, the DBC
= 3 is added. In the packet 105b, the DB
C = 7 and syt = 1000 are added. This syt =
The data block at the same time as the time of 1000 is DA0. In the packet 105d, DBC = 16, s
yt = 9000 is added. The data block at the same time as this time of syt = 9000 is DA8. DA
8 is a data block 8 data blocks after DA0. On the other hand, in the packet 106a transmitted by the transmitting node B 102, DBC = 7 and syt = 7000 are added. In the packet 106b, DBC = 1
2 in the packet 106c, DBC =
16, syt = F000 is added.

[0012] One to three cables according to the IEEE 1394 standard are provided at each node with a physical layer IC that serves a physical layer.
(Integrated Circuit) and this physical layer IC
Are connected to a link layer controller IC that handles the link layer. The link layer controller IC includes IEEE
E1394 Digital Audio / MIDI Transfer LSI
(Large scale integration, hereinafter referred to as a packet handler) is connected, and executes the above-mentioned "protocol relating to audio and music data transfer". When transmitting event sequence data such as audio and music data having a real-time property in the isochronous transfer mode packet format, the transmission time and the reception interval of the packet to the receiving node are not constant because the transmission is not synchronous. Therefore, it is necessary to reproduce the received audio data at a time designated on the transmission side and output the audio data to an external device in synchronization with the input sampling clock on the transmission side.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to provide a packet transfer apparatus capable of transmitting and receiving a packet including event sequence data and coping with occurrence of an error.

[0014]

According to the first aspect of the present invention, there is provided a data processing system comprising one or a plurality of data blocks each composed of a plurality of event sequence data, and the time is provided for each predetermined number of the data blocks. A packet transfer device for transmitting a packet with a stamp added thereto to one or more desired nodes on a network, comprising: an arithmetic unit that calculates an input timing cycle of the data block based on a time of the time stamp; Error processing means for stopping transmission of the packet including the data block and transmitting the packet indicating occurrence of an error when a difference between an output of the arithmetic means and a preset cycle exceeds an allowable range. It has. Therefore, the transmitting side can detect an error to prevent abnormal transmission of the packet and notify the receiving side of the error.

According to the second aspect of the present invention, a packet including one or a plurality of data blocks each composed of one or a plurality of event sequence data, and having a timestamp added to each predetermined number of the data blocks, A packet transfer apparatus for receiving from one or more desired transmission nodes on a network, wherein a timing error is detected based on the time of the received time stamp, and a packet indicating the occurrence of the error is detected. And an error processing means for muting the output of the event sequence data constituting the data block. Therefore, on the receiving side, it is possible to detect the error and mute the output of the event sequence data forming the abnormal data block, thereby preventing generation of noise.

[0016]

FIG. 1 is a functional block diagram of a packet handler according to an embodiment of the packet transfer apparatus of the present invention. In the figure, 1 is a transmitting unit, 2 is a receiving unit, 3 is DIR
(Digital audio receiver), 4a to 4e are audio interfaces, 5 is CPU (Central Processing U)
nit) interface, 6 is CPU bus, 7a, 7b
Is a switching unit, and 8a is a transmission FIFO (first
in first out), 8b and 8c are non-audio transmission FIs
FO, 8d is a transmission FIFO for syt, 9 is a packetizing unit, and 10 is a link interface. 11 is an unpacketizing unit, and 12a to 12h are audio reception FIs.
FO, 12i and 12j are non-audio receiving buffers,
12k and 12l are receiving buffers for syt, 13 is a patch section, 14a to 14e are audio interface sections,
15 is a CPU interface unit, 16a and 16b are switching units, 17 is a DIT (Digital audio transmitter),
18a and 18b are adders, 19 is a synchronizing unit, 20 is a link layer controller, and 32a and 32b are delay offset registers. Although not shown in the functional block diagram, each function is executed by executing a program using hardware such as a CPU and a memory.

In the transmission unit 1, audio data of eight channels output from digital audio equipment such as a mixer is input from input terminals DAI0 to DAI3 to the audio interfaces 4b to 4e. In each of the input terminals DAI0 to DAI3, two-channel audio data is multiplexed in a time-division manner. The switches 7a and 7b may input IEC958-standard data via the DIR3 from the input terminal IEC958I instead of the input terminal DAI0. The output of DIR3 is supplied to output terminal DIRO via audio interface 4a.

On the other hand, MIDI data is stored in the M of the external CPU.
An input FIFO from the IDI interface and a transmission FIFO 8 via the CPU bus 6 and the CPU interface 5
b, 8c. Audio interface 4
b-4e output (audio0-audio7) and transmission F
The outputs of the FIFOs 8b and 8c are input to the transmission FIFO 8a. "FIFO" is a specific memory function,
Data is sequentially stored at the time of an input request, and stored data is read in a first-come-first-served manner in response to a read request generated asynchronously with the input request, but is used as a means for realizing a buffer function.

The syt (time stamp) is input to the transmission FIFO 8d every eight data blocks. Transmission FIF
The output of O8a is input to the packetizing unit 9 together with the output of the transmission FIFO 8d, added with a header, and output to the link interface 10. The link interface 10 outputs a packet to the link layer controller 20. The link layer controller 20 transmits and receives packets to and from the packet handler via a 16-bit width isochronous bus.

The packets transmitted from the plurality of transmitting nodes are input to the link interface 10 via the link layer controller 20, input to the unpacketizing unit 11, and are unpacketized based on header information and the like. . The packet is interpreted, and a plurality of audio data and the like are temporarily stored in a plurality of reception FIFOs 12a to 12j, respectively. By looking at the isochronous transfer channel in the packet header, it is also possible to receive only the packet from the desired transmitting node.

Using the time information of the received syt, the reproduction time of the received audio data is adjusted to the time of the cycle timer of the reception unit, and the reproduction timing clock is synchronized with the input sampling clock of the transmission side.
Output to external device. Therefore, the reception F for audio
IFOs 12a to 12h, first and second syt reception FIs
FOs 12k and 12l are provided.

Each of the audio data separated from the packet by the unpacketizing unit 11 is an audio reception F.
The data is written to the IFOs 12a to 12h. Similarly, non-audio channel data is also written to the non-audio receiving FIFOs 12i and 12j. The syt extracted from the packet is the first syt reception FIFO1
It is written to the 2k or second syt reception FIFO 121. Syt read from the first syt reception FIFO 12k and the second syt reception FIFO 12l
Are set for each transmission node in the adders 18a and 18b, respectively, and the delay offset registers 32a and
The value is added to the predetermined offset value stored in 32b and input to the synchronization unit 19. The synchronization unit 19 controls the read timing and read pointer of audio data from the audio reception FIFOs 12a to 12h. The synchronizer 19 has an external output terminal PLLout and an external input terminal PLLin of a reproduction sampling clock, and enables external output or external input of the reproduction sampling clock. The operation of the synchronization unit 19 will be described in detail with reference to FIGS.

Audio receiving FIFOs 12a to 12h
Are provided for each transmission node and for each audio channel. Therefore, even when audio channels separated from packets from different transmission nodes are mixed, it is not only easy to independently start reading and perform synchronous reproduction for each channel, but also
It is easy to flexibly change the number of channels even when the specification of the packet handler is changed.

Audio receiving FIFOs 12a-12
The output of h is output to the patch unit 13. Here, the audio data read from the eight audio reception FIFOs 12a to 12h is transferred to an audio channel (au).
dio0 to audio7). The audio data of the eight channels is stored in the audio interface 14b.
-14e are time-division multiplexed by two channels and output. In the assignment, the unpacketizing unit 11 extracts from the transmitting node, from which transmitting node, the format of the sampling data of the audio channel and the format of the data, in the data block of the packet. This is done from the information in the header.

The control of the patch section 13 is performed by using a setting operator or the like provided outside the packet handler.
It can also be done by inputting external settings. For example, it is possible to switch and output received audio data to an output terminal different from the original output destination, or to simultaneously supply one received audio data to a plurality of output terminals. Such user setting is possible because the audio reception FIFOs 12a to 12h are provided for each transmission node and are provided for each audio channel.

On the other hand, the non-audio receiving FIFO 12
The two-channel data output from i, 12j is CP
The data is output to a MIDI input / output interface of an external CPU (not shown) via the U interface 15 and the CPU bus 6. When the data for IEC958 is received, the two audio channels (audio0 and audio1) are output to the output terminal IEC958 via the switches 16a and 16b and the DIT17. In the state where the switches 16a and 16b are switched to the other, audio data from the input terminal DITI is output to the DIR 17 via the audio interface 14a.

FIG. 6 is a flowchart for explaining the outline of the operation of the packet handler shown in FIG. FIG. 6A is a flowchart for explaining an outline of processing as a transmitting node, and FIG. 6B is a flowchart for explaining an outline of processing as a receiving node. In the transmission node process shown in FIG. 6A, in S51, audio data of a plurality of channels is fetched from the external input terminals DAI0 to DAI3 at a predetermined sampling rate to form one data block. To form a data field,
Processing proceeds to In the case of MIDI data, an external C
It is fetched from the MIDI interface of the PU via the CPU bus. In S52, a header is formed, the packet is attached by attaching the header to the data field, and the process proceeds to S53.

In S53, it is determined whether or not a processing error has occurred in the transmission unit. If no error has occurred, the process proceeds to S54. If any error has occurred, the process proceeds to S55. Proceed. As a processing error, for example, a cycle of a sampling clock, which is an input timing of a data block, is calculated based on the time of a time stamp, and a difference between the calculated output and a preset sampling clock cycle exceeds an allowable range. There are times. In S54, a packet is transmitted. In S55, the transmission data is muted by suspending the transmission of the normal packet, and an interrupt signal for reporting an error is transmitted to generate an interrupt signal on the receiving node side.

In the receiving node process shown in FIG. 6B, in S61, the packet data is unpacketized based on the header information, and the audio data, the non-audio data, and the syt are respectively received by the reception FIFO 12a.
１２12h, 12i, 12j, 12k, and 12l. At this time, the write pointers (WP) of the reception FIFOs 12a to 12l are managed.

FIG. 2 is a block diagram for explaining a receiving node reproducing process of the packet handler according to the embodiment of the present invention. In the figure, the same parts as those in FIG. Synchronization unit 19 shown in FIG.
Are comparators 33a, 33b, cycle timer 34, PL
L (Phaselocked loop) 35, read control unit 36, switching unit 37, and CPU register 38. 31 is a writing control unit. The cycle timer 34 may be built in the packet handler or provided externally.

The packetized audio data is 1
Or come from multiple sending nodes. For each packet from each transmitting node and for each audio channel in the packet, the audio reception FIFO 12
a to 12h are assigned one by one.

The receiving node outputs the received audio data with a reproduction sampling clock synchronized with the input sampling clock of the transmitting node.
The input sampling clock at this transmitting node is
Synchronous playback is performed and restored based on the transmitted syt time. Each transmitting node transmits a packet by putting syt in a predetermined header field of the packet. For each transmitting node, it is also possible to synchronously reproduce the sampling clock using the syt from each transmitting node. However, synchronous reproduction of the sampling clock is performed by any one of the transmitting nodes, for example, when a packet is first received. This is performed using the syt included in the packet of the transmission node A1. Hereinafter, the transmitting node that has transmitted the syt for synchronously reproducing the sampling clock is referred to as a synchronous reproduction reference node for convenience.

The write control unit 31 includes first and second sy
Write pointers (W) to the reception buffers 12k and 121 for t and the reception FIFOs 12a to 12h for audio.
P) and a write timing signal. The syt from the synchronous playback reference node is first s
Every time the data is written to the reception FIFO 12k for yt, the first s
The write pointer (WP) of the reception buffer 12k for yt is incremented. On the other hand, the first receiving FIFO for syt
Receive FIF for audio of the same transmission node as O12k
The value of the write pointer (WP) of O is calculated based on the value of the write pointer (WP) of the reception FIFO 12k for the first syt, and data of 8 data blocks (for 8 sampling clocks) is sequentially written. The write pointer (WP) for the correction second syt receiving FIFO 121, which will be described later, is the second syt receiving FIFO 12l.
k is incremented each time a syt from a certain transmission node is written. The value of the write pointer (WP) of the audio reception FIFO of the same transmission node as the second syt reception FIFO 121 is the second s.
It is incremented every time syt is written to the reception FIFO 12k for yt.

For the sake of simplicity, the case where the value stored in the delay offset register 32a is 0, and therefore, the same as the case without the adder 18a will be described. In the comparator 33a, the reception FI for syt is used.
When the time of the syt already read from the FO 12k matches the time of the cycle timer 34 of the receiving node, a match pulse is output to the PLL 35 and the read control unit 36.

The PLL 35 controls the frequency of the built-in VCO (voltage controlled oscillator) so that the output phase of the VCO becomes zero when the coincidence pulse is input. This VCO is
It is designed to self-run at a period of about 1/8 (determined by the synt interval) of the period of the coincidence pulse. PL
In L35, the output of the VCO is phase-synchronized with the above-mentioned coincidence pulse, thereby receiving the first syt reception FI.
The sampling clock is synchronously reproduced at a period of 1/8 of the time difference between adjacent syts read from the FO 12k.
Since the time interval of the coincidence pulse has a time difference between adjacent syts, the reproduction pulse is obtained by multiplying the coincidence pulse by eight. The PLL 35
The phase synchronization may not be performed every time a coincidence pulse is output, and the phase may be synchronized with an appropriately thinned coincidence pulse. The reproduction sampling clock output from the PLL 35 is supplied to the read control unit 36 via the switching unit 37.
And reproduction sampling clock output terminal PLLout
Is output to

The read control unit 36 includes first and second sy
The read pointers (R) for the receiving buffers 12k and 121 for t and the receiving FIFOs 12a to 12h for audio.
P) and a read timing signal. Transmission node A101 which is a synchronous reproduction reference node
Is temporarily stored in the audio receiving FIFOs 12a and 12b, for example. In the read control unit 36, every time a coincidence pulse is generated from the comparator 33a, the first SYT reception FI
The read pointer (RP) of the FO 12k is incremented to read the next syt. At the same time, when the comparator 33a generates a coincidence pulse for the first time, the audio reception FIFOs 12a and 12b start reading data blocks corresponding to the syt time read from the first syt reception FIFO 12k. The value of the read pointer is calculated and corrected (time adjustment), and the data block is read. Thereafter, the value of the read pointer is incremented by the reproduction sampling clock output from the PLL 35, and the data block is read.

As a result, after the time when the syt time of the transmitting node A 101 first matches the time of the cycle timer 34 of the receiving node, the audio data from the transmitting node A 101 is synchronized with the PLL 35 synchronized with the cycle timer 34.
The reading is started from the audio receiving FIFOs 12a and 12b in synchronization with the reproduction sampling clock of the audio data.
Note that, even in the period before this point, the value of the read pointer of the audio reception FIFOs 12a and 12b is incremented for each reproduction sampling clock, whereby
It is also possible to read and output audio data whose time is not guaranteed.

On the other hand, it is assumed that audio data from another transmitting node B 102 which is not the synchronous reproduction reference node is temporarily stored in, for example, the audio receiving FIFOs 12c and 12d, and correction of each read pointer (RP) (time adjustment). Is performed by the second receiving FIFO for syt 121l. Each bit position of the CPU register 37 corresponds to the audio reception FIFOs 12a to 12h. The audio reception FIFO corresponding to the bit position in which the flag bit is inserted is set as a target of time adjustment by the second syt reception FIFO 121. When the number of audio reception FIFOs to be corrected by one read pointer is limited to one, one flag bit may be sequentially shifted to each bit position of the CPU register 37, so that the configuration is simple. However, if one or a plurality of audio reception FIFOs 12c and 12d that temporarily store an event sequence (audio data) from the same transmission node are corrected simultaneously with the read pointer, the correction can be performed in a short time. It can be carried out. The following operation example illustrates the latter case.

For example, syt from the transmitting node B 102
Is written into the second receiving FIFO for syt 121l. The audio data from transmitting node B 102 is
It is assumed that data has been written to the FOs 12c and 12d. To simplify the description, the delay offset register 31
The value stored in b is 0, and a case similar to the case without the adder 18b will be described.

In the comparator 33b, when the time of the syt temporarily stored and read in the second syt receiving FIFO 121 and the time of the cycle timer 34 coincide with each other and a coincidence pulse is output, the coincidence pulse becomes , To the read control unit 36. In the read control unit 36,
Each time a coincidence pulse occurs, the reception F for the second syt
The read pointer (RP) of the IFO 121 is incremented.
At the same time, when the coincidence pulse is generated for the first time, the second s
syt read from yt reception FIFO 121
Then, the values of the read pointers of the audio receiving FIFOs 12c and 12d are calculated so as to start reading the data block corresponding to the time of, and the data block is read.
Thereafter, the read pointer value is incremented by the reproduction sampling clock output from the PLL 35,
Read the data block.

As a result, after the time when the syt time of the transmitting node B 102 coincides with the time of the cycle timer 34 of the receiving node for the first time, the audio data from the transmitting node B 102 is also synchronized with the PLL 35 synchronized with the cycle timer 34.
Are read from the audio reception FIFOs 12c and 12d in synchronization with the reproduction sampling clock. Note that audio data whose time is not guaranteed can be read out and output even in a period before this time.

Once the read pointer whose time has been set can be obtained, the pointer may simply be incremented for each reproduction sampling clock unless synchronization is lost. Therefore, audio data from another transmission node, for example, transmission node C103,
For example, when temporarily stored in the audio receiving FIFOs 12e and 12f, the second syt receiving FIFO is used.
The function of the O12l is changed to the reception FIFO 12e for audio,
It switches to correction of each read pointer of 12f.

That is, sy from the transmitting node C103
Write t to the second receiving FIFO for syt 121l.
In the comparator 33b, the second receiving FIFO for syt 1
When the time of the syt temporarily stored and read in the 2l coincides with the time of the cycle timer 34 and a coincidence pulse is output, the read control unit 36 reads the read pointer (12h) of the second syt reception FIFO 121l. RP). At the same time, audio reception FIFOs 12e and 12f
After the switching to the correction of each read pointer, the second synchronizing reception FIFO
The values of the read pointers of the audio reception FIFOs 12e and 12f are calculated so as to start reading the data block corresponding to the syt time read from the 12l, and the data block is read. As a result, after the time when the syt time of the transmission node C103 first matches the time of the cycle timer 34 of the reception node, the transmission node C103
The audio data from 103 is also stored in the cycle timer 34.
The data is read from the audio reception FIFOs 12e and 12f in synchronization with the reproduction sampling clock of the PLL 35 synchronized with.

As described above, there is no need to provide the same number of syt reception FIFOs as the number of audio reception FIFOs, and the audio data from each transmission node is transmitted to each transmission node based on the time of the cycle timer 34 of the reception node. It can be output from the node at the time specified by syt. Also, audio data can be output with a reproduction sampling clock synchronized with an input sampling clock at each transmission node. As a result, synchronization can be performed with an accuracy of one sampling clock.

In the above description, the read control unit 36
Has increased the read pointer (RP) of the reception FIFO 121 for the second syt every time a coincidence pulse is generated from the second comparator 33b. However, the second syt
The receiving FIFO 121 for a certain audio receiving FI
When the audio data written in the FO is used for adjusting the time of the cycle timer 34 only once for the first time, after the time matches, when the subsequent coincidence pulse is generated, the syt from the transmission node is changed. There is no need to read.

The correction for time adjustment is not performed when the time of the syt read from the first and second syt reception FIFOs 121 coincides with the time of the cycle timer 34 only once. Then, the time may be strictly adjusted so that the correction is performed on condition that the time of the read syt and the time of the cycle timer 34 continuously match a plurality of times. After the correction is performed once, the data blocks are read from the audio reception FIFOs 12a to 12h with the reproduction sampling clock synchronized with the input sampling clock for a while, but after a predetermined time, the data blocks are read. When the time of the syt coincides with the time of the cycle timer 34, the time may be corrected again. As described above, a match is determined only once, a plurality of successive matches, a plurality of matches with a time interval, and the like.
Although there are various modes, it may be appropriately determined according to the strictness of the time management required for actual use. Conversely, in the case of home use where strict time management of audio data is not required and time adjustment is not performed, only a function of obtaining a reproduction sampling clock synchronized with an input sampling clock may be provided. In this case, the second FIFO receiving FIFO 121, the second comparator 33b, and the like are not required.

In the above description, since the reception FIFOs 12k and 121 for the first and second syts and the first and second comparators 33a and 33b are simultaneously operated, two transmission nodes from the two transmission nodes simultaneously operate. Time adjustment of audio data can be performed. In addition to this, the second syt
If one or more devices similar to the reception FIFO 121 are provided, the number of audio data channels that can be synchronized at the same time can be increased, and the time for time adjustment can be shortened. In addition, it is also possible to allocate the same one as the second syt reception FIFO 12l to each of the audio reception FIFOs 12a to 12h without distinguishing whether or not the audio data is from the same transmission node. .

FIG. 3 is a first explanatory diagram showing an example of the operation of the block diagram shown in FIG. In the figures, FIGS. 1 and 2
The same reference numerals are given to the same parts as those described above, and the description is omitted. FIG. 4 is a second explanatory diagram showing an example of the operation of the block configuration diagram shown in FIG. FIG. 7 is a flowchart for explaining the reproduction processing of the receiving node. The specific example illustrated is that shown in FIG. Each transmitting node has two audio channels (for example, a left channel and a right channel) for one block data.

As shown in FIG. 3, audio reception FI
The FO 12a temporarily stores left channel audio data constituting each data block of DA0 to DAf..., And the audio reception FIFO 12b temporarily stores right channel audio data. DA0
Is a data block at a time corresponding to syt = 1000, and DA8 is a data block at a time corresponding to syt = 9000. On the other hand, audio reception FIF
In O12c and 12d, audio data of two channels constituting each data block of DB0 to DBf... Is temporarily stored. DB0 is a data block corresponding to syt = 7000, and DB8 is syt = F00
This is a data block corresponding to 0.

The operation of the audio data reproducing process in the receiving node will be specifically described with reference to the flowchart shown in FIG. The receiving node reproduction process 1 describes the receiving FIFO 12k for syt. In S71, the comparator 3 shown in FIGS.
3a, the time of the cycle timer 34 and the first s
It is determined whether or not the time of the syt after the offset value (assumed to be 0) read from the reception FIFO 12k for yt is added matches the time of the syt. Alternatively, after the first syt reception FIFO 12k previously updated the read pointer,
It is also determined whether a predetermined time has elapsed. When they match,
Alternatively, if the predetermined time has elapsed, the process proceeds to S72; otherwise, the process returns to S71.

If the time of the syt is earlier than the time of the cycle timer 34 of the receiving node (the cycle timer value of the syt is smaller) for some reason, the time of the syt and the time of the cycle Do not match. Therefore, when the predetermined time has elapsed, the process is forcibly advanced to S72, and the next time s is advanced.
yt is read. In the specific example shown in FIG. 3, syt = 1000 is read from the first syt reception buffer 12k. When the time of the cycle timer 34 reaches 1000, the comparator 33a
A coincidence pulse is output as shown in FIG.

In S72 of FIG. 7, the read pointer of the first syt reception FIFO 12k is incremented, and in S73, the first syt reception FIFO1k is read.
Based on the 2k read pointer, the next syt is read, and in S74, the time of the offset is added to the read syt time and sent to the comparator 33a, and the process proceeds to S75. In the specific example of FIG. 3, in S72, s
yt = 9000 is read and sent to the comparator 33a.

In S75 of FIG. 7, the PLL 35 generates a reproduction sampling clock synchronized with the coincidence pulse, and proceeds to S76. At the same time, a receiving node reproduction process 2 described later is executed in parallel. In S76, it is determined whether an error has occurred. For example, the occurrence of an error is detected when the value of the counter for counting the number of received data blocks does not match the value of the DBC included in the CIP header of the packet. Alternatively, based on the received syt, the change (increment value) of the time of the received syt does not match the time interval of the set syt.
Alternatively, the occurrence of an error is detected, for example, when the count value of the number of reproduction sampling clocks in the interval between adjacent coincidence pulses does not match the value (eight) determined by the syt interval (out of phase synchronization in the PLL 35). At the same time, reception of an interrupt packet indicating the occurrence of an error from the transmitting node is also detected. When an error occurs or an interrupt packet is received, S
The process proceeds to S77, otherwise returns to S71 to continue the reproduction process. In S77, the audio output is muted (silenced). When the error recovery processing is performed, reading of the audio reception FIFOs 12a to 12h can be started again when the time of the syt received from each transmission node matches the time of the cycle timer.

In the example shown in FIG. 3, since no error has occurred, the process returns to S71. When the cycle timer 34 of the receiving node next outputs 9000, the comparator 33a outputs a coincidence pulse as shown in FIG. The read pointer of the first syt reception FIFO 12k is incremented again, syt = 11000 is read, and output to the comparator 33a. It operates simultaneously with the reception FIFO 12k for the first syt, and writes the syt of the transmission node B 102. The reception FIFO 121l for the second syt.
Is omitted, but is almost the same as S71 to S77 except that S75 is not provided.

Next, reproduction process 2 of the receiving node will be described. In S78, the audio reception FIFO 12
Acquire and manage the read pointers a to 12h. First, the read pointers of the audio receiving FIFOs 12a and 12b will be described. The data block corresponding to the time of syt when the coincidence pulse is output from the comparator 33a is DA0. Therefore, the read control unit 36 sets the respective read pointers of the audio reception FIFOs 12a and 12b to the position of DA0, and starts reading from DA0. Thereafter, the read pointer is incremented for each reproduction sampling clock output from the PLL 35 via the read control unit 36.

As a result, in FIG. 3, the read pointers of the audio reception FIFOs 12a and 12b are syt
= 1000 is output, and at the time when the coincidence pulse is output, DA0 is at the stored position and DA0
Is read. Next, when the reproduction sampling clock shown in FIG. 4 is output from the PLL 35 via the read control unit 36, the read pointer is incremented and DA1 is read. Similarly, DA2 to DA7 are read out in synchronization with the reproduction sampling clock. When the coincidence pulse shown in FIG. 4 is output when syt = 9000, the audio reception FIFO
The read pointers 12a and 12b are located at positions where DA8 is stored, and DA8 is read. Thereafter, similarly, subsequent data blocks are read.

Next, the audio receiving FIFO 12c,
The 12d read pointer will be described. In FIG. 3, syt =
7000 is read. When the cycle timer 34 of the receiving node outputs 7000, the comparator 33b
The coincidence pulse shown in FIG. 4 is output. This time is the timing at which the audio data read from the audio reception FIFOs 12c and 12d is read in synchronization with the time. Since the data block corresponding to the time of this syt is DB0, the read control unit 36
Sets the read pointers of the audio reception FIFOs 12c and 12d to the position of DB0 and reads DB0.
After that, the read pointer is incremented for each reproduction sampling clock output from the PLL 34.

In S79 of FIG. 7, audio data of one data block is supplied to the patch unit 13 from each of the audio receiving FIFOs 12a to 12f. In the normal mode, one data block is composed of audio data of a plurality of channels output at the same reproduction sampling clock. Each audio data is simultaneously read as parallel data for each reproduction sampling clock. In S80, the patch unit 13
Destination playback channel (audio
0 to audio 7) are supplied with the read audio data.

The patch unit 13 shown in FIG. 1 determines to which reproduction channel the event sequence (audio data) of a plurality of channels is output according to the data structure in the data field in the packet of the received transmitting node or the user setting. Is set. For example, the audio data from the transmission node A101 read from the audio reception FIFOs 12a and 12b is the first audio data.
And the second reproduction channel (audio0, audio1). Audio data of another transmission node B102 and the like is also assigned so as to be output to another reproduction channel at the same time. In S81, the audio data is reproduced and output on each of the reproduction channels (audio0 to audio7) under the conditions (volume, effects, and the like) preset for this channel.

FIG. 5 is a block diagram for explaining an example using a plurality of packet handlers shown in FIG. In the figure, 41 to 43 are packet handlers shown in FIG. In FIG. 5, the master-slave setting terminal S
LV and control input terminal SEQ for simultaneous use
I, the control output terminal SEQO is specified. By setting the SLV terminal of the packet handler 41 to LO, the packet handler 41 is set as a master, and by setting the SLV terminals of the packet handlers 42 and 43 to HI, these are set as slaves. The switching unit 37 of each of the packet handlers 41 to 43 is switched depending on whether it is a master or a slave.

The packet handlers 41 to 43 are commonly connected to the link layer controller 20 by a parallel bus. First, the packet handler 41 serving as a master receives a packet. However, new sending nodes are added,
Alternatively, when a new audio channel is added to an existing transmitting node, the audio receiving FI
When the FOs 12a to 12h run out of space, their own SEQ
Set the O terminal to HI. As a result, the packet handler 42
, The SEQI terminal is set to HI to receive the above-mentioned new transmission node or the above-mentioned packet of the new audio channel.

When the audio receiving FIFOs 12a to 12h are full, the packet handler 42 also sets its SEQO terminal to HI. As a result, the packet handler 43 changes the SEQI terminal to HI and receives the packet. However, the packet handler 43 also sets its SEQO terminal to HI when there is no room in the audio reception FIFOs 12a to 12h. As a result, the master packet handler 41
The QI terminal is set to HI, and the packet is received again.

At this time, if there is a vacancy in the audio reception FIFOs 12a to 12h of the packet handler 41, S
The EQO terminal is LO, and the received packet is processed. However, when there is no free space, the SEQO terminal of the packet handler 41 is set to HI. If there is no free space in all the packet handlers 41 to 43, the SEQO terminals of all the packet handlers 41 to 43 are HI, and new packet reception processing cannot be performed.

The master packet handler 41 outputs the reproduced sampling clock output from the PLL 35 to the PLLin of the packet handler 42 via the switching unit 37 and PLLout. Since the packet handler 42 is a slave, the switching unit 37 is switched to the PLLin side. Therefore, PLLi
The reproduced sampling clock input to n is output to the read control unit 36 and also to PLLin of the packet handler 43 via PLLout. The packet handler 43 is the same as the packet handler 42.

As described above, the reproduction sampling clock is generated by the master, and the slave receives the reproduction sampling clock, thereby causing the packet handler 4 to receive the reproduction sampling clock.
The reproduction sampling clocks 1 to 43 are shared.
However, a configuration for adjusting the generation time of the audio data received by each of the packet handlers 41 to 43 to the cycle timer 34 of the receiving node is required in each of the packet handlers. Therefore, the second s
The time stamps received from the plurality of transmitting nodes are sequentially assigned to the receiving FIFO for yt 121l and output. When a time obtained by adding a predetermined offset value to the time of the time stamp matches the time of the cycle timer 34,
The output of the audio data forming the data block corresponding to the time of the time stamp is read.

The packet handler 4 serving as a slave
2 and 43, the operation of the first syt FIFO 12k and the operation of the PLL 35 become unnecessary, so if these processing functions are stopped, the processing load on the CPU built in the packet handlers 42 and 43 is reduced. And power consumption of hardware can be reduced. Or the first
May be made to perform only the correcting operation. In this case, the time is fixed to a specific transmitting node, and the second synchronizing FIFO 12
1 and the first and second syt FIFOs 1
Syt from a plurality of transmitting nodes may be alternately and sequentially assigned to 2k and 12l to perform the correcting operation.

In the example of FIG. 5, the packet handlers 41 to 4
Although all the devices 3 have the same internal configuration, a packet handler exclusively for master and slave may be manufactured. In this case, a configuration in which unnecessary functions are omitted can be adopted. For example, as can be seen from FIG.
Is unnecessary, a master-specific packet handler does not require a reproduction sampling clock input terminal, and a slave-specific packet handler requires a PLL 35.
Is unnecessary, and the slave-specific packet handler connected to the terminal end like the packet handler 43 does not need the reproduction sampling clock output terminal.

As described above, by simultaneously using a plurality of packet handlers 41 to 43, the system scale can be flexibly changed according to the required specification of the receiving node. This is possible because a plurality of independent audio channel receiving FIFOs 12a to 12h share the link layer controller 20 as the structure of the packet handlers 41 to 43. Also, the transmitting side has a plurality of data input terminals for each of the packet handlers 41 to 43, and each of them can independently generate a packet and output it to one link layer controller 20, so that it is free. A high transmission method becomes possible.

In the above description, the case where all the delay offsets are set to 0 has been described. When always setting the delay offset to 0, the offset register 32
a, 32b and the adders 18a, 18b need not be provided. However, the delay offset registers 32a and 32b shown in FIGS. 1 and 2 are for arbitrarily delaying the read timing when reading the first and second syts from the reception FIFOs 12k and 12l. The value stored in the delay offset register 32a is an offset value set in the reference synchronous reproduction node, and the value stored in the delay offset register 32b is a transmission node to which the second syt reception FIFO performs read control. Is the offset value that is set to The offset values stored in the delay offset registers 32a and 32b can be set from outside the packet handlers 41 to 43. The transmission node can be identified by the isochronous transfer channel number in the isochronous header field.

On the transmitting side, the time syt is set as the value of the reproduction time on the receiving side in consideration of the propagation delay. However, by adjusting the offset value on the receiving side, the reproduction time of the audio data from each transmitting node can be shifted from the syt time. As a result, on the receiving node side, the reproduction time of the audio data to be reproduced can be finely adjusted according to the transmission node or the like from which the sequence data is transmitted. Further, it is possible to normally reproduce sequence data at a past time due to various factors. Adding a delay in anticipation of a propagation delay at the time of transmission means only an expected value. On the other hand, if the delay can be freely set by setting the offset value on the receiving side, it is possible to cope with the delay time as a result of the delay through the actually complicated network.

FIG. 8 is an explanatory diagram of a first transmission / reception operation example of the packet handler shown in FIG. 8A is an explanatory diagram on the transmitting side, FIG. 8B is an explanatory diagram of a packet input / output to / from the link layer controller 20, and FIG. 8C is an explanatory diagram on the receiving side. This will be described with reference to the block diagram of the packet handler shown in FIG. This first transmission / reception operation example is an operation example in which audio data, which is an event sequence of six channels with an input sampling clock of 48 kHz, is packetized. In synchronization with the sampling clock WCKI, audio data D0 and D1 are input from the input terminal DAI0 to the input terminal DAI1.
From the input terminal DAI2
Input audio data D4 and D5, respectively.

One of the 3D sound systems,
Taking "5.1 system" as an example, the front left (FL)
To D0, front right (FR) to D1, rear left (R
L) to D2, rear right (RR) to D3, center (C)
To D4 and the subwoofer (SU) to D5.
In FIG. 8A, audio data of two channels is time-division multiplexed and input to each of the input terminals DAI0 to DAI2.
At 4e, each channel (D0 to D5) is demultiplexed into parallel data and output as audio channels (audio0 to audio5) shown in FIG. Transmission FIFO
8a, when the sampling clock WCKI falls, the data D0 of the sampling cycle (n) is output.
(N), D2 (n), and D4 (n) are written, and when the sampling clock WCKI rises, data D1 (n), D3 (n), and D5 of the sampling period (n) are written.
Write (n).

Subsequently, the sampling clock WCKI
At the falling edge of the data, the data D0 (n + 1), D2 (n + 1), D4 (n + 1) of the sampling cycle (n + 1) are written, and at the rising of the sampling clock WCKI, the data D1 (n +) of the sampling cycle (n + 1) are written.
1), D3 (n + 1), D5 (n + 1) are written, and thereafter, similarly, audio channels (audio0 to audio)
5) Write the audio data. Transmission FIFO 8a
Is the data D at the timing requested by the packetizing unit 9.
0 (n) to D5 (n), D0 (n + 1) to D5 (n +
1), D0 (n + 2) to D5 (n + 2) are sequentially read.

As shown in FIG. 8B, the packetizing section 9
Is a header and data blocks DA0, DA1,
A packet consisting of DA2 is formed, and the parallel data is output to the link layer controller 20. One data block is a unit of 32 bits, and each data block is composed of six event sequences, that is, six channels of audio data. Therefore, the data block size DBS = 6 is put in the header portion.

In FIG. 8 (c), the process on the receiving side is the reverse of that on the transmitting side. Link layer controller 20
Is divided into a header, audio data, non-audio data, syt, and the like in the unpacketizing unit 11 via the link interface 10. For the audio data in the packet shown in FIG. 8B, one data block is separated into six event sequences (six channel audio data) from the header information of DBS = 6. Therefore, the data block DA0 includes a plurality of audio channels D0 (n).
.. D5 (n) (32 bits each) and output.

Subsequently, the data blocks DA1, DA2
Respectively have a plurality of audio channels D0 (n +
1) to D5 (n + 1), D0 (n + 2) to D5 (n +
It is separated and output in 2). Note that the already described 24
In the bit * 4 audio pack format,
Each audio data is converted into 32 bits and output from the unpacketizing unit 11.

The unpacketizing unit 11 converts the audio data D0 to D5 into audio reception FIFOs according to the arrangement order in the data field.
12a to 12f. Receive FI for audio
The FOs 12a to 12f temporarily store 32-bit parallel data. The audio data D0 to D5 read out at the reproduction sampling period are output to the audio reproduction channel 0 in the patch unit 13 as set in advance.
To 7 (audio0 to audio7). In this operation example, D0 is assigned to audio playback channel 0, D1 is assigned to audio playback channel 1, D2 is assigned to audio playback channel 2, and so on.

As shown in FIG. 8C, the audio interface 14b has audio reproduction channels 0,
1 audio data is time-division multiplexed and output terminal DAO
Serial output to 0. Similarly, in the audio interface 14c, the audio data of the audio reproduction channels 2 and 3 are time-division multiplexed and serially output to the output terminal DAO1, and in the audio interface 14d, the audio reproduction channels 4 and 5 are output.
Time-division multiplexes the audio data of
Serial output. As a result, audio data corresponding to FIG. 8A is output.

FIG. 9 is an explanatory diagram of a second transmission / reception operation example of the packet handler shown in FIG. FIG. 9A is an explanatory diagram of a transmitting side, FIG. 9B is an explanatory diagram of a packet input / output to / from a link layer controller, and FIG. 9C is an explanatory diagram of a receiving side. In the second transmission / reception operation example, even if the input sampling clock on the transmitting side remains at 48 kHz, the 3-channel audio data A / D converted by the sampling clock of 96 kHz twice the 48 kHz is packetized and transmitted. This is an operation example in the case of performing. In synchronization with a half cycle of the sampling clock WCK, the audio data D0 from the input terminal DAI0, the audio data D1 from the input terminal DAI1, and the input terminal DAI
2 is serially input with audio data D2.

One of the 3D sound systems,
Taking "2.1 system" as an example, the front left (FL)
To D0, front right (FR) to D1, center (C)
Is assigned to D2. As shown in FIG. 9A, the audio data of three channels is input to the input channel (D0) in the audio interfaces 4b to 4e of FIG.
To D2), the data is converted into parallel data and distributed, and the first to fifth audio channels (audio0 to a
udio5). In the transmission FIFO 8a, when the sampling clock WCKI falls,
Data D0 (n), D1 of sampling period (n)
(N) and D2 (n), and the sampling clock W
At the rise of CKI, the sampling period (n + 1)
Data D0 (n + 1), D1 (n + 1), D2 (n +
Enter 1).

Subsequently, the sampling clock WCKI
At the falling edge of the data, the data D0 (n + 2), D1 (n + 2), D2 (n + 2) of the sampling period (n + 2) are input, and at the rising of the sampling clock WCKI, the data D0 (n + 3) of the sampling period (n + 3).
3), D1 (n + 3), and D2 (n + 3), and thereafter, similarly, the audio channels (audio0 to aud)
Write the audio data of io5). Transmission FIFO8
a indicates the audio data D0 (n) to D2 (n), D0 (n + 1) to D at the timing requested by the packetizer 9.
D2 (n + 1), D0 (n + 2) to D2 (n + 2),.
Read out D0 (n + 5) to D2 (n + 5).

As shown in FIG. 9B, the packetizing section 9
Forms a packet consisting of a header and data blocks DA0-DA5,
Output to One data block is a unit of 32 bits, and each data block has three event sequences,
That is, since it is composed of three channels of audio data, the header section contains a data block size DB.
S = 3 is entered.

In FIG. 9 (c), a process reverse to that of the transmitting unit is performed. The packet output from the link layer controller 20 is divided into a header, audio data, non-audio data, syt, and the like in the unpacketizing unit 11 via the link interface 10. For the audio data in the packet shown in FIG. 9B, one data block is separated into three event sequences (audio channels) from the header information of DBS = 3. Therefore, data block DA0
Are three-channel audio data D0 (n) to D2
(N) (32 bits each) and output. Subsequently, the data blocks DA1 to DA5 are 3
Channel audio data D0 (n + 1) to D2
(N + 1) and output as D0 (n + 2) to D2 (n + 2).

In the unpacketizing section 11, the audio data D is recorded in accordance with the arrangement order in the data field.
0 (n), D1 (n), D2 (n), D0 (n + 1),
D1 (n + 1) and D2 (n + 1) are converted to audio reception F
Assigned to IFOs 12a to 12f. Similarly,
The next audio data D0 (n + 2), D1 (n +
2), D2 (n + 3), D0 (n + 4), D1 (n +
4), D2 (n + 4) is again converted to the audio reception FI
The signals are supplied to the FOs 12a to 12f. The audio data D0 to D2 temporarily stored as 32-bit parallel data in the reception FIFOs 12a to 12f for audio are A / D signals at a sampling cycle of 96 kHz.
It has been converted.

In the patch section 13, audio reproduction channels 0 to 5 (audi
o0 to audio7). In this operation example, D0 stored in the audio reception FIFO 12a is assigned to the audio channel 0,
D0 stored in b is assigned to audio channel 1, D1 stored in the reception FIFO for audio 12c is assigned to audio channel 2, and so on.

As shown in FIG. 9C, in the audio interface 14b, the audio data of the audio channels 0 and 1 are time-division multiplexed and serially output to the output terminal DA0. Similarly, in the audio interface 14c, the audio data of the audio channels 2 and 3 are time-division multiplexed and serially output to the output terminal DA1, and in the audio interface 14d, the audio data of the audio channels 4 and 5 are time-division-multiplexed. They are multiplexed and serially output to the output terminal DA2. As a result, audio data corresponding to FIG. 9A is output, so that even if the reproduction sampling clock remains at 48 kHz, 96 kHz is output.
A / D-converted audio data D0 to D2 can be read at the sampling period of.

Switching between the two transfer modes as shown in FIGS. 8 and 9 can be performed by using information contained in the header portion of the packet format shown in FIG. At that time, it is also possible to identify the two transfer modes by the value of DBS. As described above, the patch unit 13
Is an audio receiving FIFO 1 according to the transfer mode.
Output destinations of the audio data stored in 2a to 12f are assigned. In one transfer mode, the patch unit 13 can change the assignment destination of the audio data by changing the assignment according to the user setting in the receiving node. For example, in the “5.1 system” described above, the left channel (FL, RL) and the right channel (FR, RR) are exchanged, or the front channel (FL, FR) and the rear channel (RL, RR) are replaced. The sound image localization can be changed by exchanging.

The two transfer modes shown in FIG. 8 and FIG.
Utilizing the fact that the sampling clock has a duty ratio of 50%, two pulses per sampling period are synchronized with the rising and falling of the sampling clock.
The sample was externally input or output by time division multiplexing. In this case, there is an advantage that input and output can be easily performed in synchronization with the sampling clock signal. Instead, m samples (m is a natural number of 3 or more) per sampling cycle are externally input or output by time division multiplexing. Similarly, in addition to the transfer mode of the reproduction sampling clock f _s kHz, , it can be provided the transfer mode of reproduction sampling clock m × f _s kHz.

In the above description, the audio reception FI
The event sequence (audio data) temporarily stored in one of the FOs 12a to 12h is one-channel audio data. However, the event sequence (audio data) of a plurality of channels is defined as one unit, and the unit event sequence is defined as the audio reception FIFO 12.
a to 12h may be temporarily stored.
For example, time-division multiplexed and input to one input terminal, time-division multiplexed and output to one output terminal,
For example, audio channels 0 and 1 (audio0, audio
1) Audio channels 6, 7 (audio 6, aud)
io7) is defined as one unit, and the unit audio channel is set to the same audio reception FIFOs 12a and 12a.
You may make it memorize | store temporarily in b, 12c, 12d.

In the above description, the audio data sampling clock is used as the input timing clock on the transmitting node side and the reproduction timing clock on the receiving side. However, this sampling clock is n times (n is 2).
As a timing clock having a frequency of the above (natural number) or 1 / n times, one data block may be configured using this timing clock as a unit.

[0091]

As is apparent from the above description, the present invention has an effect that a packet including event sequence data such as audio and music data is transmitted and received, and an error can be dealt with.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a packet handler according to an embodiment of a packet transfer device of the present invention.

FIG. 2 is a block diagram illustrating a receiving node reproducing process of the packet handler according to the embodiment of the present invention.

FIG. 3 is a first explanatory diagram showing an example of the operation of the block configuration diagram shown in FIG. 2;

FIG. 4 is a second explanatory diagram showing an example of the operation of the block configuration diagram shown in FIG. 2;

FIG. 5 is a block diagram for explaining an example in which a plurality of packet handlers shown in FIG. 1 are used.

FIG. 6 is a flowchart for explaining an outline of the operation of the packet handler shown in FIG. 1;

FIG. 7 is a flowchart illustrating a reproduction process of a receiving node.

FIG. 8 is an explanatory diagram of a first transmission / reception operation example of the packet handler shown in FIG. 1;

FIG. 9 is an explanatory diagram of a second transmission / reception operation example of the packet handler shown in FIG. 1;

FIG. 10 is an explanatory diagram showing a flow of a packet on a network.

FIG. 11 is an explanatory diagram of a packet format at the time of isochronous transfer.

FIG. 12 is a diagram illustrating the operation of isochronous transfer.

[Explanation of symbols]

1 transmitting section, 2 receiving section, 4a-4e audio interface, 5 CPU interface, 6 CP
U bus, 11 unpacketizing unit, 12a to 12h audio receiving FIFO, 12i, 12j non-audio receiving buffer, 12k, 12l syt receiving buffer, 13 patch unit, 14a to 14e audio interface unit, 16a, 16b switching unit , 18a, 1
8b adder, 19 synchronization unit

Claims (2)

(57) [Claims] 1. A packet including one or a plurality of data blocks composed of a plurality of event sequence data and having a time stamp added for each predetermined number of the data blocks is transmitted to a desired one or more nodes on a network. A packet transfer device for transmitting the data block, based on the time of the time stamp, calculating means for calculating the input timing cycle of the data block, the difference between the output of the calculating means and a preset cycle is an allowable range A packet transfer device comprising: an error processing unit that stops transmission of the packet including the data block when the number of packets exceeds the threshold value and transmits the packet indicating occurrence of an error. 2. The method according to claim 1, further comprising one or more data blocks each including one or more event sequence data,
A packet transfer device for receiving a packet to which a time stamp is added for each predetermined number of data blocks from a desired one or more transmitting nodes on a network, wherein a timing error is detected based on a time of the received time stamp. A packet transfer device comprising: an error processing unit that mutes the output of the event sequence data that constitutes the data block when the packet is detected and when a packet indicating the occurrence of an error is detected.