JP2000078170A - Communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To synchronize data to be communicated among plural communication nodes by generating second synchronizing information, for which a maximum transfer delay amount is added to first synchronizing information generated by a timer, and transmitting a sample count and second synchronizing information to a network at every prescribed timing. SOLUTION: The second synchronizing information, for which the maximum transfer delay amount is added to the first synchronizing information generated by the timer, is generated and the sample count corresponding to timing and the second synchronizing information are transmitted to the network at every prescribed timing. On this network, maximum delay time SYT-OFFSET is added to a WC packet 5. With a sample count axis as a reference, the nodes are synchronized. For example, a WC master node 1 transmits a WC packet 5 to first and second transmission nodes 2 and reception nodes 3. The first and second transmission nodes 2 respectively transmit data packets 6 to the reception nodes 3 corresponding to the WC packet 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to communication technology.
More particularly, the present invention relates to a communication technique for synchronizing a plurality of communication devices.

[0002]

2. Description of the Related Art Digital serial communication conforming to the IEEE 1394 standard is becoming widespread. In the IEEE 1394 standard,
A network can be configured by connecting a plurality of communication nodes. For example, one receiving node can receive audio data from a plurality of transmitting nodes.

[0003] It is assumed that the first and second transmitting nodes simultaneously transmit data to one receiving node. In this case, the time at which the receiving node receives from the first transmitting node and the time at which the receiving node receives from the second transmitting node usually differ due to a difference in distance between the nodes and the like. For example, data is received from a first transmitting node, and then data is received from a second transmitting node.

[0004] Each of the transmitting node and the receiving node has its own cycle timer. Each cycle timer is not synchronized. It is difficult for the receiving node to synchronize data received from the first transmitting node with data received from the second transmitting node.

[0005] One transmitting node may transmit the same data to the first and second receiving nodes almost simultaneously. However, as described above, the time when the first receiving node receives and the time when the second receiving node receives are usually different. Since the first and second receiving nodes reproduce the received data in accordance with their own cycle timers, the reproduction process of the first and second receiving nodes is likely to be shifted.

[0006]

SUMMARY OF THE INVENTION It is difficult for a receiving node to synchronize data transmitted from a plurality of transmitting nodes. Further, when the transmitting node transmits data to a plurality of receiving nodes, it is difficult to synchronize the plurality of receiving nodes.

An object of the present invention is to provide a communication device which can synchronize data to be communicated between a plurality of communication nodes.

[0008]

According to one aspect of the present invention, a timer for generating first synchronization information, and a second synchronization information including a maximum transfer delay added to the first synchronization information generated by the timer. There is provided a communication apparatus comprising: a generation unit configured to generate synchronization information; and a transmission unit configured to transmit a sample count corresponding to a predetermined timing and the second synchronization information to a network at each predetermined timing.

According to another aspect of the present invention, the first
Receiving means for receiving the first synchronization information, generating means for generating the second synchronization information in which the maximum transfer delay amount is added to the first synchronization information received by the receiving means, and the second synchronization information and the corresponding A communication unit for transmitting data to be transmitted to a network.

According to another aspect of the present invention, the first
First receiving means for receiving the synchronization information and the data corresponding thereto, second receiving means for receiving the second synchronization information from the outside, and first synchronization information received by the first receiving means. Processing means for performing a first synchronization adjustment based on the second synchronization information based on the second synchronization information received by the second reception means and processing data received by the first reception means; Is provided.

According to another aspect of the present invention, first synchronization information generating means for generating first synchronization information and first synchronization information generated by the first synchronization information generating means are transmitted via a network. Second synchronization information generating means for generating second synchronization information based on the first synchronization information in consideration of a transfer maximum delay amount when transferring to another communication device, and the second synchronization information. Transmitting means for transmitting the second synchronization information generated by the generation means to the network, and directly receiving the second synchronization information generated by the second synchronization information generation means without passing through the network; And a processing unit for processing data based on the communication device.

According to another aspect of the present invention, a first receiving means for receiving first synchronization information from an external communication device, a second receiving means for receiving second synchronization information from outside, Measuring means for measuring the arrival delay time of the first synchronization information received by the first receiving means from the external communication device; and the first or second synchronization information according to the arrival delay time measured by the measuring means. Determining means for determining a correction value of the information, and the first or second receiving means receiving the first or second synchronization information each time the first or second synchronization information is received, in accordance with the correction value determined by the determining means. A communication device having a correction unit for correcting the second synchronization information is provided.

[0013]

FIG. 1 is a block diagram showing a configuration of a communication network according to a first embodiment of the present invention.
In the present embodiment, “audio” conforming to the IEEE 1394 standard is used.
and music data transmission protocol ".
It is preferable to perform the transfer by isochronous packet transfer of the EEE1394 standard.

An IEEE 1394 bus 4 has a word clock (WC) master node 1 and a WC slave node 2,
3 are connected. The WC slave node 2 is a transmitting node (hereinafter, referred to as a Tx node), and the WC slave node 3 is a receiving node (hereinafter, referred to as an Rx node). A plurality of Tx nodes 2 and / or a plurality of Rx nodes 3 may be connected to the bus 4.

WC master node 1 has a cycle timer 1a
Tx node 2 has a cycle timer 2a, and Rx
The x node 3 has a cycle timer 3a. The cycle timers 1a, 2a, 3a are basically counters operating at about 25 MHz.

The WC master node 1 is connected via a bus 4
The WC packet 5 is transmitted to the Tx node 2 and the Rx node 3. The WC packet 5 is a packet for synchronization, and includes a system time 5a and a sample count 5b.

The WC master node 1 sequentially transmits, for example, WC packets 5-24, 5-32, and 5-40 at predetermined intervals. The WC packet 5-24 is a packet for synchronizing the audio data of the 24th sample. W
The C packets 5-32 and 5-40 are packets for synchronizing the audio data of the 32nd sample and the 40th sample, respectively.

The Tx node 2 adjusts the timing according to the WC packet 5 received from the WC master node 1,
The data packet 6 is transmitted to the Rx node 3 via the bus 4. Data packet 6 has a D indicating a sample count.
It includes a BC 6a and eight sample data 6b.

The Tx node 2 has a data packet 6
-24, 6-32, 6-40, etc. are sequentially transmitted to the Rx node 3 at predetermined intervals. The data packet 6-24 is the 24th data packet.
Includes audio data 6b of .about.31 samples. The data packets 6-32 and 6-40 are the 32nd to 3rd, respectively.
It includes audio data 6b of 9 samples and 40th to 47th samples.

The Rx node 3 adjusts the timing according to the WC packet 5 received from the WC master node 1,
The sample data (for example, audio data) 6b in the data packet 6 received from the Tx node 2 is reproduced.

FIG. 2 is a timing chart for explaining the operation of Tx node 2.

First, a method of generating the data packet 6-24 (FIG. 1) will be described. The Tx node 2 has 8 samples from the 24th sample data D24 to the 31st sample data D31.
Pieces of data are generated as one data packet 6b. The interval SYT_INTERVAL is a cycle for generating a packet.

The cycle timer 2a increases a 32-bit cycle time value as time passes. Here, the 24th, 32nd, and 40th sample data D24, D3
2, the cycle time of D40 is CT24, CT
32 and CT40.

The system times SYT24, SYT32 and SYT40 correspond to the cycle times CT24 and CTS, respectively.
It is the value of the lower 16 bits of T32 and CT40.

The DBC 6a indicates a sample count.
For example, since the head data of the data packet 6b is the 24th sample data D24, the value of the DBC 6a corresponding to the data packet 6b is 24.

The data packet 6 (FIG. 1) has a DBC 6a
And a data packet 6b. A system time SYT24 may be included instead of the DBC 6a. The system time SYT24 indicates the timing of the first sample data D24 of the data packet 6b as described above.

The data packet 6-32 (FIG. 1) can be generated in the same manner as described above. Tx node 2
From the sample data D32 to the 39th sample data D39
The above eight data are generated as one data packet 6b. Since the head data of the data packet 6b is the 32nd sample data D32, the value of the DBC 6a corresponding to the data packet 6b is 32. Instead of the DBC 6a, the system time SYT32
May be used. The DBC and the system time (SYT) are based on "aud" conforming to the IEEE 1394 standard.
io and music data transmission protocol ", which is included in the CIP header for isochronous packet transfer. DBC is 8 bits, and SYT is 16 bits.

FIG. 3 is a timing chart showing the operation between the nodes in FIG.

The WC master node 1 stores the sample data 2
WC packet 5 indicating the timing of 4, 32, 40, etc.
24, 5-32, 5-40, etc. are sequentially transmitted to the Tx node 2 and the Rx node 3. The transmission interval of the WC packet 5 is the interval SYT_INTERVAL (see FIG. 2).

The maximum communication time from when the WC packet 5 reaches the Tx node 2 or the Rx node 3 from the WC master node 1 is SYT_OFFSET. Time SYT_O
FFSET is the maximum delay time (transfer delay) determined by the IEEE 1394 standard, and is 352
μs. That is, when a packet is transmitted from a certain node to another node, it is guaranteed that the packet will arrive within 352 μs at the latest.

The WC packet 5 has a maximum delay time SYT_
OFFSET is added. That is, the WC packet 5-24 includes a sample count 5b indicating the 24th sample count and a corresponding system time SYT.
24 (FIG. 2) shows the maximum delay time SYT_OFFSE.
And a system time WC_SYT 24 to which T has been added. System time WC_SYT24 = SYT24 + S
YT_OFFSET. Similarly, the maximum delay time SYT_OFFSET is also used for the WC packets 5-32 and 5-40.
Is added.

The vertical axis of the WC master node 1 in FIG. 3 indicates the sample count 5b in the WC packet 5 transmitted by itself.
Shows the value of The vertical axis of each of the Tx node 2 and the Rx node 3 indicates the value of the sample count 5b in the WC packet 5 received from the WC master node 1. Three nodes 1,
Steps 2 and 3 perform processing based on the axis of the sample count. The sample count axis corresponds to the time axis.
The axes of the three nodes have different absolute times but the same relative times. Tx node 2 and Rx node 3 can be synchronized based on their respective sample count axes.

The WC master node 1 transmits, for example, a WC packet 5-32 to the Tx node 2 and the Rx node 3. The WC packet 5-32 includes the maximum delay time SYT_OFF in the sample count 5b indicating the 32nd sample count and the corresponding system time SYT32.
System time WC_ with SET (352 μs) added
SYT32.

When receiving the WC packet 5-32, the Tx node 2 adds the offset value S to the 32nd sample count.
A data packet 6-49 including the 49th (= 32 + 17) sample data to which AMPLE_OFFSET (for example, 17 samples) is added is transmitted. In the data packet 6-49, the DBC 6a is 49, and the sample data 6b is the 49th to 56th sample data.

Offset value SAMPLE_OFFSET
Adding (for example, 17 samples) takes into account the maximum communication delay time of the data packet 6 from the Tx node 2 to the Rx node 3, and means transmitting the sample data 17 samples ahead. That is, if the sample count 5b in the WC packet 5 is 32, the Tx node 2 transmits the data packet 6-49 in which the sample data of the sample count value obtained by adding 17 samples to the value is the head.

The fact that the maximum communication delay time is equivalent to 17 samples will be described. As described above, the maximum communication delay time SYT_OFFSET is 352 μs. The sampling frequency of audio data is, for example, 48 kHz.
It is.

The number of samples in this case is 48 kHz × 3
52 μs = 16.896. Therefore, the sample offset value must be equal to or greater than 16.896 samples. The sample offset value is preferably 17 samples as the minimum integer.

The Rx node 3 has already received the data packet 6-49 from the Tx node 2 when the sample count is 49 at the latest. The total delay time of the above communication is T1 + T2. The delay time T1 is equal to the WC packet 5-3 from the WC master node 1 to the Tx node 2.
2 is the communication time. The delay time T2 is a communication time of the data packet 6-49 from the Tx node 2 to the Rx node 3.

The Rx node 3 stores the received data packet 6-49 in a first-in first-out buffer (FIFO), and starts the reproduction process of the data packet 6-49 when the sample count reaches 49. By storing the packet in the FIFO and waiting for the processing until the sample count reaches 49, the delay time T1 + T2 can be absorbed.

As described above, the WC packet 5-32 is
The maximum delay time SYT_OFFSET includes the offset system time WC_SYT32. The maximum delay time SYT_OFFSET is an offset value for absorbing the communication delay time T1.

It is assumed that the system time offset value SYT
_OFFSET WC packet 5-3 without offsetting
If the Rx node 3 receives the WC packet 5-32, the system time corresponding to 32 of the sample count has already passed, and
It cannot be processed.

The data packet 6-49 includes the DBC 6a offset by the sample count offset value SAMPLE_OFFSET. This offset value SAM
PLE_OFFSET is an offset value for absorbing the communication delay time T2.

It is assumed that the sample count offset value SA
If the data packet 6-32 is transmitted without offsetting the MPLE_OFFSET, when the Rx node 3 receives the data packet 6-32, the sample count of 32 has already passed, and processing cannot be performed.

FIG. 4 is a flowchart showing the processing of the WC master node 1.

At Step SA1, the register sampl
Add a constant SYT_INTERVAL to ecount. The register sample count is a register for storing a count value of the number of samples of audio data. The constant SYT_INTERVAL is the number of samples in one packet, for example, eight. This register sample count corresponds to the sample count 5b in the WC packet 5 of FIG.

Next, the value obtained by adding the offset value SYT_OFFSET to the system time SYT (FIG. 2) is stored in the register syt. The system time SYT is, for example, the SYT 24 in FIG. Offset value SYT_OFF
SET is the maximum delay time, for example, 352 μs. By adding the offset value SYT_OFFSET, the delay time T1 shown in FIG. 3 can be absorbed. This register syt corresponds to the system time 5a in the WC packet 5 in FIG.

In step SA2, as shown in FIG.
A WC packet 5 is generated using the register sample count as the sample count 5b and the register syt as the system time 5a, and sent out onto the bus 4.

Although the above has described the processing for generating one packet, the WC master node 1 repeats the above processing at predetermined time intervals, for example, the WC packets 5-24, 5-3.
2, 5-40, etc. are sequentially transmitted.

The WC packet 5-24 has a system time 5a whose WC_SYT24 (= SYT24 + SYT_OF).
FSET), and the sample count 5b is 24. The WC packet 5-32 has a system time 5a of W
C_SYT32 (= SYT32 + SYT_OFFSE
T), and the sample count 5b is 32.

FIG. 5 is a block diagram showing a configuration example of the first Tx node 2.

The Tx node 2 has an IEEE 1394 interface system 11 and a node system 12.

The WC packet 5 includes the system time 5a and the sample count 5b, and is a packet received from the WC master node 1. Sample count FIFO
13 stores the sample count 5b on a first-in first-out basis. System time FIFO14
Stores the system time 5a on a first-in first-out basis.

The system time comparator 15 has a FIFO1
4 outputs the system time 5a and the cycle timer 2a
Are compared with the lower 16 bits of the cycle time output by. The cycle time is 32 bits. The system time 5a includes a maximum delay time SYT_OFFSET (35) in the lower 16 bits of the cycle time of the WC master node 1.
2 μs).

The system time 5a is the maximum delay time SY
Since T_OFFSET has been added, the cycle time is longer than the cycle time of the cycle timer 2a. The cycle timer 2a sequentially increments the cycle time at about 25 MHz.

Eventually, the cycle time coincides with the system time 5a. When the two match, the comparator 15 outputs a match signal. Processing shown later is waited until the coincidence signal is output. By making the subsequent processing wait, the WC
Communication delay time T from master node 1 to Tx node 2
1 (FIG. 3) can be absorbed. When transmitting the WC packet 5 from the WC master node 1 to the plurality of Tx nodes 2, it is possible to absorb the difference in the reception time of each Tx node 2.

A phase-locked loop circuit (PLL)
16 is, for example, 48 kHz in synchronization with the above coincidence signal.
The word clock WCK for audio is generated and supplied to the node system 12.

When the timing adjuster 17 receives the above coincidence signal, the sample adjuster 5 in the FIFO 13
b is output to the adder 18. The adder 18 adds the offset value SAMPLE_OFFSET to the sample count 5b.
(For example, 17 samples) and outputs a sample count SCN. For example, if the sample count 5b is 3
In the case of 2, the adder 18 calculates the sample count SCN = 32
+ 17 = 49 is output. By adding the offset value, the preparation for absorbing the communication delay time T2 (FIG. 3) from the Tx node 2 to the Rx node 3 is completed. Absorption of the communication delay time T2 is performed by an Rx node 3 (FIG. 7) described later.

The node system 12 uses the word clock W
In synchronization with CK, the sample count SCN (for example, 4
9), eight sample data (for example, 49th to
The 56th sample data) is read as data SDT and stored in the data FIFO 19 on a first-in first-out basis.

The DBC generator 20 generates a DBC according to the sample count SCN in synchronization with the word clock WCK.

The DBC 6a is generated by the DBC generator 20. The sample data 6b is stored in the FIFO 19
Is generated on the basis of the sample data SDT.

The data packet 6 is generated by packetizing the DBC 6a and the sample data 6b. Data packet 6 is transmitted from Tx node 2 to Rx node 3.

It is to be noted that the sampler 5b
Not limited to the case where the value SCN obtained by adding the offset value SAMPLE_OFFSET to the node system 12 is used, the sample count 5b may be directly supplied. In this case, the node system 12 needs to perform processing in consideration of the offset value SAMPLE_OFFSET.

The sample count SCN is not limited to being supplied to the node system 12 for each packet, but may be supplied for each sample.

FIG. 6 is a flowchart showing the processing of the Tx node 2. Processing SB1 on the left side of the flowchart
SB8 indicates processing of the interface system 11, and processing SB9 on the right side indicates processing of the node system 12.

At step SB1, the system time 5a and the sample count 5b in the WC packet 5 are stored in FIFOs 14 and 13, respectively.

In step SB2, the comparator 15 compares the system time with the cycle time, and waits until the two match. If they match, the process proceeds to Step SB3.

At step SB3, the next system time stored in the FIFO 14 is loaded into the comparator 15 to prepare for the next comparison.

At step SB4, the PLL 16 generates the word clock WCK.

In step SB5, the adder 18 sets the sample count 5b and the offset value SAMPLE_OFFS
ET is added, and the added value SCN is output to the node system 12.

Next, the interface system 11 processes step SB6, and the node system 12 executes step SB6.
Process B9.

At Step SB6, a DBC is generated based on the generated sample count SCN. If necessary,
The generated DBC is stored in the FIFO. Next, the process proceeds to step SB7.

At step SB9, the sample data SDT corresponding to the input sample count CNT is supplied to the interface system 11. Next, step SB
Proceed to 7.

At step SB7, sample data SDT is received from the node system 12.

At Step SB8, the sample data SD
T and DBC are packetized and the data packet 6 is transmitted to the Rx node 3.

FIG. 7 is a block diagram showing a configuration example of the first Rx node 3.

The Rx node 3 has an IEEE 1394 interface system 31 and a node system 32.

The WC packet 5 includes the system time 5a and the sample count 5b, and is a packet received from the WC master node 1. Sample count FIFO
33 stores the sample count 5b on a first-in first-out basis. System time FIFO 34
Stores the system time 5a on a first-in first-out basis.

The system time comparator 35 is a FIFO3
4 outputs the system time 5a and the cycle timer 3a
Are compared with the lower 16 bits of the cycle time output by. The system time 5a includes a maximum delay time SYT_O in the lower 16 bits of the cycle time of the WC master node 1.
This is a value obtained by adding FFSET (325 μs).

When the cycle time matches the system time 5a, the comparator 35 outputs a match signal. Processing shown later is waited until the coincidence signal is output. By making the subsequent processing wait, the communication delay time from the WC master node 1 to the Rx node 3 can be absorbed. W
When transmitting the WC packet 5 from the C master node 1 to the plurality of Rx nodes 3, it is possible to absorb the difference in the reception time of each Rx node 3.

The PLL 36 synchronizes with the above-mentioned coincidence signal and, for example, a 48 kHz audio word clock W.
CK is generated and supplied to the node system 32.

When the timing adjuster 37 receives the above coincidence signal, the sample adjuster 5
b as the sample count SCN and the node system 32
Supply to

The data packet 6 includes the DBC 6a and the sample data 6b, and is a packet received from the Tx node 2. The DBC-FIFO 40 stores the DBC 6a on a first-in first-out basis. Data FI
The FO 39 stores the sample data 6b on a first-in first-out basis.

The DBC comparator 38 calculates the sample count 5b output from the FIFO 33 and the D count output from the FIFO 40.
Compare BC6a. The DBC 6a is a value obtained by adding the offset value SAMPLE_OFFSET (for example, 17) to the sample count 5b by the adder 18 of the Tx node 2 in FIG.

The DBC 6 a is larger than the sample count 5 b of the FIFO 33 because the offset value is added. The FIFO 33 outputs the value of the input sample count 5b, and then outputs a value obtained by sequentially incrementing the sample count.

Eventually, the DBC and the sample count match. When the two match, the comparator 38 outputs a match signal. Until the coincidence signal is output, the data FIFO 39
The reading process of the data in is waited. By causing the read process to wait, the Tx node 2 changes to the Rx node 3
3 can be absorbed. When transmitting the data packet 6 from the Tx node 2 to the plurality of Rx nodes 3, it is possible to absorb the difference in the reception time of each Rx node 3.

Data FIFO 39 and DBC-FIFO
Reference numeral 40 controls a read pointer (address) based on the comparison result of the comparator 38.

When the comparator 38 outputs the coincidence signal, the sample data is read out from the data FIFO 39 and output to the timing adjuster 41.
The next DBC in the FIFO 40 is set.

The timing adjuster 41 supplies the data output from the FIFO 39 to the node system 32 as sample data SDT in synchronization with the word clock WCK.

The node system 32 uses the word clock W
In synchronization with CK, the sample data (audio data) SDT is reproduced according to the sample count SCN,
Make the speaker sound.

The WC packet 5 may use a DBC instead of the sample count 5b. In that case, F
DBC is stored in the IFO 33, and the comparator 38
The DBC in O33 and the DBC in FIFO 40 are compared.

Further, when the Rx node 3 starts receiving,
It is necessary to control the read pointers of the data FIFO 39 and the DBC-FIFO 40 to predetermined values. In particular,
The head DBC value of the DBC-FIFO 40 is compared with the head sample count value of the sample count FIFO 33, and the data FIFO 39 and the DBC-F are sampled.
Each read pointer of the IFO 40 is controlled. As a result, the sample count SCN and the corresponding sample data SDT can be supplied to the node system 32 at a predetermined timing.

According to the IEEE 1394 standard, data for a plurality of channels can be transferred in an isochronous packet. When data exists for multiple channels,
A plurality of the above read pointer controllers may be provided.
One read pointer controller may be switched to control one channel at a time. When data exists for a plurality of channels, the data FIFO 39 is required for the number of channels.

FIG. 8 is a flowchart showing the processing of the Rx node 3.

At step SC1, the system time 5a and the sample count 5b in the received WC packet 5
Are stored in FIFOs 34 and 33, respectively.

At step SC2, when data packet 6 is received, DBC 6a and sample data 6b in packet 6 are stored in FIFOs 40 and 39, respectively.

At step SC3, the comparator 35 compares the system time with the cycle time, and waits until the two match. If they match, the process proceeds to step SC4.

At step SC4, the next system time stored in the FIFO 34 is loaded into the comparator 35, and preparation for the next comparison is made.

At step SC5, the PLL 36 generates the word clock WCK.

At step SC6, the comparator 38 sets the FIF
Sample count in O33 and DBC in FIFO40
And adjust the read pointers of the FIFOs 39 and 40 according to the comparison result.

At step SC7, the sample data SDT is read from the FIFO 39 based on the adjusted pointer, and is supplied to the node system 32. And FIFO
The sample count SCN in 33 is read and supplied to the node system 32.

In the first embodiment, as shown in FIG. 3, synchronization between nodes is established by using the sample count axis as a reference. First and second two transmitting nodes 2
Transmits a data packet 6 to one receiving node 3. The WC master node 1 transmits a WC packet 5 to the first and second transmitting nodes 2 and the receiving node 3. The first and second transmitting nodes 2 each transmit a data packet 6 to the receiving node 3 according to the WC packet 5. For example, the first transmitting node transmits a tone played at the first performance hall as audio data in real time, and the second transmission node transmits a tone played at the second performance hall in real time. . The receiving node can synchronously reproduce the audio data received from the first and second transmitting nodes, respectively.
Thereby, the joint performance at the first and second performance venues becomes possible.

Next, a second embodiment will be described. In the second embodiment, synchronization between nodes is obtained by using the system time axis as a reference instead of the sample count axis.

FIG. 9 is a block diagram showing a configuration example of the second Tx node 2.

In the second embodiment, as shown in FIG.
The system time 6c is used instead of the BC 6a. That is, the data packet 6 includes the system time 6c and the sample data 6b.

The Tx node 2 has an IEEE 1394 interface system 51 and a node system 52.

The WC packet 5 includes a system time 5a and a sample count 5b. Sample Count FI
The FO 53 stores the sample count 5b on a first-in first-out basis. System time FIFO5
4 stores the system time 5a on a first-in first-out basis.

The system time comparator 55 has a FIFO5
4 outputs the system time 5a and the cycle timer 2a
Are compared with the lower 16 bits of the cycle time output by. The system time 5a includes a maximum delay time SYT_O in the lower 16 bits of the cycle time of the WC master node 1.
This is a value obtained by adding FFSET (352 μs).

When the cycle time matches the system time 5a, the comparator 55 outputs a match signal. Processing shown later is waited until the coincidence signal is output. By making the subsequent processing wait, the communication delay time T1 (FIG. 3) from the WC master node 1 to the Tx node 2 can be absorbed.

The PLL 56 synchronizes with the above-mentioned coincidence signal, for example, a 48 kHz audio word clock W.
CK is generated and supplied to the node system 52.

When the timing adjuster 57 receives the coincidence signal, the timing adjuster 57 sets the sample count in the FIFO 53 to 5
b as the sample count SCN
To supply.

The node system 52 uses the word clock W
In synchronization with CK, the sample count SCN (for example, 4
9), eight sample data (for example, 49th to
The 56th sample data) is read as data SDT and stored in the data FIFO 59 on a first-in first-out basis.

The timing adjuster 100 controls the system time 5 output from the system time FIFO 54 as described above.
The value of a (the value matched by the comparator 55) is supplied to the adder 58 at the timing matched by the comparator 55. Adder 58
Is the offset value SYT_OFF at the system time 5a.
SET (for example, system time corresponding to 17 samples) is added and stored in the system time FIFO 60 on a first-in first-out basis. By adding the offset value, the preparation for absorbing the communication delay time T2 (FIG. 3) from the Tx node 2 to the Rx node 3 is completed. The absorption of the communication delay time T2 is performed by the Rx node 3 described later.
(FIG. 11).

The data packet 6 is generated based on the system time 6a in the FIFO 60 and the sample data 6b in the FIFO 59. Data packet 6 is transmitted from Tx node 2 to Rx node 3.

FIG. 10 is a flowchart showing the processing of the second Tx node 2 (FIG. 9). Processes SD1 to SD7 on the left side of the flowchart show processes of the interface system 51, and process SD8 on the right side shows processes of the node system 52.

At step SD1, the system time 5a and the sample count 5b in the WC packet 5 are stored in FIFOs 54 and 53, respectively.

At step SD2, the comparator 55 compares the system time with the cycle time, and waits until the two match. If they match, the process proceeds to step SD3.

At step SD3, the next system time stored in the FIFO 54 is loaded into the comparator 55 to prepare for the next comparison.

At step SD4, the PLL 66 generates the word clock WCK.

At step SD5, the sample count SCN in the FIFO 53 is supplied to the node system 52.

Next, the interface system 51 processes step SD6, and the node system 52 executes step S6.
Process D8.

In step SD6, the adder 58 sets the coincident system time 5a and the offset value SYT_O
The FFSET is added, and the added value is stored in the FIFO 60. Next, the process proceeds to step SD7.

At step SD8, sample data SDT corresponding to the input sample count SCN is supplied to the interface system 51. Next, step SD7
Proceed to.

At Step SD7, the sample data SD
T and the system time are packetized, and the data packet 6 is transmitted to the Rx node 3 via the bus 4.

FIG. 11 is a block diagram showing a configuration example of the second Rx node 3. As shown in FIG.

In the second embodiment, the first embodiment (FIG. 7)
Unlike the data packet 6, the data packet 6 includes a system time 6c instead of the DBC 6a. The data packet 6 includes a system time 6c and sample data 6b.

The Rx node 3 has an IEEE 1394 interface system 71 and a node system 72.

The received data packet 6 includes a system time 6c and sample data 6b. The system time FIFO 80 stores the system time 6c on a first-in first-out basis. Data FIFO 79
Stores the sample data 6b in a first-in first-out manner.

The system time comparator 78 has a FIFO8
System time 5c output by 0 and cycle timer 3a
Compare the cycle times output by. The system time 6c is a value obtained by adding the offset value SYT_OFFSET to the system time 5a by the adder 58 of the Tx node 2 in FIG.

The system time 6c is equal to the offset value SY
Since T_OFFSET is added, the initial value is larger than the value of the cycle time of the cycle timer 3a. The cycle timer 3a sequentially increments the cycle time.

When the system time 6c and the cycle time match, the comparator 78 outputs a match signal. Until the coincidence signal is output, the process of reading the data in the data FIFO 79 is waited. Due to this waiting, the communication delay time T2 from the Tx node 2 to the Rx node 3 (FIG. 3)
Can be absorbed.

When the timing adjuster 81 receives the coincidence signal from the comparator 78, it reads the sample data from the data FIFO 79 and stores it in the data FIFO 73.
When the comparator 78 outputs the coincidence signal, the next system time within the system time 80 is set in the comparator 78.

The received WC packet 5 includes a system time 5a and a sample count 5b. The system time FIFO 74 stores the system time 5a on a first-in first-out basis. Sample Count FI
The FO 82 stores the sample count 5b on a first-in first-out basis.

The system time comparator 75 is a FIFO7
4 outputs the system time 5a and the cycle timer 3a
Are compared with the lower 16 bits of the cycle time output by. The system time 5a includes a maximum delay time SYT_O in the lower 16 bits of the cycle time of the WC master node 1.
This is a value obtained by adding FFSET (352 μs).

When the cycle time matches the system time 5a, the comparator 75 outputs a match signal. Since the processing shown later is waited until the coincidence signal is output, the WC
The communication delay time from the master node 1 to the Rx node 3 can be absorbed.

The PLL 76 synchronizes with the above-mentioned coincidence signal and outputs, for example, a 48 kHz audio word clock W.
CK is generated and supplied to the node system 72.

The timing adjuster 77 uses the sample data 6b in the data FIFO 73 as the sample data SDT when receiving the above coincidence signal.
Supply to 2.

The timing adjuster 83 supplies the sample count 5b in the sample count FIFO 82 to the node system 72 as the sample count SCN when receiving the above coincidence signal.

The node system 72 has the word clock W
By reproducing the sample data (audio data) SDT according to the sample count SCN in synchronization with CK, it is possible to make a speaker emit sound.

As described above, according to the second embodiment, it is possible to synchronize the nodes based on the system time axis. The comparator 78 absorbs the communication delay time of the data packet 6 from the Tx node 2 to the Rx node 3, and the comparator 75 operates from the WC master node 1 to the Rx node.
The communication delay time of the WC packet 5 up to the node 3 can be absorbed. By absorbing these communication delay times, synchronization between nodes can be obtained.

FIG. 12 is a flowchart showing the processing of the second Rx node 3 (FIG. 11).

At step SE1, the system time 5a and the sample count 5b in the received WC packet 5
Are stored in FIFOs 74 and 82, respectively.

At step SE2, when the data packet 6 is received, the system time 6c and the sample data 6b in the packet 6 are stored in FIFOs 80 and 79, respectively.

In step SE3, the comparator 78
The system time 6c in O80 is compared with the cycle time of the cycle timer 3a, and the process waits until they match. If they match, the process proceeds to step SE4.

At step SE4, the next system time stored in the FIFO 80 is loaded into the comparator 78, and preparation for the next comparison is made.

At the step SE5, the data FIFO 79
Are stored in the data FIFO 73.

At step SE6, the comparator 75 sets the FIF
The system time 5a in O74 is compared with the cycle time of the cycle timer 3a, and the process waits until the two match. If they match, the process proceeds to step SE7.

In step SE7, the next system time stored in the FIFO 74 is loaded into the comparator 75, and preparation for the next comparison is made.

At step SE8, the PLL 76 generates the word clock WCK.

At Step SE9, the sample count SCN in the FIFO 82 and the sample data SDT in the FIFO 73 are supplied to the node system.

FIG. 13 is a block diagram showing a configuration example of the third Tx node 90.

The third Tx node 90 has a configuration including a second Tx node 2 (FIG. 9) and a WC master node 1 (FIG. 4). The third Tx node 90 has a function as a WC master node in addition to a function as a Tx node. When the third Tx node 90 is connected to the network, there is no need to connect the independent WC master node 1 to the network.

The third Tx node 90 is connected to the IEEE 139
4 interface system 91 and node system 52
Having. The interface system 91 has a WC
The lower part corresponds to a Tx node.
The lower Tx node has the same configuration as the second Tx node 2 (FIG. 9). Hereinafter, the configuration of a portion corresponding to the upper WC master node will be described.

The oscillator (OSC) 93 is provided outside the interface system 91 and oscillates a signal of a predetermined frequency. The oscillator 93 may be provided inside the interface system 91. The frequency divider 94 divides the frequency of the signal oscillated by the oscillator 93 and outputs a predetermined frequency (the packet period S in FIG. 2).
(A frequency corresponding to YT_INTERVAL). The sample counter 95 generates a word clock WCK (for example, 48
The sample count is incremented at the same frequency as (kHz).

The latch 96 outputs the sample count generated by the sample counter 95 as the sample count 5b in synchronization with the output signal of the frequency divider 94.

The latch 97 outputs the cycle time generated by the cycle timer 2a to the adder 98 in synchronization with the output signal of the frequency divider 94. The adder 98 adds the offset value SYT_OFFSET to the lower 16 bits of the cycle time output from the latch 97, and outputs the added value as the system time 5a.

The system time 5a and the sample count 5b are packetized and sent out on the bus 4 as WC packets 5.

At the same time, the system time 5a is
The sample count 5b is directly stored in the system time FIFO 54 in the Tx node 90 without passing through the EEE1394 bus, and the sample count 5b in the Tx node 90 is used.
It is stored directly in the FO 53. The subsequent processing of the Tx node unit is the same as the processing of the Tx node in FIG.

By including the WC master node in the Tx node, there is no need to connect a single WC master node to the network, and the number of nodes can be reduced. The WC master node may be included in the Rx node in the same manner as the WC master node is included in the Tx node.

Next, the WC master node 1 and the Tx node 2
And each cycle timer 1a, 2a, 3a of the Rx node 3
A method for adjusting the phase of FIG. 1 will be described. WC master node 1, Tx node 2 and Rx node 3 are all IE
This is a node connected to the EE1394 bus. One of these nodes is determined as the root node.
For example, an identification number is assigned to each node, and the node having the smallest or largest identification number is the root node. The configuration is shown below.

FIG. 14 shows a network configuration expressing the network of FIG. 1 from another viewpoint.

The root node RN is one of the WC master node 1, the Tx node 2, and the Rx node 3. 1st node N1 to nth node Nn
Is a node other than the root node.

The root node RN sends out the cycle time CT generated by its own cycle timer onto the bus. The nodes N1 to Nn receive the cycle time CT transmitted by the root node RN,
The value of T is set in its own cycle timer.

FIG. 15 is a flowchart showing the processing performed by the root node RN.

At step SF1, the value CT of its own cycle timer is transmitted to another node, and the process is terminated. The root node RN determines the value of the cycle timer CT at a predetermined cycle.
Is broadcast on the bus.

FIG. 16 is a flowchart showing processing performed by nodes N1 to Nn.

At Step SG1, the value CT of the cycle timer is received from the root node RN.

At step SG2, its own cycle timer is updated to the value CT of the received cycle timer.

This flowchart is similar to that of the root node RN.
, Every time the value CT of the cycle timer is received at a predetermined cycle.

According to the above-described method, the cycle timer of each node can be synchronized. Here, a delay time in which the root node RN transmits the cycle time CT will be considered. The time at which each of the nodes N1 to Nn receives the cycle time CT differs due to the difference in the delay time. Next, processing in consideration of the communication delay time will be described.

Each of nodes N1 to Nn transmits a pin packet to root node RN. When receiving the pin packet, the root node RN returns a response packet.
The nodes N1 to Nn measure the time from transmitting the pin packet to receiving the response packet. The time is a round-trip communication delay time from the nodes N1 to Nn to the root node RN. Each of the nodes N1 to Nn advances its own cycle timer by the one-way communication delay time, and adjusts the phase of the cycle timer of the root node RN.

For example, when the round-trip communication delay time is measured as 100 μs, the one-way communication delay time is 50 μs. The nodes N1 to Nn add their own cycle timers for the one-way communication delay time (50 μs).

By adding the cycle timer by the one-way communication delay time, the phase of the cycle timer of each node can be adjusted. Thereby, the plurality of Rx nodes can reproduce the audio data almost simultaneously. Next, the above process will be described with reference to a flowchart.

FIG. 17 is a flowchart showing a process for determining a delay time correction value of the cycle timer. The processes SH1, SH4, SH5, and SH6 on the left side of the flowchart show the processes of the nodes N1 to Nn, and the processes SH2 and SH on the right side.
3 shows the process of the root node RN.

At step SH1, the nodes N1 to Nn transmit pin packets to the root node RN, and start time measurement.

In step SH2, the root node RN receives the ping packet.

At step SH3, the root node RN immediately transmits a response packet to the transmission source nodes N1 to Nn.

In step SH4, the nodes N1 to Nn receive the response packet.

At step SH5, the round trip communication delay time from when the nodes N1 to Nn transmit the pin packet (step SH1) to when the response packet is received (step SH4) is calculated.

In step SH6, a half value of the calculated round-trip communication delay time is calculated as a one-way communication delay time.
Next, a correction value is determined by converting the value of the one-way communication delay time into a cycle time. The cycle time is a value counted at about 25 MHz in principle.

FIG. 18 is a flowchart showing the correction processing performed by the nodes N1 to Nn, which replaces the flowchart of FIG.

In step SI1, the value CT of the cycle timer transmitted from the root node RN in FIG. 15 is received.

At step SI2, the correction value determined in FIG. 17 is added to the received value CT of the cycle timer.

At step SI3, its own cycle timer is updated to the value of the corrected cycle time.

By correcting the cycle time, the phase of the cycle timer of each node can be adjusted. For example, in the first Tx node 2 (FIG. 5), the value of the cycle timer 2a is corrected, and in the first Rx node 3 (FIG. 7), the value of the cycle timer 3a is corrected.

Next, a method of correcting the system time instead of the cycle time will be described. In the first Tx node 2 (FIG. 5), the comparator 15 compares the value of the cycle timer 2a with the value of the system time FIFO 14. In the above description, the value of the cycle timer 2a is corrected. Instead, the value of the system time FIFO 14 is corrected and set in the comparator 15.

Similarly, at the first Rx node 3 (FIG. 7), the value of the system time FIFO 34 is corrected and set in the comparator 35 instead of correcting the value of the cycle timer 3a.

Similarly, at the second Tx node 2 (FIG. 9), instead of correcting the value of the cycle timer 2a, the value of the system time FIFO 54 is corrected and set in the comparator 55.

Similarly, in the second Rx node 3 (FIG. 11), instead of correcting the value of the cycle timer 3a, the value of the system time FIFO 74 is corrected and set in the comparator 75, and the value of the system time FIFO 80 is The value is corrected and set in the comparator 78.

FIG. 19 is a flowchart showing the above system time correction processing.

At step SJ1, the value of the system time is extracted from the receiving FIFOs 14, 34, 54, 74 and 80.

In step SJ2, calculation is performed based on the value of the system timer taken out and the correction value determined in FIG. For example, the correction value is subtracted from the value of the system timer.

At step SJ3, the comparators 15, 35,
The above calculated values of 55, 75 and 78 are set.

The second Tx node (FIG. 9) may correct the system time in the system time FIFO 60 and transmit the data packet 6. In that case, the system FIFO of the second Rx node (FIG. 11)
There is no need to correct the value of 80.

As described above, by correcting the cycle time or the system time, the phases of the time axes of the nodes can be matched. By adjusting the phases, the transmission timing of a plurality of Tx nodes or the plurality of Rx
The phases of the reproduction timing of the nodes can be matched.

According to the first and second embodiments, the WC master node 1 sends a WC packet 5 to the Tx node 2 and the Rx node 3. Tx node 2 transmits data packet 6 to Rx node 3. The data packet 6 includes the DBC 6a or the system time 6 in addition to the sample data 6b.
c.

In the first embodiment, using the DBC 6a,
Synchronization between nodes can be achieved based on the sample count axis. In the second embodiment, the system time 6c can be used to synchronize the nodes based on the system time axis.

By synchronizing the nodes, when the same data is transmitted almost simultaneously from one Tx node to a plurality of Rx nodes, the data reproduction time can be adjusted between the plurality of Rx nodes. Further, each Rx node can reproduce a series of data without causing a timing shift.

Further, by synchronizing the nodes,
When transmitting data from a plurality of Tx nodes to one Rx node, the Rx node can match the timing of data transmitted from the plurality of Tx nodes.

The data in the packet is not limited to audio data, but may be image data or the like. Communication is I
The communication is not limited to the EEE1394 digital serial communication, but may be other serial communication or parallel communication. For example,
The Internet or LAN may be used.

FIG. 20 is a diagram showing a specific hardware configuration of the personal computer 12. As shown in FIG.

The configuration of the personal computer 12 will be described. The bus 21 includes a CPU 22, a RAM 24, an external storage device 25, a MIDI interface 26 for transmitting and receiving MIDI data to and from the outside, a sound card 27, a ROM 28, a display device 29, input means 30 such as a keyboard, a switch, and a mouse. A communication interface 31 for connecting to the Internet is connected.

[0202] The sound card 27 has a buffer 27a and a codec circuit 27b. The buffer 27a buffers data to be input or output to the outside. The codec circuit 27b has an A / D converter and a D / A converter, and can perform conversion between an analog format and a digital format. Further, the codec circuit 27b has a compression / expansion circuit, and can compress and expand data.

The external storage device 25 includes, for example, a hard disk drive, a floppy disk drive, a CD-R
OM drive, magneto-optical disk drive, etc.
DI data, audio data, image data, computer programs, and the like can be stored.

The ROM 28 can store computer programs and various parameters. RAM 24
Has working areas such as buffers and registers,
The content stored in the external storage device 25 can be copied and stored.

The CPU 22 has a ROM 28 or a RAM 24
Performs various calculations or processes according to the computer program stored in the. The system clock 23 generates time information. The CPU 22 obtains time information from the system clock 23 and can perform timer interrupt processing.

[0206] The communication interface 31 of the personal computer 12 is connected to the Internet line 32. The communication interface 31 is an interface for transmitting and receiving MIDI data, audio data, image data, computer programs, and the like via the Internet.

The MIDI interface 26 has
The DI sound source 13 is connected, and the sound output device 14 is connected to the sound card 27. The CPU 22 receives MIDI data, audio data, image data, computer programs, and the like from the Internet line 32 via the communication interface 31.

The communication interface 31 may be an Internet interface, an Ethernet interface, an IEEE 1394 standard digital communication interface, or an RS-232C interface, and may be connected to various networks.

[0209] The personal computer 12 stores a computer program for receiving and reproducing audio data. By storing a computer program, various parameters, and the like in the external storage device 25 and reading them into the RAM 24, it is possible to easily add a computer program, upgrade the version, and the like.

[0210] A CD-ROM (compact disk-read only memory) drive is a device for reading computer programs and the like stored in a CD-ROM. The read computer program and the like are stored in the hard disk. New installation and version upgrade of a computer program can be easily performed.

[0211] The communication interface 31 is connected to a communication network 32 such as a LAN (local area network), the Internet, or a telephone line, and is connected to a computer 33 via the communication network 32. When the above-described computer programs and the like are not stored in the external storage device 25, the computer programs and the like can be downloaded from the computer 33. The personal computer 12 transmits a command requesting download of a computer program or the like to the computer 33 via the communication interface 31 and the communication network 32. The computer 33 receives the command and distributes the requested computer program and the like to the personal computer 12 via the communication network 32. Personal computer 12
However, the computer program or the like is received via the communication interface 31 and stored in the external storage device 25, whereby the download is completed.

The present embodiment may be implemented by a commercially available personal computer or the like in which a computer program or the like corresponding to the present embodiment is installed. In that case, the computer program corresponding to the present embodiment may be provided to the user in a state of being stored in a computer-readable storage medium such as a CD-ROM or a floppy disk. When the personal computer or the like is connected to a communication network such as a LAN, the Internet, or a telephone line, the computer program or various data may be provided to the personal computer or the like via the communication network.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0214]

As described above, according to the present invention,
By transmitting synchronization information between a plurality of communication devices, data transmission or processing can be performed in synchronization.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a network according to an embodiment of the present invention.

FIG. 2 is a timing chart showing processing of a transmission node (Tx node).

FIG. 3 is a timing chart of each node shown in FIG. 1;

FIG. 4 is a flowchart showing processing of a WC master node.

FIG. 5 is a block diagram showing a configuration of a first Tx node.

FIG. 6 is a flowchart showing processing of a first Tx node.

FIG. 7 is a block diagram illustrating a configuration of a first receiving node (Rx node).

FIG. 8 is a flowchart illustrating a process of a first Rx node.

FIG. 9 is a block diagram illustrating a configuration of a second Tx node.

FIG. 10 is a flowchart showing processing of a second Tx node.

FIG. 11 is a block diagram showing a configuration of a second Rx node.

FIG. 12 is a flowchart illustrating processing of a second Rx node.

FIG. 13 is a block diagram illustrating a configuration of a third Tx node.

FIG. 14 is a block diagram illustrating a configuration of a network.

FIG. 15 is a flowchart illustrating processing of a root node.

FIG. 16 is a flowchart illustrating processing of a node other than the root node.

FIG. 17 is a flowchart showing a process of determining a delay time correction value of a cycle timer.

FIG. 18 is a flowchart illustrating a first correction process of a delay time.

FIG. 19 is a flowchart illustrating a second correction process of the delay time.

FIG. 20 is a diagram showing a specific hardware configuration of the personal computer 12.

[Explanation of symbols]

1 WC master node, 2 transmitting node (Tx node), 3 receiving node (Rx node), 1a,
2a, 3a cycle timer, 4 IEEE139
4 bus, 5 WC packet, 5a system time, 5b sample count, 6 data packet, 6a DBC, 6b sample data,
6c System time, 11 IEEE1394
Interface system, 12 node system,
13 Sample count FIFO, 14 System time FIFO, 15 System time comparator, 16 PLL, 17 Timing adjuster,
18 adder, 19 data FIFO, 20
DBC generator, 31 IEEE1394 interface system, 32 node system,
33 sample count FIFO, 34 system time FIFO, 35 system time comparator,
36 PLL, 37 timing adjuster, 3
8 DBC comparator, 39 data FIFO, 4
0 DBC-FIFO, 41 timing adjuster,
51 IEEE 1394 interface system,
52 node system, 53 sample count F
IFO, 54 System time FIFO, 55
System time comparator, 56 PLL, 57
Timing adjuster, 58 adder, 59 data FIFO, 60 system time FIFO,
71 IEEE 1394 interface system,
72 node system, 73 data FIFO,
74 System time FIFO, 75 System time comparator, 76 PLL, 77, 81, 8
3 Timing adjuster, 78 System time comparator, 79 Data FIFO, 80 System time FIFO, 82 Sample count FIFO,
90 Tx node, 91 IEEE 1394 interface system, 93 oscillator, 94
Frequency divider, 95 sample counter, 96, 97
Latch, 98 adder

Claims (5)

[Claims] A timer for generating first synchronization information; a generation means for generating second synchronization information in which the maximum synchronization delay is added to the first synchronization information generated by the timer; A communication device for transmitting a sample count corresponding to the timing and the second synchronization information to a network; 2. Receiving means for receiving first synchronization information from outside, generating means for generating second synchronization information in which a maximum transfer delay is added to the first synchronization information received by the receiving means, A communication unit that transmits the second synchronization information and data corresponding to the second synchronization information to a network. 3. A first receiving means for receiving first synchronization information and corresponding data from outside, a second receiving means for receiving second synchronization information from outside, and the first receiving means. Performs the first synchronization adjustment based on the first synchronization information received by the first reception unit, performs the second synchronization adjustment based on the second synchronization information received by the second reception unit, and receives the first synchronization adjustment. And a processing unit for processing data to be processed. 4. A first synchronization information generating means for generating first synchronization information, and transferring the first synchronization information generated by the first synchronization information generating means to another communication device via a network. A second synchronization information generating unit that generates second synchronization information based on the first synchronization information in consideration of a transfer maximum delay amount in the case; and a second synchronization information generation unit that generates the second synchronization information. Transmitting means for transmitting synchronization information to a network; processing for directly receiving the second synchronization information generated by the second synchronization information generating means without passing through a network, and processing data based on the second synchronization information A communication device having means. 5. A first receiving means for receiving first synchronization information from an external communication device; a second receiving means for receiving second synchronization information from the outside; and a first receiving means for receiving the first synchronization information. Measuring means for measuring an arrival delay time of the first synchronization information from the external communication device; and the first means according to the arrival delay time measured by the measuring means.
Or a determining means for determining a correction value of the second synchronization information, and a correction value determined by the determining means each time the first or second receiving means receives the first or second synchronization information. And a correcting means for correcting the first or second synchronization information.