JP3697302B2 - 高速桁上げ回路 - Google Patents

高速桁上げ回路 Download PDF

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Publication number
JP3697302B2
JP3697302B2 JP26637495A JP26637495A JP3697302B2 JP 3697302 B2 JP3697302 B2 JP 3697302B2 JP 26637495 A JP26637495 A JP 26637495A JP 26637495 A JP26637495 A JP 26637495A JP 3697302 B2 JP3697302 B2 JP 3697302B2
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Japan
Prior art keywords
carry
signal
logic
input
circuit
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Expired - Fee Related
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JP26637495A
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English (en)
Japanese (ja)
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JPH08110853A (ja
Inventor
ジェイ．ニュウ バーナード
エム．ピアース ケリー
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ジリンクス，インコーポレーテッド
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Publication of JPH08110853A publication Critical patent/JPH08110853A/ja
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Publication of JP3697302B2 publication Critical patent/JP3697302B2/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4812—Multiplexers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
JP26637495A 1994-09-20 1995-09-20 高速桁上げ回路 Expired - Fee Related JP3697302B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/310,113 US5481206A (en) 1993-09-02 1994-09-20 Circuit for fast carry and logic
US08/310,113 1994-09-20

Publications (2)

Publication Number Publication Date
JPH08110853A JPH08110853A (ja) 1996-04-30
JP3697302B2 true JP3697302B2 (ja) 2005-09-21

Family

ID=23201040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26637495A Expired - Fee Related JP3697302B2 (ja) 1994-09-20 1995-09-20 高速桁上げ回路

Country Status (3)

Country Link
US (1) US5481206A (forum.php)
EP (1) EP0707382A2 (forum.php)
JP (1) JP3697302B2 (forum.php)

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USRE35977E (en) * 1992-05-08 1998-12-01 Altera Corporation Look up table implementation of fast carry arithmetic and exclusive-or operations
US6288570B1 (en) * 1993-09-02 2001-09-11 Xilinx, Inc. Logic structure and circuit for fast carry
US5898318A (en) * 1994-11-04 1999-04-27 Altera Corporation Programmable logic array integrated circuits with enhanced cascade
US5581199A (en) * 1995-01-04 1996-12-03 Xilinx, Inc. Interconnect architecture for field programmable gate array using variable length conductors
US5594367A (en) * 1995-10-16 1997-01-14 Xilinx, Inc. Output multiplexer within input/output circuit for time multiplexing and high speed logic
US5675262A (en) * 1995-10-26 1997-10-07 Xilinx, Inc. Fast carry-out scheme in a field programmable gate array
US5924115A (en) * 1996-03-29 1999-07-13 Interval Research Corporation Hierarchical memory architecture for a programmable integrated circuit having an interconnect structure connected in a tree configuration
US5724276A (en) * 1996-06-17 1998-03-03 Xilinx, Inc. Logic block structure optimized for sum generation
US6427156B1 (en) 1997-01-21 2002-07-30 Xilinx, Inc. Configurable logic block with AND gate for efficient multiplication in FPGAS
US6201410B1 (en) 1997-02-26 2001-03-13 Xilinx, Inc. Wide logic gate implemented in an FPGA configurable logic element
US6204689B1 (en) 1997-02-26 2001-03-20 Xilinx, Inc. Input/output interconnect circuit for FPGAs
US5920202A (en) * 1997-02-26 1999-07-06 Xilinx, Inc. Configurable logic element with ability to evaluate five and six input functions
US5914616A (en) * 1997-02-26 1999-06-22 Xilinx, Inc. FPGA repeatable interconnect structure with hierarchical interconnect lines
US5963050A (en) 1997-02-26 1999-10-05 Xilinx, Inc. Configurable logic element with fast feedback paths
US5889411A (en) * 1997-02-26 1999-03-30 Xilinx, Inc. FPGA having logic element carry chains capable of generating wide XOR functions
US5942913A (en) * 1997-03-20 1999-08-24 Xilinx, Inc. FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines
JP3123977B2 (ja) * 1998-06-04 2001-01-15 日本電気株式会社 プログラマブル機能ブロック
US6034546A (en) 1998-06-09 2000-03-07 Cypress Semicondutor Corp. High performance product term based carry chain scheme
US6353920B1 (en) * 1998-11-17 2002-03-05 Xilinx, Inc. Method for implementing wide gates and tristate buffers using FPGA carry logic
US6505337B1 (en) * 1998-11-24 2003-01-07 Xilinx, Inc. Method for implementing large multiplexers with FPGA lookup tables
EP1076931A1 (en) * 1999-03-04 2001-02-21 Altera Corporation Programmable logic device with carry-select addition
US6329838B1 (en) * 1999-03-09 2001-12-11 Kabushiki Kaisha Toshiba Logic circuits and carry-lookahead circuits
US6724810B1 (en) 2000-11-17 2004-04-20 Xilinx, Inc. Method and apparatus for de-spreading spread spectrum signals
US7003545B1 (en) 2001-09-11 2006-02-21 Cypress Semiconductor Corp. High performance carry chain with reduced macrocell logic and fast carry lookahead
US6990508B1 (en) * 2001-09-11 2006-01-24 Cypress Semiconductor Corp. High performance carry chain with reduced macrocell logic and fast carry lookahead
US6556042B1 (en) * 2002-02-20 2003-04-29 Xilinx, Inc. FPGA with improved structure for implementing large multiplexers
US6798240B1 (en) 2003-01-24 2004-09-28 Altera Corporation Logic circuitry with shared lookup table
US7800401B1 (en) 2003-02-10 2010-09-21 Altera Corporation Fracturable lookup table and logic element
US6943580B2 (en) * 2003-02-10 2005-09-13 Altera Corporation Fracturable lookup table and logic element
US6888373B2 (en) 2003-02-11 2005-05-03 Altera Corporation Fracturable incomplete look up table for area efficient logic elements
US7290026B2 (en) * 2003-09-30 2007-10-30 International Business Machines Corporation Low-power high-speed 4-2 compressor with minimized transistor count
US7185035B1 (en) 2003-10-23 2007-02-27 Altera Corporation Arithmetic structures for programmable logic devices
US7565388B1 (en) 2003-11-21 2009-07-21 Altera Corporation Logic cell supporting addition of three binary words
US7167021B1 (en) 2003-11-24 2007-01-23 Altera Corporation Logic device logic modules having improved arithmetic circuitry
US7205791B1 (en) 2004-03-12 2007-04-17 Altera Corporation Bypass-able carry chain in a programmable logic device
US7061268B1 (en) 2004-03-15 2006-06-13 Altera Corporation Initializing a carry chain in a programmable logic device
US7167022B1 (en) 2004-03-25 2007-01-23 Altera Corporation Omnibus logic element including look up table based logic elements
US7617269B2 (en) * 2004-08-03 2009-11-10 Stmicroelectronics Pvt. Ltd. Logic entity with two outputs for efficient adder and other macro implementations
US7772879B1 (en) * 2007-04-11 2010-08-10 Actel Corporation Logic module including versatile adder for FPGA
US7394287B1 (en) * 2007-05-21 2008-07-01 Altera Corporation Programmable logic device having complex logic blocks with improved logic cell functionality
US7663400B1 (en) 2007-12-21 2010-02-16 Actel Corporation Flexible carry scheme for field programmable gate arrays
US8244791B1 (en) 2008-01-30 2012-08-14 Actel Corporation Fast carry lookahead circuits
US7746100B2 (en) * 2008-04-28 2010-06-29 Altera Corporation Flexible adder circuits with fast carry chain circuitry
US7919991B1 (en) 2008-07-08 2011-04-05 Netlogic Microsystems, Inc. Comparator circuit
US8805916B2 (en) * 2009-03-03 2014-08-12 Altera Corporation Digital signal processing circuitry with redundancy and bidirectional data paths
WO2015051105A1 (en) * 2013-10-02 2015-04-09 The Penn State Research Foundation Techniques and devices for performing arithmetic
KR102561988B1 (ko) * 2015-09-11 2023-07-31 자일링크스 인코포레이티드 캐스케이드 룩업테이블(lut) 자리올림 논리 회로
CN105680847B (zh) * 2016-03-03 2019-02-12 深圳市紫光同创电子有限公司 一种fpga电路及其设计方法

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US5274581A (en) * 1992-05-08 1993-12-28 Altera Corporation Look up table implementation of fast carry for adders and counters
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US5352940A (en) * 1993-05-27 1994-10-04 Altera Corporation Ram convertible look-up table based macrocell for PLDs
US5386156A (en) * 1993-08-27 1995-01-31 At&T Corp. Programmable function unit with programmable fast ripple logic
US5349250A (en) 1993-09-02 1994-09-20 Xilinx, Inc. Logic structure and circuit for fast carry
GB201718533D0 (en) 2017-11-09 2017-12-27 Agco Int Gmbh Seed replacement unit

Also Published As

Publication number Publication date
JPH08110853A (ja) 1996-04-30
EP0707382A3 (forum.php) 1996-05-22
US5481206A (en) 1996-01-02
EP0707382A2 (en) 1996-04-17

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