JP3696362B2 - Control device for electronic game machines - Google Patents

Description

[0001]
[Industrial application fields]
The present invention is a technique introduced to an electronic game machine installed in a playground such as a pachinko hall, and particularly relates to a control device for an electronic game machine for controlling the game operation of this type of electronic game machine. .
[0002]
[Prior art]
In the pachinko hall, there are a number of electronic game machines such as pachinko machines and slot machines. These electronic game machines incorporate a control board on which electronic circuit components are mounted, and the operation of the game machine is controlled in series.
[0003]
By the way, it is necessary to control electronic game machines of this type of customs business model based on laws and regulations, and each game machine manufacturer provides fixed data such as a control program for actually operating the game machine and a winning probability. It is created according to this regulation and stored in ROM. On the control board, a chip component (hereinafter referred to as “ROM chip component”) incorporating the ROM, a chip component including a CPU serving as a control body (hereinafter referred to as “CPU chip component”), and the like are mounted. After the inspection, it is enclosed in a case and incorporated into the aircraft.
[0004]
The completed game machine is delivered to a pachinko hall or the like, but after this delivery, there is a risk of illegal acts of breaking the seal and replacing the ROM chip part with a part written with an illegal program. .
[0005]
In order to detect such illegal activities, it is necessary to check the sealing of the control board in the machine for each game machine, which requires a great deal of labor and time. If there is no suspicion that illegal activities are being conducted, it is difficult to check the control board after delivery, and it is virtually impossible to completely prevent illegal activities.
[0006]
In order to solve this problem, as disclosed in Japanese Patent Laid-Open No. 8-238375, it has been proposed to provide a control device with a function for checking whether or not the control program in the ROM is appropriate. Yes.
Specifically, in this method, a security code obtained by converting an appropriate control program in a predetermined format is registered in the control device in advance, and the control program is read from the ROM and converted by this conversion format. The obtained code information is collated with the registered security code.
[0007]
[Problems to be solved by the invention]
As described above, when determining the suitability of the ROM using the control program in the ROM, it is necessary to secure a processing time for reading the program and generating code information. However, in a pachinko game or slot game that requires instantaneous game determination, this processing time becomes a fatal delay time, and it is virtually impossible to perform the determination processing during the game. For this reason, the current game machine is set so that the verification process is performed only when the apparatus is turned on or reset.
[0008]
However, in recent years, in order to bypass this verification process and carry out fraud, the program is performed after another illegal ROM chip is mounted while the original ROM chip component is held on the board, and the verification process for the regular ROM is completed. Control boards that have been altered so as to switch the reading destination to the illegal ROM side are on the market. For this reason, game machine manufacturers are required to develop a method for checking the suitability of ROMs even during game operations.
[0009]
The present invention has been made paying attention to the above-mentioned problems, and even when game control is being executed, by making it possible to determine the suitability of ROM without delaying the control, the program read destination is illegal. It is a technical problem to be able to extract fraudulent acts such as switching to a ROM .
[0010]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, in the invention of claim 1, a ROM chip component in which a ROM for storing a game control program is embedded and a CPU for reading and executing the program in the ROM are embedded. In a control device for an electronic game machine comprising a CPU chip part, the CPU has a function of executing a refresh on a working memory while decoding a command, and does not require a refresh process. Connect to the working memory of the mold and the ROM chip component. The ROM chip component is embedded with an arithmetic circuit that captures data exchanged between the ROM and the CPU and generates a security code by an operation using the acquired data.
The CPU generates code information that matches the security code by an operation using the same data as the data fetched for the operation by the arithmetic circuit, and when the command is input from the ROM, the command , In place of the refresh process for the working memory, to execute the process of fetching the security code from the arithmetic circuit and collating the code information with the code information generated by the own circuit, When it is determined that the security code and the code information are inconsistent by the collation, the decoded command is not executed.
[0011]
According to a second aspect of the present invention, the arithmetic circuit is connected to a data input path from the ROM to the CPU, and executes the calculation using the input data every time data is input from the ROM to the CPU. .
[0012]
[Action]
When performing a series of game controls, an address signal is first output from the CPU to the ROM, and an address to be referenced in the ROM is designated. Receiving this designation, the ROM outputs the data stored at the corresponding address to the CPU. As described above, when the address designation data and the program data exchanged between the CPU and the ROM are sequentially fetched and a calculation based on a predetermined calculation rule is executed, certain code information can be generated.
[0013]
In the present invention, an arithmetic circuit is embedded in the ROM chip component, the security circuit is generated by the arithmetic processing described above, and the CPU uses the same data as the arithmetic circuit uses. To generate code information that matches the security code.
[0014]
The CPU has a function of executing refresh on the work memory while decoding the command. However, since a static memory is used as the work memory, the calculation is performed instead of executing the refresh process. It is possible to retrieve the security code from the circuit and collate the code information with the code information generated by the own circuit. Since this collation process is executed every time a command is input from the ROM, the collation process can be repeatedly executed during game control. In addition, since the verification process is performed using the time for the refresh process, the game operation of the game machine is not delayed even if the verification process is performed.
[0015]
【Example】
FIG. 1 shows the appearance of a slot machine to which a control device for an electronic game machine according to the present invention is applied.
The machine body of the slot machine 1 is configured such that a door portion 2 is attached to the front surface of a box-shaped airframe main body portion so that the door portion 2 can be opened and closed, and a reel display window 3, a medal slot 4, A start lever 5, three stop button switches 6a, 6b, 6c, a medal discharge port 7, a medal tray 8, and the like are provided.
[0016]
The reel display window 3 displays a total of five stop lines L _{1 to} L ₅ , up, middle, down, and diagonal. If the number of inserted medals is one, only the center stop line L ₁ is displayed. If there are two, the upper, middle, and lower three stop lines L _{1 to} L ₃ are activated, and if there are three, all the stop lines L _{1 to} L ₅ are activated.
[0017]
Three reels 9a, 9b, and 9c are incorporated in the body main body in accordance with the position of the reel display window 3. Reels 9a, 9b, and each of the peripheral surface of 9c are drawn plurality of symbols, at the time of reel stop the reels 9a, 9b, 3 frame of symbols of 9c is, each stop line L ₁ ~L ₅ above It is arranged in line with.
[0018]
When medals are inserted from the medal insertion slot 4, the number of stop lines corresponding to the number of inserted medals is activated, and when the start lever 5 is operated, the three reels 9a, 9b, 9c are started all at once. To do. Thereafter, each time the stop button switches 6a, 6b, 6c are operated, the corresponding reels 9a, 9b, 9c are individually stopped. If a predetermined symbol combination is established on the activated line at this time, a hopper (not shown) inside the apparatus is operated, and a predetermined number of medals are transferred from the medal discharge port 7 to the medal tray 8. And released.
[0019]
FIG. 2 shows a basic electrical configuration of the slot machine 1.
In the figure, reference numeral 10 denotes a control device for an electronic game machine according to the present invention (hereinafter simply referred to as “control device 10”), which is a CPU 11 which is a control body, a RAM 12 which is used for reading and writing data, and a control program for game execution. And a ROM 13 for storing a symbol arrangement of each reel, a winning probability, and the like.
[0020]
Of the control device 10, the CPU 11 and the RAM 12 are configured as CPU chip components 14 housed in one package. On the other hand, the ROM 13 is configured as a single chip component so as to be able to cope with a model change, and is mounted on the same control board as the CPU chip component 14.
[0021]
The control device 10 drives an input unit such as the start lever 5, stop button switches 6a, 6b, 6c, a reel driving unit 15 for driving the reels 9a, 9b, 9c, and the hopper via a bus 19. A hopper drive unit 16 and the like are connected. The CPU 11 outputs a control signal to the reel drive unit 16 based on the operation signal from each switch, thereby realizing the start and stop operation of each reel 9a, 9b, 9c. Further, the CPU 11 recognizes a symbol located on the effective line for each reel by using the driving timing of the reel and the symbol arrangement data stored in the ROM 13, and all the reels stop and are on the effective line. When it is determined that the winning combination of symbols is established, the hopper driving unit 16 is driven to release a predetermined number of medals.
[0022]
In the control device 10 of this embodiment, a CPU having a refresh function for a dynamic RAM (DRAM) such as a Z80 system is used as the CPU 11, while a static memory that does not require refresh processing is adopted as the RAM 12. The processing time for performing the refresh process is set to a free time during which no external processing is performed. Further, the CPU 11 is set with a function for determining the suitability of the ROM 13 within this idle time, and this determination process is performed during command decoding during normal game control.
[0023]
FIG. 3 shows the detailed configuration of the CPU 11 and the ROM 13 and the relationship between them. Hereinafter, the details of the discrimination processing will be described with reference to FIG.
The ROM 13 includes a ROM main body 17 for storing programs and data, and arithmetic circuits 18 for performing arithmetic processing described later as individual integrated circuits, which are embedded in the same package. is there.
[0024]
The arithmetic circuit 18 is connected to a data bus 20 that connects between the ROM main body 17 and the CPU 11, and takes in the output data DT each time data is output from the ROM main body 17. Predetermined calculations are performed such as sequentially integrating the numerical values shown.
[0025]
The output data DT is output based on the reference address data ADR given from the CPU 11 via the address bus 21, and this data DT is given to the control unit 22 in the CPU 11, and processing according to the contents is performed. Executed.
[0026]
The calculation unit 23 of the CPU 11 performs normal calculation operation in response to a command from the control unit 22 and receives this data via the control unit 22 every time data DT is input. A similar operation is performed.
If the data DT indicates a command, a refresh period during which no external processing is performed while the control unit 22 decodes the command causes the arithmetic unit 23 to store the data on the ROM 13 side. The readout signal is output to the arithmetic circuit 18 to fetch the arithmetic result SC, and the value of this SC is collated with its own arithmetic result SC ′. The collation result is given to the control unit 22 after the decoding process, and the control unit 22 determines whether or not to execute the command decoded based on the collation result.
[0027]
In this embodiment, the calculation is executed using only the data DT input from the ROM 13 to the CPU 11. However, the present invention is not limited to this, and the reference address data ADR output from the CPU 11 to the ROM 13 is incorporated in the calculation processing target. But it ’s okay.
Further, if the arithmetic circuit 18 is formed in a format area in which code information such as a manufacturer code or a device code is normally formed by the component manufacturer, it becomes more difficult to decode the arithmetic logic, and security for the program check of the ROM main body 17 is increased. Further improvement can be achieved.
[0028]
FIG. 4 shows a control procedure for checking the suitability of the ROM by the CPU 11. Note that c in the figure is a counter for counting the number of times each calculation result does not match by the collation process, and is set to “0” in the initial state and stored in a register in the CPU.
First, when the apparatus is turned on, in step 1, the control unit 22 of the CPU 11 resets the internal register and the RAM 12, and then outputs the reference address data ADR to the ROM 13 to set the address of the data reading destination. Specify (address 0 is specified in the initial state). In response to this, when the data DT at the corresponding address in the ROM main body 17 is input to the CPU 11, the control unit 22 checks whether the data DT indicates fixed data such as a numerical value or a command. (Steps 2 and 3).
[0029]
If the input data DT is data other than the command, step 4 becomes “NO” and the process proceeds to step 5, and the arithmetic unit 23 executes arithmetic processing using the data DT.
At this time, the arithmetic circuit 18 in the ROM 13 similarly performs an operation using the data DT. By repeating the processes in steps 2 to 5 for a plurality of cycles, both the CPU 11 and the ROM 13 have a predetermined code. Information is generated.
[0030]
When the data DT input from the ROM 13 at a certain point in time represents a command, the control unit 22 starts to decode this command. At the same time, the calculation unit 23 fetches the calculation result of the calculation circuit 18 and executes a collation process with its own calculation result SC ′ (step 6).
[0031]
When the decoding of the command ends, the control unit 22 of the CPU 11 checks the collation process. As a result, if the calculation results SC and SC ′ match, step 7 becomes “YES”, the process proceeds to step 11, and the control unit 22 performs a process based on the decoded command, Return to 2.
Thereafter, as long as the chip components constituting the ROM 13 are appropriate, the above processing is repeatedly executed, and the CPU 11 executes the program while confirming that the ROM 13 is appropriate.
[0032]
On the other hand, when an illegal program is stored in a general-purpose ROM chip part and replaced with the chip part constituting the ROM 13, the illegal part does not include the arithmetic circuit 18, so the CPU 11 displays the calculation result from the ROM 13 side. It can no longer be obtained. Further, when another ROM chip component is mounted on the control board and the program reading destination is switched from the regular ROM 13 to the illegal ROM side during the operation of the apparatus, the calculation result SC of the calculation circuit 18 side and the calculation unit 23 The calculation result SC ′ does not match. Therefore, if these frauds are made, the determination in step 7 is “NO”, the process proceeds to step 8, and the counter c is incremented.
[0033]
In the next step 9, the control unit 22 has occurred for the number of times that the count value of the counter c has exceeded a predetermined threshold value TH, that is, the event that the result of each operation does not match exceeds the threshold value TH. If this step 9 is “YES”, the control unit 22 stops the execution of the decoded command in the next step 10. As a result, the aircraft is set in an inoperable state thereafter, and the illegal program cannot be continued.
It should be noted that the operation of the apparatus may be stopped immediately after the calculation results are inconsistent once without performing steps 8 and 9 above.
[0034]
As described above, during the normal operation of the CPU 11, both the CPU 11 and the ROM 13 perform calculations using data exchanged between them, and the calculation results are obtained within a short time when the CPU 11 is not performing external processing. Therefore, it is possible to determine whether the ROM 13 is appropriate or not, so that the determination process can be repeatedly executed during the operation of the apparatus without delaying the process timing of the game control. In addition, when the chip parts constituting the ROM 13 are replaced with illegal ones, or when the program reading destination is switched during the operation, the illegal act can be immediately determined, so that the security is greatly improved.
In addition, since the collation operation is executed when the apparatus is started up, such as when the apparatus is turned on or reset, it is not necessary to prepare an algorithm for generating a security code from a program in the ROM as in the prior art.
[0035]
Note that the time period during which the operation result comparison operation is performed is not limited to the refresh period described above, and other idle time during which the CPU is not processing externally may be used. In addition, a CPU having a pipeline capable of executing a plurality of processes developed in recent years may be introduced, and any one line may be set exclusively for ROM chip component verification processing.
[0036]
【The invention's effect】
In the present invention, an arithmetic circuit that generates a security code by an operation using data exchanged between the CPU and the ROM is embedded in the ROM chip part, and the CPU also generates code information that matches the security code. did. In addition, a CPU having a function of refreshing the work memory while decoding the command and a static work memory that does not require a refresh process are used, and a security code is used instead of the refresh process for the work memory. Since the process for verifying the security code is executed, the security code verification process can be repeatedly performed while the game control is being executed. Moreover, by using the time for the refresh process, the processing timing of the game control is not delayed for the collation process. Therefore, the suitability of the ROM chip parts can be checked even during normal game control. it is possible to easily determine the ing. In addition, since the decrypted command is not executed when the above verification result is inconsistent, the execution of the program can be stopped promptly if it is replaced with an illegal program, and the security of the game machine Can be greatly improved.
[Brief description of the drawings]
FIG. 1 is a front view showing a schematic configuration of a slot machine to which an electronic game machine control device of the present invention is applied.
2 is a block diagram showing an electrical configuration of the slot machine of FIG. 1. FIG.
FIG. 3 is a block diagram illustrating a detailed configuration of a CPU and a ROM and a relationship between the two.
FIG. 4 is a flowchart showing a control procedure for checking the suitability of ROM.
[Explanation of symbols]
10 Electronic game machine controller 11 CPU
13 ROM
17 ROM main body 18 arithmetic circuit 22 control part 23 arithmetic part

Claims (2)

A ROM chip component in which a ROM for storing a game control program is embedded, and a CPU chip component in which a CPU for reading and executing a program in the ROM is embedded;
The CPU has a function of executing refresh for the work memory while decoding a command, and is connected to a static work memory that does not require a refresh process and the ROM chip component,
In the ROM chip component, an arithmetic circuit that captures data exchanged between the ROM and the CPU and generates a security code by an arithmetic operation using the captured data is embedded,
The CPU generates code information that matches the security code by an operation using the same data as the data fetched for the operation by the arithmetic circuit, and when the command is input from the ROM, the command , In place of the refresh process for the working memory, to execute the process of fetching the security code from the arithmetic circuit and collating the code information with the code information generated by the own circuit, An electronic game machine control device characterized in that when the security code and the code information are determined to be inconsistent by the collation, the decoded command is not executed . The arithmetic circuit is connected to a data input path from the ROM to the CPU, and each time data is input from the ROM to the CPU, the arithmetic is performed using the input data . Control device for electronic game machines.

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