JP3693503B2 - Processor with instruction cache write mechanism - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a processor, and more particularly to a microprocessor suitable for executing a virtual machine interpreter or the like that dynamically generates and executes a machine language instruction program at the time of execution.
[0002]
[Prior art]
In a conventional microprocessor, a cache is often provided as a high-speed intermediate storage device between a main memory (main memory) and a CPU. This cache can be classified into a non-integrated cache in which the data cache and the instruction cache are separated, and an integrated cache in which the data cache and the instruction cache are integrated. Compared with the latter integrated cache, the former non-integrated cache can provide a high data supply bandwidth to each of the data cache and the instruction cache independently, so that generally high performance can be obtained. For this reason, non-integrated caches are often used in high-end microprocessors.
[0003]
On the other hand, Java (Java is a trademark of Sun Microsystems, Inc., USA) and Smalltalk are known as programming languages for describing a program executed by such a microprocessor. Programs written in these programming languages are once converted into virtual computer instructions called byte codes, and the byte codes are usually executed by software called a virtual machine interpreter.
[0004]
However, execution by such a virtual machine interpreter has a large overhead such as interpretation and execution of virtual machine instructions. Therefore, a program written in Java or Smalltalk generally has a lower execution speed than a program written in a conventional compiler type language such as C or FORTRAN. On the other hand, it is shown in “Efficient Implementation of the Smalltalk-80 System” by LP Deutsch and AM Chiffman (In Proceedings of the 11th Annual ACM Symposium on Principles of Programming Languages pp.297-302, 1984). In this way, a machine language instruction that performs processing equivalent to the virtual machine instruction sequence to be executed is generated at the time of execution, and the generated machine language instruction is directly executed to speed up interpreter execution. It is done. Such a technique involves dynamic compilation from the dynamic generation of machine language instructions at the time of execution, or compilation at the time of execution, and JIT (Just-In-Time) compilation. It is called and used for speeding up Java virtual machines.
[0005]
[Problems to be solved by the invention]
JIT compilation technology that dynamically generates instructions at the time of execution is effective for speeding up virtual machine interpreters, etc., but is considered to be used in microprocessors that employ a non-integrated cache mechanism. Since the instruction generated at the time of execution needs to be written into the main memory at the time of execution, the following problem arises.
[0006]
Writing dynamically generated instructions to the main memory is not different from normal data writing when viewed from the processor, so in a processor employing a non-integrated cache, it is performed via the data cache. Become. For this reason, even if it is attempted to execute the written instruction immediately after the generated instruction is written to the memory via the data cache, the instruction cache and the data cache are not consistent, so that the instruction can be executed as it is. Can not. That is, since the instruction cache is not updated, an unexpected instruction may be executed as it is. Therefore, most microprocessors are provided with instructions for writing back data on a designated data cache to the main memory and invalidating a cache block on the instruction cache. Before executing the instruction written in the main memory, the instruction cache data corresponding to the written address is discarded (invalidated) and written back (write-back) type. In this cache, the data in the data cache corresponding to the written address is written back to the main memory so that the change is reflected in the main memory.
[0007]
That is, dynamic instruction generation / execution processing is performed in the following flow.
[0008]
1. Writing dynamically generated machine language instructions to the cache block of the data cache corresponding to the write target address (hereinafter referred to as address A)
2. Discard the cache block of the instruction cache corresponding to address A
3. Write back the cache block of the data cache corresponding to address A to the main memory (in the case of a write-back cache)
4. Reading from main memory address A to the corresponding cache block in the instruction cache
5). Reading and executing instructions from the instruction cache
As described above, in a microprocessor employing a non-integrated cache, when an instruction is dynamically generated at the time of execution and an attempt is made to execute the generated instruction, the dynamically generated instruction is stored in the data cache. After being written, it needs to be written to the main memory and then read to the instruction cache, which involves writing to and reading from the main memory, which can be a cause of a decrease in execution speed.
[0009]
In particular, in high-end microprocessors that can process many instructions in the time required for main memory reference due to improved instruction level parallelism and operating frequency in the processor, dynamic instruction generation processing due to the overhead required for main memory reference There is a possibility that the problem that the operating performance of the program that performs the above-mentioned will deteriorate becomes serious.
[0010]
In conventional static compiler type languages such as C and FORTRAN, conversion into machine language instructions is performed in advance before program execution, and instructions are not dynamically generated at the time of execution. But it was not a big problem.
An object of the present invention is to suppress performance degradation caused by main memory reference at the time of dynamic instruction generation in a process of dynamically generating machine language instructions at the time of execution such as JIT compilation in a virtual machine interpreter. It is to provide a processor that can be used.
[0011]
[Means for Solving the Problems]
In the instruction set, the processor according to the present invention may specify, for each predetermined memory area, whether the area is an area where data is written via a data cache or an area where data is written via an instruction cache. It has the command which can be performed. In this case, when writing is instructed to the memory area designated as an area to be written via the instruction cache by the instruction, the writing is performed via the instruction cache.
[0012]
The second processor according to the present invention includes a flag indicating whether the mode is a mode in which writing is performed via the data cache or a mode in which writing is performed via the instruction cache, and the flag is written via the instruction cache. If the mode indicates that the mode is to be performed, writing is performed through the instruction cache. In this case, it is preferable to have an instruction for manipulating the flag in the instruction set.
[0013]
The third processor according to the present invention is characterized in that the instruction set includes an instruction for instructing writing to the memory via the instruction cache.
[0014]
In the first to third processors, when an instruction to write via the instruction cache is given, writing to both the instruction cache and the data cache may be performed. In this way, there will be a copy of the instruction cache update data in the data cache, so if there is a cache overflow in the instruction cache without providing a direct write-back path from the instruction cache to the memory. Can be written back to the main memory.
[0015]
Further, the dynamic compilation method according to the present invention is a dynamic compilation method using the first to third processors described above, and when writing dynamically generated instructions to the memory, the instruction is passed through the instruction cache. It is characterized by writing.
[0016]
Since the processor according to the present invention can write to the memory via the instruction cache, when writing dynamically generated instructions to the memory by dynamic compilation, it can be written via the instruction cache. The need for memory reference is reduced, and in the process of dynamically generating machine language instructions at the time of execution, such as JIT compilation in a virtual machine interpreter, performance degradation caused by main memory reference at the time of dynamic instruction generation can be kept low. be able to
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0018]
FIG. 9 is a diagram showing an example of a computer system that implements the present invention. Software that performs instruction generation processing at the time of execution, such as a JIT compiler in a virtual machine interpreter, is read from the disk device 204 to the main memory 203 and executed by the processor 201. Machine language instructions generated by this software are read and written between the main memory 203 and the processor 201 via the cache 202 which is a high-speed intermediate storage device. Here, for the sake of simplicity, the memory hierarchy is assumed to be two levels of the cache and the main memory, but the present invention can also be applied to a microprocessor having a plurality of cache hierarchies.
[0019]
FIG. 1 is a diagram for explaining an operation outline of a microprocessor employing a non-integrated cache according to the present invention. For comparison with the present invention, first, the operation of a conventional microprocessor employing a non-integrated cache will be described with reference to FIG. In a conventional microprocessor that employs a non-integrated cache, an instruction executed by the CPU 101 is read from the main memory 104 to the instruction cache 102 and transferred to the CPU 101. The instruction fetched in this way is passed to the instruction decoder 108 via the memory unit 107. Further, the instruction is decoded by the instruction decoder 108, and the ALU 105 and the register 106 are controlled based on the decoding result to execute the instruction. Frequently executed instructions are stored in the instruction cache 102, which is a high-speed intermediate storage device, so that it is not necessary to refer to the low-speed main memory 104, so that high-speed execution can be performed.
[0020]
In FIG. 1, a broken line represents a flow of instructions dynamically generated in a dynamic instruction generation process in a conventional microprocessor. A solid line represents the flow of dynamically generated instructions in the present invention. In the description here, for the sake of simplicity, first, a description will be given of a case where no overflow occurs due to cache block contention or insufficient capacity, and a case where cache block overflow occurs will be described later.
[0021]
In the conventional dynamic instruction generation process, as dynamically indicated by the ALU 105 at the time of execution, an instruction dynamically generated at the time of execution is stored in the register 106 and then the data cache 103 via the memory unit 107 as shown by a broken line in FIG. Is written to. When the data cache 103 adopts the write-back method, in this state, the instruction to be executed exists only on the data cache 103, so the cache block in which the instruction is written is written back to the main memory 104. Further, since there is a possibility that a cache block corresponding to the address at which the writing has been performed exists on the instruction cache 102, the block on the instruction cache 102 is invalidated. As a result, the cache block corresponding to the address to which the dynamically generated instruction is written does not exist on the instruction cache 102. Therefore, when the generated instruction is executed, the instruction is read from the main memory 104. An instruction is read out on the cache 102 and transferred to the instruction decoder 108 via the memory unit 107, and the CPU 101 executes the instruction according to the decoding result.
[0022]
On the other hand, in the flow of generated instructions in the dynamic instruction generating process according to the present invention, instructions dynamically generated by the ALU 105 are stored in the register 106 and then stored in the instruction cache 102 via the memory unit 107. Written directly. When the generated instruction is executed, since the generated instruction exists on the instruction cache 102, the memory unit 107 reads the instruction to be executed from the instruction cache 102, and reads the read instruction to the instruction decoder 108. To pass.
[0023]
As described above, in the conventional microprocessor, the instruction written in the data cache 103 is once written from the high-speed cache memory to the low-speed main memory 104 regardless of whether the cache capacity is sufficient or not, and the instruction cache 102 is set again. Via the CPU 101. On the other hand, the microprocessor according to the present invention can execute instructions written directly on the instruction cache 102 without going through the main memory 104, so that the execution of dynamically generated instructions can be executed at high speed. Can do.
[0024]
The above description does not consider cache block eviction due to cache block contention or capacity shortage. Actually, the cache capacity is limited, and cache block contention occurs. Therefore, it is necessary to consider processing at the time of eviction. Therefore, in the following, an instruction write process taking into account the process at the time of cache eviction will be described.
[0025]
In the cache write process, the process for evicting a cache block due to competition or the like differs depending on whether the cache employs a write-through system or a write-back system.
[0026]
In the case of the write-through method, since writing to the main memory is performed simultaneously with writing to the cache, it is only necessary to invalidate the cache block to be evicted. That is, when the instruction cache according to the present invention is configured as a write-through cache, the instruction to be written is written in both the instruction cache and the main memory, so that the latest data is stored in the main memory. Therefore, the contents of the cache block may be discarded when the cache block is evicted.
[0027]
On the other hand, in the case of the write back method, since the latest data exists only in the cache, it is necessary to perform a data write back process to the main memory when the cache block including the update data is evicted. In the conventional processor, since data is written from the CPU to the cache only in the data cache, the data write-back processing from the cache to the main memory is performed only in the data cache. Since the processor according to the present invention also writes to the instruction cache, when the write back method is adopted, it is necessary to consider the process of writing back data from the instruction cache to the main memory. In such a process of writing back data from the instruction cache to the main memory, a method that enables writing directly from the instruction cache to the main memory, and writing to the main memory as before is performed only from the data cache. It is conceivable to do this. Below, the implementation example is shown about each system.
[0028]
FIG. 2 shows the flow of dynamically generated instructions when the architecture is expanded so that cache blocks can be written from the instruction cache to the main memory. In FIG. 2, an instruction dynamically generated by the ALU 105 and stored in the register 106 is written to the instruction cache 102 via the memory unit 107. Here, when an instruction corresponding to an address different from the write address is already held in the cache block 301 to be written, it is necessary to make the cache block available, but depending on the update state of the cache block 301 The process is different. If the cache block 301 is not written (clean), the contents on the main memory 104 and the contents on the instruction cache 102 match, so the write back to the main memory 104 is not performed. The data in the cache block 301 on the instruction cache 102 is discarded. On the other hand, if the cache block 301 is in a written state (dirty), the latest instruction exists only on the instruction cache 102. First, the cache block 301 is moved to the corresponding main storage area 302. Write back.
[0029]
When the original data on the instruction cache 102 is discarded or written back, the data block 303 on the main memory 104 corresponding to the write target address of the dynamically generated instruction is read into the cache block 301 and the memory unit 107 is read. Writes the write target instruction passed from. These operations are the same as those of a normal write-back data cache.
[0030]
FIG. 3 is a diagram showing the flow of a write process to the main memory when the cache block write-back mechanism from the instruction cache to the main memory shown in FIG. 2 is added. As shown in the figure, when the process is started (S401), first, it is determined whether or not the write is a write through the instruction cache (S402). A method for designating / determining whether a certain data write instruction is a write through the data cache or a write through the instruction cache will be described later.
[0031]
As a result of the determination, if the write is via the data cache (S402: NO), the write process via the same data cache as the conventional one is performed (S403), and the process is terminated (S408). On the other hand, if it is a write through the instruction cache (S402: YES), it is checked whether or not a cache block corresponding to the write target address exists on the instruction cache (S404). As a result, when the cache block corresponding to the write target address does not exist on the instruction cache (S404: NO), it is checked whether or not the cache block corresponding to the write target address exists in the data cache. If such a cache block exists and the cache block of the data cache is in a dirty state, the block is written to the main memory (S405), and the block corresponding to the write target address is read to the instruction cache (S406). As a result, since the cache block of the write target address is secured on the instruction cache, the dynamically generated instruction is written into the block of the instruction cache (S407), and the process is terminated (S408). On the other hand, when the cache block corresponding to the write target address exists in the instruction cache (S404: YES), the cache block of the write target address is already secured in the instruction cache. Write (S407), and the process ends (S408).
[0032]
If the cache block corresponding to the instruction write target address exists in the data cache, the data block of the corresponding data cache is discarded (invalidated) or the instruction cache is stored in order to maintain consistency with the instruction cache. Instructions may be written to the data cache together with the cache.
[0033]
FIG. 4 shows the flow of dynamically generated instructions when there is no mechanism for writing directly from the instruction cache 102 to the main memory 104. In this case, since it is not necessary to provide a direct write-back path from the instruction cache to the main memory, the amount of hardware change with respect to the conventional microprocessor can be reduced as compared with that shown in FIG.
[0034]
As shown in FIG. 4, instructions dynamically generated by the ALU 105 and stored in the register 106 are written into the instruction cache 102 and the data cache 103 via the memory unit 107. That is, the data cache 103 also has a copy of the instruction.
[0035]
In this embodiment, there is no cache block write-back path from the instruction cache 102 to the main memory 104 in this embodiment because the data cache 103 has a copy of the instruction (corresponding cache block). This is because when a dynamically generated instruction is written to the instruction cache 102, when the cache overflows and the write back to the main memory becomes necessary, the write back can be performed.
[0036]
When writing to the instruction cache 102 is performed, if the cache overflows and it is necessary to write back to the main memory, the block 501 on the instruction cache to be written back is discarded and the corresponding data cache The update status of the block 502 on 103 is checked, and if it is dirty, it is written back to the corresponding area 504 on the main memory 104. Next, the block 503 corresponding to the write target address is read from the main memory 104 and read into both the instruction cache 102 and the data cache 103. Then, the instruction to be written is written to the block 501 on the instruction cache 102 and the block 502 on the data cache 103.
[0037]
The cache block secured on the data cache 103 corresponding to the data on the instruction cache 102 may be written back to the main memory due to contention due to the data writing to the data cache. Since the contents of the cache block on the instruction cache 102 match the data on the main memory 104, no special operation is required.
[0038]
FIG. 5 is a diagram showing a flow of a write process to the main memory when the cache block write-back mechanism from the instruction cache to the main memory shown in FIG. 4 is not added. As shown in the figure, when writing to the main memory (S601), first, it is checked whether or not the writing is via the instruction cache (S602). A method for specifying / determining whether or not the write is performed via the instruction cache will be described later.
[0039]
As a result of the check, if the write is not a write through the instruction cache (S602: NO), a write process through a normal data cache is performed (S603), and the write process is terminated (S610).
[0040]
On the other hand, if it is a write through the instruction cache (S602: YES), it is first checked whether or not there is a block corresponding to the write target address in the data cache (S604). As a result, if the corresponding block does not exist in the data cache (S604: NO), the block is read out to the data cache (S605). Further, it is checked whether there is a block corresponding to the write target address in the instruction cache (S606).
[0041]
As a result, if the block does not exist in the instruction cache (S606: NO), it is checked whether the block in the data cache is dirty. If it is dirty, the block is written back to the main memory. (S607). Next, the block corresponding to the write target address is read from the main memory to the instruction cache (S608). As a result, the contents of the main memory, the data cache, and the instruction cache match, so the instruction to be written is written to the data cache and the instruction cache (S609), and the process ends (S610).
[0042]
On the other hand, if the block exists in the instruction cache (S606: YES), since the block exists in both the data cache and the instruction cache, the instruction to be written is written in the data cache and the instruction cache (S609). The process ends (S610).
[0043]
In the processing flow described above, if there is no block corresponding to the write target address in the data cache, data is read from the main memory to the data cache (S605), but data is transferred between the instruction cache and the data cache. If data corresponding to the instruction cache exists, the transfer to the main memory can be omitted. Similarly, the block corresponding to the write target address is read from the main memory to the instruction cache (S608), but data can be transferred between the instruction cache and the data cache, and there is data corresponding to the data cache. Can be optimized to copy from the instruction cache, omitting transfers to and from main memory.
[0044]
Next, a method for specifying / determining whether a certain data write is a write through the data cache or a write through the instruction cache will be described. As such a method, for example, the following methods (a) to (c) can be considered.
[0045]
(A) A method of determining for each predetermined memory area such as a page whether the area is to be written via an instruction cache or a data cache, and discriminating based on an address to be written.
[0046]
(B) A method in which an internal flag is provided in the CPU, and it is specified / determined whether the mode is to perform writing via the instruction cache or the data cache by setting the flag.
[0047]
(C) A method for specifying and discriminating by separately preparing a data write command via an instruction cache and a data cache command and using these commands separately.
[0048]
First, as a method corresponding to the method (a) described above, in the instruction set of the microprocessor, for each memory area, writing is performed via the data cache, or writing is performed via the instruction cache. A case where an instruction (for example, “set-dwrite” and “set-iwrite”) for designating an area is provided will be described. When executing writing to the memory, the processor checks which area the write target address corresponds to, and performs writing via the instruction cache or data cache according to the result.
[0049]
The instruction “set-dwrite” is an instruction that specifies that the address area specified by the operand (for example, one page from the address specified by the operand) is an area to be written via the data cache. After the instruction is executed, writing to the designated address area is performed via the data cache. Similarly, the instruction “set-iwrite” is an instruction that specifies that the address area specified by the operand is an area that is to be written via the instruction cache, and is specified after execution of the instruction. Writing to the address area is performed via the instruction cache.
[0050]
FIG. 6 is a diagram illustrating a hardware configuration example when instructions “set-dwrite” and “set-iwrite” are provided. These instructions are read from the memory by the instruction fetch / decode unit 1001, decoded, and subjected to execution control. When the instruction “set-dwrite” or the instruction “set-iwrite” is executed, an address specified by the operand is stored in the direction table 1002 together with a bit indicating whether writing is performed via the instruction cache or data cache. Remembered.
[0051]
When an instruction for writing to the memory, for example, a store instruction is executed and data is stored, first, the value of the register 1003 and the value specified in the store instruction are specified according to the addressing mode specified by the store instruction. One of the immediate values thus selected is selected by the multiplexer 1004, and the adder 1005 calculates the value of the register 1003 to generate an effective address for storing data. Then, the comparator 1006 confirms whether the generated address exists in the direction table 1002, and at the same time, the comparator 1007 determines whether the write target cache designated for the address is an instruction cache. Investigate. As a result, when the store address exists in the direction table 1002 and the write target cache is designated as the instruction cache, the demultiplexer 1008 and the demultiplexer 1009 use the write address and write data as the supply destination. The instruction cache 1011 is selected and writing is performed. On the other hand, when the store address does not exist in the direction table 1002 or when the write target cache is not designated as the instruction cache, the demultiplexer 1008 and the demultiplexer 1009 serve as the write address and write data supply destination. The data cache 1010 is selected and writing is performed. Note that the number of bits to be compared by the comparator 1006 is determined by the size of the designated area.
[0052]
Next, as a method corresponding to the method (b) described above, it indicates whether the mode is a mode in which writing to the memory is performed through the data cache or the instruction cache in the microprocessor. A case will be described in which a flag is provided and flag setting instructions (for example, “set-iwrite-flag” and “reset-iwrite-flag”) are provided in the instruction set. The commands “set-iwrite-flag” and “reset-iwrite-flag” are commands for controlling (setting / resetting) an internal flag (iwrite-flag) provided in the CPU. In accordance with the set value, it is determined whether to write data via the instruction cache or to write data via the data cache.
[0053]
Here, the instruction “set-iwrite-flag” is an instruction for setting an internal flag so that writing is performed via the instruction cache, and all write instructions after execution of the instruction are performed via the instruction cache. . On the other hand, the instruction “reset-iwrite-flag” is an instruction that resets the internal flag so that writing is performed via the data cache. All writing after the execution of the instruction is performed via the data cache. Is called.
[0054]
FIG. 7 is a diagram illustrating a hardware configuration example in the case where an internal flag and instructions “set-iwrite-flag” and “reset-iwrite-flag” are provided. The instructions “set-iwrite-flag” and “reset-iwrite-flag” are read from the memory by the instruction fetch / decode unit 1101, decoded, and subjected to execution control. When the instruction “set-dwrite-flag” or “set-iwrite-flag” is executed, a flag indicating the current write mode is stored in the internal flag (iwrite-flag) 1102.
[0055]
When data is written by a store instruction or the like, an effective address is generated by the register 1103, the multiplexer 1104, and the adder 1105 as in the case of FIG. Then, the demultiplexers 1106 and 1107 select an address and data supply destination according to the value of the flag 1102, and write to the data cache 1109 or the instruction cache 1108.
[0056]
Finally, as a method corresponding to the method (c) described above, a case will be described in which designation / determination of whether to write data via the instruction cache or to write data via the data cache is performed according to the instruction code. To do. That is, in the microprocessor instruction set, as a data write instruction, in addition to a normal instruction for writing data via a data cache (for example, “write”), a data write via an instruction cache is performed. An instruction to be executed (for example, “iwrite”) is prepared, and the software or the like selects a cache to be used when writing to the main memory by appropriately selecting and using these two kinds of instructions.
[0057]
When the instruction “iwrite” is executed, the data (instruction) stored in the register or the like specified by the operand is written to the effective address specified by the operand via the instruction cache.
[0058]
FIG. 8 is a diagram illustrating a hardware configuration example when the instruction “iwrite” is provided. The instruction “iwrite” is read from the main memory or the instruction cache by the instruction fetch / decode unit 1201, decoded, and execution control is performed. When data is stored by the store instruction “iwrite” for the instruction cache, an address is first generated by the register 1203, the multiplexer 1204, and the adder 1205 in the same manner as described above. The demultiplexers 1206 and 1207 select the instruction cache 1208 as a data write destination by the output signal 1202 indicating that the instruction is a store instruction for the instruction cache from the instruction fetch / decode unit 1201, and write I do.
[0059]
Similarly, when data is stored by the store instruction “write” for the data cache, the demultiplexers 1206 and 1207 use the output signal 1202 from the instruction fetch / decode unit 1201 as the address and data supply destination. A cache is selected and writing to the data cache 1209 is performed.
[0060]
By providing the microprocessor with a mechanism that can control the writing to the instruction cache as described above, the transfer of unnecessary data between the main memory and the cache (or between the upper cache and the lower cache) is reduced. Therefore, it is possible to improve the performance of a program that performs dynamic instruction generation.
[0061]
Finally, a dynamic compiler executed on the microprocessor according to the present invention as described above will be described. In the microprocessor according to the present invention, writing to the instruction cache can be controlled by software, so that the dynamic compiler uses any of the above-described methods when storing dynamically generated instructions in the main memory during program execution. Write through the instruction cache. Other operations may be the same as those of the conventional dynamic compiler. In this way, the necessity of referring to the main memory when storing dynamically generated instructions in the main memory is reduced, and the program can be executed at high speed.
[0062]
【The invention's effect】
As described above in detail, according to the present invention, in a program that dynamically generates machine language instructions at the time of execution, the generated machine language instructions can be directly written to the instruction cache. As a result, the execution speed of a program that dynamically generates machine language instructions at the time of execution can be increased.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining an outline of operation of a microprocessor of a non-integrated cache according to the present invention.
FIG. 2 is a diagram showing a flow of dynamically generated instructions in a microprocessor provided with a write path from an instruction cache to main memory.
FIG. 3 is a diagram showing a flow of write processing in a microprocessor provided with a write path from an instruction cache to main memory.
FIG. 4 is a diagram illustrating a flow of dynamically generated instructions in a microprocessor that does not have a write path from the instruction cache to the main memory.
FIG. 5 is a diagram showing the flow of write processing in a microprocessor that does not have a write path from the instruction cache to the main memory.
FIG. 6 is a diagram illustrating a hardware configuration example of a microprocessor provided with an instruction that can specify a write target cache for each predetermined memory area;
FIG. 7 is a diagram illustrating a hardware configuration example of a microprocessor provided with an internal flag that designates a mode for writing via an instruction cache or a mode for writing via a data cache.
FIG. 8 is a diagram illustrating a hardware configuration example of a microprocessor provided with an instruction to perform writing via an instruction cache.
FIG. 9 is a diagram showing an example of a computer system to which the present invention is applied.
[Explanation of symbols]
101 CPU
102 Instruction cache
103 Data cache
104 Main memory
105 ALU
106 registers
107 Memory unit
108 Instruction decoder

Claims (5)

Provided with a flag indicating whether it is a mode for writing via the data cache or a mode for writing via the instruction cache,
A processor which performs writing through an instruction cache when the flag indicates a mode of writing through the instruction cache. The processor of claim 1 in the instruction set, and having an instruction for operating the flag. A processor comprising an instruction in the instruction set for instructing writing to a memory through an instruction cache. The processor according to any one of claims 1 to 3 , wherein when an instruction to write through the instruction cache is instructed, writing to both the instruction cache and the data cache is performed. A method of dynamic compilation using a processor according to any one of claims 1 to 4 ,
A method of dynamic compilation, wherein when dynamically generated instructions are written to a memory, the instructions are written via an instruction cache.

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