JP2000029787A - Processor equipped with writing-in mechanism for instruction caches - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress low the decrease in performance due to main storage reference at dynamic instructing generating by providing in an instruction set an instruction, capable of specifying by each memory area as an area which is written through a data cache or an area which is written through an instruction cache. SOLUTION: In the instruction set, the instruction is provided which can specify each memory area as an area which is written via the data case or an area which is written through the instruction cache. This processor writes an instruction generated dynamically by ALU 105 directly to the instruction cache 102 through a memory unit 107, after it is stored in a register 106. The generated instruction, when executed is read out of the instruction cache 102 by a memory unit 107 and passed to an instruction decoder 108. Thus, the instruction written to the instruction cache 102 can be executed directly not through a main storage 104, so that the execution of the dynamically generated instruction can be speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a processor and, more particularly, to a microprocessor suitable for executing a virtual machine interpreter or the like which dynamically generates and executes a machine language instruction program at the time of execution.

[0002]

2. Description of the Related Art In a conventional microprocessor, a cache is often provided as a high-speed intermediate storage device between a main memory (main memory) and a CPU. This cache can be classified into a non-integrated cache in which a data cache and an instruction cache are separated, and an integrated cache in which a data cache and an instruction cache are integrated. Compared with the latter unified cache, the former non-integrated cache can generally provide higher data supply bandwidth to each of the data cache and the instruction cache, so that generally higher performance can be obtained. For this reason, non-integrated caches are often used in high-end microprocessors.

On the other hand, as a programming language for describing a program executed by such a microprocessor, Java (Java is a trademark of Sun Microsystems, I.
nc. and Smalltalk are known. Programs written in these programming languages are temporarily converted into virtual computer instructions called bytecodes, and the bytecodes are usually executed by software called a virtual machine interpreter.

However, execution by such a virtual machine interpreter has a large overhead such as interpretation and execution of a virtual machine instruction. Therefore, Java and Smallta
Generally, the execution speed of a program described in lk is lower than that of a program described in a conventional compiler type language such as C or FORTRAN. For example, LP Deutsch and AM Chiffman
Efficient Implementation of the Smalltalk-80 Syste
m ”(In Proceedings of the 11th Annual ACM Symposi
um on Principles of Programming Languages pp.297-3
02, 1984), a machine language instruction that performs the equivalent processing is generated at execution time for a virtual machine instruction sequence to be executed, and the generated machine language instruction is directly executed to execute the interpreter. A technique for speeding up execution is used. Such a method is called dynamic compilation because machine language instructions are dynamically generated at the time of execution, or JIT (Just-In-Time) compilation because it is compiled when execution is attempted. Called, Ja
It is used for speeding up va virtual machines.

[0005]

The JIT compilation technique for dynamically generating instructions at the time of execution is effective for speeding up a virtual machine interpreter or the like, but a microcontroller employing a non-integrated cache mechanism is effective. Considering the use in the processor, the instruction generated at the time of execution,
Since it is necessary to write to main memory at the time of execution,
The following problems will occur.

[0006] Writing a dynamically generated instruction to the main memory is not different from normal data writing from the viewpoint of the processor. Therefore, in a processor employing a non-integrated cache, the instruction is written via the data cache. Will be Therefore, immediately after the generated instruction is written to the memory via the data cache, even if the written instruction is to be executed, the instruction cache and the data cache are not maintained in a consistent state. Can not. That is, since the instruction cache is not updated, an unexpected instruction may be executed as it is. Therefore, most microprocessors have instructions for writing back data in a specified data cache to a main memory or invalidating a cache block in an instruction cache.
Before executing the instruction written to the main memory, the instruction cache data corresponding to the written address is discarded (invalidated) and the write-back type is used. In this case, the data in the data cache corresponding to the written address is written back to the main memory so that the change is reflected in the main memory.

In other words, dynamic instruction generation and execution processing
It is performed in the following flow.

[0008] 1. Write a dynamically generated machine language instruction to the cache block of the data cache corresponding to the write target address (hereinafter, referred to as address A) 2. Discard the cache block of the instruction cache corresponding to address A 3. Address A 3. Write-back of the cache block of the data cache corresponding to the above to the main memory (in the case of the write-back type cache) 4. Read from the address A of the main memory to the corresponding cache block of the instruction cache Reading and Executing Instructions from the Instruction Cache As described above, in a microprocessor employing a non-integrated cache, if an instruction is dynamically generated at the time of execution, and if the generated instruction is executed, the The generated instruction must be written to the data cache, written to the main memory, and then read to the instruction cache, which involves writing and reading to the main memory. This can be a factor in reducing speed.

Particularly, in a high-end microprocessor capable of processing a large number of instructions in the time required for referring to the main memory by improving the instruction level parallelism and the operating frequency in the processor, the dynamic required by the overhead required for the main memory reference is increased. There is a possibility that the problem that the operation performance of the program that performs the instruction generation processing is reduced may become serious.

In a conventional static compiler type language such as C or FORTRAN, conversion into machine language instructions is performed in advance before program execution, and instructions are not dynamically generated at the time of execution. Even with this cache configuration, there was no major problem. An object of the present invention is to suppress a decrease in performance caused by referencing main memory at the time of dynamic instruction generation in a process of dynamically generating machine language instructions at the time of execution, such as JIT compilation in a virtual machine interpreter. It is to provide a processor which can do it.

[0011]

According to the present invention, there is provided a processor in which, for each predetermined memory area, an area for writing via a data cache or an area for writing via an instruction cache is included in an instruction set. Characterized by having an instruction capable of designating an area for performing In this case, for the memory area designated as the area to be written via the instruction cache by the instruction,
When writing is instructed, writing is performed via the instruction cache.

Further, a second processor according to the present invention comprises:
If there is a flag indicating whether the mode is a mode for writing via the data cache or a mode for writing via the instruction cache, and if the flag indicates a mode for writing via the instruction cache, , Writing is performed via an instruction cache. In this case, it is preferable that the instruction set includes an instruction for operating the flag.

Further, a third processor according to the present invention comprises:
The present invention is characterized in that an instruction set includes an instruction for instructing writing to a memory via an instruction cache.

In the first to third processors, when writing via the instruction cache is instructed, writing may be performed to both the instruction cache and the data cache. In this case, since a copy of the updated data of the instruction cache exists in the data cache, a cache overflow occurs in the instruction cache without providing a direct write-back path from the instruction cache to the memory. Write-back of the updated data to the main memory becomes possible.

Further, a dynamic compilation method according to the present invention is a dynamic compilation method using the above-described first to third processors, wherein a dynamically generated instruction is written in a memory. It is characterized in that writing is performed via a cache.

In the processor according to the present invention, writing to the memory can be performed via the instruction cache. Therefore, when dynamically generated instructions are written to the memory by dynamic compilation, the instructions can be written via the instruction cache. And the need for main memory reference is reduced, and in processing that dynamically generates machine language instructions at execution time, such as JIT compilation in a virtual machine interpreter, performance degradation caused by main memory reference during dynamic instruction generation Can be kept low

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 9 is a diagram showing an example of a computer system for implementing the present invention. Software that performs instruction generation processing at the time of execution, such as a JIT compiler in a virtual machine interpreter, is read from the disk device 204 to the main storage 203 and executed by the processor 201. The machine language instructions generated by this software are sent to the main memory 20 via a cache 202 which is a high-speed intermediate storage device.
3 and the processor 201. Here, for simplicity, the memory hierarchy is a cache and a main memory, but the present invention can also be applied to a microprocessor having a plurality of cache hierarchies.

FIG. 1 is a diagram for explaining the outline of the operation of a microprocessor employing a non-integrated cache according to the present invention. First, the operation of a conventional microprocessor employing a non-integrated cache will be described with reference to FIG. In a conventional microprocessor employing a non-integrated cache, instructions to be executed by the CPU 101 are read from the main memory 104 to the instruction cache 102 and passed to the CPU 101. The instruction fetched in this way is passed to the instruction decoder 108 via the memory unit 107. Further, the instruction is decoded by the instruction decoder 108, and based on the decoding result, the ALU 105 and the register 106 are controlled to execute the instruction. Frequently executed instructions are stored in the instruction cache 10 which is a high-speed intermediate storage.
By saving the data in the second storage area, it is not necessary to refer to the low-speed main memory 104, so that high-speed execution can be performed.

In FIG. 1, a broken line indicates a flow of dynamically generated instructions in a dynamic instruction generation process in a conventional microprocessor. The solid line represents the flow of dynamically generated instructions in the present invention. In this description, for simplicity, first, a case where overflow due to cache block contention or capacity shortage does not occur will be described, and a case where cache block overflow occurs will be described later.

As shown by the broken line in FIG. 2, in the conventional dynamic instruction generation processing, an instruction dynamically generated at the time of execution by the ALU 105 is stored in the register 106 and then transmitted to the memory unit 107 via the memory unit 107. The data is written to the data cache 103. When the data cache 103 employs the write-back method, the instruction to be executed exists only in the data cache 103 in this state, so that the cache block in which the instruction is written is written back to the main memory 104. Further, since there is a possibility that a cache block corresponding to the address at which the writing has been performed exists on the instruction cache 102, the block on the instruction cache 102 is invalidated if it exists. As a result, the cache block corresponding to the address at which the dynamically generated instruction has been written no longer exists in the instruction cache 102. Therefore, when the generated instruction is executed, The instruction is read onto the cache 102 and passed to the instruction decoder 108 via the memory unit 107,
The instruction is executed by the CPU 101 according to the decoding result.

On the other hand, in the flow of the generated instruction in the dynamic instruction generation processing of the present invention, the instruction dynamically generated by the ALU 105 is stored in the register 106 and then transmitted through the memory unit 107. Written directly to cache 102. When executing the generated instruction, since the generated instruction exists in the instruction cache 102, the memory unit 107 reads the instruction to be executed from the instruction cache 102, and stores the read instruction in the instruction decoder 108. Pass to

As described above, in the conventional microprocessor, regardless of whether there is a margin in the cache capacity,
The instruction written in the data cache 103 must once be written from the high-speed cache memory to the low-speed main memory 104 and read out to the CPU 101 again via the instruction cache 102. On the other hand, in the microprocessor according to the present invention, the instruction written in the instruction cache 102 can be directly executed without the intervention of the main memory 104, so that the speed of execution of the dynamically generated instruction can be increased. Can be.

The above description does not consider cache block eviction due to cache block contention or capacity shortage. Actually, the cache capacity is limited, and contention of cache blocks occurs. Therefore, it is necessary to consider processing at the time of eviction. Therefore, an instruction writing process in consideration of a cache eviction process will be described below.

In the process of writing data to the cache, the process for flushing the cache block due to competition or the like depends on whether the cache employs a write-through system or a write-back system. different.

In the case of the write-through method, since writing to the main memory is performed simultaneously with writing to the cache, it is sufficient to simply invalidate the cache block to be evicted. That is, when the instruction cache according to the present invention is configured as a write-through cache, the instruction to be written is written to both the instruction cache and the main memory, so that the latest data is stored in the main memory. When the cache block is evicted, the contents of the cache block may be discarded.

On the other hand, in the case of the write-back method, since the latest data exists only in the cache, it is necessary to write back the data to the main memory when flushing the cache block containing the updated data. In a conventional processor, data is written from the CPU to the cache only in the data cache.
The process of writing back data from the cache to the main memory has been performed only by the data cache. In the processor according to the present invention, writing to the instruction cache is also performed. Therefore, when the write-back method is adopted, it is necessary to consider a process of writing back data from the instruction cache to the main memory. For the write-back processing of data from the instruction cache to the main memory, a method that enables writing from the instruction cache directly to the main memory is used. It is considered that the method is In the following, examples of realizing the respective methods will be described.

FIG. 2 shows the flow of dynamically generated instructions when the architecture is extended so that a cache block can be written from the instruction cache to the main memory. 2, an instruction dynamically generated by the ALU 105 and stored in the register 106 is written to the instruction cache 102 via the memory unit 107. Here, when an instruction corresponding to an address different from the write address is already held in the cache block 301 to be written, it is necessary to make the cache block available, but depending on the update state of the cache block 301, The processing is different. If the cache block 301 has not been written (clean), the contents in the main memory 104 and the contents in the instruction cache 102 match, so that writing back to the main memory 104 is not performed. , The data in the cache block 301 on the instruction cache 102 is discarded. On the other hand, if the cache block 301 has been written (dirty), the latest instruction exists only in the instruction cache 102.
Area 3 in main memory corresponding to cache block 301
Write back to 02.

When the discarding or writing back of the original data in the instruction cache 102 is completed, the data block 303 in the main memory 104 corresponding to the write target address of the dynamically generated instruction is read into the cache block 301, and The write target instruction passed from the memory unit 107 is written. These operations are the same as those of a normal write-back type data cache.

FIG. 3 is a diagram showing a flow of a write process to the main memory when a mechanism for writing back a cache block from the instruction cache to the main memory shown in FIG. 2 is added. As shown in the figure, when the processing is started (S40)
1) First, it is determined whether the write is a write via the instruction cache (S402). A method of designating and determining whether a certain data write instruction is a write via a data cache or a write via an instruction cache will be described later.

As a result of the determination, if the write is via the data cache (S402: NO), the same write processing via the data cache as in the prior art is performed (S402).
403), and the process ends (S408). On the other hand, if the write is via the instruction cache (S402: YE
S), it is checked whether or not a cache block corresponding to the write target address exists in the instruction cache (S).
404). As a result, if the cache block corresponding to the write target address does not exist in the instruction cache (S404: NO), it is subsequently checked whether or not there is a cache block corresponding to the write target address in the data cache. If such a cache block exists and the cache block of the data cache is in a dirty state, the block is written to the main memory (S405), and the block corresponding to the write target address is read to the instruction cache (S406). As a result, a cache block of the address to be written is secured in the instruction cache, and the dynamically generated instruction is written in the block of the instruction cache (S4).
07), the process ends (S408). On the other hand, if the cache block corresponding to the write target address exists in the instruction cache (S404: YES), the cache block of the write target address is already secured in the instruction cache, and the instruction is stored in the instruction cache as it is. Write (S407) and end the process (S4
08).

When a cache block corresponding to an instruction write target address exists in the data cache, the data block of the data cache is discarded (invalidated) in order to maintain consistency with the instruction cache.
Alternatively, the instructions may be written in the data cache together with the instruction cache.

FIG. 4 shows the flow of dynamically generated instructions when there is no mechanism for directly writing from the instruction cache 102 to the main memory 104. In this case, since there is no need to provide a direct write-back path from the instruction cache to the main memory, the amount of hardware changes to the conventional microprocessor is smaller than that shown in FIG.

As shown in FIG. 4, the instructions dynamically generated by ALU 105 and stored in register 106 are:
Instruction cache 102 via memory unit 107
Is written to the data cache 103. That is, it is assumed that the data cache 103 has a copy of the instruction.

As described above, the data cache 103 also has a copy of the instruction (the cache block corresponding to the instruction). In this embodiment, there is a cache block write-back path from the instruction cache 102 to the main memory 104. Therefore, when writing a dynamically generated instruction to the instruction cache 102, cache overflow occurs, and if writing back to the main memory is required, the writing back can be performed. It is.

When writing to the instruction cache 102 causes overflow of the cache and writing back to the main memory is necessary, the block 501 in the instruction cache to be written back is discarded, and The update status of the block 502 on the data cache 103 is checked, and if it is dirty, it is written back to the corresponding area 504 on the main memory 104. Next, the block 503 corresponding to the write target address is read from the main memory 104 and read into both the instruction cache 102 and the data cache 103. Then, the instruction to be written is stored in the block 501 on the instruction cache 102 and the data cache 10.
3 to block 502.

It should be noted that a cache block secured on the data cache 103 corresponding to the data on the instruction cache 102 may be written back to the main memory due to contention caused by writing data to the data cache. In this case, since the contents of the cache block in the instruction cache 102 and the data in the main memory 104 match, there is no need to perform any special operation.

FIG. 5 is a diagram showing a flow of a write process to the main memory when the mechanism for writing back the cache block from the instruction cache to the main memory shown in FIG. 4 is not added. As shown in the figure, when writing to the main memory (S601), first, it is checked whether or not writing is performed via the instruction cache (S602). A method of specifying / determining whether the writing is a writing via the instruction cache will be described later.

As a result of the check, if the write is not a write via the instruction cache (S602: NO),
A write process is performed via a normal data cache (S603), and the write process ends (S610).

On the other hand, if the write is via the instruction cache (S602: YES), it is first checked whether or not a block corresponding to the write target address exists in the data cache (S604). As a result, if the corresponding block does not exist in the data cache (S604:
NO), the block is read out to the data cache (S605). Further, it is checked whether a block corresponding to the write target address exists in the instruction cache (S606).

As a result, if the block does not exist in the instruction cache (S606: NO), it is checked whether or not the block in the data cache is dirty. Is written back (S607). Next, the block corresponding to the write target address is read from the main memory to the instruction cache (S
608). As a result, the contents of the main memory, the data cache, and the instruction cache match, so that the instruction to be written is written to the data cache and the instruction cache (S
609), and the process ends (S610).

On the other hand, if the block exists in the instruction cache (S606: YES), the block exists in both the data cache and the instruction cache, so that the instruction to be written is written in the data cache and the instruction cache ( In step S609, the process ends (S6).
10).

In the above-described processing flow, if there is no block corresponding to the write target address in the data cache, the data is read from the main memory to the data cache (S605). If data corresponding to the instruction cache exists, transfer to and from the main memory can be omitted if data transfer is possible between them. Similarly, the block corresponding to the write target address is read from the main memory to the instruction cache (S608), but data can be transferred between the instruction cache and the data cache and there is data corresponding to the data cache. Can be optimized to copy from the instruction cache, omitting transfers to and from main storage.

Next, a method for designating and determining whether a certain data write is a write via a data cache or a write via an instruction cache will be described. For example, the following methods (a) to (c) are conceivable.

(A) For each predetermined memory area such as a page,
A method in which a write area can be designated via an instruction cache or a data cache, and a determination is made based on an address to be written.

(B) A method in which an internal flag is provided in the CPU, and the setting of the flag specifies / determines whether the mode is one in which writing is performed via the instruction cache or the data cache.

(C) A method in which an instruction via a command cache and an instruction via a data cache are separately prepared as data write instructions, and these instructions are properly used to specify / determine.

First, as a method corresponding to the above method (a), the instruction set of the microprocessor includes:
An instruction (for example, “set-dw”) for specifying, for each memory area, whether the area is to be written via the data cache or the area to be written via the instruction cache.
rite ”and“ set-iwrite ”). When executing writing to the memory, the processor checks which area the write target address corresponds to, and performs writing via the instruction cache or the data cache according to the result.

The instruction "set-dwrite" indicates that the address area specified by the operand (for example, one page from the address specified by the operand) is an area to be written via the data cache. This is an instruction to be specified, and after execution of the instruction, writing to the specified address area is performed via the data cache. Similarly, the instruction "set-iwrite"
Is an instruction designating that the address area specified by the operand is an area where writing should be performed via the instruction cache. After execution of the instruction, writing to the specified address area is performed via the instruction cache. Done.

FIG. 6 shows instructions “set-dwrite” and “set-iw”.
FIG. 6 is a diagram illustrating an example of a hardware configuration when “rite” is provided. These instructions are read from the memory by the instruction fetch / decode unit 1001, decoded, and execution control is performed. When the instruction “set-dwrite” or the instruction “set-iwrite” is executed, the address specified by the operand is stored in the direction table 1002 together with the bit indicating whether the write is performed through the instruction cache or the data cache. It is memorized.

Then, an instruction for writing to the memory,
For example, when a store instruction is executed to store data, first, according to the addressing mode specified by the store instruction, either the value of the register 1003 or the immediate value (immediate) specified in the store instruction is stored. The selection is performed by a multiplexer 1004 and an adder 1005 is selected.
Then, an effective address for storing data is generated by calculating the value of the register 1003. Then, the comparator 1006 checks whether the generated address exists in the direction table 1002, and at the same time, the comparator 1007 determines whether the write target cache specified for the address is an instruction cache. Find out. As a result, when the store address exists in the direction table 1002 and the cache to be written is specified as the instruction cache, the demultiplexer 1008 and the demultiplexer 1009 set the write address and the write data as the supply destination. The instruction cache 1011 is selected and writing is performed. On the other hand, if the store address does not exist in the direction table 1002 or the write target cache is not designated as the instruction cache, the demultiplexer 1008 and the demultiplexer 1009 use the demultiplexer 1008 and the demultiplexer 1009 as the write address and write data supply destination. , The data cache 1010 is selected and writing is performed. Note that the number of bits to be compared by the comparator 1006 depends on the size of the designated area.
Is determined.

Next, as a method corresponding to the above-mentioned method (b), a mode in which writing to a memory is performed via a data cache or an instruction cache inside a microprocessor is performed. And a flag setting instruction (for example, “set-iwrite-flag” and “reset
-iwrite-flag ") will be described. The instructions "set-iwrite-flag" and "reset-iwrite-flag"
This is an instruction for controlling (set / reset) an internal flag (iwrite-flag) provided in the PU.
Determines whether to write data via the instruction cache or to write data via the data cache according to the setting value of this flag.

Here, the instruction "set-iwrite-flag" is an instruction for setting an internal flag so that writing is performed via the instruction cache, and all write instructions after execution of the instruction are transmitted via the instruction cache. Done. On the other hand, the instruction “reset-iwrite-flag” is an instruction for resetting an internal flag so that writing is performed via the data cache, and all writing after execution of the instruction is performed via the data cache. Will be

FIG. 7 shows an internal flag and an instruction "set-iwri".
It is a figure which shows the example of a hardware structure at the time of providing "te-flag" and "reset-iwrite-flag". The instruction `` set-iwrite-f
The “lag” and “reset-iwrite-flag” are read from the memory and decoded by the instruction fetch / decode unit 1101, and execution control is performed. The instruction `` set-dw
When "rite-flag" or "set-iwrite-flag" is executed,
The flag indicating the current write mode is an internal flag (iwri
te-flag) 1102.

When data is written by a store instruction or the like, the effective address is stored in the register 1103, the multiplexer 1104,
It is generated by the adder 1105. Then, the demultiplexers 1106 and 1107 select an address and a data supply destination in accordance with the value of the flag 1102, and write the data and data into the data cache 1109 or the instruction cache 1108.

Finally, as a method corresponding to the above-mentioned method (c), it is designated and determined whether to write data via an instruction cache or to write data via a data cache by an instruction code. The case will be described. That is, in the instruction set of the microprocessor, as a data write instruction, in addition to a normal instruction for writing data via the data cache (for example, “write”), a data write via the instruction cache is included. The instruction to perform (eg, "iwrite")
, And software or the like selects a cache for writing to the main memory by appropriately selecting and using these two types of instructions.

When the instruction “iwrite” is executed, the data (instruction) stored in the register or the like specified by the operand is written to the effective address specified by the operand via the instruction cache.

FIG. 8 is a diagram showing an example of a hardware configuration in the case where the instruction "iwrite" is provided. The instruction "iwrite"
The instruction fetch / decode unit 1201 reads the data from the main memory or the instruction cache, decodes the data, and controls the execution. When data is stored by a store instruction “iwrite” for the instruction cache, first, the register 120
3. The address is generated by the multiplexer 1204 and the adder 1205. In the demultiplexers 1206 and 1207, the instruction fetch / decode unit 1201
The instruction cache 1208 is selected as a data write destination by the output signal 1202 indicating that the instruction is a store instruction for the instruction cache, and writing is performed.

Similarly, when data is stored by a store instruction “write” for a data cache, the demultiplexers 1206 and 1207 output signals 120 from the instruction fetch / decode unit 1201.
2, the data cache is selected as the address and data supply destination, and writing to the data cache 1209 is performed.

By providing a mechanism for controlling writing to the instruction cache by software as described above in the microprocessor, transfer of unnecessary data between the main memory and the cache (or between the upper cache and the lower cache) is performed. , And the performance of a program that dynamically generates instructions can be improved.

Finally, a dynamic compiler executed on the microprocessor according to the present invention as described above will be described. In the microprocessor according to the present invention, since writing to the instruction cache can be controlled by software, the dynamic compiler uses any one of the above-described methods when storing dynamically generated instructions in the main memory during program execution. And write via the instruction cache. Other operations may be the same as those of the conventional dynamic compiler. This reduces the need for main memory reference when storing dynamically generated instructions in main memory,
The program can be executed at high speed.

[0062]

As described above in detail, according to the present invention, in a program for dynamically generating a machine language instruction at the time of execution, it is possible to write the generated machine language instruction directly to the instruction cache. Become. As a result, it is possible to speed up the execution of a program that dynamically generates a machine language instruction at the time of execution.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an operation outline of a microprocessor of a non-integrated cache according to the present invention.

FIG. 2 is a diagram showing a flow of dynamically generated instructions in a microprocessor provided with a write path from an instruction cache to a main memory.

FIG. 3 is a diagram showing a flow of a write process in a microprocessor provided with a write path from an instruction cache to a main memory.

FIG. 4 is a diagram showing a flow of dynamically generated instructions in a microprocessor having no write path from an instruction cache to a main memory.

FIG. 5 is a diagram showing a flow of a write process in a microprocessor having no write path from an instruction cache to a main memory.

FIG. 6 is a diagram illustrating an example of a hardware configuration of a microprocessor provided with an instruction capable of specifying a write target cache for each predetermined memory area;

FIG. 7 shows a mode for writing via an instruction cache;
FIG. 3 is a diagram illustrating an example of a hardware configuration of a microprocessor provided with an internal flag that specifies a writing mode via a data cache.

FIG. 8 is a diagram illustrating a hardware configuration example of a microprocessor provided with an instruction to perform writing via an instruction cache.

FIG. 9 is a diagram illustrating an example of a computer system to which the present invention is applied.

[Explanation of symbols]

 101 CPU 102 Instruction Cache 103 Data Cache 104 Main Memory 105 ALU 106 Register 107 Memory Unit 108 Instruction Decoder

Claims (7)

[Claims] 1. An instruction capable of designating, in an instruction set, for each predetermined memory area, whether the area is an area for writing via a data cache or an area for writing via an instruction cache. A processor comprising: 2. The method according to claim 1, wherein when writing is instructed to a memory area specified as an area to be written via an instruction cache by the instruction, writing is performed via the instruction cache. The processor according to claim 1. 3. A mode for writing data via a data cache or a mode for writing data via an instruction cache, wherein the flag is a mode for writing data via an instruction cache. If so, writing is performed via an instruction cache. 4. The processor according to claim 3, further comprising an instruction for operating said flag in an instruction set. 5. The processor according to claim 1, further comprising an instruction in the instruction set for instructing writing to the memory via the instruction cache. 6. The processor according to claim 1, wherein when writing via the instruction cache is instructed, writing is performed to both the instruction cache and the data cache. 7. A method for dynamically compiling using a processor according to claim 1, wherein when dynamically generated instructions are written to a memory, said instructions are transmitted via an instruction cache. A dynamic compilation method characterized by writing.