JP3675073B2 - Electronics - Google Patents

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Publication number
JP3675073B2
JP3675073B2 JP32257196A JP32257196A JP3675073B2 JP 3675073 B2 JP3675073 B2 JP 3675073B2 JP 32257196 A JP32257196 A JP 32257196A JP 32257196 A JP32257196 A JP 32257196A JP 3675073 B2 JP3675073 B2 JP 3675073B2
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JP
Japan
Prior art keywords
insulating film
hole
insulating
sides
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP32257196A
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Japanese (ja)
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JPH10163606A (en
Inventor
安成 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP32257196A priority Critical patent/JP3675073B2/en
Publication of JPH10163606A publication Critical patent/JPH10163606A/en
Application granted granted Critical
Publication of JP3675073B2 publication Critical patent/JP3675073B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は両面基板を有する電子機器に関するものである。
【０００２】
【従来の技術】
両面基板は電子部品の実装効率を上げることができることから、この両面基板自体を小さくして電子機器の小型化を図ることができるものであって、従来のものは図２に示す構成となっていた。
【０００３】
すなわち図２に示すごとく両面に導電パターン１を有し、少なくとも、両面の導電パターン１の一部がスルーホール２を介して接続された基板３を備え、前記基板３のスルーホール２部両側を絶縁膜４，５で覆い、一方の絶縁膜４上には導電パターン６を介して第１の電子部品７を導電性接着剤８で実装し、他方の絶縁膜５上には第２の電子部品９を絶縁性接着剤１０で実装した構成となっていた。
【０００４】
【発明が解決しようとする課題】
上記従来例においてはスルーホール２の両側が絶縁膜４，５で覆われているので、これらの絶縁膜４，５を塗布後焼成する時にスルーホール２内の空気が膨張し、その結果としてこれらの絶縁膜４，５が外方に膨れてしまい、これによって第１、第２の電子部品７，９の実装が出来なくなってしまうという問題があった。
【０００５】
そこで本発明はスルーホールの両面側において電子部品の実装が確実に行えるようにすることを目的とするものである。
【０００６】
【課題を解決するための手段】
そしてこの目的を達成するために本発明は、絶縁膜は焼成によって形成し、前記一方の絶縁膜は、前記スルーホールを覆って形成するとともに、前記他方の絶縁膜は、前記スルーホール対向部分を開口させるものであって、スルーホールの他方側の絶縁膜に開口を設けているので、絶縁膜の焼成時にスルーホール内の空気が膨張しても、スルーホール対向部分の絶縁膜が膨れ上がることはない。これにより、両方の絶縁膜に、電子部品を確実に実装することができる。
【０００７】
【発明の実施の形態】
本発明の請求項１の発明は、両面に導電パターンを有し、少なくとも、両面の導電パターンの一部がスルーホールを介して接続された基板と、前記基板のスルーホール部両側を覆う絶縁膜と、この一方の絶縁膜上に導電パターンを介して導電性接着剤で実装された第１の電子部品と、他方の絶縁膜上に絶縁性接着剤で実装された第２の電子部品とを備え、前記絶縁膜は焼成によって形成し、前記一方の絶縁膜は、前記スルーホールを覆って形成するとともに、前記他方の絶縁膜は、前記スルーホール対向部分を開口させる電子機器であって、一方の絶縁膜は、前記スルーホールを覆って形成するとともに、スルーホールの他方側の絶縁膜に開口を設けているので、絶縁膜の焼成時にスルーホール内の空気が膨張しても、スルーホール対向部分の絶縁膜が膨れ上がることはない。従って、両方の絶縁膜上に、電子部品を確実に実装することができるものとなる。
【０００８】
また本発明の請求項２の発明は、他方の絶縁膜のスルーホール対向部分に設けた開口の直径は、スルーホールの直径よりも大きくした請求項１に記載の電子機器であって、他方の絶縁膜の塗布時にスルーホール内にその一部が流入することがなく、常にスルーホールとしての開口が確実に得られ、よって第１、第２の電子部品の実装も確実に行われるものとなる。
【０００９】
さらに本発明の請求項３の発明は、一方の絶縁膜が、基板上に塗布された後に
、この塗布面を上面側にして焼成されたものである請求項１に記載の電子機器であって、一方の絶縁膜はスルーホールの一方側を覆っており、そこ絶縁膜に対する支持接着面が無い部分となっているので、この面を下面側にして絶縁膜の焼成を行うと、下方に垂れ下がって膨れた状態となってしまうのを、この面を上面側として焼成することで、防止するのである。
【００１０】
以下本発明の一実施形態を添付図面とともに説明する。
図１に示すごとく本実施形態においては、両面に銀−パラジウムの合金よりなる導電パターン１１を有し、少なくとも、両面の導電パターン１１の一部がスルーホール１２を介して接続されたセラミック製の基板１３を備えている。前記基板１３のスルーホール１２部両側をガラス材料よりなる絶縁膜１４，１５で覆い、一方の絶縁膜１４上には導電パターン１６を介して第１の電子部品１７を導電性接着剤１８で電気的・機械的に接続して実装している。また他方の絶縁膜１５のスルーホール１２対向部分は開口させられており、この絶縁膜１５上には第２の電子部品１９を絶縁性接着剤２０で機械的に接続して実装し、ワイヤー２１によって導電パターン１１と電気的に接続している。
【００１１】
つまり本実施形態においては、スルーホール１２の他方側の絶縁膜１５に開口１５ａを設けているので、絶縁膜１５の塗布後の焼成時にスルーホール１２内の空気が膨張する結果としてスルーホール１２対向部分の絶縁膜１４，１５が膨れ上がることはなく、よって両方の絶縁膜１４，１５に、第１、第２の電子部品１７，１９を確実に実装することができるものとなるのである。
【００１２】
なお他方の絶縁膜１５のスルーホール１２対向部分に設けた開口１５ａの直径は、スルーホール１２の直径よりも大きくしたものであって、他方の絶縁膜１５の塗布時にスルーホール１２内にその一部が流入することがなく、常にスルーホールとしての開口が確実に得られ、よって第１、第２の電子部品１７，１９の実装も確実に行われるものとなるのである。
【００１３】
さらに一方の絶縁膜１４は、基板１３上に塗布された後に、この塗布面を上面側にして焼成されたものであって、この一方の絶縁膜１４はスルーホール１２の一方側を覆っており、そこは絶縁膜１４に対する支持接着面が無い部分となっているので、この面を下面側にして絶縁膜１４の焼成を行うと、下方に垂れ下がって膨れた状態となってしまうのを、この面を上面側として焼成することで、防止するのである。
【００１４】
【発明の効果】
以上のように本発明は両面に導電パターンを有し、少なくとも、両面の導電パターンの一部がスルーホールを介して接続された基板と、前記基板のスルーホール部両側を覆う絶縁膜と、この一方の絶縁膜上に導電パターンを介して導電性接着剤で実装された第１の電子部品と、他方の絶縁膜上に絶縁性接着剤で実装された第２の電子部品とを備え、前記絶縁膜は焼成によって形成し、前記一方の絶縁膜は、前記スルーホールを覆って形成するとともに、前記他方の絶縁膜は、前記スルーホール対向部分を開口させる電子機器であって、一方の絶縁膜は、前記スルーホールを覆って形成するとともに、スルーホールの他方側の絶縁膜に開口を設けているので、絶縁膜の焼成時にスルーホール内の空気が膨張しても、スルーホール対向部分の絶縁膜が膨れ上がることはない。従って、両方の絶縁膜上に、電子部品を確実に実装することができるものとなる。
【図面の簡単な説明】
【図１】本発明の一実施形態の断面図
【図２】従来例の断面図
【符号の説明】
１１ 導電パターン
１２ スルーホール
１３ 基板
１４ 絶縁膜
１５ 絶縁膜
１５ａ 開口
１６ 導電パターン
１７ 電子部品
１８ 導電性接着剤
１９ 電子部品
２０ 絶縁性接着剤[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic device having a double-sided substrate.
[0002]
[Prior art]
Since the double-sided board can increase the mounting efficiency of electronic components, the double-sided board itself can be made small to reduce the size of the electronic device. The conventional one has the configuration shown in FIG. It was.
[0003]
That is, as shown in FIG. 2, a conductive pattern 1 is provided on both sides, and at least a part of the conductive pattern 1 on both sides is connected via a through hole 2. Covering with insulating films 4 and 5, a first electronic component 7 is mounted on one insulating film 4 with a conductive adhesive 8 via a conductive pattern 6, and a second electron is mounted on the other insulating film 5. The component 9 was mounted with an insulating adhesive 10.
[0004]
[Problems to be solved by the invention]
In the above conventional example, since both sides of the through-hole 2 are covered with the insulating films 4 and 5, the air in the through-hole 2 expands when these insulating films 4 and 5 are baked after coating, and as a result, these Insulating films 4 and 5 swell outward, which makes it impossible to mount the first and second electronic components 7 and 9.
[0005]
Accordingly, an object of the present invention is to ensure that electronic components can be mounted on both sides of a through hole.
[0006]
[Means for Solving the Problems]
In order to achieve this object, according to the present invention, the insulating film is formed by baking, the one insulating film is formed so as to cover the through hole, and the other insulating film is formed so as to cover the through hole facing portion. Since the opening is provided in the insulating film on the other side of the through hole, even if the air in the through hole expands during firing of the insulating film, the insulating film in the portion opposite the through hole expands There is no . Thereby , an electronic component can be reliably mounted on both insulating films .
[0007]
DETAILED DESCRIPTION OF THE INVENTION
The invention of claim 1 of the present invention has a conductive pattern on both sides, at least a substrate portion of both surfaces of the conductive patterns are connected through the through hole, an insulating film covering the through hole portion on both sides of the substrate And a first electronic component mounted on the one insulating film with a conductive adhesive via a conductive pattern, and a second electronic component mounted on the other insulating film with an insulating adhesive. wherein the insulating film is formed by baking, the one insulating film, thereby forming covering the through hole, the other insulating film is an electronic device to open the through hole facing portion, whereas Since the insulating film is formed so as to cover the through hole and an opening is provided in the insulating film on the other side of the through hole, even if the air in the through hole expands during firing of the insulating film, portion Not that swell the insulating film. Therefore, electronic components can be reliably mounted on both insulating films .
[0008]
The invention according to claim 2 of the present invention is the electronic device according to claim 1, wherein the diameter of the opening provided in the through hole facing portion of the other insulating film is larger than the diameter of the through hole. A part of the through-hole does not flow into the through-hole when the insulating film is applied, and an opening as a through-hole is always obtained with certainty, so that the mounting of the first and second electronic components is also performed reliably. .
[0009]
Furthermore the invention of claim 3 of the present invention, one of the insulating film, after being coated on a substrate, an electronic device according to claim 1 of this application surface is obtained by firing in the upper surface One insulating film covers one side of the through-hole, and there is no supporting adhesive surface for the insulating film. When the insulating film is baked with this surface as the lower surface, it hangs downward. This is prevented by firing with this surface as the upper surface side.
[0010]
Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.
As shown in FIG. 1, in this embodiment, the conductive pattern 11 made of a silver-palladium alloy is provided on both sides, and at least a part of the conductive pattern 11 on both sides is connected via a through hole 12. A substrate 13 is provided. Both sides of the through-hole 12 portion of the substrate 13 are covered with insulating films 14 and 15 made of a glass material, and the first electronic component 17 is electrically connected to the insulating film 14 with a conductive adhesive 18 via a conductive pattern 16. It is mounted by connecting mechanically and mechanically. Also, the other insulating film 15 is opposed to the through hole 12, and the second electronic component 19 is mechanically connected to the insulating film 15 with an insulating adhesive 20 and mounted thereon. Is electrically connected to the conductive pattern 11.
[0011]
That is, in the present embodiment, since the opening 15a is provided in the insulating film 15 on the other side of the through hole 12, the air in the through hole 12 expands as a result of expansion of the air in the through hole 12 during baking after the application of the insulating film 15. The insulating films 14 and 15 in the portion do not swell, so that the first and second electronic components 17 and 19 can be reliably mounted on both the insulating films 14 and 15.
[0012]
Note that the diameter of the opening 15 a provided in the portion of the other insulating film 15 facing the through hole 12 is larger than the diameter of the through hole 12, and one of the openings is formed in the through hole 12 when the other insulating film 15 is applied. Therefore, the opening as a through hole is always obtained reliably, so that the first and second electronic components 17 and 19 are also mounted reliably.
[0013]
Further, one insulating film 14 is applied on the substrate 13 and then baked with the coated surface as the upper surface side. The one insulating film 14 covers one side of the through hole 12. Since there is no support adhesive surface for the insulating film 14, if the insulating film 14 is baked with this surface as the lower surface side, it will hang downward and swell. This is prevented by firing the surface as the upper surface side.
[0014]
【The invention's effect】
The present invention as described above has a conductive pattern on both sides, at least a substrate portion of both surfaces of the conductive patterns are connected through the through hole, an insulating film covering the through hole portion on both sides of the substrate, this A first electronic component mounted with a conductive adhesive on one insulating film via a conductive pattern, and a second electronic component mounted with an insulating adhesive on the other insulating film, The insulating film is formed by firing, the one insulating film is formed so as to cover the through hole, and the other insulating film is an electronic device that opens the through hole facing portion, and the one insulating film is adapted to form covering the through hole, since an opening on the other side of the insulating film of the through hole, even if the air in the through holes during the firing of the insulating film expands, the insulating through hole facing portion Not that swell. Therefore, electronic components can be reliably mounted on both insulating films .
[Brief description of the drawings]
FIG. 1 is a sectional view of an embodiment of the present invention. FIG. 2 is a sectional view of a conventional example.
DESCRIPTION OF SYMBOLS 11 Conductive pattern 12 Through hole 13 Substrate 14 Insulating film 15 Insulating film 15a Opening 16 Conductive pattern 17 Electronic component 18 Conductive adhesive 19 Electronic component 20 Insulating adhesive

Claims (3)

両面に導電パターンを有し、少なくとも、両面の導電パターンの一部がスルーホールを介して接続された基板と、前記基板のスルーホール部両側を覆う絶縁膜と、この一方の絶縁膜上に導電パターンを介して導電性接着剤で実装された第１の電子部品と、他方の絶縁膜上に絶縁性接着剤で実装された第２の電子部品とを備え、前記絶縁膜は焼成によって形成し、前記一方の絶縁膜は、前記スルーホールを覆って形成するとともに、前記他方の絶縁膜は、前記スルーホール対向部分を開口させる電子機器。A substrate having a conductive pattern on both sides, at least a part of the conductive pattern on both sides being connected via a through hole, an insulating film covering both sides of the through hole portion of the substrate, and a conductive material on the one insulating film A first electronic component mounted with a conductive adhesive via a pattern, and a second electronic component mounted with an insulating adhesive on the other insulating film, wherein the insulating film is formed by firing The one insulating film is formed so as to cover the through hole, and the other insulating film is an electronic device which opens the through hole facing portion. 他方の絶縁膜のスルーホール対向部分に設けた開口の直径は、スルーホールの直径よりも大きくした請求項１に記載の電子機器。  The electronic device according to claim 1, wherein the diameter of the opening provided in the through hole facing portion of the other insulating film is larger than the diameter of the through hole. 一方の絶縁膜は、基板上に塗布された後に、この塗布面を上面側にして焼成された請求項１に記載の電子機器。One of the insulating film, after being coated on a substrate, an electronic device according to claim 1, the coated surface was fired in the upper surface.
JP32257196A 1996-12-03 1996-12-03 Electronics Expired - Fee Related JP3675073B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32257196A JP3675073B2 (en) 1996-12-03 1996-12-03 Electronics

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32257196A JP3675073B2 (en) 1996-12-03 1996-12-03 Electronics

Publications (2)

Publication Number Publication Date
JPH10163606A JPH10163606A (en) 1998-06-19
JP3675073B2 true JP3675073B2 (en) 2005-07-27

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Family Applications (1)

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JP32257196A Expired - Fee Related JP3675073B2 (en) 1996-12-03 1996-12-03 Electronics

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001066992A (en) * 1999-08-31 2001-03-16 Lintec Corp Adhesive label

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JPH10163606A (en) 1998-06-19

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