JP3668186B2 - Variable threshold threshold element circuit, functional function reconfigurable integrated circuit, and circuit state holding method - Google Patents

Description

【００６３】
次に、フローティングゲートＦＧの電荷量保存に着目する。前述同様、フローティングゲートＦＧの初期電荷量は０であるとする。
【００６４】
【数２】

【００６５】
式（２）に、ΣＣｉ＞＞Ｃmos の関係を適用し、Ｖfgについて解くと次式を得る。
【００６６】
【数３】

【００６７】
式（１）と式（３）とから、Ｑfeと（Ｖfe1 −Ｖfe2 ）との関係は次式になる。
【００６８】
【数４】

【００６９】
今、電源電位をＶdd、グランド電位を０とする。全ての入力変数用端子input1についてＶｉ＝０、Ｖfe1 ＝０である場合を（Ｉ）とし、全ての入力変数用端子input1についてＶｉ＝０、Ｖfe1 ＝Ｖddである場合を（II）とし、全ての入力変数用端子input1についてＶｉ＝Ｖdd、Ｖfe1 ＝０である場合を（III ）とし、全ての入力変数用端子input1についてＶｉ＝Ｖdd、Ｖfe1 ＝Ｖddである場合を（IV）とする。
【００７０】
図１３において、前述の（Ｉ）と（III ）との場合は、原点を通り、傾きが−ＣｖΣＣｉ／（Ｃｖ＋ΣＣｉ）である直線である。また、（II）の場合は、ヒステリシスループと各容量値との関係で図１３のＡ０点を交点とすることが可能である。また、（IV）の場合は、（II）と同様にＢ０点を交点とすることができる。前記（II）と（IV）との場合を２つの初期設定とする。
【００７１】
〔しきい値の保持方法〕
上述した初期設定の後に、図１０のスイッチＳＷ２を遮断状態にし、スイッチＳＷ１を導通状態にする。これにより、端子Ｐ１と端子Ｐ２とは同電位になり、（Ｖfe1 −Ｖfe2 ）＝０となる。これによって、初期設定でＡ０点であった場合はＡ１点に移行し、Ｂ０点であった場合はＢ１点に移行する。この操作によって、Ａ１点、Ｂ１点で各々残留分極による電荷量Ｑ_A1、Ｑ_B1が不揮発的に保持される。
【００７２】
強誘電体容量Ｃｐの端子Ｐ１にＱ_A1または、Ｑ_B1の電荷量が現れる時、常誘電体容量Ｃｖの端子Ｐ２には逆極性の同電荷量が現れる。図１４は、図１０中のフローティングゲートＦＧの電位Ｖfgと、入力変数用端子input1〔１〕〜input1〔ｋ〕に入力される電位Ｖｉと容量値Ｃｉとの積和との関係を表す図である。また、図１４中のＣsum はΣＣｉを意味し、Ｖdd／２は電源電位の（１／２）の電位を意味する。
【００７３】
フローティングゲートＦＧからみた場合、後に続くνＭＯＳインバータＩＮＶが論理的に反転するか否かはνＭＯＳインバータＩＮＶを構成するｐチャネル電界効果トランジスタＱ１とｎチャネル電界効果トランジスタＱ２との電気的特性に依存し、図１４ではフローティングゲート電位ＶfgがＶdd／２の時にνＭＯＳインバータＩＮＶの出力電位がＶdd／２になると仮定している。図１０のスイッチＳＷ１が接続状態であり、強誘電体容量Ｃｐの端子Ｐ１にＱ_A1またはＱ_B1の電荷が保持されている場合、容量Ｃｖにも同電荷量が保持されるため、各々の保持電荷量について次式が成り立つ。
【００７４】
【数５】

【００７５】
式（５）と式（６）と、Ｖdd／２との交点のΣＣｉ・Ｖｉ座標は各々α_A とα_B となる。式（５）が成立している場合、入力変数の物理的表現であるＶｉの或組合せの時にその積和値が初めてα_A を越えた時、図１０のνＭＯＳインバータＩＮＶは論理反転を起こす。また、式（６）が成立している場合は、入力変数の物理的表現であるＶｉの或組合せの時にその積和値が初めてα_B を越えた時、図１０のνＭＯＳインバータＩＮＶは論理反転を起こす。このように、入力変数からみたしきい値を可変にし、かつ、そのしきい値を不揮発的に保持することが可能である。
【００７６】
次に、論理回路としての動作を明確にするために、図１４の変数を変更する。まず、簡単化のために図１０のνＭＯＳインバータ回路１０００において、入力変数用端子input1〔１〕〜input1〔ｋ〕とフローティングゲートＦＧとの間の容量値を全て等しくＣにする。しきい素子において入力変数の重みを等しくすることは、入力変数によって形成される状態の数、即ち、入力状態数が（ｋ＋１）個であり、対称関数を表すことを意味する。
【００７７】
対称関数でない論理関数を表現するためには、各入力変数の重みを、文献８（青山一生、澤田宏、名古屋彰、ニューロンＭＯＳによる論理関数回路の一設計手法、第１３回回路とシステム（軽井沢ワークショップ）２０００年）に示される入力ベクトルの識別方法を適用することにより実現可能である。例として、（１≦ｉ≦ｋ）の整数ｉについて、ｉ番目の入力変数用端子とフローティングゲートＦＧとの間の容量値をＣ・２^i-1に設定する方法がある。
【００７８】
本実施の形態では簡単化のために、対称関数の場合について説明をする。図１５は、νＭＯＳインバータ回路１０００における入力状態数と規格化フローティングゲート電位との関係を表す図である。今、（Ｖｉ／Ｖdd）＝Ｘｉとし、ΣＸｉ＝Ｘ₁ ＋Ｘ₂ ＋・・・・＋Ｘｋ＝Ｚ、Ｖfg＝Ｖdd＝Ｕfgとする。Ｘｉは入力変数の論理値に相当する。前述のＵfgを規格化フローティングゲート電位と呼ぶ。また、Ｑ_A1＝（ｋ・Ｃ・Ｖdd）＝Ｕ_A1、Ｑ_B1＝（ｋ・Ｃ・Ｖdd）＝Ｕ_B1とする。この時、式（５）と式（６）とは次式に変更される。
【００７９】
【数６】

【００８０】
各々の式と（１／２）との交点のＺ座標は、Ｚ_A ，Ｚ_B によって表される。仮に、１＜Ｚ_A ＜２であり、３＜Ｚ_B ＜４であるとすると、νＭＯＳインバータ回路１０００は入力状態数が１と２との間、または、３と４との間のどちらか一方にしきい値を持つように設定される。
【００８１】
〔実施の形態５：しきい値の調整方法としきい値調整が可能なνＭＯＳインバータ回路の回路構成〕
図１６は、固定電位を供給する端子を付加したνＭＯＳインバータ回路を表す図である。このνＭＯＳインバータ回路１６００は図１０に示したνＭＯＳインバータ回路１０００と同様に、入力変数用端子input1〔１〕〜input1〔ｋ〕を持ち、制御変数用端子input2を持ち、しきい値を不揮発的に保持する強誘電体容量Ｃｐを含むしきい値データ保持回路ＨＬＤを持つ。回路１６００が回路１０００と異なる点は、固定電位に接続された端子を有するところにある。具体的には、電源電位Ｖddに接続された端子Ｐvdd 及び、グランド電位に接続された端子Ｐgnd を有する。固定電位として電源電位とグランド電位を挙げたが、他の電位であってもしきい値の調整に対して同様の効果を得ることができる。
【００８２】
次に、付加した端子Ｐvdd ，Ｐgnd の効果を説明する。図１７は、図１６の回路１６００における入力状態数Ｚと規格化フローティングゲート電位Ｖfg／Ｖdd＝Ｕfgとの関係を表す図である。図１６の端子Ｐvdd とフローティングゲートＦＧとの間の容量値をＣvdd とし、端子Ｐgnd とフローティングゲートとの間ＦＧの容量値をＣgnd とする。この時、Ｃ’sum ＝ｋ・Ｃ＋Ｃvdd ＋Ｃgnd とすると、前記の式（５）と式（６）と同じ式は、各々式（９）と式（１０）とになる。
【００８３】
【数７】

【００８４】
式（９）、式（６）を電源電位によって規格化すると次式となる。
【００８５】
【数８】

【００８６】
ここで、入力状態数Ｚの定義は前記と同じであり、Ｕvdd ＝（Ｃvdd ／Ｃ’sum ）であり、Ｕ’_A1＝Ｑ_A1＝（Ｖdd・Ｃ’sum ）、Ｕ’_B1＝Ｑ_B1＝（Ｖdd・Ｃ’sum ）である。Ｃvdd は、式（１１）と式（１２）とのＣ’sum と（Ｕdd＋Ｕ’_A1）または（Ｕdd＋Ｕ’_B1）に寄与し、一方、Ｃgnd はＣ’sum とＵ’_A1またはＵ’_B1に寄与する。前記２つの容量値は、図１７中の直線lineＡまたはlineＢの傾きとＵfg軸との切片を変えることができる。このように、固定電位に接続された端子を用いることによって、Ｕfg＝１／２との交点のＺ座標であるしきい値Ｚ’_A またはＺ’_B を任意のＺの値に設定することが可能となる。
【００８７】
〔しきい値データ保持回路の回路構成〕
図１８は、図１６中のしきい値データ保持回路ＨＬＤの具体的な回路を表す図である。図１６中のスイッチＳＷ２とスイッチＳＷ１とを各々トランスミッションゲートＴＧ１とＴＧ２とで置き換えた回路構成である。端子ctl3はトランスミッションゲートＴＧ１とＴＧ２との接続または遮断を制御するスイッチ制御信号入力端子である。端子ctl3から入力された信号はインバータ回路inv2によって論理反転される。端子ctl3から入力される信号が論理値「１」である時、トランスミッションゲートＴＧ２は接続状態であり、トランスミッションゲートＴＧ１は遮断状態となる。逆に、信号が論理値「０」の場合はトランスミッションゲートＴＧ２が遮断され、トランスミッションゲートＴＧ１が接続され、残留分極による電荷量が強誘電体容量Ｃｐに保持される。
【００８８】
〔実施の形態６〕
実施の形態６では、設定可能な複数のしきい値の中から１つのしきい値を選択し、不揮発的に保持を行うことが可能な回路構成について説明する。実施の形態５では設定可能な２つのしきい値の中から１つのしきい値を選択していた。これに対し、実施の形態６では、設定可能なしきい値の数を２よりも大きくしている。
【００８９】
図１９は、複数の設定可能なしきい値の中から選択された１つのしきい値を不揮発的に保持可能なｋ入力変数のνＭＯＳインバータ回路の構成図である。このνＭＯＳインバータ回路１９００は、図１６のνＭＯＳインバータ回路１６００に、同回路中のしきい値データ保持回路ＨＬＤを複数付加した回路構成である。今、図１９の回路１９００中にしきい値データ保持回路ＨＬＤがｍ個あるとする。しきい値データ保持回路ＨＬＤ₁ 〜ＨＬＤｍに保持される２つの電荷量Ｑ’_A1及びＱ’_B1が全てのしきい値データ保持回路ＨＬＤ₁ 〜ＨＬＤｍにおいて各々等しいとする。即ち、保持される電荷量の総電荷量として、（ｍ・Ｑ’_B1）から（ｍ・Ｑ’_A1）までの（ｍ＋１）通りの総電荷量を保持することができる。
【００９０】
図２０は、図１９のνＭＯＳインバータ回路１９００における入力状態数Ｚと規格化フローティングゲート電位Ｕfgとの関係を表す図である。図２０中のline〔ｍ〕は総電荷量が（ｍ・Ｑ’_A1）の場合のＵfgとＺの関係を表しており、line〔ｍ−１〕は、（（ｍ−１）・Ｑ’_A1＋Ｑ’_B1）を表し、line〔ｍ−２〕も同様であり、line〔２〕は（２・Ｑ’_A1＋（ｍ−２）・Ｑ’_B1）を表しており、line〔１〕、line〔０〕も同様である。
【００９１】
この時、line〔ｍ〕、line〔ｍ−１〕、line〔ｍ−２〕、・・・、line〔２〕、line〔１〕、line〔０〕の各々は、Ｕfg＝（１／２）と交わり、その交点のＺ座標は各々、Ｚ_m 、Ｚ_m-1 、Ｚ_m-2 、・・・、Ｚ₂ 、Ｚ₁ 、Ｚ₀ となる。これらの値の全てが互いに重なることなく、ある整数ＺとＺ＋１との間の値になる時、νＭＯＳインバータ回路１９００は設定可能なしきい値を（ｍ＋１）通り有する。
【００９２】
また、図１９のスイッチＳＷ２₁ 〜ＳＷ２ｍが接続状態であり、スイッチＳＷ１₁ 〜ＳＷ１ｍが遮断状態である初期化時に制御変数用端子input2〔１〕〜input2〔ｍ〕までのｍ個の端子から入力される電位に応じて、（ｍ＋１）個の設定可能なしきい値の中から１つのしきい値が選択され、スイッチＳＷ２₁ 〜ＳＷ２ｍが遮断状態であり、スイッチＳＷ１₁ 〜ＳＷ１ｍが接続状態である時に前記選択された１つのしきい値が不揮発的に保持される。
【００９３】
（実施の形態７：関数機能再構成可能集積回路）
図２１は、しきい値を不揮発的に保持可能な２入力変数の可変しきい値しきい素子回路を多段構成で用いた任意の２入力変数対称関数を実現可能な関数機能再構成可能集積回路（２入力変数可変関数回路）の構成を表す図である。この２入力変数可変関数回路２１００は、入力変数用端子input1〔１〕とinput1〔２〕を持ち、図１６に示したνＭＯＳインバータ回路１６００と同じ回路構成を有するＦＴＥ〔１〕，ＦＴＥ〔２〕，ＦＴＥ〔３〕を持ち、ＦＴＥ〔１〕，ＦＴＥ〔２〕，ＦＴＥ〔３〕に初期化時に入力される制御変数用の端子としてinput2〔１〕，input2〔２〕，input2〔３〕を持ち、ＦＴＥ〔１〕，ＦＴＥ〔２〕，ＦＴＥ〔３〕におけるしきい値データ保持回路ＨＬＤ₁ ，ＨＬＤ₂ ，ＨＬＤ₃ の初期化時（しきい値設定期間）と関数実行時（しきい値保持期間）とを切替える制御端子ctl1を持つ。
【００９４】
なお、νＭＯＳインバータ回路２１００はＦＴＥ〔１〕，ＦＴＥ〔２〕，ＦＴＥ〔３〕の後段にバッファ回路ＢＦ〔１〕，ＢＦ〔２〕，ＢＦ〔３〕を持つ。バッファ回路ＢＦ〔１〕，ＢＦ〔２〕，ＢＦ〔３〕によって、ＦＴＥ〔１〕，ＦＴＥ〔２〕，ＦＴＥ〔３〕の出力電位は増幅と波形整形とが行われる。入力変数用端子input1〔１〕，input1〔２〕については、フローティングゲートＦＧ〔Ｓ〕と容量結合する端子の前に遅延時間制御回路ＤＥＬ〔１〕，ＤＥＬ〔２〕を持つ。
【００９５】
遅延時間制御回路ＤＥＬ〔１〕，ＤＥＬ〔２〕を有することによって、入力変数用端子input1〔１〕，input1〔２〕からフローティングゲートＦＧ〔Ｓ〕と容量結合する端子に入力される信号と、ＦＴＥ〔１〕，ＦＴＥ〔２〕，ＦＴＥ〔３〕とバッファー回路ＢＦ〔１〕，ＢＦ〔２〕，ＢＦ〔３〕とを経てフローティングゲートＦＧ〔Ｓ〕と容量結合する端子に入力される信号との信号遅延時間の差を小さくすることが可能となる。信号遅延時間差を小さくすることによって、多入力組合せ回路において同時に複数の信号が変化する際に発生するハザードを回避することができる。
【００９６】
input1〔１〕，input1〔２〕からの入力変数とＦＴＥ〔１〕，ＦＴＥ〔２〕，ＦＴＥ〔３〕からの出力信号とが、フローティングゲートＦＧ〔Ｓ〕に常誘電体容量によって容量結合する端子に入力される。フローティングゲートＦＧ〔Ｓ〕の後段には、フローティングゲートＦＧ〔Ｓ〕を入力ゲートとするνＭＯＳインバータＩＮＶ〔Ｓ〕があり、このνＭＯＳインバータ回路ＩＮＶ〔Ｓ〕の出力は、後段のバッファー回路ＢＦ〔Ｓ〕を経て出力される。
【００９７】
〔動作〕
ＦＴＥ〔１〕，ＦＴＥ〔２〕，ＦＴＥ〔３〕において、しきい値データ保持回路はＨＬＤ₁ 〜ＨＬＤｍは先に説明した初期設定方法によって、Ｑ’_A1とＱ’_B1とのいずれか一方の電荷量またはそれに類する電荷量を保持している。また、先に説明したしきい値調整のための回路構成と方法によって、ＦＴＥ〔１〕のしきい値は、入力状態数ＺがＺ＜０の領域、または０＜Ｚ＜１の領域のいずれか一方に設定され、ＦＴＥ〔２〕のしきい値は、０＜Ｚ＜１、または、１＜Ｚ＜２のいずれか一方の領域に設定され、ＦＴＥ〔３〕のしきい値は、１＜Ｚ＜２、または、Ｚ＞２のいずれか一方の領域に設定されている。
【００９８】
また、ＦＴＥ〔１〕，ＦＴＥ〔２〕，ＦＴＥ〔３〕において、入力変数用端子input1〔１〕，input1〔２〕とフローティングゲートＦＧ〔１〕，ＦＧ〔２〕，ＦＧ〔３〕との間の常誘電体容量の容量値は互いに全て等しく、また、フローティングゲートＦＧ〔Ｓ〕に容量結合されている常誘電体容量の容量値も互いに全て等しいとする。
【００９９】
図２２は、図２１に示した２入力変数可変関数回路２１００を論理記述した典型的な可変しきい値しきい素子回路網を表す図である。図２２の可変しきい値しきい素子回路ＦＴＥ〔１〕，ＦＴＥ〔２〕，ＦＴＥ〔３〕は全て否定出力型の回路であるとする。即ち、入力変数と重み係数との積和がしきい値よりも大きい場合は論理値「０」を、小さい場合は論理値「１」を出力する。また、入力変数に対する重み係数は簡単化のために１とした。
【０１００】
図２２のＦＴＥ〔１〕は制御変数用端子input2〔１〕から入力される信号によって、−０．５または＋０．５のいずれか一方のしきい値を選択保持でき、ＦＴＥ〔２〕は制御変数用端子input2〔２〕から入力される信号によって、０．５または＋１．５のいずれか一方のしきい値を選択保持でき、ＦＴＥ〔３〕は制御変数用端子input2〔３〕から入力される信号によって、１．５または２．５のいずれか一方のしきい値を選択保持でき、ＳＴＥのしきい値は２．５に設定されている。
【０１０１】
また、ＦＴＥ〔１〕，ＦＴＥ〔２〕，ＦＴＥ〔３〕のしきい値として、初期設定時に制御変数用端子input2〔１〕，input2〔２〕，input2〔３〕から論理値「１」が入力された場合に大きい値が、論理値「０」が入力された場合に小さい値が選択される。
【０１０２】
今、ＦＴＥ〔１〕，ＦＴＥ〔２〕，ＦＴＥ〔３〕のしきい値として、各々０．５，０．５，２．５が選択保持されたとする。入力状態数０に対して、ＦＴＥ〔１〕，ＦＴＥ〔２〕，ＦＴＥ〔３〕の出力は論理値「１」，「１」，「１」であり、ＳＴＥの入力の積和値は３であり、出力は論理値「０」となる。入力状態数１に対して、ＦＴＥ〔１〕，ＦＴＥ〔２〕，ＦＴＥ〔３〕の出力は論理値「０」，「０」，「１」であり、ＳＴＥの入力の積和値は２であり、出力は論理値「１」となる。入力状態数２に対して、ＦＴＥ〔１〕，ＦＴＥ〔２〕，ＦＴＥ〔３〕の出力は論理値「０」，「０」，「１」であり、ＳＴＥの入力の積和値は３であり、出力は論理値「０」となる。
【０１０３】
このように、制御変数用端子input2〔１〕，input2〔２〕，input2〔３〕から入力する信号を論理値「１」，「０」，「１」とすることによって、ＸＯＲ（Exclusive-OR）を実現することができる。前記と同様に、制御変数用端子input2〔１〕，input2〔２〕，input2〔３〕から入力する信号の論理値が、（０，０，０）の場合は関数１を、（１，０，０）の場合はＯＲを、（０，１，０）の場合はＸＮＯＲを、（１，１，０）の場合はＡＮＤを、（０，０，１）の場合はＮＡＮＤを、（０，１，１）の場合はＮＯＲを、（１，１，１）の場合は関数０を実現することができる。
【０１０４】
以上説明したように、この２入力変数可変関数回路２１００では、ＦＴＥ〔１〕，〔２〕，〔３〕に保持される制御変数値に対応する電荷量によって、任意の対称関数を実現することが可能になる。この関数は、しきい値データ保持回路ＨＬＤ₁ 〜ＨＬＤｍに強誘電体容量Ｃｐを使用しているので、不揮発的に保持される。これにより、経時的誤動作の問題が解消され、長期間安定して２入力変数可変関数回路２１００を使用することができる。
【０１０５】
なお、この実施の形態７では、入力変数を２つとしたが、任意の自然数ｋに対しても同様に構成することができる。また、任意の論理関数については、重み係数の値を変更し、２段論理回路の１段目のＦＴＥの数を適宜増加させることによって、実現することができる。
【０１０６】
【発明の効果】
以上説明したことから明らかなように、本発明の可変しきい値しきい素子回路によれば、強誘電体容量と常誘電体容量との直列接続回路を介して、しきい値を制御する制御変数を伝搬する１以上の制御変数用端子をしきい素子のゲート電極に結合したので、強誘電体容量に不揮発的に保持される電荷量によってしきい値を不揮発的に保持させ、経時的誤動作の問題を解消することが可能となる。
【０１０７】
また、本発明の可変しきい値しきい素子回路を用いて関数機能再構成可能集積回路を構成することにより、関数の再構成を高速に行え、また、その関数を不揮発的に保持することができ、安定して長期、間関数機能再構成可能集積回路を使用することができるようになる。
【０１０８】
関数機能再構成可能集積回路の適用領域は、特定用途ＬＳＩのプロトタイプとしてだけでなく、製造後であっても関数機能を入出力信号に応じて適応的に変化させる進化型ハードウェアや、システムが動作中であっても関数機能を切替え、ハードウェア資源を高効率に使用することが可能なリコンフィギュアラブルコンピューティングシステムへの応用など幅広い応用分野がある。このように、システムが動作中に動的に関数機能を変えたり、入出力信号に適応して関数を変化させたりする場合には、できるだけ高速に関数機能の書き換えが行われることが望ましい。また、一度記憶した関数機能は消去または、書き込み命令を受けるまでは保持することが可能であり、電源を切った後であっても状態保持が可能であることが望ましい。本発明の関数機能再構成可能集積回路では、このような要望に応えることができる。
【図面の簡単な説明】
【図１】 強誘電体メモリに用いられている強誘電体容量を表す回路図である。
【図２】 強誘電体容量の端子間に電圧Ｖが印加された時の電圧Ｖと電荷量Ｑの関係を表す図である。
【図３】 文献５に開示されているＭＦＭＩＳ型の強誘電体容量を持つ電界効果トランジスタを表す回路図である。
【図４】 文献６に開示されているＭＦＭＩＳ型の強誘電体容量を持つ電界効果トランジスタを表す回路図である。
【図５】 文献７に開示されているＭＦＭＩＳ型の強誘電体容量を持つ電界効果トランジスタを表す回路図である。
【図６】 本発明の実施の形態で用いるＭＦＭＩＳ型電界効果トランジスタを表す回路図である。
【図７】 本発明の可変しきい値しきい素子回路の一実施の形態を示す容量結合入力型電界効果トランジスタの回路図である。
【図８】 この容量結合入力型電界効果トランジスタを用いたνＭＯＳインバータ回路の基本構成を示す回路構成図である。
【図９】 スイッチを有する容量結合入力型電界効果トランジスタの回路図である。
【図１０】 このスイッチを有する容量結合入力型電界効果トランジスタを用いたνＭＯＳインバータ回路の基本構成を示す回路構成図である。
【図１１】 図１０に示したνＭＯＳインバータ回路においてしきい処理を行う非線形回路の他の構成例を示す回路図である。
【図１２】 図１０に示したνＭＯＳインバータ回路においてしきい処理を行う非線形回路の他の構成例を示す回路図である。
【図１３】 強誘電体容量の一方側の端子に現れる電荷量Ｑfeと強誘電体容量を挟む両端の電圧（Ｖfe1 −Ｖfe2 ）との関係を表す図である。
【図１４】 図１０に示したνＭＯＳインバータ回路におけるフローティングゲートの電位Ｖfgと入力変数用端子に入力される電位Ｖｉと容量値Ｃｉとの積和との関係を表す図である。
【図１５】 図１０に示したνＭＯＳインバータ回路における入力状態数Ｚと規格化フローティングゲート電位との関係を表す図である。
【図１６】 固定電位を供給する端子を付加したνＭＯＳインバータ回路を表す図である。
【図１７】 図１６に示したνＭＯＳインバータ回路における入力状態数Ｚと規格化フローティングゲート電位Ｕfgとの関係を表す図である。
【図１８】 しきい値データ保持回路の具体的な回路を表す図である。
【図１９】 複数の設定可能なしきい値の中から選択された１つのしきい値を不揮発的に保持可能なｋ入力変数のνＭＯＳインバータ回路の構成図である。
【図２０】 図１９に示したνＭＯＳインバータ回路における入力状態数Ｚと規格化フローティングゲート電位Ｕfgとの関係を表す図である。
【図２１】 しきい値を不揮発的に保持可能な２入力変数の可変しきい値しきい素子回路を多段構成で用いた任意の２入力変数対称関数を実現可能な関数機能再構成可能集積回路（２入力変数可変関数回路）の構成を表す図である。
【図２２】 この２入力変数可変関数回路を論理記述した典型的なしきい素子回路網を表す図である。
【図２３】 従来のしきい値可変機能を備えたｋ入力変数のνＭＯＳインバータ回路を示す回路図である。
【図２４】 従来の回路状態保持機能を備えたｋ入力変数のνＭＯＳインバータ回路の代表的な回路構成を示す図である。
【図２５】 図２４に示したνＭＯＳインバータ回路を用いた関数機能再構成可能集積回路の一例（２入力変数可変関数回路）を示す図である。
【符号の説明】
７００…容量結合入力型電界効果トランジスタ、７０１…電界効果トランジスタ、input1〔１〕〜input1〔ｋ〕…入力変数用端子、input2〔１〕〜input2〔ｍ〕…制御変数用端子、７０２…ゲート電極、７０３₁ 〜７０３ｋ…常誘電体容量、７０４₁ 〜７０４ｍ…しきい値データ保持回路、７０５₁ 〜７０５ｍ…常誘電体容量、７０６₁ 〜７０６ｍ…強誘電体容量、８００…νＭＯＳインバータ回路、ＨＬＤ₁ 〜ＨＬＤｍ…しきい値データ保持回路、Ｃ₁ 〜Ｃｋ，Ｃ_v1〜Ｃ_vm…常誘電体容量、Ｃ_p1〜Ｃ_pm…強誘電体容量、ＦＧ…フローティングゲート、ＩＮＶ…νＭＯＳインバータ、Ｑ１…ｐチャネル電界効果トランジスタ、Ｑ２…ｎチャネル電界効果トランジスタ、９００…νＭＯＳインバータ回路、９０１…電界効果トランジスタ、９０２…ゲート電極、９０３₁ 〜９０３ｋ…常誘電体容量、９０４₁ 〜９０４ｍ…しきい値データ保持回路、９０５₁ 〜９０５ｍ…常誘電体容量、９０６₁ 〜９０６ｍ…強誘電体容量、９０７₁ 〜９０７ｍ…第２のスイッチ、９０８₁ 〜９０８ｍ…第１のスイッチ、２１００…２入力変数可変関数回路、ctl1，ctl2 …状態制御端子、ＦＴＥ〔１〕〜ＦＴＥ〔３〕…１段目のνＭＯＳインバータ回路、ＳＴＥ…２段目のνＭＯＳインバータ回路、ＦＧ〔１〕〜ＦＧ〔３〕，ＦＧ〔Ｓ〕…フローティングゲート、ＢＦ〔１〕〜ＢＦ〔３〕，ＢＦ〔Ｓ〕…バッファ回路、ＤＥＬ〔１〕〜ＤＥＬ〔２〕…遅延制御回路、ＩＮＶ〔１〕〜ＩＮＶ〔３〕，ＩＮＶ〔Ｓ〕…νＭＯＳインバータ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a variable threshold threshold element circuit having a function of holding a threshold value in a non-volatile manner, and is configured using the variable threshold threshold element circuit and has a function function even after the circuit is fabricated. The present invention relates to a function state reconfigurable integrated circuit that can be used and a circuit state holding method applied to a variable threshold threshold element circuit.
[0002]
[Prior art]
As a threshold element (nonlinear element) manufactured by the CMOS process technology, for example, there is an inverter constituted by a neuron MOS transistor (νMOS transistor) disclosed in Document 1 (Japanese Patent No. 2662559: semiconductor device). Hereinafter, this inverter is referred to as a νMOS inverter.
[0003]
A circuit and method for making the threshold value of this νMOS inverter variable are disclosed in Reference 2 (Japanese Patent Laid-Open No. 2001-44823: Variable threshold generation method in a neuron MOS circuit and a neuron MOS circuit using the method). .
[0004]
[Threshold element circuit with variable threshold function (variable threshold threshold element circuit)]
FIG. 23 is a circuit diagram showing a typical k-input variable νMOS inverter circuit as a threshold element circuit (variable threshold threshold element circuit) having a threshold variable function. In this νMOS inverter circuit 2300, a gate electrode (hereinafter referred to as a floating gate) FG of a νMOS inverter INV having no threshold variability in an electrically floating state FG is connected to a signal input terminal ( Input1 [1] to input1 [k] (hereinafter referred to as input variable terminals), input terminals for control variables (hereinafter referred to as control variable terminals) input2 for controlling threshold values, and power supply potential Vdd The fixed potential terminal Pvdd and the fixed potential terminal Pgnd connected to the ground potential are capacitively coupled.
[0005]
The threshold value of the νMOS inverter INV includes a capacitance value Cv between the control variable terminal input2 and the floating gate FG, a capacitance value Cvdd between the fixed potential terminal Pvdd and the floating gate FG, and a fixed potential terminal Pgnd. The capacitance value Cgnd between the gate FG and the capacitance value C between the input variable terminals input1 [1] to input1 [k] and the floating gate FG ₁ ~ C _k And the potential Vv applied to the control variable input terminal input2. In this νMOS inverter circuit 2300, the combination of input variables depends on whether the potential Vv applied to the control variable terminal input2 is the power supply potential Vdd (logic value “1”) or the ground potential (logic value “0”). It is possible to set a logical threshold value to an arbitrary value on the input state formed by. Hereinafter, the logical threshold is abbreviated as a threshold when it is not necessary to distinguish from other thresholds.
[0006]
[Variable threshold threshold element circuit with circuit state holding function]
Document 3 (Japanese Patent Laid-Open No. 2001-196920: Function and function configuration data holding method and integrated circuit using the method) uses a structure peculiar to a νMOS inverter circuit and a method for holding a set threshold value. A circuit configuration using the method is disclosed. FIG. 24 is a diagram showing a typical circuit configuration of a k-input variable νMOS inverter circuit having a circuit state holding function.
[0007]
In this νMOS inverter circuit 2400, an NMOS type pass transistor swn that is turned on / off by a control signal from the state control terminal ctl2 is added between the floating gate FG and the fixed potential terminal Pgnd on the ground side. Further, a transmission gate tgin is provided between the control variable terminal input2 and a terminal capacitively coupled to the floating gate FG (hereinafter referred to as a control variable input terminal) input2a, and the control variable input terminal input2a and the power source A PMOS type pass transistor swp is provided between the fixed potential terminal Pvdd on the side. Further, an inverter inv1 is provided between the state control terminal ctl1 and the transmission gate tgin. The transmission gate tgin and the pass transistor swp are turned on / off by a control signal from the state control terminal ctl1.
[0008]
With such a circuit configuration, it is possible to set and hold a threshold value selected by a potential Vv applied to the control variable terminal input2 (hereinafter, this potential Vv is referred to as configuration data). .
[0009]
[Circuit state holding operation]
The threshold holding operation in FIG. 24 will be briefly described. First, the state control terminal ctl2 is set to the power supply potential having the logical value “1”, the pass transistor swn is turned on, and the potential of the floating gate FG is set to the ground potential. Next, the state control terminal ctl1 is set to the power supply potential, the pass transistor swp is cut off, and the transmission gate tgin is turned on. At this time, all input variables input from the input variable terminals input1 [1] to input1 [k] are set to the ground potential having the logical value “0”.
[0010]
Now, the time when the first state control terminal ctl1 and the second state control terminal ctl2 are the logical value “1” is referred to as initialization. Further, the potential of the floating gate FG when the logical value “1” is input from the control variable terminal input2 of the νMOS inverter circuit 2300 of FIG. 23 having a complete floating gate is called a first floating gate potential. The potential when the logical value “0” is input is referred to as a second floating gate potential.
[0011]
The above operation is performed at the time of initialization, and the logical value “0” is continuously input to the control variable terminal input2. At this time, the logical value “0” is given to the control variable input terminal input2a that is capacitively coupled to the floating gate FG, similarly to the input of the control variable terminal input2. That is, when the floating gate FG is at the ground potential, an input variable having a logical value “0” and a control variable are given. The input to the first state control terminal ctl1 and the second state control terminal ctl2 is switched from the logical value “1” to the logical value “0” while maintaining this input state. When the first state control terminal ctl1 and the second state control terminal ctl2 have the logical value “0”, this is called function execution time.
[0012]
When the function is executed, the pass transistor swn is cut off, and the floating gate FG is in a high impedance state, and transiently becomes substantially floating (electrically floating state). At the same time, the transmission gate tgin is cut off, the pass transistor swp is turned on, and the power supply potential having the logical value “1” is applied to the control variable input terminal input2a. For this reason, charge redistribution occurs on the floating gate FG, and the floating gate FG becomes the first floating gate potential.
[0013]
Similarly, when a power supply potential having a logical value “1” is given to the control variable terminal input2 at the time of initialization, the same power supply potential as that at the time of initialization is given to the control variable input terminal input2a at the time of function execution. If the input variable is a logical value “0”, it becomes the second floating gate potential.
[0014]
Thus, the floating gate potential at the time of function execution is determined depending on the logical value given as the control variable at the time of initialization. That is, the configuration data determined at the time of initialization is held at the time of function execution. This configuration data holding operation and necessary elements will be described below.
[0015]
Since the floating gate potential is fixed to the ground potential at the time of initialization, when a predetermined potential which is a control variable is given to the control variable input terminal input2a, charge is injected into the floating gate FG from the ground side.
[0016]
Next, when the function is executed, the injected charge is held in the floating gate FG, charge redistribution occurs depending on the logical value of the input variable, and the floating gate potential is determined. There are two elements necessary for holding the configuration data, one is injection of charge from one terminal connected to the floating gate FG, and the other is injection when the floating gate FG is high impedance. The charged charge is retained.
[0017]
[Functional Function Reconfigurable Integrated Circuit]
A circuit capable of reconfiguring a function function for a two-input variable will be described with reference to Reference 4 (Japanese Patent Laid-Open No. 2001-223576: an integrated circuit capable of reconfiguring a function function). FIG. 25 is a diagram showing a function function reconfigurable integrated circuit (two-input variable variable function circuit) using the νMOS inverter circuit 2400 shown in FIG. This two-input variable variable function circuit is a two-stage logic feedforward type circuit. The first stage is composed of three νMOS inverter circuits FTE [1], FTE [2], FTE [3], and the second stage It is composed of one νMOS inverter circuit STE.
[0018]
In the two-input variable variable function circuit 2500, the two input variables are input variable terminals input1 [1], input1 [2] to the first stage νMOS inverter circuits FTE [1], FTE [2], FTE [3 ] And floating gates FG [1], FG [2], FG [3] and the floating gate FG [S] of the second stage νMOS inverter circuit STE, and the first stage νMOS inverter circuit FTE [1]. , FTE [2], FTE [3] are amplified and waveform shaped by the buffers BF [1], BF [2], BF [3], and the floating gate FG [S of the second stage νMOS inverter circuit STE. ] Is given.
[0019]
Note that the floating gate FG [S] of the STE is initialized between the first stage νMOS inverter circuits FTE [1], FTE [2], FTE [3] and the second stage νMOS inverter circuit STE. At this time, transmission gates tgs1, tgs2, and tgs3 and pass transistors swi1, swi2, and swi3 are inserted in order to set all input signals to the ground potential.
[0020]
In FTE [1], FTE [2], FTE [3], and STE, the capacitance values between the input variable terminals and the floating gate are set equal. In STE, the capacitance value between the terminal to which the output values of FTE [1], FTE [2], and FTE [3] are given and the floating gate is between the terminal to which the input variable is given and the floating gate. Is set equal to the capacity value. By this setting, the input state of the STE, that is, the product sum of the input variable and the weight becomes three, “0”, “1”, and “2”. The number corresponding to this input state is called the number of states of the input variable (number of input states). In addition, the state quantity (input state quantity) of the input variable is used as the upper word of the number of states of the input variable.
[0021]
Taking FTE [1] as an example, between FTE [1] and STE, when the floating gate FG [S] of STE is initialized, the input signals of all input terminals are set to the ground potential. The transmission gate tgs1 and the pass transistor swi1 are inserted. The same applies to FTE [2] and FTE [3]. Similarly to FTE [1], FTE [2], and FTE [3], STE uses two periods for initialization and function execution.
[0022]
At the time of initialization, a logical value “1” is applied to the first state control terminal ctl1 and the second state control terminal ctl2, and the pass transistor sws connected to the floating gate FG [S] is made conductive. At the same time, the transmission gate tgs1 is cut off, the pass transistor swi1 is turned on, and a ground potential having a logical value “0” is applied to the floating gate FG [S] that is capacitively coupled through the buffer BF [1]. When a logical value “0” is given as an input variable, all inputs are logical values “0”. While maintaining this state, by giving a logical value “1” to the first state control terminal ctl1 and the second state control terminal ctl2, the state at the time of function execution can be formed.
[0023]
Next, the case where an arbitrary function can be realized with a variable threshold value will be described by taking an example where XOR (Exclusive-OR) is realized. The threshold values of FTE [1], FTE [2], and FTE [3] can be selected from either of two threshold values before and after the input state number 0, before and after 1, and before and after 2, respectively. Can be set. In FTE [1], FTE [2], and FTE [3], when a logical value “0” is given as a control variable at initialization, the smaller threshold value can be selected, and conversely, the logical value “1” is set. If given, the larger threshold is selected.
[0024]
As the threshold value of FTE [1], a value greater than 0 and less than 1 is selected, and as the threshold value of FTE [2], a value smaller than 1 and greater than 0 is selected. 3] is selected as a threshold value greater than two input states. At this time, the logical value of the output of FTE [1] is “1”, “0”, “0” with respect to the input state numbers 0, 1, and 2. The logical value of the output of FTE [2] is “1”, “0”, “0” for the input state numbers 0, 1, 2 and the logical value of the output of the FTE [3] is “1” for the input state numbers 0, 1, 2 , “1”, “1”.
[0025]
When the number of input states is 0, 1, and 2, the number of terminals having a logical value “1” among the five input terminals of the STE is 3, 2, and 3, respectively. Since the output value of the STE is the logical inversion of the result of the majority of the inputs, the output values are “0”, “1”, “0” for the input state numbers 0, 1, 2, and XOR is realized. . This is an FTE having a threshold before and after each input state number, FTE [1] if the number of input states is 0, FTE [2] if the number of input states is 1, and if the number of input states is 2. For FTE [3], it means that the logical inversion of the logical value given as the control variable at the time of initialization is output.
[0026]
As can be seen from the above-described XOR implementation, according to the two-input variable variable function circuit 2500 shown in FIG. 25, the floating gates FG [1] of FTE [1], FTE [2], FTE [3], and STE. , FG [2], FG [3], and FG [S] hold the circuit state determined by the configuration data input to the control variable terminals input2 [1] to input2 [3] By doing so, an arbitrary symmetric function can be realized.
[0027]
However, the symmetric function is a logical function in which the function value is defined by the number of input states as represented by the AND, OR, NAND, NOR, XOR, XNOR, 0, 1 function, and the variables are interchanged. However, the function value is invariant.
[0028]
[Problems to be solved by the invention]
[Problems of variable threshold threshold element circuit with circuit state maintaining function]
In the νMOS inverter circuit 2400 shown in FIG. 24, two elements necessary for maintaining the circuit state, namely, injection of charge into the floating gate FG and retention of the injected charge are connected to the floating gate FG. This is accomplished by manipulating the pass transistor swn which is a switch.
[0029]
However, the pass transistor swn is referred to as a subthreshold current and a PN junction reverse saturation current between the drain terminal and the substrate (or well) even if the state control terminal ctl2 is at the ground potential of logic “0”. Has two leakage currents. For this reason, the amount of charge held in the floating gate FG changes with time. This change then changes the threshold to another value. That is, the state to be held is volatile, and the threshold value is also volatile. The volatility of the threshold value causes the problem of malfunction over time of the νMOS inverter INV.
[0030]
[Problems of functional function reconfigurable integrated circuit]
In the two-input variable variable function circuit 2500 shown in FIG. 25, the function function to be realized is determined by the logical values of the control variables input to the FTE [1], FTE [2], and FTE [3] during initialization. It is determined by the threshold. As described above, the threshold holding state changes with time. For this reason, in the two-input variable variable function circuit 2500, the function that is realized changes with the passage of time, and the problem that the originally realized function cannot be realized, that is, the problem of temporal malfunction occurs.
[0031]
The present invention has been made to solve such a problem, and an object of the present invention is to provide a variable threshold value that can hold the threshold value in a nonvolatile manner and eliminate the problem of malfunction over time. It is an object of the present invention to provide a threshold element circuit, a circuit state maintaining method in the variable threshold threshold element circuit, and a function function reconfigurable integrated circuit using the variable threshold threshold element circuit.
[0032]
[Means for Solving the Problems]
In order to achieve such an object, the variable threshold threshold element circuit of the present invention provides a control variable for controlling the threshold value via a series connection circuit of a ferroelectric capacitor and a paraelectric capacitor. One or more control variable terminals that propagate are coupled to the gate electrode of the threshold element (first invention).
In this case, as a circuit state holding method (10th invention), a control variable is input from a control variable terminal (first step), an input variable is input from an input variable terminal (second step), and a control variable terminal The control variable input to is removed (third step). Note that the control variable input to the control variable terminal may be removed between the first step and the second step.
[0033]
The ferroelectric capacitor retains the charge amount for spontaneous polarization even after the control variable is removed, that is, after the input potential disappears. This redistributes the charge on the gate electrode depending on the potential of each terminal capacitively coupled to the gate electrode of the threshold element, determines the potential of the gate electrode, and maintains the threshold element threshold value. Is done.
For example, when the threshold element is a field effect transistor, the switching point (transistor threshold) of the on / off operation of the field effect transistor transistor with respect to the state quantity of the input variable is maintained. Further, when the threshold element is a νMOS inverter, the switching point (logic threshold value) of the logic inversion operation of the νMOS inverter with respect to the state quantity of the input variable is held.
[0034]
In the variable threshold threshold element circuit of the present invention, one end of the paraelectric capacitor in the series connection circuit is connected to the gate electrode, and the other end of the paraelectric capacitor is connected to one end of the ferroelectric capacitor. The first switch is connected between one end and the other end of the ferroelectric capacitor, and the second switch is connected between the other end of the ferroelectric capacitor and the control variable terminal (first). 2 invention).
In this case, as a circuit state holding method (11th invention), the first switch is turned off and the second switch is turned on (first step). After executing the first step, the control variable terminal is used. The control variable is input and the input variable is input from the input variable terminal (third step: threshold value setting period). After execution of the second step, the second switch is turned off, and the first switch The switch is turned on (third step: threshold holding period).
[0035]
The ferroelectric capacitor retains the amount of charge for spontaneous polarization even after the second switch is turned off, that is, after the control variable from the control variable input terminal to the ferroelectric capacitor is removed. To do. In the threshold holding period, the first switch is in a conductive state and holds the charge amount due to remanent polarization in a nonvolatile manner. Further, since the ferroelectric capacitor is connected in series with the paraelectric capacitor, a charge amount equivalent to the charge amount held in the ferroelectric capacitor is also induced in the paraelectric capacitor. This redistributes the charge on the gate electrode depending on the potential of each terminal capacitively coupled to the gate electrode of the threshold element, determines the potential of the gate electrode, and maintains the threshold element threshold value. Is done.
[0036]
The function-function reconfigurable integrated circuit according to the present invention (the eighth invention) is such that at least one of the variable threshold threshold element circuits connected in multiple stages is the variable threshold threshold element circuit according to the present invention. It is.
For example, two stages of variable threshold threshold element circuits are connected, and the first stage variable threshold threshold element circuit is connected in common to the first to kth input variable terminals. A variable threshold threshold element circuit is constituted by a plurality of variable threshold threshold element circuits, and a second stage variable threshold threshold element circuit is constituted by one variable threshold threshold element circuit. The first to k-th input variable terminals of the circuit are connected in common with the first to k-th input variable terminals of each variable threshold threshold element circuit of the first stage, and each variable of the first stage is changed. The output signal from the threshold threshold element circuit is applied to each input terminal capacitively coupled to the gate electrode of the second-stage variable threshold threshold element circuit.
In such a structure, for example, the above-described variable threshold threshold element circuit of the present invention is used for the first stage variable threshold threshold element circuit (ninth invention).
[0037]
In the variable threshold threshold element circuit of the present invention, various types of threshold elements can be considered. For example, a field effect transistor is used as a threshold element, and either one of the source terminal and the drain terminal of the field effect transistor is connected to a circuit having an element that serves as an electrical load (fourth invention). In this case, the element that becomes an electrical load may be a resistor (fifth invention), or a field effect transistor that transports charges having a polarity opposite to that of the field effect transistor (sixth invention). . In addition, the threshold element may be an inverter circuit including a first field effect transistor and a second field effect transistor that transports electric charges having a polarity opposite to that of the first field effect transistor. (Seventh invention). In the function-function reconfigurable integrated circuit according to the eighth or ninth invention, it is sufficient that at least one of these variable threshold threshold element circuits is used, and these variable threshold threshold element circuits are used. It may be configured by combining.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
[Ferroelectric memory]
First, a ferroelectric memory and a MFIS field effect transistor will be described before the description of embodiments of the present invention. Currently, DRAM, SRAM, flash memory, ferroelectric memory (FeRAM) and the like are being researched and developed. DRAM is characterized by high-capacity and medium-speed data rewriting, and SRAM is characterized by medium-memory capacity and high-speed data rewriting, both of which are volatile. Flash memory operates at a low speed in writing and data erasing, but is non-volatile.
[0039]
On the other hand, the ferroelectric memory is PZT (Pb (Zr _x Ti _1-x ) O _Three ) And SBT (SbBi ₂ Ta ₂ O ₉ Since the polarization characteristics of the ferroelectric material represented by (1) are applied, it is non-volatile and data can be rewritten at a speed equivalent to DRAM. Furthermore, the ferroelectric memory can be manufactured by simply adding a layer for forming a ferroelectric capacitor to the CMOS process technology, and has good compatibility with a standard CMOS process. FIG. 1 is a circuit diagram showing a ferroelectric capacitor 100 used in a ferroelectric memory. A predetermined voltage V is applied between one terminal 101 and the other terminal 102 of the ferroelectric capacitor 100, and a positive applied voltage is when the terminal 102 is at a high potential.
[0040]
FIG. 2 is a diagram illustrating the relationship between the voltage V and the charge amount Q when the voltage V is applied between the terminals 101 and 102. In FIG. 2, Vc represents a coercive voltage, and Qr represents a charge amount due to remanent polarization. Even if the voltage between the terminals 101 and 102 is zero, Qr remains at both terminals. The memory function for holding binary values uses these two states. In recent years, research and development of ferroelectric memories having the feature that data is nonvolatile and can be rewritten at high speed using the bistability of spontaneous polarization has been energetically advanced.
[0041]
[MFMIS type field effect transistor]
As a ferroelectric capacitor used in the ferroelectric memory, a metal electrode typified by Pt or IrO ₂ And SrRuO _Three An oxide electrode represented by (SRO) includes a planar type and a stack type in which a ferroelectric material is sandwiched. Other structures include metal / ferroelectric / silicon (MFS) type, metal / ferroelectric / insulator / silicon (MFIS) type, metal / ferroelectric / metal / insulator / silicon (MFMIS). A mold has also been proposed.
[0042]
FIG. 3 is a circuit diagram showing a field effect transistor having an MFMIS type ferroelectric capacitor disclosed in Reference 5 (Japanese Patent Laid-Open No. 11-177038: MFMIS type ferroelectric memory element and manufacturing method thereof). This circuit has a structure in which a MFMIS type ferroelectric capacitor 303 is connected in series to a metal (or Poly-Si) electrode terminal 302 above a gate oxide film 301 formed of a paraelectric material of the MOS transistor 300.
[0043]
FIG. 4 is a circuit diagram showing a field effect transistor having a MFMIS type ferroelectric capacitor disclosed in Reference 6 (Japanese Patent Laid-Open No. 2000-349251: Semiconductor device). This circuit has a structure in which one terminal of an MFMIS type ferroelectric capacitor 402 and one terminal of a paraelectric capacitor 403 are connected to an input gate 401 of a standard field effect transistor 400. That is, in this circuit, a ferroelectric capacitor 402 and a paraelectric capacitor 403 are connected in parallel to the input gate 401.
[0044]
FIG. 5 is a circuit diagram showing a field effect transistor having a MFMIS type ferroelectric capacitor disclosed in Reference 7 (Japanese Patent Laid-Open No. 2000-138351: Ferroelectric nonvolatile memory and reading method thereof). This circuit has a structure in which MFMIS type ferroelectric capacitors 503 and 504 having substantially the same remanent polarization are connected in parallel to an input gate 502 of a standard field effect transistor 501.
[0045]
The circuit structure of the three MFMIS type field effect transistors having ferroelectric capacitors has been described above. However, in the embodiments of the present invention to be described later, the MFMIS type field effect having ferroelectric capacitors which are not any of these types. A transistor is used. FIG. 6 shows a circuit diagram of an MFMIS type field effect transistor having a ferroelectric capacitor used in the embodiment of the present invention. This circuit has a structure in which a paraelectric capacitor 601 and an MFMIS type ferroelectric capacitor 603 are connected in series to an input gate of a standard field effect transistor 601. That is, one terminal of the paraelectric capacitor 601 is connected to the input gate 602 of the field effect transistor 600, and the other terminal of the paraelectric capacitor 601 and one terminal of the ferroelectric capacitor 603 are connected. .
[0046]
[Embodiment 1: Capacitive coupling input type field effect transistor]
FIG. 7 is a circuit diagram of a capacitively coupled input field effect transistor showing an embodiment of a variable threshold threshold element circuit according to the present invention. In this capacitively coupled input type field effect transistor 700, input variable terminals input 1 [1] to input 1 [k] are connected to the gate electrode 702 of the field effect transistor 701 as a paraelectric capacitor 703. ₁ ˜703k, the control variable terminals input2 [1] to input2 [m] are connected to the threshold data holding circuit 704 ₁ It is connected through ~ 704m.
[0047]
Threshold data holding circuit 704 ₁ Is a paraelectric capacitor 705 ₁ And MFMIS type ferroelectric capacitor 706 ₁ And a paraelectric capacitor 705 ₁ Is connected to the gate electrode 702 of the field effect transistor 701, and the paraelectric capacitor 705 is connected. ₁ The other terminal of the ferroelectric capacitor 706 ₁ Connected to one terminal of the ferroelectric capacitor 706 ₁ Is connected to the control variable terminal input2 [1]. Other threshold data holding circuits have the same configuration.
[0048]
In this capacitively coupled input field effect transistor 700, control variables are input from control variable terminals input2 [1] to input2 [m] as a first step, and input variable terminals input1 [1] to [2] as a second step. Input variables from input1 [k]. As a third step, the control variable input to the control variable terminals input2 [1] to input2 [m] is removed. Note that the control variable input to the control variable terminals input2 [1] to input2 [m] may be removed between the first step and the second step.
[0049]
Threshold data holding circuit 704 ₁ ˜704 m, ferroelectric capacitor 706 ₁ ˜706 m retains the amount of charge for spontaneous polarization even after the control variable is removed, ie, after the input potential disappears. As a result, charge redistribution on the gate electrode 702 is performed depending on the potential of each terminal capacitively coupled to the gate electrode 702 of the field effect transistor 701, the potential of the gate electrode 702 is determined, and the number of states of the input variable The switching point (transistor threshold) of the on / off operation of the field effect transistor 701 with respect to (the state quantity of the input variable) is maintained. The transistor threshold value of the field effect transistor 701 can be set to an arbitrary value by a combination of control variables to the control variable terminals input2 [1] to input2 [m].
[0050]
[Embodiment 2: Basic configuration of νMOS inverter circuit using capacitively coupled input field effect transistor]
FIG. 8 is a circuit configuration diagram showing a basic configuration of a νMOS inverter circuit using the capacitively coupled input field effect transistor 700 shown in FIG. In this νMOS inverter circuit 800, the input variable terminals input1 [1] to input1 [k] are connected to the floating gate FG of the νMOS inverter INV by a paraelectric capacitor C. ₁ Are connected through ~ Ck, and control variable terminals input2 [1] to input2 [m] are connected to the threshold data holding circuit HLD. ₁ Bound through ~ HLDm. Threshold data holding circuit HLD ₁ Is the ferroelectric capacitor C _p1 And paraelectric capacitance C _v1 And a series connection circuit. Other threshold data holding circuits are similarly configured.
[0051]
In this νMOS inverter circuit 800, control variables are input from control variable terminals input2 [1] to input2 [m] as a first step, and input variable terminals input1 [1] to input1 [k] as a second step. Input variable from. Then, as a third step, the control variables input to the control variable terminals input2 [1] to input2 [m] are removed. Note that the control variable input to the control variable terminals input2 [1] to input2 [m] may be removed between the first step and the second step.
[0052]
Threshold data holding circuit HLD ₁ ~ HLDm, ferroelectric capacitor C _p1 ~ C _pm Retains the amount of charge due to spontaneous polarization even after the control variable is removed, i.e., after the input potential disappears. Thereby, depending on the potential of each terminal capacitively coupled to the floating gate FG, charge redistribution on the floating gate FG is performed, the potential of the floating gate FG is determined, and the number of states of the input variable (the state of the input variable) The switching point (logical threshold value) of the logic inversion operation of the νMOS inverter INV with respect to (quantity) is held. The logical threshold value of the νMOS inverter INV can be set to an arbitrary value by a combination of control variables to the control variable terminals input2 [1] to input2 [m].
[0053]
[Embodiment 3: Capacitively coupled input field effect transistor having a switch]
FIG. 9 is a circuit diagram of a capacitively coupled input field effect transistor having a switch. The threshold value data holding circuit 904 is different from the circuit 700 shown in FIG. ₁ The configuration of ~ 904m is different. Threshold data holding circuit 904 ₁ The paraelectric capacitor 905 will be described as a representative. ₁ And ferroelectric capacitor 906 ₁ Are the same in that the ferroelectric capacitors 906 are connected in series. ₁ The first switch 908 that conducts or cuts off the terminals Pa and Pb between the terminals Pa and Pb. ₁ Are connected, the control variable input terminal input2 [1] and the ferroelectric capacitor 906 ₁ The second switch 907 is connected to the terminal Pb of ₁ Are different in that they are connected. Other threshold data holding circuits have the same configuration.
[0054]
In this capacitively coupled input field effect transistor 900, as the first step, the first switch 908 is used. ₁ ˜908m is cut off, and the second switch 907 ₁ ˜907m is turned on. As a second step, control variables are input from control variable terminals input2 [1] to input2 [m], and input variables are input from input variable terminals input1 [1] to input1 [k]. As a third step, the second switch 907 ₁ ~ 907m cut off, the first switch 908 ₁ ˜908 m is turned on.
[0055]
Threshold data holding circuit 904 ₁ ˜904 m, ferroelectric capacitor 906 ₁ ˜906m is the second switch 907 ₁ The ferroelectric capacitor 906 from the control variable input terminals input2 [1] to input2 [m] even after .about.907m is cut off. ₁ Even after the control variable to ˜906 m is removed, the amount of charge is retained for spontaneous polarization. Thus, charge redistribution on the gate electrode 902 is performed depending on the potential of each terminal capacitively coupled to the gate electrode 902 of the field effect transistor 901, the potential of the gate electrode 902 is determined, and the number of states of the input variable The switching point (transistor threshold value) of the on / off operation of the field effect transistor 901 with respect to (state quantity of input variable) is maintained. The transistor threshold value of the field effect transistor 901 can be set to an arbitrary value by a combination of control variables to the control variable terminals input2 [1] to input2 [m].
[0056]
[Embodiment 4: Basic Configuration of νMOS Inverter Circuit Using Capacitively Coupled Input Field Effect Transistor with Switch]
FIG. 10 is a circuit configuration diagram showing a basic configuration of a νMOS inverter circuit using the capacitively coupled input field effect transistor 900 having the switch shown in FIG. In this νMOS inverter circuit 1000, the input variable terminals input1 [1] to input1 [k] are connected to the floating gate FG of the νMOS inverter INV by a paraelectric capacitor C. ₁ Are coupled via .about.Ck, and the control variable terminal input2 is coupled via the threshold data holding circuit HLD. The threshold data holding circuit HLD is constituted by a series connection circuit of a ferroelectric capacitor Cp and a paraelectric capacitor Cv. Further, in the threshold data holding circuit HLD, a first switch SW1 for connecting or blocking between the terminals P1 and P2 is connected between the terminals P1 and P2 of the ferroelectric capacitor Cp, and the control variable input terminal. A second switch SW2 is connected between input2 [1] and the terminal P1 of the ferroelectric capacitor Cp.
[0057]
In FIG. 10, a νMOS inverter INV is a non-linear circuit that performs threshold processing in a variable threshold threshold element circuit, and causes logic inversion when the potential of the floating gate FG exceeds a certain logic threshold. In this example, a νMOS inverter composed of a p-channel field effect transistor (PMOSFET) Q1 and an n-channel field effect transistor (NMOSFET) Q2 is used as the nonlinear circuit. For example, FIG. 11A, FIG. It is good also as a circuit structure as shown to a) and (b).
[0058]
FIG. 11A shows a configuration in which a load impedance element Zi is connected to an n-channel field effect transistor Q2, and FIG. 11B shows a configuration in which a load impedance element Zi is connected to a p-channel field effect transistor Q1. FIG. 12A shows a configuration in which a resistor R is connected to the n-channel field effect transistor Q2 instead of the load impedance Zi, and FIG. 12B shows a p-channel instead of the load impedance Zi to the n-channel field effect transistor Q2. The field effect transistor Q1 is connected. In FIG. 12B, the p-channel field effect transistor Q1 and the n-channel field effect transistor Q2 may be interchanged. Even with such a circuit configuration, it is possible to operate as a threshold processing circuit and use it as a threshold element circuit, similarly to the νMOS inverter circuit INV shown in FIG.
[0059]
〔Initial setting〕
In the νMOS inverter circuit 1000 shown in FIG. 19, when the switch SW2 is in the connected state and the switch SW1 is in the cut-off state, the charge amount Qfe appearing at the terminal P1 on one side, which is the electrode of the ferroelectric capacitor Cp, The relationship between the potential Vfe1 of the terminal P1 and the potential Vfe2 of the other terminal P2 is derived as follows.
[0060]
First, the potentials of the input variable terminals input1 [1] to input1 [k] are sequentially set to V. ₁ , V ₂ ,..., Vk, the potential of the control variable terminal input2 is Vfe1, the potential of the terminal P2 is Vfe2, and the potential of the floating gate FG is Vfg. The capacitance values between the input variable terminals input1 [1] to input1 [k] and the floating gate FG are sequentially set to C. ₁ , C ₂ ,..., Ck. In addition, the capacitance value between the terminal P2 and the floating gate FG is Cv, and the capacitance value between the floating gate FG and each terminal of the field effect transistors Q1 and Q2 is collectively Cmos. Cmos is ΣCi = C ₁ + C ₂ It is assumed that this temporary capacitance Cmos exists between the floating gate FG and the ground.
[0061]
FIG. 13 is a diagram showing the relationship between the charge amount Qfe appearing at one terminal P1 of the ferroelectric capacitor Cp and the voltage (Vfe1−Vfe2) across the ferroelectric capacitor Cp. If the initial charge amount at the terminal P2 is 0, the charge amount of Qfe is also induced on the terminal P2 side of the paraelectric capacitance Cv from the law of conservation of charge. Therefore, the following equation holds for the paraelectric capacitor Cv.
[0062]
[Expression 1]

[0063]
Next, attention is paid to the charge amount storage of the floating gate FG. As described above, the initial charge amount of the floating gate FG is assumed to be zero.
[0064]
[Expression 2]

[0065]
Applying the relationship of ΣCi >> Cmos to equation (2) and solving for Vfg, the following equation is obtained.
[0066]
[Equation 3]

[0067]
From equations (1) and (3), the relationship between Qfe and (Vfe1−Vfe2) is
[0068]
[Expression 4]

[0069]
Now, assume that the power supply potential is Vdd and the ground potential is 0. The case where Vi = 0 and Vfe1 = 0 for all input variable terminals input1 is (I), and the case where Vi = 0 and Vfe1 = Vdd for all input variable terminals input1 is (II). The case where Vi = Vdd and Vfe1 = 0 is set for the input variable terminal input1 (III), and the case where Vi = Vdd and Vfe1 = Vdd is set for all the input variable terminals input1 is set (IV).
[0070]
In FIG. 13, the cases (I) and (III) described above are straight lines that pass through the origin and have an inclination of −CvΣCi / (Cv + ΣCi). In the case of (II), the point A0 in FIG. 13 can be set as the intersection point due to the relationship between the hysteresis loop and each capacitance value. In the case of (IV), the point B0 can be set as the intersection point as in (II). The cases (II) and (IV) are two initial settings.
[0071]
[Threshold retention method]
After the initial setting described above, the switch SW2 in FIG. 10 is turned off and the switch SW1 is turned on. As a result, the terminal P1 and the terminal P2 have the same potential, and (Vfe1-Vfe2) = 0. Thereby, when it is A0 point by the initial setting, it shifts to A1 point, and when it is B0 point, it shifts to B1 point. By this operation, the charge quantity Q due to remanent polarization at each of the points A1 and B1. _A1 , Q _B1 Is held in a nonvolatile manner.
[0072]
Q is connected to the terminal P1 of the ferroelectric capacitor Cp. _A1 Or Q _B1 When the same amount of charge appears, the same amount of charge of opposite polarity appears at the terminal P2 of the paraelectric capacitor Cv. FIG. 14 is a diagram showing the relationship between the potential Vfg of the floating gate FG in FIG. is there. Further, Csum in FIG. 14 means ΣCi, and Vdd / 2 means (1/2) the potential of the power supply potential.
[0073]
When viewed from the floating gate FG, whether or not the subsequent νMOS inverter INV is logically inverted depends on the electrical characteristics of the p-channel field effect transistor Q1 and the n-channel field effect transistor Q2 constituting the νMOS inverter INV. In FIG. 14, it is assumed that the output potential of the νMOS inverter INV becomes Vdd / 2 when the floating gate potential Vfg is Vdd / 2. The switch SW1 in FIG. 10 is in a connected state, and Q is connected to the terminal P1 of the ferroelectric capacitor Cp. _A1 Or Q _B1 Since the same amount of charge is held in the capacitor Cv, the following equation holds for each held charge amount.
[0074]
[Equation 5]

[0075]
The ΣCi · Vi coordinates of the intersections of Equation (5), Equation (6), and Vdd / 2 are α _A And α _B It becomes. If equation (5) holds, the product-sum value for the first time when a combination of Vi, which is a physical representation of the input variable, is α _A , The νMOS inverter INV in FIG. 10 causes logic inversion. If equation (6) holds, the product-sum value for the first time when a combination of Vi, which is a physical representation of the input variable, is α _B , The νMOS inverter INV in FIG. 10 causes logic inversion. In this way, it is possible to make the threshold value as seen from the input variable variable and hold the threshold value in a nonvolatile manner.
[0076]
Next, in order to clarify the operation as a logic circuit, the variables in FIG. 14 are changed. First, for simplification, in the νMOS inverter circuit 1000 of FIG. 10, the capacitance values between the input variable terminals input1 [1] to input1 [k] and the floating gate FG are all set equal to C. Making the weight of the input variable equal in the threshold element means that the number of states formed by the input variable, that is, the number of input states is (k + 1), and represents a symmetric function.
[0077]
In order to express a logical function that is not a symmetric function, the weights of each input variable are expressed in Reference 8 (Kazuo Aoyama, Hiroshi Sawada, Akira Nagoya, A design method for a logic function circuit using neuron MOS, 13th Circuit and System (Karuizawa) This can be realized by applying the input vector identification method shown in Workshop 2000). As an example, for an integer i of (1 ≦ i ≦ k), the capacitance value between the i-th input variable terminal and the floating gate FG is expressed as C · 2 ^i-1 There is a way to set.
[0078]
In this embodiment, the case of a symmetric function will be described for simplification. FIG. 15 is a diagram illustrating the relationship between the number of input states and the normalized floating gate potential in the νMOS inverter circuit 1000. Now, (Vi / Vdd) = Xi and ΣXi = X ₁ + X ₂ ... + Xk = Z, Vfg = Vdd = Ufg. Xi corresponds to the logical value of the input variable. The aforementioned Ufg is referred to as a normalized floating gate potential. Q _A1 = (K ・ C ・ Vdd) = U _A1 , Q _B1 = (K ・ C ・ Vdd) = U _B1 And At this time, the equations (5) and (6) are changed to the following equations.
[0079]
[Formula 6]

[0080]
The Z coordinate of the intersection of each equation and (1/2) is Z _A , Z _B Represented by 1 <Z _A <2, 3 <Z _B If <4, the νMOS inverter circuit 1000 is set so that the number of input states has a threshold value between 1 and 2 or between 3 and 4.
[0081]
[Embodiment 5: Threshold adjustment method and circuit configuration of νMOS inverter circuit capable of threshold adjustment]
FIG. 16 is a diagram illustrating a νMOS inverter circuit to which a terminal for supplying a fixed potential is added. Similar to the νMOS inverter circuit 1000 shown in FIG. 10, this νMOS inverter circuit 1600 has input variable terminals input1 [1] to input1 [k], has a control variable terminal input2, and has a non-volatile threshold value. It has a threshold data holding circuit HLD including a ferroelectric capacitor Cp to hold. The circuit 1600 is different from the circuit 1000 in that it has a terminal connected to a fixed potential. Specifically, it has a terminal Pvdd connected to the power supply potential Vdd and a terminal Pgnd connected to the ground potential. Although the power supply potential and the ground potential are mentioned as the fixed potential, the same effect can be obtained with respect to the adjustment of the threshold value even if other potentials are used.
[0082]
Next, the effect of the added terminals Pvdd and Pgnd will be described. FIG. 17 is a diagram illustrating the relationship between the number of input states Z and the normalized floating gate potential Vfg / Vdd = Ufg in the circuit 1600 of FIG. The capacitance value between the terminal Pvdd and the floating gate FG in FIG. 16 is Cvdd, and the capacitance value of FG between the terminal Pgnd and the floating gate is Cgnd. At this time, assuming that C′sum = k · C + Cvdd + Cgnd, the same expressions as Expression (5) and Expression (6) become Expression (9) and Expression (10), respectively.
[0083]
[Expression 7]

[0084]
When the equations (9) and (6) are normalized by the power supply potential, the following equation is obtained.
[0085]
[Equation 8]

[0086]
Here, the definition of the number of input states Z is the same as described above, Uvdd = (Cvdd / C′sum), and U ′ _A1 = Q _A1 = (Vdd · C'sum), U ' _B1 = Q _B1 = (Vdd · C'sum). Cvdd is the sum of C′sum and (Udd + U ′) in equations (11) and (12). _A1 ) Or (Udd + U ' _B1 ), While Cgnd is C'sum and U ' _A1 Or U ' _B1 Contribute to. The two capacitance values can change the intercept of the straight line A or line B in FIG. 17 and the Ufg axis. Thus, by using a terminal connected to a fixed potential, a threshold value Z ′ which is the Z coordinate of the intersection with Ufg = 1/2. _A Or Z ' _B Can be set to an arbitrary value of Z.
[0087]
[Circuit configuration of threshold data holding circuit]
FIG. 18 is a diagram showing a specific circuit of threshold data holding circuit HLD in FIG. This is a circuit configuration in which the switches SW2 and SW1 in FIG. 16 are replaced with transmission gates TG1 and TG2, respectively. A terminal ctl3 is a switch control signal input terminal that controls connection or disconnection between the transmission gates TG1 and TG2. The signal input from the terminal ctl3 is logically inverted by the inverter circuit inv2. When the signal input from the terminal ctl3 is the logical value “1”, the transmission gate TG2 is in the connected state and the transmission gate TG1 is in the cutoff state. On the contrary, when the signal is a logical value “0”, the transmission gate TG2 is cut off, the transmission gate TG1 is connected, and the electric charge due to remanent polarization is held in the ferroelectric capacitor Cp.
[0088]
[Embodiment 6]
In the sixth embodiment, a circuit configuration in which one threshold value can be selected from a plurality of settable threshold values and held in a nonvolatile manner will be described. In the fifth embodiment, one threshold value is selected from two settable threshold values. On the other hand, in the sixth embodiment, the number of thresholds that can be set is larger than two.
[0089]
FIG. 19 is a configuration diagram of a k-input variable νMOS inverter circuit capable of holding one threshold selected from a plurality of settable thresholds in a nonvolatile manner. This νMOS inverter circuit 1900 has a circuit configuration in which a plurality of threshold data holding circuits HLD in the same circuit are added to the νMOS inverter circuit 1600 of FIG. Assume that there are m threshold value data holding circuits HLD in the circuit 1900 of FIG. Threshold data holding circuit HLD ₁ ~ Two charge quantities Q 'held in HLDm _A1 And Q ' _B1 Is all threshold data holding circuit HLD ₁ It is assumed that each is equal in ~ HLDm. That is, as the total amount of charges held, (m · Q ′ _B1 ) To (m · Q ' _A1 (M + 1) total charge amounts up to () can be held.
[0090]
FIG. 20 is a diagram showing the relationship between the number of input states Z and the normalized floating gate potential Ufg in the νMOS inverter circuit 1900 of FIG. In FIG. 20, line [m] has a total charge amount of (m · Q ′. _A1 ) Represents the relationship between Ufg and Z, and line [m−1] is ((m−1) · Q ′. _A1 + Q ' _B1 The line [m-2] is the same, and the line [2] is (2 · Q ′ _A1 + (M-2) · Q ' _B1 The same applies to line [1] and line [0].
[0091]
At this time, each of line [m], line [m-1], line [m-2],..., Line [2], line [1], line [0] is Ufg = (1/2 ) And the Z coordinate of the intersection is Z _m , Z _m-1 , Z _m-2 ... Z ₂ , Z ₁ , Z ₀ It becomes. The νMOS inverter circuit 1900 has (m + 1) settable threshold values when all of these values do not overlap each other and become a value between certain integers Z and Z + 1.
[0092]
Further, the switch SW2 in FIG. ₁ ~ SW2m is connected, switch SW1 ₁ ~ When (m + 1) threshold values are set according to the potentials input from the m terminals from the control variable terminals input2 [1] to input2 [m] during initialization when SW1m is in the cut-off state One threshold is selected from the switch SW2 ₁ ~ SW2m is cut off, switch SW1 ₁ When the switch SW1m is in a connected state, the selected one threshold value is held in a nonvolatile manner.
[0093]
Embodiment 7 Integrated Function Function Reconfigurable Integrated Circuit
FIG. 21 shows a function function reconfigurable integrated circuit capable of realizing an arbitrary two-input variable symmetric function using a variable threshold threshold element circuit of two input variables capable of holding the threshold value in a non-volatile manner in a multistage configuration. It is a figure showing the structure of (2 input variable variable function circuit). The two-input variable variable function circuit 2100 has input variable terminals input1 [1] and input1 [2], and has the same circuit configuration as the νMOS inverter circuit 1600 shown in FIG. 16, FTE [1], FTE [2]. , FTE [3], and input2 [1], input2 [2], input2 [3] as terminals for control variables input to the FTE [1], FTE [2], and FTE [3] at the time of initialization. Threshold data holding circuit HLD in FTE [1], FTE [2], FTE [3] ₁ , HLD ₂ , HLD _Three Has a control terminal ctl1 for switching between initialization (threshold setting period) and function execution (threshold holding period).
[0094]
Note that the νMOS inverter circuit 2100 has buffer circuits BF [1], BF [2], and BF [3] at the subsequent stage of FTE [1], FTE [2], and FTE [3]. The buffer circuits BF [1], BF [2], and BF [3] amplify and shape the output potential of the FTE [1], FTE [2], and FTE [3]. The input variable terminals input1 [1] and input1 [2] have delay time control circuits DEL [1] and DEL [2] in front of the terminals capacitively coupled to the floating gate FG [S].
[0095]
By having the delay time control circuits DEL [1] and DEL [2], signals input from the input variable terminals input1 [1] and input1 [2] to the terminals capacitively coupled to the floating gate FG [S]; A signal input to a terminal capacitively coupled to the floating gate FG [S] via the FTE [1], FTE [2], FTE [3] and the buffer circuit BF [1], BF [2], BF [3]. It is possible to reduce the difference in signal delay time from By reducing the signal delay time difference, it is possible to avoid a hazard that occurs when a plurality of signals change simultaneously in the multi-input combinational circuit.
[0096]
Input variables from input1 [1] and input1 [2] and output signals from FTE [1], FTE [2] and FTE [3] are capacitively coupled to the floating gate FG [S] by a paraelectric capacitor. Input to the terminal. At the subsequent stage of the floating gate FG [S], there is a νMOS inverter INV [S] having the floating gate FG [S] as an input gate. The output of the νMOS inverter circuit INV [S] ] Is then output.
[0097]
[Operation]
In FTE [1], FTE [2], and FTE [3], the threshold data holding circuit is HLD. ₁ ˜HLDm is determined by the initial setting method described above, Q ′ _A1 And Q ' _B1 The charge amount of either one or the similar charge amount is retained. Further, according to the circuit configuration and method for threshold adjustment described above, the threshold value of FTE [1] is set to either the region where the input state number Z is Z <0 or the region where 0 <Z <1. The threshold value of FTE [2] is set in one of the areas 0 <Z <1 or 1 <Z <2, and the threshold value of FTE [3] is 1 <Z <2 or Z> 2 is set in one of the regions.
[0098]
In addition, in FTE [1], FTE [2], and FTE [3], input variable terminals input1 [1], input1 [2] and floating gates FG [1], FG [2], FG [3] It is assumed that the capacitance values of the paraelectric capacitors are all equal to each other, and the capacitance values of the paraelectric capacitors that are capacitively coupled to the floating gate FG [S] are all equal to each other.
[0099]
FIG. 22 is a diagram showing a typical variable threshold threshold element circuit network that logically describes the two-input variable variable function circuit 2100 shown in FIG. It is assumed that the variable threshold threshold element circuits FTE [1], FTE [2], and FTE [3] in FIG. 22 are all negative output type circuits. That is, when the sum of products of the input variable and the weight coefficient is larger than the threshold value, a logical value “0” is output, and when the sum is smaller, a logical value “1” is output. In addition, the weighting factor for the input variable is set to 1 for simplification.
[0100]
The FTE [1] in FIG. 22 can selectively hold one of the threshold values of −0.5 or +0.5 depending on the signal input from the control variable terminal input2 [1], and the FTE [2] is controlled. A threshold value of either 0.5 or +1.5 can be selected and held by a signal input from the variable input terminal input2 [2], and FTE [3] is input from the control variable terminal input2 [3]. Depending on the signal, either the threshold value of 1.5 or 2.5 can be selected and held, and the STE threshold value is set to 2.5.
[0101]
Further, as threshold values of FTE [1], FTE [2], and FTE [3], a logical value “1” is set from control variable terminals input2 [1], input2 [2], and input2 [3] at the initial setting. A large value is selected when input, and a small value is selected when a logical value “0” is input.
[0102]
Assume that 0.5, 0.5, and 2.5 are selected and held as threshold values for FTE [1], FTE [2], and FTE [3], respectively. For an input state number of 0, the outputs of FTE [1], FTE [2], FTE [3] are logical values “1”, “1”, “1”, and the product-sum value of the STE input is 3 The output is a logical value “0”. For the number of input states 1, the outputs of FTE [1], FTE [2], FTE [3] are logical values “0”, “0”, “1”, and the product-sum value of the STE input is 2 The output is a logical value “1”. For the number of input states 2, the outputs of FTE [1], FTE [2], FTE [3] are logical values “0”, “0”, “1”, and the product-sum value of the STE input is 3 The output is a logical value “0”.
[0103]
In this way, by setting the signals input from the control variable terminals input2 [1], input2 [2], input2 [3] to logical values “1”, “0”, “1”, XOR (Exclusive-OR ) Can be realized. Similarly to the above, when the logical value of the signal input from the control variable terminals input2 [1], input2 [2], input2 [3] is (0, 0, 0), the function 1 is set to (1, 0 , 0), XNOR for (0, 1, 0), AND for (1, 1, 0), NAND for (0, 0, 1), (0 , 1, 1), NOR can be realized, and (1, 1, 1) can realize function 0.
[0104]
As described above, in this two-input variable variable function circuit 2100, an arbitrary symmetric function is realized by the charge amount corresponding to the control variable value held in FTE [1], [2], [3]. Is possible. This function is the threshold data holding circuit HLD. ₁ Since the ferroelectric capacitor Cp is used for .about.HLDm, it is held in a nonvolatile manner. Thereby, the problem of malfunction over time can be solved, and the two-input variable variable function circuit 2100 can be used stably for a long period of time.
[0105]
In the seventh embodiment, two input variables are used. However, the same configuration can be applied to an arbitrary natural number k. An arbitrary logic function can be realized by changing the value of the weighting coefficient and appropriately increasing the number of first-stage FTEs in the two-stage logic circuit.
[0106]
【The invention's effect】
As is apparent from the above description, according to the variable threshold threshold element circuit of the present invention, the control for controlling the threshold value is performed via the series connection circuit of the ferroelectric capacitor and the paraelectric capacitor. Since one or more control variable terminals that propagate the variable are coupled to the gate electrode of the threshold element, the threshold value is held in a nonvolatile manner by the amount of charge held in the ferroelectric capacitor in a non-volatile manner, and malfunctions with time It becomes possible to solve the problem.
[0107]
In addition, by configuring a function function reconfigurable integrated circuit using the variable threshold threshold element circuit of the present invention, the function can be reconfigured at high speed, and the function can be held in a nonvolatile manner. This makes it possible to use an integrated circuit having a reconfigurable interfunction function for a long period of time.
[0108]
Functional function reconfigurable integrated circuits can be applied not only as prototypes for special-purpose LSIs, but also with evolved hardware and systems that adaptively change function functions according to input / output signals even after manufacturing. There are a wide range of application fields such as application to a reconfigurable computing system capable of switching function functions even during operation and using hardware resources with high efficiency. As described above, when the function is dynamically changed during operation of the system or the function is changed in accordance with the input / output signal, it is desirable that the function function is rewritten as fast as possible. Further, it is desirable that the function function once stored can be retained until an erase or write command is received, and the state can be retained even after the power is turned off. The functional function reconfigurable integrated circuit of the present invention can meet such a demand.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a ferroelectric capacitor used in a ferroelectric memory.
FIG. 2 is a diagram illustrating a relationship between a voltage V and a charge amount Q when a voltage V is applied between terminals of a ferroelectric capacitor.
FIG. 3 is a circuit diagram showing a field effect transistor having a MFMIS type ferroelectric capacitor disclosed in Document 5. FIG.
4 is a circuit diagram showing a field effect transistor having a MFMIS type ferroelectric capacitor disclosed in Document 6. FIG.
FIG. 5 is a circuit diagram showing a field effect transistor having a MFMIS type ferroelectric capacitor disclosed in Document 7. FIG.
FIG. 6 is a circuit diagram showing an MFMIS field effect transistor used in the embodiment of the present invention.
FIG. 7 is a circuit diagram of a capacitively coupled input field effect transistor showing one embodiment of a variable threshold threshold element circuit of the present invention.
FIG. 8 is a circuit configuration diagram showing a basic configuration of a νMOS inverter circuit using this capacitively coupled input type field effect transistor.
FIG. 9 is a circuit diagram of a capacitively coupled input field effect transistor having a switch.
FIG. 10 is a circuit configuration diagram showing a basic configuration of a νMOS inverter circuit using a capacitively coupled input field effect transistor having this switch.
11 is a circuit diagram showing another configuration example of a nonlinear circuit that performs threshold processing in the νMOS inverter circuit shown in FIG. 10;
12 is a circuit diagram showing another configuration example of a nonlinear circuit that performs threshold processing in the νMOS inverter circuit shown in FIG. 10;
FIG. 13 is a diagram showing a relationship between a charge amount Qfe appearing at one terminal of a ferroelectric capacitor and a voltage (Vfe1−Vfe2) at both ends sandwiching the ferroelectric capacitor.
14 is a diagram showing the relationship between the potential Vfg of the floating gate in the νMOS inverter circuit shown in FIG. 10, the product sum of the potential Vi inputted to the input variable terminal, and the capacitance value Ci.
15 is a diagram illustrating the relationship between the number of input states Z and the normalized floating gate potential in the νMOS inverter circuit illustrated in FIG.
FIG. 16 is a diagram illustrating a νMOS inverter circuit to which a terminal for supplying a fixed potential is added.
17 is a diagram showing the relationship between the number of input states Z and the normalized floating gate potential Ufg in the νMOS inverter circuit shown in FIG.
FIG. 18 is a diagram illustrating a specific circuit of a threshold data holding circuit.
FIG. 19 is a block diagram of a k-input variable νMOS inverter circuit capable of holding one threshold selected from a plurality of settable thresholds in a nonvolatile manner.
20 is a diagram showing the relationship between the number of input states Z and the normalized floating gate potential Ufg in the νMOS inverter circuit shown in FIG. 19;
FIG. 21 is a functional reconfigurable integrated circuit capable of realizing an arbitrary two-input variable symmetric function using a variable-threshold threshold element circuit of a two-input variable capable of holding a threshold in a non-volatile manner in a multistage configuration. It is a figure showing the structure of (2 input variable variable function circuit).
FIG. 22 is a diagram showing a typical threshold element circuit network in which the two-input variable variable function circuit is logically described.
FIG. 23 is a circuit diagram showing a conventional k-input variable νMOS inverter circuit having a variable threshold function.
FIG. 24 is a diagram showing a typical circuit configuration of a k-input variable νMOS inverter circuit having a conventional circuit state holding function;
FIG. 25 is a diagram illustrating an example (two-input variable variable function circuit) of a functional function reconfigurable integrated circuit using the νMOS inverter circuit illustrated in FIG. 24;
[Explanation of symbols]
700: capacitively coupled input type field effect transistor, 701: field effect transistor, input1 [1] to input1 [k] ... input variable terminal, input2 [1] to input2 [m] ... control variable terminal, 702 ... gate electrode 703 ₁ ˜703k, paraelectric capacity, 704 ₁ ˜704m... Threshold data holding circuit, 705 ₁ ~ 705m ... Paraelectric capacity, 706 ₁ ˜706 m Ferroelectric capacity, 800 νMOS inverter circuit, HLD ₁ ~ HLDm ... Threshold data holding circuit, C ₁ ~ Ck, C _v1 ~ C _vm ... paraelectric capacitance, C _p1 ~ C _pm ... Ferroelectric capacity, FG ... floating gate, INV ... νMOS inverter, Q1 ... p-channel field effect transistor, Q2 ... n-channel field effect transistor, 900 ... νMOS inverter circuit, 901 ... field effect transistor, 902 ... gate electrode, 903 ₁ ~ 903k ... Paraelectric capacity, 904 ₁ ... 904 m... Threshold data holding circuit, 905 ₁ ~ 905m ... Paraelectric capacity, 906 ₁ ˜906 m. Ferroelectric capacity, 907 ₁ ~ 907m ... the second switch, 908 ₁ ... 908 m... 1st switch, 2100... 2 input variable variable function circuit, ctl1, ctl2... State control terminal, FTE [1] to FTE [3]. Inverter circuit, FG [1] to FG [3], FG [S] ... floating gate, BF [1] to BF [3], BF [S] ... buffer circuit, DEL [1] to DEL [2] ... delay Control circuit, INV [1] to INV [3], INV [S]... ΝMOS inverter.

Claims (11)

A threshold element that has an electrically floating gate electrode and operates when a state quantity of an input variable given to the gate electrode exceeds a set threshold value;
First to kth (k> 1) input variable terminals that are coupled to the gate electrode of the threshold element via a paraelectric capacitor and propagate the input variable;
One or more control variable terminals that are coupled to the gate electrode of the threshold element via a serial connection circuit of a ferroelectric capacitor and a paraelectric capacitor and propagate a control variable that controls the threshold value. A variable threshold threshold element circuit characterized by that. The variable threshold threshold device circuit of claim 1, wherein
One end of a paraelectric capacitor in the series connection circuit is connected to the gate electrode,
The other end of this paraelectric capacitor is connected to one end of the ferroelectric capacitor,
A first switch is connected between one end and the other end of the ferroelectric capacitor;
2. A variable threshold threshold element circuit, wherein a second switch is connected between the other end of the ferroelectric capacitor and the control variable terminal. The variable threshold threshold element circuit of claim 2 wherein:
The variable threshold threshold element circuit, wherein the first switch and the second switch are constituted by field effect transistors. In the variable threshold threshold element circuit according to any one of claims 1 to 3,
The threshold element is a field effect transistor;
A variable threshold threshold element circuit, wherein either one of a source terminal and a drain terminal of the field effect transistor is connected to a circuit having an element that is an electrical load as a constituent element. The variable threshold threshold device circuit of claim 4, wherein
A variable threshold threshold element circuit, wherein the electrically load element is a resistor. The variable threshold threshold device circuit of claim 4, wherein
2. The variable threshold threshold element circuit according to claim 1, wherein the electrically loaded element is a field effect transistor that transports charges having a polarity opposite to that of the field effect transistor. In the variable threshold threshold element circuit according to any one of claims 1 to 3,
The threshold element is an inverter circuit including a first field-effect transistor and a second field-effect transistor that transports electric charges having a polarity opposite to that of the first field-effect transistor. A characteristic variable threshold threshold element circuit. In a function-function reconfigurable integrated circuit configured by connecting multiple stages of variable threshold threshold element circuits,
8. The function function re-actuating method, wherein at least one of the variable threshold threshold element circuits connected in multiple stages is the variable threshold threshold element circuit according to any one of claims 1 to 7. Configurable integrated circuit. In a function-function reconfigurable integrated circuit configured by connecting multiple stages of variable threshold threshold element circuits,
The first stage variable threshold threshold element circuit is configured by a plurality of variable threshold threshold element circuits,
A function function reconfiguration characterized in that at least one of the first-stage variable threshold threshold element circuits is the variable threshold threshold element circuit according to any one of claims 1 to 7. Possible integrated circuit. A circuit state holding method applied to the variable threshold element circuit according to claim 1,
A first step of inputting a control variable from the control variable terminal;
A second step of inputting an input variable from the input variable terminal;
A circuit state holding method comprising: a third step of removing the control variable input to the control variable terminal after the second step or between the first step and the second step. . A circuit state holding method applied to the variable threshold threshold element circuit according to claim 2,
A first step in which the first switch is turned off and the second switch is turned on;
After this first step, a second step of inputting a control variable from the control variable terminal and an input variable from the input variable terminal;
After the second step, a circuit state holding method comprising: a third step of putting the second switch into a cut-off state and bringing the first switch into a conductive state.

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