JP3578749B2 - Semiconductor device - Google Patents

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が成立する。
【００９０】
図２は、強誘電体膜８の残留分極の電圧依存性（ヒステリシスループ）を示す図である。なお、本実施形態においては、強誘電体膜４において半導体基板側に正の電荷が生じるような分極を正の分極とする。図２から、強誘電体膜に抗電圧＋Ｖｃ又は−Ｖｃが印加されたときに、分極が反転することがわかる。また、印加電圧を０に戻したときの残留分極は、＋Ｐｒ又は−Ｐｒとなる。
【００９１】
次に、各入力部５の容量Ｃ１ 〜Ｃｎ と、学習記憶部−フローティングゲート間の実効容量ＣＭ と、フローティングゲート−半導体基板間の容量Ｃ０ とを調整することにより、ＮＭＩＳＦＥＴ１の閾値電圧ＶＴＨと、強誘電体膜８の抗電圧Ｖｃとがほぼ等しくなるように素子を設計する。ｎ個の信号入力部５の入力値の合計がある値になると、フローティングゲート４の電位ＶＦ がＮＭＩＳＦＥＴ１の閾値電圧ＶＴＨを越え、ＮＭＩＳＦＥＴ１はＯＮとなり、ソース端子２とドレイン端子３との間に電流が流れ、導通状態となる。この時、ソース端子２とドレイン端子３との間の抵抗は負荷抵抗素子９よりも小さくなり、出力端子１０の出力電圧はほとんど０Ｖとなる。一方、強誘電体膜８の抗電圧ＶｃはＮＭＩＳＦＥＴ１の閾値電圧ＶＴＨとほぼ等しく設計されているため、ＮＭＩＳＦＥＴ１がＯＮすると同時に、強誘電体膜８の分極は＋ＱＭ から−ＱＭ に反転し、−２ＱＭ だけ変化する。
【００９２】
以上の作用について、図１に示す回路と図３に示す等価回路図を参照しながら説明する。ただし、前述の通り、ゲート絶縁膜６はフローティングゲート４をゲート電極とするＮＭＩＳＦＥＴのゲート絶縁膜を示す。このＮＭＩＳＦＥＴ１の閾値電圧ＶＴＨは、強誘電体膜８の抗電圧Ｖｃとほぼ等しく設計されており、フローティングゲート４の電圧が正方向にＶｃを越えるとＮＭＩＳＦＥＴ１はＯＮとなり、それ以外はＯＦＦとなる。
【００９３】
信号入力部５にいろいろな電圧が印加されると、フローティングゲート４の電圧は前述の式（１）で表されるＶＦ となる。前述の通り、フローティングゲート４をゲート電極とするＮＭＩＳＦＥＴ１の閾値電圧ＶＴＨは強誘電体膜８の抗電圧Ｖｃとほぼ等しく設計されている。よって、信号入力部５に全部０Ｖの状態からいろいろな正の電圧が印加されて、フローティングゲート４の電圧が閾値電圧ＶＴＨを越えると、ＮＭＩＳＦＥＴ１がＯＮする。それと同時に、強誘電体膜８の両端には抗電圧Ｖｃを越える電圧が印加され、強誘電体膜８の分極は反転を開始する。信号入力部５の電圧が再度全部０Ｖに戻ると、強誘電体膜８の分極は結局＋ＱＭ から−ＱＭ に反転したことになり、−２ＱＭ だけ変化する。なお、ＱＭ とは、図２に示すＰｒに強誘電体膜の面積を乗じたものである。このとき、フローティングゲート４の電圧は以上の電圧操作を行なう前と比較して、２ＱＭ ／（Ｃ１＋Ｃ２＋…＋Ｃｎ＋ＣＭ＋Ｃ０）だけ負の電圧になる。
【００９４】
よって、次にＮＭＩＳＦＥＴ１がＯＮするためには、フローティングゲート４の電圧ＶＦ が初期状態よりも２ＱＭ ／（Ｃ１＋Ｃ２＋…＋Ｃｎ＋ＣＭ＋Ｃ０ ）だけ大きくなるような電圧を信号入力部５に印加する必要がある。これは、言い換えれば、強誘電体膜８の残留分極が、ＮＭＩＳＦＥＴ１のＯＮしたことを学習記憶し、負の方向に抑制していることと同じになる。よって、図１に示す回路を１つの人工ニューロンとして考えると、本実施形態を用いれば、人工ニューロンが「１」もしくは「０」を出力した情報を学習記憶することが可能となる。この場合、ｎ個の信号入力部５の電圧はアナログ値でも、ＨもしくはＬのデジタル値でもどちらでもよい。
【００９５】
図４は、図１に示す回路において、２つの信号入力部５を設けた場合の動作波形例を示す図である。電源電圧ＶＤＤは５Ｖとし、学習記憶部７の電圧端子７ａの電圧は０Ｖとしている。２つの信号入力部５の電圧Ｖ１，Ｖ２を同時に０Ｖから５Ｖにすると、図４に示すように、出力端子１０の電圧ＶＯＵＴ は５Ｖから約０．５Ｖになる。さらに、２つの信号入力部５の電圧Ｖ１，Ｖ２を同時に０Ｖにした後、再度、同時に５Ｖにすると、出力電圧ＶＯＵＴ は５Ｖから約１．４Ｖになる。すなわち、１回目の入力時に約０．５Ｖになったのに対し、２回目の入力時は約１．４Ｖにまでしか降下しない。これは、ＮＭＩＳＦＥＴ１がＯＮしにくくなっていることを示しており、強誘電体膜１０８の残留分極が、ＮＭＩＳＦＥＴ１のＯＮしたことを学習記憶し、抑制していることと同じになる。
【００９６】
さらに、学習記憶部７の分極用電極７ｂに、強誘電体膜８に−Ｖｃ以上の電圧が印加されるような正の電圧を印加すると、強誘電体膜８の残留分極は−ＱＭ から＋ＱＭ へ反転して、＋２ＱＭ だけ変化するので、初期状態へ戻る。分極用電極７ｂにもう少し小さな電圧を印加すると、電圧に応じて減少する強誘電体膜８の分極量が変化する。これは、ニューロンの学習記憶情報をリセットする動作と言える。よって、本実施形態を用いれば、ＮＭＩＳＦＥＴ１の構造に関係なく、学習記憶部７の電圧を制御するだけで簡便にニューロンの学習記憶情報をリセットする動作が可能となる。本実施形態を用いれば、各ＭＩＳ型ニューロン素子の基板部分を電気的に絶縁したり、非常に複雑な制御回路を設計したりする必要がない。
【００９７】
よって、本実施形態により、各ニューロンの出力状況を簡便に学習記憶でき、かつその学習記憶を容易にリセットもしくは弱める機構を組み込んだニューロン素子として機能する半導体装置を簡便な方法で提供することができる。
【００９８】
−第１の変形例−
本実施形態のＭＩＳ型ニューロン素子は、学習記憶情報を保持する学習記憶部７を１つしか備えていないが、複数個の学習記憶部７を備えていてもよい。
【００９９】
図５は、複数個の学習記憶部を複数設けた第１の実施形態の第１の変形例に係る半導体装置であるニューロン素子の構成を示す模式図である。この変形例に係るニューロン素子は、分極用電圧を受ける電圧端子７Ａａと、フローティングゲート４に強誘電体膜８Ａを挟んで対向する分極用電極７Ａｂとを有する学習記憶部７Ａに加えて、分極用電圧を受ける電圧端子７Ｂａと、フローティングゲート４に強誘電体膜８Ｂを挟んで対向する分極用電極７Ｂｂとを有する学習記憶部７Ｂを備えている。その他の構成は、図１に示す構成と同じである。
【０１００】
この変形例の場合、２つの学習記憶部７Ａ，７Ｂとフローティングゲート４との間に介在する強誘電体膜８Ａ，８Ｂとの容量の比率は同じでもよいし、異なっていてもよい。また、この変形例では、学習記憶部７Ａ，７Ｂ及び強誘電体膜８Ａ，８Ｂをフローティングゲート４の両端部に配置したが、学習記憶部７Ａ，７Ｂ及び強誘電体膜８Ａ，８Ｂの配置部位は、学習記憶部７Ａ，７Ｂの機能に影響を与えない。
【０１０１】
この変形例によると、学習記憶部７Ａと学習記憶部７Ｂとを互いに独立な電圧で制御することで、分極の制御を多段に行なうことができ、さらに高精度の又は多様な学習記憶を実現することができる。
【０１０２】
よって、この変形例によっても、各ニューロンの出力状況を簡便に学習記憶でき、かつその学習記憶を容易にリセットもしくは弱める機構を組み込んだニューロン素子として機能する半導体装置を簡便な方法で提供することができる。
【０１０３】
−第２の変形例−
本実施形態では、ＮＭＩＳＦＥＴ１と負荷抵抗素子９との組み合わせで回路を構築したが、負荷抵抗素子９の代わりに、ｐ型ＭＩＳトランジスタを用いることもできる。
【０１０４】
図６は、第１の実施形態の第２の変形例に係る半導体装置であるニューロン素子の構成を示す模式図である。この変形例に係るニューロン素子は、図１に示す構造における負荷抵抗素子９に代えて、ＮＭＩＳＦＥＴ１に直列に接続されるｐチャネル型ＭＩＳトランジスタ１１（ＰＭＩＳＦＥＴ１１）を備えている。そして、ＰＭＩＳＦＥＴ１１のソース端子１２は電源電圧ＶＤＤを供給する電源電圧供給部に接続され、ＰＭＩＳＦＥＴ１１のドレイン端子１３は、ＮＭＩＳＦＥＴ１のドレイン端子３に接続されている。出力端子１０は、ＮＭＩＳＦＥＴ１のドレイン端子３及びＰＭＩＳＦＥＴ１１のドレイン端子１３に接続されている。また、フローティングゲート４は、ＮＭＩＳＦＥＴ１及びＰＭＩＳＦＥＴ１１に跨って設けられており、フローティングゲート４とＰＭＩＳＦＥＴ１１の基板領域との間には、常誘電体膜１６が介在している。
【０１０５】
この変形例によると、前述のＮＭＩＳＦＥＴと負荷抵抗素子との組み合わせ回路で説明した中で、フローティングゲートと半導体基板の間の容量をＣ０ としたのに対して、ｐ型ＭＩＳＦＥＴ１１を用いる場合は、ＮＭＩＳＦＥＴ１とＰＭＩＳＦＥＴ１１とに跨っているフローティングゲート４と半導体基板との間の容量の和をＣ０ とすれば、上記式（１）と同様の関係が成立する。
【０１０６】
（第２の実施形態）
第１の実施形態では、ＮＭＩＳＦＥＴ１の閾値電圧ＶＴＨと、強誘電体膜８の抗電圧Ｖｃとをほぼ等しくなるよう素子を設計したが、第１の実施形態とは異なる方式で素子設計をすることもできる。本実施形態においては、第１の実施形態と同じ回路構成を採りながら、異なる方式で設計した素子について、図１と図７とを参照しながら説明する。すなわち、本実施形態のニューロン素子の回路構成は、図１に示す通りである。
【０１０７】
図７は、第１の実施形態とは異なる方式を採用した時の強誘電体膜８の残留分極の電圧依存性（ヒステリシスループ）を示す図である。例えば、ＮＭＩＳＦＥＴ１の閾値電圧ＶＴＨが強誘電体膜８の抗電圧Ｖｃよりも小さく、ｎ個の信号入力部５の入力電圧が最大値を取った時のフローティングゲート４の電位ＶＦ が抗電圧Ｖｃ以下になるよう、素子の設計を行なうことができる。ｎ個の信号入力部５とフローティングゲート４との間に介在する各常誘電体膜５ｃの容量はすべて同じ容量でもよいし、重み付けのために互いに異なる容量にしてもよい。
【０１０８】
図１に示すニューロン素子において、ｎ個の信号入力部５の全ての入力電圧が最大値を取った時、フローティングゲート４の電位ＶＦ はＮＭＩＳＦＥＴ１の閾値電圧ＶＴＨよりも大きくなるため、ＮＭＩＳＦＥＴ１はＯＮとなり、ソース端子２とドレイン端子３との間に電流が流れ、ＮＭＩＳＦＥＴ１は導通状態となる。この時、ソース端子２とドレイン端子３との間の抵抗は負荷抵抗素子９よりも小さくなり、出力端子１０の出力電圧はほとんど０Ｖとなる。一方、強誘電体膜８の抗電圧ＶｃはＮＭＩＳＦＥＴ１の閾値電圧ＶＴＨよりも大きく設計されているため、ＮＭＩＳＦＥＴ１がＯＮしても、強誘電体膜８の分極状態は少し変化するが、大きくは変わらない。
【０１０９】
図７において、ｎ個の信号入力部５の全ての入力電圧が０Ｖの時はフローティングゲート４の電位ＶＦ も０Ｖであり、強誘電体膜８の残留分極は初期化後の最初の状態であるＡ点にある。この後、ｎ個の信号入力部５の全ての入力電圧が最大値を取った時でも、フローティングゲート４の電位ＶＦ は強誘電体膜８の抗電圧Ｖｃより小さいので、分極状態はＣ点に移動するのみであり、ｎ個の信号入力部５の全ての入力電圧が０に戻った時は、分極状態はＢ点に移動する。よって、残留分極はＡ点とＢ点の残留分極差Ｘだけ変化する。このように、残留分極が小さくなるので、ＮＭＩＳＦＥＴ１がＯＮしにくくなる方向に変化したことになる。よって、次にＮＭＩＳＦＥＴ１をＯＮさせるためには、ＶＦ はＸ／（Ｃ１＋Ｃ２＋．．．＋Ｃｎ＋ＣＭ＋Ｃ０）だけ大きいことが必要となり、言い換えれば、強誘電体膜８の残留分極が、ＮＭＩＳＦＥＴ１のＯＮしたことを学習記憶し、再度ＮＭＩＳＦＥＴ１がＯＮするのが抑制されることになる。
【０１１０】
ｎ個の信号入力部５のうち，いくつかの信号入力部５が最高電圧を取らない場合は、残留分極は、フローティングゲート４の電位ＶＦ に応じてＡ点とＣ点との間のどこかに位置する。また、全ての信号入力部５の電圧を０Ｖに戻した時は、残留分極はＡ点とＢ点との間のどこかに位置する。フローティングゲート４の電位ＶＦ が徐々に大きくなるように、ｎ個の信号入力部５の全ての電圧が変化する場合は、全ての信号入力部５の電圧を０Ｖに戻した時の残留分極が徐々に小さくなるように変化する。これは、学習強化が行われていることと同じになる。
【０１１１】
一方、フローティングゲート４の電位ＶＦ がある値を取った後、徐々に小さくようにｎ個の信号入力部５の全ての電圧が変化する場合は、全ての信号入力部５の電圧を０Ｖに戻した時の残留分極は変化せず、学習強化はされない。
【０１１２】
さらに高度の学習強化を行う場合は、学習記憶部７にフローティングゲート４に対して負の電圧を印加し、強誘電体膜８の両端に抗電圧Ｖｃ以上の電圧が印加されるようにする。印加時間は、強誘電体膜８の分極反転が生じるのに要する時間以上であれば、任意の時間でよい。例えば、強誘電体膜８の両端に抗電圧Ｖｃ以上の電圧が印加される時間が１００ｎｓ程度のパルスでもよい。この時、図７に示すヒステリシス特性において、強誘電体膜８の両端に印加されている電圧は、パルス電圧の印加前は０Ｖなので、残留分極は、Ａ点とＢ点との間のどこかに位置する。パルス印加中は、強誘電体膜８の両端に印加されている電圧がＶｃより大きくなるため、分極状態はＤ点に移る。パルス印加後は、印加電圧が０Ｖに戻るため、分極状態はＥ点に移る。当初、分極状態がＡ点にあったとすると、Ｙだけ残留分極が変化し、正から負の方向に大きく分極する。よって、ｎ個の信号入力部５の入力電圧が、より大きくなければＮＭＩＳＦＥＴ１がＯＮしないようになる。これは、学習記憶部７に印加したパルスによりＮＭＩＳＦＥＴ１がさらにＯＮしにくくなることを意味しており、負の学習が強化され、大きな抑制がされたことと同値である。
【０１１３】
続いて、正の学習を行う機能について説明する。先に説明したのと同様の手順で、学習記憶部７に電圧を印加するが、この場合は、学習記憶部７にフローティングゲート４に対して正の電圧を印加し、強誘電体膜８の両端に抗電圧Ｖｃ以上の電圧が印加されるようにする。印加時間は、強誘電体膜８の分極反転が生じるのに要する時間以上であれば、任意に設定することができる。例えば、強誘電体膜８の両端にＶｃ以上の電圧が印加される時間が１００ｎｓ程度のパルス信号を強誘電体膜８の両端に印加してもよい。この時、図７に示すヒステリシス特性において、強誘電体膜８の両端に印加されている電圧は、パルス電圧の印加前は印加電圧が０Ｖなので、分極状態はＥ点に位置する。パルス信号の印加中は、強誘電体膜８の両端に印加されている電圧が抗電圧−Ｖｃを越えるため、分極状態はＦ点へ移る。また、パルス信号の印加後は、印加電圧が０Ｖに戻るため、分極状態はＡ点へ移る。当初Ｅ点にあった分極状態がＡ点に移ったのであるから、Ｙだけ残留分極が変化し、負から正の方向に大きく分極する。よって、ｎ個の信号入力部５の入力電圧がより小さくてもＮＭＩＳＦＥＴ１がＯＮするようになる。これは、学習記憶部７に印加したパルスによりＮＭＩＳＦＥＴ１がさらにＯＮしやすくなることを意味しており、正の学習がされたことになる。
【０１１４】
また、この時のパルス信号の電圧を強誘電体膜８の両端に抗電圧Ｖｃ未満の電圧が印加されるように少し小さく設定すると、パルス信号の印加前にＥ点にあった分極状態は、パルス信号の印加中はＧ点へ移り、パルス信号の印加後は、印加電圧が０Ｖに戻るため、分極状態はＨ点へ移る。当初、Ｅ点にあった分極状態がＨ点へ移ったのであるから、Ｚだけ残留分極が変化し、負の分極が若干減少する。よって、各信号入力部５の入力電圧が若干小さくてもＮＭＩＳＦＥＴ１がＯＮするようになる。これは、学習記憶部７に印加されたパルス信号によりＮＭＩＳＦＥＴ１が少しＯＮしやすくなることを意味しており、正の弱い学習がされたことになる。
【０１１５】
以上のように、本実施形態によると、学習記憶部７に印加する電圧を制御することで、学習の強化や抑制をいろんな割合で行うことができる。本実施形態により、ＮＭＩＳＦＥＴ１に関係なく、学習記憶部７の電圧を制御するだけで簡便にニューロンの学習記憶情報の強化や抑制をいろんな割合で行うことが可能となる。しかも、本実施形態により、各ＭＩＳ型ニューロン素子の基板部分を電気的に絶縁したり、非常に複雑な制御回路を設計したりする必要がない。
【０１１６】
よって、本実施形態を用いれば、各ニューロンの出力状況を簡便に学習記憶でき、かつその学習記憶を容易に強化・抑制する機構を組み込んだニューロン素子を簡便な方法で提供することができる。さらに、このニューロン素子を組み合わせて演算回路を構成することで、ニューロン素子を形成することもできるし、このニューロン素子を用いて学習機能を有する半導体応用機器を実現することもできる。さらに、この半導体応用機器を用いて、認識、判断等の高度なことを行うシステム、いわば人工知能システムを実現することも可能となる。
【０１１７】
なお、本実施形態では、ＮＭＩＳＦＥＴ１と負荷抵抗素子９との組み合わせによって回路を構築したが、第１の実施形態と同様に、負荷抵抗素子９の代わりにｐ型ＭＩＳトランジスタを用いることもできる。
【０１１８】
（第３の実施形態）
図８は、本発明の第３の実施形態に係る半導体装置であるニューロン素子及び制御回路の構成を示す模式図である。
【０１１９】
本実施形態では、第１の実施形態におけるニューロン素子に加えて、制御回路を備えている。本実施形態の制御回路は、出力端子１０に接続され、第１の出力信号Ｖｏｕｔ１を受ける論理回路２１と、論理回路２１に接続され論理回路２１から出力される第２の出力信号Ｖｏｕｔ２を受ける次段の論理回路２２と、各種データを内蔵する評価回路２３と、学習記憶部７に供給するパルス信号を発生するためのパルス信号発生回路２４とを備えている。
【０１２０】
本実施形態におけるＮＭＩＳＦＥＴ１の基本的な構成及び動作は、第１又は第２の実施形態で説明したとおりである。
【０１２１】
出力端子１０から出力される第１の出力信号Ｖｏｕｔ１は、論理回路２１を通った後、第２の出力信号Ｖｏｕｔ２となり、さらに次段の論理回路２２に伝送される。第１の実施形態で説明したように、ｎ個の信号入力部５の入力値の合計がある値になると、フローティングゲート４の電位ＶＦ がＮＭＩＳＦＥＴ１の閾値電圧ＶＴＨを越え、ＮＭＩＳＦＥＴ１はＯＮとなり、ソース端子２とドレイン端子３との間に電流が流れ、導通状態となる。ＮＭＩＳＦＥＴ１がＯＮした時、第１の出力信号Ｖｏｕｔ１は１から０に変化する。
【０１２２】
また、評価回路２３により、第２の出力信号Ｖｏｕｔ２と評価回路２３に格納されている評価用基準値とが比較され、その結果の評価信号Ｓｅｖが論理回路２１にフィードバックされる。評価信号Ｓｅｖは、第２の出力信号Ｓｏｕｔ２が回路全体の信号出力が求める結果に近いかどうかを評価した結果出力される信号であり、評価信号Ｓｅｖは、これを必要とする他のニューロン素子全てに供給することができる。評価信号Ｓｅｖは、例えば、第２の出力信号Ｖｏｕｔ２が求める結果（評価用基準値）と近い場合は正の電圧信号であり、第２の出力信号Ｖｏｕｔ２が求める結果（評価用基準値）と非常にかけ離れた場合は負の電圧信号であり、その中間である場合は０Ｖの信号であるとする。つまり、第１の出力信号Ｖｏｕｔ１を学習強化するか、抑制するかの判断が評価信号Ｓｅｖを用いて論理回路２１で行われる。
【０１２３】
例えば、ＮＭＩＳＦＥＴ１がＯＮして第１の出力信号Ｖｏｕｔ１が０Ｖに近く、評価信号Ｓｅｖが正の電圧信号である場合、第１の出力信号Ｖｏｕｔ１を強化するために、論理回路２１からは正の教師信号Ｓｐｔがパルス信号発生回路２４に供給される。このとき、パルス信号発生回路２４から、第１の出力信号Ｖｏｕｔ１と正の教師信号Ｓｐｔとを受けて、学習記憶部７に供給する学習信号Ｓｌｎとして、学習を強化するための正電圧のパルス信号が出力される。したがって、強誘電体膜８の両端には、負方向の強い電界が印加される。よって、正電圧のパルス信号が印加された後除かれたときには、強誘電体膜８の残留分極は負となり、かつその絶対値が増大することになる。これは、入力部５に正の入力信号を受けたときにＮＭＩＳＦＥＴ１がＯＮしやすくなることを意味している。すなわち、正電圧のパルス信号である学習信号Ｓ ｌｎにより、ＮＭＩＳＦＥＴ１がＯＮしやすくなって、正の学習が強化されたことを意味する。学習信号Ｓｌｎの印加時間は、強誘電体膜８の分極反転が生じるのに要する時間以上であればよい。例えば、学習信号Ｓｌｎは、強誘電体膜８の両端に抗電圧Ｖｃ以上の電圧が印加される時間が１００ｎｓ程度になるようなパルス信号でもよい。
【０１２４】
同様に、ＮＭＩＳＦＥＴ１がＯＦＦであり第１の出力信号Ｖｏｕｔ１が電源電圧に近く、評価信号Ｓｅｖが正の電圧信号である場合、第１の出力信号Ｖｏｕｔ１を強化するために、論理回路２１からは正の教師信号Ｓｐｔがパルス信号発生回路２４に供給される。パルス信号発生回路２４では、第１の出力信号Ｖｏｕｔ１と正の教師信号Ｓｐｔとを受けて、学習記憶部７に供給する学習信号Ｓｌｎとして、学習を強化するための負電圧のパルス信号が出力される。
【０１２５】
一方、ＮＭＩＳＦＥＴ１がＯＮして第１の出力信号Ｖｏｕｔ１が０Ｖに近く、評価信号Ｓｅｖが負の電圧の場合、第１の出力信号Ｖｏｕｔ１を弱めるために、論理回路２１からは負の教師信号Ｓｎｔがパルス信号発生回路２４に供給される。このとき、パルス信号発生回路２４から、第１の出力信号Ｖｏｕｔ１と負の教師信号Ｓｎｔとを受けて、学習記憶部７に供給する学習信号Ｓｌｎとして、学習を弱める（抑制する）ための負電圧のパルス信号が出力される。したがって、強誘電体膜８の両端には、正方向の強い電界が印加される。よって、負電圧のパルス信号が印加された後除かれたときには、強誘電体膜８の残留分極は正となり、かつその絶対値が増大することになる。これは、入力部５に正の入力信号を受けたときにＮＭＩＳＦＥＴ１がＯＮしにくくなることを意味している。すなわち、負電圧のパルス信号である学習信号Ｓ ｌｎにより、ＮＭＩＳＦＥＴ１がＯＮしにくくなって、学習が弱められた（抑制された）ことを意味する。学習信号Ｓｌｎの印加時間は、強誘電体膜８の分極反転が生じるのに要する時間以上であればよい。例えば、学習信号Ｓｌｎは、強誘電体膜８の両端に抗電圧Ｖｃ以上の電圧が印加される時間が１００ｎｓ程度になるようなパルス信号でもよい。
【０１２６】
同様に、ＮＭＩＳＦＥＴ１がＯＦＦであり第１の出力信号Ｖｏｕｔ１が電源電圧に近く、評価信号Ｓｅｖが負の電圧信号である場合、第１の出力信号Ｖｏｕｔ１を弱めるために、論理回路２１からは負の教師信号Ｓｎｔがパルス信号発生回路２４に供給される。パルス信号発生回路２４では、第１の出力信号Ｖｏｕｔ１と負の教師信号Ｓｎｔとを受けて、学習記憶部７に供給する学習信号Ｓｌｎとして、学習を弱めるための正電圧のパルス信号が出力される。
【０１２７】
以上のように、出力端子１０からの出力信号Ｓｏｕｔ１，Ｓｏｕｔ２に応じて、学習信号Ｓｌｎの電圧を制御することで、第２の実施形態と同様に、学習の強化や抑制をいろんな割合で行うことができる。
【０１２８】
なお、評価信号Ｓｅｖが０Ｖの場合は論理回路２１からは、正の教師信号Ｓｐｔも負の教師信号Ｓｎｔも出力しないため、学習信号Ｓｌｎは０Ｖのままであり、学習の強化や抑制は行われない。
【０１２９】
以上述べた通り、学習信号Ｓｌｎとしては正電圧のパルス信号も、負電圧のパルス信号も用いることができる。その際、ＮＭＩＳＦＥＴ１は通常動作モードで使用でき、ＮＭＩＳＦＥＴ１の基板領域の電圧を制御する必要もない。
【０１３０】
よって、本実施形態のニューロン素子によると、複雑な制御回路を用いることなく、簡便に強誘電体膜８を用いた学習の強化・抑制を行うことができる。よって、本実施形態のニューロン素子を多数組み合わせることにより、各ニューロン素子の出力状態を簡便に学習記憶でき、かつ、その学習記憶を容易に強化もしくは弱める機構を組み込んだニューロン素子を簡便な方法で提供することができる。
【０１３１】
なお、本実施形態では、ＮＭＩＳＦＥＴ１と負荷抵抗素子９との組み合わせでニューロン素子の回路を構築したが、第２の実施形態と同様に、負荷抵抗素子９の代わりに、ｐ型ＭＩＳトランジスタを用いることもできる。また、評価信号Ｓｅｖは正の電圧，負の電圧，０Ｖの３種類としたが、評価信号Ｓｅｖの電圧をアナログ値もしくはパルス数などにより諧調調整することにより、学習信号Ｓｌｎの電圧をアナログ的に制御することができ、さらに精度の高い学習強化・抑制を行うことができる。
【０１３２】
（第４の実施形態）
第１〜第３の実施形態では、本発明を主として出力抑制型のニューロン素子に適用した例について説明したが、本実施形態においては、本発明を、主として出力強化型、または出力抑制型と出力強化型との選択が可能なタイプのニューロン素子に適用した例について説明する。
【０１３３】
図９は、本発明の第４の実施形態に係る半導体装置であるニューロン素子の構成を示す模式図である。
【０１３４】
本実施形態のニューロン素子は、ソース端子３２と、ドレイン端子３３と、ゲート絶縁膜３６と、ゲート電極４１とを有するｎチャネル型ＭＩＳトランジスタ（ＮＭＩＳＦＥＴ３１）を備えている。ソース端子３２は、ＮＭＩＳＦＥＴ３１の基板領域と共に接地され、ドレイン端子３３は出力端子４０に接続されている。出力端子４０は、電源電圧ＶＤＤを供給するための電源電圧供給部に負荷抵抗素子３９を介して接続されている。
【０１３５】
また、ＮＭＩＳＦＥＴ３１のゲート電極４１に強誘電体膜３８を挟んで対向するフローティング電極３４が設けられている。そして、フローティング電極３４に容量結合するｎ個の信号入力部３５が設けられている。信号入力部３５は、入力端子３５ａと、入力端子３５ａに接続される入力ゲート電極３５ｂと、入力ゲート電極３５ｂとフローティング電極３４との間に介在する常誘電体膜３５ｃとによって構成されている。つまり、入力ゲート電極３５ｂとフローティング電極３４とは、常誘電体膜３５ｃによって容量結合している。
【０１３６】
入力ゲート電極３５ｂとフローティング電極３４との間の容量は、常誘電体膜３５ｃの材料，厚み及び面積によって定まる。各入力ゲート電極３５ｂとフローティング電極３４との間の容量は、すべて同じであってもよいし、重み付けのためにそれぞれが異なっていてもよい。
【０１３７】
また、分極用電圧を受ける電圧端子３７ａと、フローティング電極３４に常誘電体３７ｃを挟んで対向する電極３７ｂとを有する学習記憶部３７が設けられている。学習記憶部３７の電圧端子３７ａには、通常、０Ｖの一定電圧（接地電圧）が印加される。
【０１３８】
なお、第３の実施形態と同様に、出力端子４０の信号は論理回路（図示せず）へ伝送される。
【０１３９】
ここで、第１の実施形態で説明したように、ｎ個の信号入力部３５の入力値の合計がある値になると、ゲート電極４１の電位ＶＦ がＮＭＩＳＦＥＴ３１の閾値電圧ＶＴＨを越え、ＮＭＩＳＦＥＴ３１はＯＮとなり、ソース端子３２とドレイン端子３３との間に電流が流れ、導通状態となる。ＮＭＩＳＦＥＴ３１がＯＮした時、出力端子４０の電圧は電源電圧ＶＤＤから０に変化する。ゲート電極４１の電位ＶＦ がＮＭＩＳＦＥＴ３１の閾値電圧ＶＴＨになった時に、強誘電体膜３８の両端には抗電圧Ｖｃが印加されるように、強誘電体膜３８の容量と、ＮＭＩＳＦＥＴ３１のゲート容量と、ｎ個の信号入力部３５の各常誘電体膜３５ｃと、学習記憶部３７の常誘電体膜３７ｃの容量とを最適化した設計をしておく。すると、ＮＭＩＳＦＥＴ３１がＯＮすると同時に強誘電体膜３８の分極は−ＱＭから＋ＱＭへ反転し、＋２ＱＭだけ大きくなる。よって、次にＮＭＩＳＦＥＴ３１をＯＮさせるためには、フローティング電極３４の電位ＶＦ は２ＱＭ／（Ｃ１＋Ｃ２＋．．．＋Ｃｎ＋ＣＭ＋Ｃ０）だけ小さくてもよいことになる。これは、言い換えれば、強誘電体膜３８の残留分極が、ＮＭＩＳＦＥＴ３１のＯＮしたことを学習記憶し、出力を強化していることと同じになる。この学習をリセットするためには、学習記憶部３７に信号入力部３５に対して負の電圧を印加すればよい。
【０１４０】
本実施形態では、出力強化型のニューロン素子の構成について説明したが、出力抑制型と出力強化型とを配線もしくはトランジスタを用いて選択する方法もある。
【０１４１】
図１０（ａ）〜（ｃ）は、それぞれ順に、本発明の第４の実施形態の変形例に係る半導体装置であるニューロン素子の切り換え配線前の構成、出力抑制型に配線されたときの構成、出力強化型に配線されたときの構成を示す模式図である。
【０１４２】
図１０（ａ）に示すように、切り換え配線前においては、ＮＭＩＳＦＥＴ３１のゲート電極４１と、フローティングゲート３４と、強誘電体膜３８を挟む２つの電極とは接続されていない。また、学習記憶部３７の電圧端子３７ａと電極３７ｂとも互いに接続されていない。
【０１４３】
１つの方法は、図１０（ｂ）に示すように、強誘電体膜３８を挟む２つの電極と、学習記憶部３７の電圧端子３７ａ，電極３７ｂを接続するように配線する方法である。言い換えると、学習記憶部３７の電圧端子３７ａ中に強誘電体膜３８を介在させるのである。このように接続することにより、第１の実施形態と同様に、電圧端子３７ａに０Ｖの一定電圧を印加すると、学習記憶部３７は学習を弱める負の学習機能を有することになる。
【０１４４】
もう１つの方法は、図１０（ｃ）に示すように、強誘電体膜３８を挟む２つの電極をゲート電極４１とフローティング電極３４とを接続するように配線する方法である。言い換えると、強誘電体膜３８をゲート電極４１とフローティング電極３４との間に介在させるのである。このように接続することにより、第４の実施形態と同様に、電圧端子３７ａに０Ｖの一定電圧を印加すると、学習記憶部３７は学習を強める正の学習機能を有することになる。
【０１４５】
なお、この変形例においては、強誘電体膜３８と、ゲート電極４１，フローティング電極３４及び学習記憶部３７との接続関係を配線によって切り替える構成としたが、配線を施しておいて、各経路にスイッチングトランジスタを介設することにより、図１０（ｂ）又は（ｃ）に示す接続関係に切り替えることも可能である。その場合には、使用の途中で機能を変更することができる。
【０２９２】
【発明の効果】
本発明により、高い学習機能，論理変換機能，荷重制御機能などを有するニューロン素子，電位発生装置，論理変換回路などとして機能する半導体装置の提供をはかることができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係る半導体装置のニューロン素子の回路構成を示す模式図である。
【図２】強誘電体膜の残留分極の電圧依存性（ヒステリシスループ）を示す図である。
【図３】第１の実施形態のニューロン素子のキャパシタ部分のみを取り出したときの等価回路図である。
【図４】図１に示す回路において、２つの信号入力部を設けた場合の動作波形例を示す図である。
【図５】複数個の学習記憶部を複数設けた第１の実施形態の第１の変形例に係る半導体装置であるニューロン素子の構成を示す模式図である。
【図６】第１の実施形態の第２の変形例に係る半導体装置であるニューロン素子の構成を示す模式図である。
【図７】第１の実施形態とは異なる方式を採用した時の強誘電体膜の残留分極の電圧依存性（ヒステリシスループ）を示す図である。
【図８】本発明の第３の実施形態に係る半導体装置であるニューロン素子及び制御回路の構成を示す模式図である。
【図９】本発明の第４の実施形態に係る半導体装置であるニューロン素子の構成を示す模式図である。
【図１０】（ａ）〜（ｃ）は、それぞれ順に、本発明の第４の実施形態の変形例に係る半導体装置であるニューロン素子の切り換え配線前の構成、出力抑制型に配線されたときの構成、出力強化型に配線されたときの構成を示す模式図である。
【図１１】従来の公報に記載されている第２の従来例に係るニューロン素子の等価回路図である。
【図１２】従来例における制御端子に負のパルス信号を加えたときの入力信号に対する各部の電荷量を出力信号の論理値とを表にして示す図である。
【図１３】従来例における制御端子にさらに振幅の大きい負のパルス信号を加えたときの入力信号に対する各部の電荷量を出力信号Ｙの論理値とを表にして示す図である。
【図１４】（ａ），（ｂ）は、それぞれ順に、従来例に係るニューロン素子のフローティングゲートの電位の時間変化を示すタイミングチャート、及び強誘電体膜に印加される電圧の時間変化を示すタイミングチャートである。
【図１５】脳の基本単位の構成を簡略化して示すブロック回路図である。
【図１６】従来例に係るνＭＯＳの構造を簡略化して示す模式図である。
【図１７】特許公報に記載されている従来例のニューロン素子の構成を示す模式図である。
【図１８】特許公報に記載されている従来の強誘電体ゲートトランジスタ構造を示す断面図である。
【図１９】電子が厚さ１０ｎｍの熱酸化シリコン膜をトンネリングする際の印加電圧とトンネル電流の相関を示す図である。
【符号の説明】
１ ＮＭＩＳＦＥＴ
２ ソース端子
３ ドレイン端子
４ フローティングゲート
５ 信号入力部
５ａ 入力端子
５ｂ 入力ゲート電極
５ｃ 常誘電体膜
６ ゲート絶縁膜
７ 学習記憶部
７ａ 電圧端子
７ｂ 分極用電極
８ 強誘電体膜
９ 負荷抵抗素子
１０ 出力端子
１１ ＰＭＩＳＦＥＴ
１２ ソース端子
１３ ドレイン端子[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and particularly to a semiconductor device functioning as a neuron element, a potential generator, a logic conversion circuit, or the like which is an element of an artificial neural network.
[0002]
[Prior art]
2. Description of the Related Art Recent advances in semiconductor integrated circuit technology have been remarkable, and various high-performance logic integrated circuits have been developed in addition to simple memory devices. However, since these logic circuits operate using binary signals, it can be said that the evolution of logic has not progressed since the advent of LSI. In the present semiconductor integrated circuit, such a binary operation can perform a very high-speed operation for a simple numerical calculation, but it is not easy for a human to perform an operation such as pattern recognition or image processing. The disadvantage is that it takes a huge amount of time.
[0003]
On the one hand, research has been conducted to develop a computer that operates like the brain of a living organism, that is, a neural circuit computer (neurocomputer), as an element capable of performing arithmetic processing at which the conventional LSI is not good at high speed. This neurocomputer has a structure in which many neuron elements are connected like a neural circuit.
[0004]
Most conventional neuron elements are manufactured by CMIS devices, and in that case, they did not have a learning function of changing the operation of a circuit by learning. For example, Japanese Patent No. 3122756 describes a MIS-type neuron element in which a number of input sections capacitively coupled to a gate electrode of a MISFET are arranged. This is to perform an operation of adding the product of each signal strength of a plurality of input terminals and the coupling strength by the number of input units using capacitive coupling, but the function of storing the operation result as a learning effect is not provided. I do not have.
[0005]
On the other hand, in recent years, proposals according to a first conventional example for realizing a learning function using remanent polarization of a ferroelectric have been issued. For example, Japanese Patent No. 2929909 describes that in a MIS type neuron element in which a plurality of input sections capacitively coupled to a gate electrode of a MISFET are arranged, all the capacitive insulating films of the input sections are made of a ferroelectric material. ing. Japanese Patent No. 2942088 discloses an MIS-type neuron element in which a plurality of input sections capacitively coupled to a gate electrode of a MISFET are arranged, wherein the gate insulating film of the MISFET on the output side is formed of a ferroelectric material. Have been.
[0006]
In addition, LSIs are developing at an extremely high speed, and miniaturization and high integration of transistors are progressing. However, miniaturization of transistors and huge chip area make it difficult to improve the yield. In addition, the circuit scale becomes very large, and system LSIs for high-mix low-volume production occupy the mainstream, requiring a large number of people and time for designing. For this reason, it is not easy to shorten the development period. As a solution to such a problem, a reconfigurable circuit has attracted attention. A reconfigurable circuit is a circuit that enables rewriting with a change in circuit specifications after manufacturing an LSI. As an example, FPGA (Field Programmable Gate Array), CPLD (Complex Programmable Logic Device), etc. are mentioned. These make it possible to realize a changeable logic circuit by combining basic logic blocks in multiple stages. That is, in the FPGA / CPLD, a switch element or a multiplexer is used as a program element, and the function is determined by a combination of the basic logic circuit with the element. However, in these systems, the area occupied by the redundant circuit in the basic logic block is large, and the wiring becomes long. On the other hand, an element has been proposed in which a program element itself is capable of converting logic using a ferroelectric substance (Naoichi Kawaguchi, Seijin Yoon, Eisuke Tokumitsu: Proceedings of the 61st Annual Conference of the Japan Society of Applied Physics 6a- g-1).
[0007]
Figure11FIG. 2 is an equivalent circuit diagram of a neuron element according to a second conventional example described in the above publication. In this example, a residual signal is generated in a ferroelectric capacitor by a pulse signal, and the residual charge is used to control the potential of a floating gate, thereby realizing a logical conversion circuit between a NOR circuit and a NAND circuit. Is trying.
[0008]
Figure11As shown in (1), this neuron element includes an n-channel MIS transistor (NMISFET 510). Here, the gate electrode of the NMISFET 510 is a floating gate 506 which is not connected to another terminal and is in a floating state. The source is grounded, and the drain is connected to the output terminal 509. The output terminal 509 is connected via a load resistance element 508 to a power supply voltage supply terminal 507 for supplying the power supply voltage VDD.
[0009]
Also, two input terminals 500 and 501 capacitively coupled to the floating gate 506, paraelectric capacitors 503 and 504 interposed between the input terminals 500 and 501 and the floating gate 506, and a control terminal 502 for receiving a control signal. And a ferroelectric capacitor 505 interposed between the control terminal 502 and the floating gate 506.
[0010]
Here, the logic of the input signal from the input terminal 500 is X1, the input signal from the input terminal 501 is X2, the charge amount of the control terminal 502 is CR, the charge amount φF of the floating gate 506, and the output signal of the output terminal 509. Let the logic be Y. The threshold voltage of the NMISFET 510 is set to 0V. Furthermore, when X1 and X2 are set to “1”, it is assumed that a charge amount Q0 is induced on each upper electrode (electrode on the input terminal side) of the paraelectric capacitors 503 and 504.
[0011]
Figure12FIG. 8 is a table showing the amounts of charge of the respective parts with respect to the input signals X1 and X2 when a negative pulse signal is applied to the control terminal 502, in a table with the logical value of the output signal Y.
[0012]
First, by applying a pulse signal of a negative voltage to the control terminal 502, a residual charge of −Q0 / 2 is generated on the upper electrode of the ferroelectric capacitor 505. At this time, the charge amount φF of the floating gate 506 is12It becomes as shown in. At this time, if the charge of the floating gate 506 is positive, SiO_Two / Si channel is formed at the interface and the MOS transistor is turned on.12It becomes the value shown in. Figure12As can be seen from the above, the circuit operation at this time is a NOR circuit operation.
[0013]
FigureThirteenFIG. 8 is a table showing the charge amounts of the respective parts with respect to the input signals X1 and X2 when a negative pulse signal having a larger amplitude is applied to the control terminal 502, in a table with the logical value of the output signal Y.
[0014]
First, by applying a pulse signal of a negative voltage having a larger amplitude to the control terminal 502, a residual charge of −3Q0 / 2 is generated on the upper electrode of the ferroelectric capacitor 505. At this time, the charge amount φF of the floating gate 506 isThirteenIt becomes as shown in.
[0015]
If the charge on the floating gate 506 is positive,_Two / Si, a channel is formed at the interface and the NMISFET 510 is turned ON.ThirteenIt becomes as shown in. FigureThirteenAs can be seen from the above, the circuit operation at this time is a NAND circuit operation. As described above, by controlling the residual charge of the ferroelectric capacitor, a program element that is a logic conversion circuit between the NOR circuit and the NAND circuit can be realized.
[0016]
Further, as a third conventional example, a conventional neurocomputer will be described. To explain the operation of the neurocomputer, the operation of the brain of a living body as a model will first be briefly described.
[0017]
FigureFifteenFIG. 3 is a block circuit diagram showing a simplified configuration of a basic unit of the brain. In the figure, 601a, 601b and 601c are neurons, and 602a, 602b and 602c are nerve fibers. 603a, 603b, and 603c are called synaptic connections, for example, multiply a signal transmitted through the nerve fiber 602a by a load of wa and input the multiplied signal to the neuron 601a. The neuron 601a calculates a linear sum of the input signal strengths, and when the total value exceeds a certain threshold, the nerve cell is activated (fired) and outputs a signal to the nerve fiber 602b. If the sum is below the threshold, the neuron does not output a signal. It is said that such relatively simple multiply-accumulate operations are performed in parallel in a very large number of times, thereby realizing brain-specific information processing.
[0018]
Research on such neuron operation has been actively conducted as software. On the other hand, there is a movement to realize a high-speed operation by realizing and optimizing the neuron function by hardware. As an example of such a neuron element development, there is a neuron MOSFET (abbreviated as νMOS) described in Japanese Patent No. 2662559.
[0019]
Figure16FIG. 9 is a schematic diagram showing a simplified structure of a νMOS according to a third conventional example. As shown in the figure, the νMOS includes a floating gate FG serving as a gate electrode of a field effect transistor (MISFET), and a plurality of capacitors CG having the floating gate FG as a lower electrode are connected in parallel. Having a configuration. With such a configuration, the gate portion of the νMOS has a configuration in which the capacitors CG and CO are connected in series. Therefore, the signals (voltages) input to the input terminals G1 to G4 are based on the voltage distribution principle of the series capacitors. , A large voltage is distributed to the gate portion of the νMOS having a smaller capacity. As the sum of the signals input to the input terminals G1 to G4 increases, the voltage distributed to the gate increases, and the drain current of the νMOS increases.
[0020]
With this operation, the above-described operation of the neuron of the brain is expressed as an element operation of the semiconductor device.
[0021]
On the other hand, when trying to realize the functions of the brain, another function is required. It is a figureFifteenThis is a function described as a synapse, and a function of realizing a load for each of a plurality of inputs for one neuron. As a conventional example of a neuron element of a neurocomputer having such a load function, there is a technique described in Japanese Patent No. 3122756, for example.
[0022]
Figure17FIG. 1 is a schematic diagram showing a configuration of a conventional neuron element described in a patent publication. In the figure, reference numerals 611 and 612 denote NMOS and PMOS transistors, respectively. The floating gate 613 is provided on the NMOS channel region via a gate oxide film. In addition, the floating gate 613 is made of SiO 2 of about 5 to 7 nm._Two It faces the charge injection electrode 616 via the film. The wiring 617 serves as the gate electrode of the PMOS transistor 611 and at the same time, the floating gate of the NMOS transistor 611 and the SiO 2 having a thickness of about 20 nm._Two It is capacitively coupled via a film, and also functions as a gate electrode of the NMOS transistor 611. 620 is a wiring. The electrode 621 is made of a 20 nm thick SiO 2 with the floating gate 613._Two Capacitively coupled through the film. The neuron circuit 630 has many input terminals 628a to 628d.
[0023]
Figure17In the conventional neuron element shown in FIG. 7, a charge is injected from a charge injection electrode 616 to a floating gate 613 by a tunnel current to thereby form a floating gate 613.ofThe potential is changing. Thus, the threshold voltage of the NMOS transistor 611 can be changed. With this effect, a voltage (voltage) at which the NMOS transistor 611 is turned on can be changed by a signal (voltage) input from the wiring 619 through the wiring 617. This is not only to change the influence of the input signal on ON (firing) of the neuron circuit, but also to realize a synapse operation for changing the load. Note that the synapse circuit of the embodiment in the above-mentioned patent publication is configured by coupling the NMOS transistor 611 and the PMOS transistor 612, so that the output has two values of VDD and GND (0V).
[0024]
In order to accurately control the amount of charge of the tunnel current for setting such a load coefficient, in this conventional example, not only the absolute value of the injection control voltage but also the injection control voltage is changed in a pulse shape or the pulse width is changed. The control is based on the pulse height or the number of pulses.
[0025]
Further, in the above conventional example, as a means for changing the threshold voltage of the NMOS transistor, a nonvolatile memory element (ferroelectric gate transistor) using a ferroelectric film is used in addition to the above-mentioned floating gate type MOS transistor. It is possible to do so.
[0026]
Figure18FIG. 1 is a sectional view showing a conventional ferroelectric gate transistor structure described in the above publication. In the figure, reference numeral 656 denotes a P-type Si substrate, and 657 denotes, for example, 5 nm SiO 2._Two It is a membrane. Reference numeral 658 denotes a ferroelectric film, for example, PZT (Pb (Zr_x Ti_1-x ) O_Two ) Is used. Reference numeral 659 denotes a Ti electrode, for example. 660a and 660b are N⁺ Source and drain of the mold. In the same publication, a ferroelectric film is polarized by adding a positive or negative pulse to the gate electrode 659, and the threshold voltage of the transistor is controlled by the magnitude of the polarization.
[0027]
[Problems to be solved by the invention]
However, the first conventional example has the following problems.
[0028]
First, when a neuron element outputs "1" or "0" from a neuron for a certain input, it is necessary to make it easier to output the same output from the next time. That is, it is necessary to learn and store the output status of each neuron. However, in the MIS-type neuron element described in Japanese Patent No. 2929909, the fact that the input section of each neuron is "1" or "0" means that the remanent polarization of the ferroelectric film provided in each input section. Can be learned and stored, but the information that the neuron outputs “1” or “0” cannot be learned and stored. This is because even if some of the input units are “1”, it cannot be unambiguously determined whether the output is “1” or “0”.
[0029]
Second, when the neuron element has a learning function, it may be desirable to add a function of resetting or weakening the learning memory. In the MIS type neuron element described in Japanese Patent No. 2940088, since the gate insulating film of the output side MISFET is made of a ferroelectric material, it is possible to learn and store the output state of the neuron, which is the first problem. Has become. However, in order to reset or weaken the learning storage information, it is necessary to change the polarization of the ferroelectric film by applying a voltage having a polarity different from that of a normal MISFET operation between the substrate and the gate electrode. . For this purpose, it is necessary to electrically insulate the substrate portion of each MIS type neuron element, which is very complicated including the control circuit.
[0030]
Further, in the neuron element functioning as the logic conversion circuit (program element) according to the second conventional example, the residual charge generated in the ferroelectric film of the ferroelectric capacitor 505 is affected by the potential φF of the floating gate 506. There was a problem.
[0031]
Here, assuming that the voltage applied to the ferroelectric film (the control terminal side is positive) is Vferr, Vferr is represented by the following equation (101).
Vferr = CR−φF = −φF (101)
Is represented by
[0032]
Here, consideration will be given by focusing on a region where the pulse signal is not applied to the control terminal 502. At this time, from Expression (101), it can be seen that the voltage applied to the ferroelectric film depends on the potential φF of the floating gate 506. Since φF varies depending on the input, the voltage applied to the ferroelectric film always varies according to the equation (101). As a result, there is a problem that the residual charge induced in the ferroelectric film varies. This problem will be described with reference to the drawings.
[0033]
Figure14(A) and (b) are, respectively, a timing chart showing a temporal change of the potential of the floating gate of the neuron element according to the second conventional example and a timing showing the temporal change of the voltage applied to the ferroelectric film. It is a chart. Here, the voltage value of the logical value “0” is 0 V, and the voltage value of the logical value “1” is 5 V. After inputting (0, 0), (1, 1), (0, 1), and (1, 0) to the input terminals 500 and 501, respectively, a -10 V pulse signal is applied to the control terminal 502, and the ferroelectric substance is applied. A residual charge is induced in the body capacitor 505. After that, the input of (0, 0), (1, 1), (0, 1), (1, 0) is repeatedly input to the input terminals 500 and 501, respectively.
[0034]
At this time,14As can be seen from (a), the voltage applied to the ferroelectric film fluctuates even in a region where no pulse signal is applied. In other words, the figure14As shown in a region Rx of (a), the potential φF of the floating gate 506 for the input (0, 1) before the pulse signal is applied and the potential φF for the input (1, 0) are different from each other. This is because, as described above, when an input signal is applied to the input terminal, the voltage applied to the ferroelectric film of the ferroelectric capacitor fluctuates. Also figure14As shown in a region Ry of FIG. 7A, after the pulse signal is applied to the control terminal 502, the potentials φF of the floating gates corresponding to the first and second same inputs are different from each other. This is also because, when a voltage is applied to the input terminal, the voltage applied to the ferroelectric film of the ferroelectric capacitor is not constant, so that the residual charge of the ferroelectric capacitor fluctuates.
[0035]
As described above, in the neuron element functioning as a logic conversion circuit between the NOR circuit and the NAND circuit according to the second conventional example, as a result of the residual charge of the ferroelectric capacitor fluctuating due to the voltage applied to the other input terminal, the ferroelectric There is a problem that the residual charge induced by the body capacitor cannot be stably held, and the logic conversion function becomes unstable.
[0036]
FIG. 4 is a diagram showing a first method of configuring a synapse circuit of the neurocomputer according to the third conventional example.17In the configuration using the tunnel current shown in (1), considering that the tunnel current changes exponentially with respect to the electric field strength, it is extremely difficult to control the tunnel charge amount by the pulse width, pulse height, and also the number of pulses. Have difficulty.
[0037]
Figure19FIG. 3 is a diagram showing a correlation between an applied voltage and a tunnel current when electrons tunnel through a 10 nm-thick thermally oxidized silicon film. As shown in the figure, since the tunnel current has the property of increasing exponentially, it is understood that the controllability of the charge to the floating electrode in the conventional example is extremely difficult. As a result, it is difficult to set the load coefficient in multiple stages and with high accuracy. In the calculation processing of the neural network, since the setting of the weighting factor requires accuracy,17According to the method disclosed in Japanese Patent Application Laid-Open No. H11-129, it is extremely difficult to set a fine weighting factor, and as a result, there is a problem that an appropriate operation cannot be obtained, such as an operation of a neuron element that is difficult to converge on learning. In addition, the electric field intensity at which the tunnel phenomenon can be effectively used in the device is about 6 MV / cm or more. As a result, there is a disadvantage that a very high driving voltage is required.
[0038]
Furthermore, the figure18As for the ferroelectric gate transistor, which is the second method for forming the conventional synapse circuit as shown in FIG. 1, specific means such as a specific wiring connection form and a driving voltage application method are taken. It is questionable whether proper operation as a synapse can be obtained.
[0039]
A first object of the present invention is to provide a neuron element which can easily learn and store the output status of each neuron and incorporates a mechanism for easily resetting or weakening the learning and memory.
[0042]
[Means for Solving the Problems]
The first semiconductor device of the present invention includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a first gate electrode provided on the first insulating film, At least one second gate electrode provided to face the one gate electrode and receiving an input signal; and at least one second gate electrode interposed between the first gate electrode and the at least one second gate electrode A second insulating film, a third gate electrode provided to face the first gate electrode, and a ferroelectric film interposed between the first gate electrode and the third gate electrode And an output unit connected to a part of the semiconductor layer and outputting an output signal in accordance with an input signal input to the at least one second electrode, wherein an output unit is provided in accordance with a polarization characteristic of the ferroelectric film. To enhance the correlation between the input signal and the output signal or It has a learning function to weakenA pulse-like voltage is applied to the third gate electrode, and a positive or negative pulse-like voltage with respect to the first gate electrode is applied to the third gate electrode; And a signal generation circuit for generating a signal to be supplied to the third gate electrode according to the evaluation result of the evaluation means.
[0043]
Thus, when the remanent polarization of the ferroelectric film is polarized in a direction to weaken the gate bias at which the semiconductor device is turned on, a negative learning effect occurs, and the remanent polarization of the ferroelectric film turns on the semiconductor device. When polarized in a direction to increase the gate bias, a positive learning effect occurs. In particular, it has a negative learning function as a basic function. Therefore, a semiconductor device suitable for a neuron element having various learning functions can be obtained.
[0044]
By supplying a constant voltage to the third gate electrode, a semiconductor device that exhibits a learning function without performing complicated control can be obtained.
[0045]
A positive or negative voltage with respect to the potential of the first electrode is applied to the third gate electrode, so that the semiconductor device can have any positive learning function or negative learning function. .
[0048]
The absolute value of the coercive voltage for inverting the polarization of the ferroelectric film is smaller than the absolute value of the threshold voltage for allowing a current to flow in a region located below the first gate electrode in the semiconductor layer. Is preferably small.
[0049]
When a maximum input voltage is applied to the at least one second gate electrode within a range in which current flows in a region located below the first gate electrode in the semiconductor layer, the first gate electrode It is preferable that the voltage between the gate electrode and the third gate electrode does not exceed the coercive voltage of the ferroelectric film.
[0050]
First and second diffusion regions formed in regions of the semiconductor layer located on both sides of the first gate electrode are connected to the first and second diffusion regions, respectively, and have a height difference. A first voltage supply unit for supplying first and second voltages, wherein the output unit is connected to the first diffusion region, and the output unit and the first voltage supply unit It is preferable that a resistive member functioning as a resistor is interposed between and.
[0051]
The semiconductor device preferably functions as a neuron element of an arithmetic circuit, particularly, a neuron element of a logical operation circuit.
[0052]
Further, it is preferable that the semiconductor device is arranged in an artificial intelligence system for performing recognition and judgment.
[0053]
Preferably, a plurality of the at least one second gate electrode and a plurality of the at least one second insulating film are provided in the same number, and the output signal is output according to a plurality of input signals.
[0084]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
FIG. 1 is a schematic diagram illustrating a circuit configuration of a neuron element of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is an equivalent circuit diagram when only the capacitor portion of the neuron element of the present embodiment is extracted.
[0085]
The neuron element of the present embodiment includes an n-channel MIS transistor (NMISFET1) having a source terminal 2, a drain terminal 3, a gate insulating film 6, and a gate electrode. Here, the gate electrode of the NMISFET 1 is a floating gate 4 which is not connected to another terminal and is in a floating state. The source terminal 2 is grounded together with the substrate region of the NMISFET 1, and the drain terminal 3 is connected to the output terminal 10. The output terminal 10 is connected to a power supply voltage supply unit for supplying the power supply voltage VDD via the load resistance element 9.
[0086]
Further, n signal input sections 5 capacitively coupled to the floating gate 4 are provided. The signal input unit 5 includes an input terminal 5a, an input gate electrode 5b connected to the input terminal 5a, and a paraelectric film 5c interposed between the input gate electrode 5b and the floating gate 4. That is, the input gate electrode 5b and the floating gate 4 are capacitively coupled by the paraelectric film 5c.
[0087]
The capacitance between the input gate electrode 5b and the floating gate 4 is determined by the material, thickness and area of the paraelectric film 5c. The capacitance between each input gate electrode 5b and the floating gate 4 may be all the same, or may be different for weighting.
[0088]
Further, a learning storage unit 7 having a voltage terminal 7a for receiving a polarization voltage and a polarization electrode 7b opposed to the floating gate 4 with the ferroelectric film 8 interposed therebetween is provided. Normally, a constant voltage (ground voltage) of 0 V is applied to the voltage terminal 7a of the learning storage unit 7.
[0089]
Here, each input gate electrode of the n signal input units 55bAnd the capacitance between the floating gate 4 and C1 to Cn. Further, the capacitance between the floating gate 4 and the semiconductor substrate is C0, the effective capacitance between the floating gate 4 and the learning storage unit 7 is CM, and the remanent polarization of the ferroelectric film 8 is QM. When the potential of the floating gate 4 is VF and the potential of the learning storage unit 7 is VM, approximately the following equation (1) is obtained.

Holds.
[0090]
FIG. 2 is a diagram showing the voltage dependence (hysteresis loop) of the remanent polarization of the ferroelectric film 8. In the present embodiment, a polarization in which a positive charge is generated on the semiconductor substrate side in the ferroelectric film 4 is defined as a positive polarization. FIG. 2 shows that the polarization is reversed when the coercive voltage + Vc or -Vc is applied to the ferroelectric film. The remanent polarization when the applied voltage is returned to 0 is + Pr or -Pr.
[0091]
Next, by adjusting the capacitances C1 to Cn of the input units 5, the effective capacitance CM between the learning storage unit and the floating gate, and the capacitance C0 between the floating gate and the semiconductor substrate, the threshold voltage VTH of the NMISFET1 is adjusted. The element is designed so that the coercive voltage Vc of the ferroelectric film 8 becomes substantially equal. When the sum of the input values of the n signal input units 5 reaches a certain value, the potential VF of the floating gate 4 exceeds the threshold voltage VTH of the NMISFET1, the NMISFET1 turns ON, and the current between the source terminal 2 and the drain terminal 3 Flows and becomes conductive. At this time, the resistance between the source terminal 2 and the drain terminal 3 becomes smaller than that of the load resistance element 9, and the output voltage of the output terminal 10 becomes almost 0V. On the other hand, since the coercive voltage Vc of the ferroelectric film 8 is designed to be substantially equal to the threshold voltage VTH of the NMISFET 1, the polarization of the ferroelectric film 8 is inverted from + QM to -QM at the same time when the NMISFET 1 is turned on, and -2QM Only change.
[0092]
The above operation will be described with reference to the circuit shown in FIG. 1 and the equivalent circuit diagram shown in FIG. However, as described above, the gate insulating film 6 is a gate insulating film of an NMISFET using the floating gate 4 as a gate electrode. The threshold voltage VTH of the NMISFET 1 is designed to be substantially equal to the coercive voltage Vc of the ferroelectric film 8. When the voltage of the floating gate 4 exceeds Vc in the positive direction, the NMISFET 1 is turned on, and otherwise turned off.
[0093]
When various voltages are applied to the signal input unit 5, the voltage of the floating gate 4 becomes VF represented by the above-mentioned equation (1). As described above, the threshold voltage VTH of the NMISFET 1 having the floating gate 4 as the gate electrode is designed to be substantially equal to the coercive voltage Vc of the ferroelectric film 8. Therefore, when various positive voltages are applied to the signal input unit 5 from the state of all 0V and the voltage of the floating gate 4 exceeds the threshold voltage VTH, the NMISFET 1 is turned on. At the same time, a voltage exceeding the coercive voltage Vc is applied to both ends of the ferroelectric film 8, and the polarization of the ferroelectric film 8 starts to be inverted. When all the voltages of the signal input unit 5 return to 0V again, the polarization of the ferroelectric film 8 is eventually inverted from + QM to -QM, and changes by -2QM. Here, QM is obtained by multiplying Pr shown in FIG. 2 by the area of the ferroelectric film. At this time, the voltage of the floating gate 4 becomes a negative voltage by 2QM / (C1 + C2 +... + Cn + CM + C0) as compared with before the voltage operation described above is performed.
[0094]
Therefore, in order for the NMISFET 1 to turn on next, it is necessary to apply a voltage to the signal input unit 5 such that the voltage VF of the floating gate 4 becomes higher than the initial state by 2QM / (C1 + C2 +... + Cn + CM + C0). This is, in other words, the same as that the remanent polarization of the ferroelectric film 8 learns and stores that the NMISFET 1 has been turned on, and suppresses it in the negative direction. Therefore, when the circuit shown in FIG. 1 is considered as one artificial neuron, the use of the present embodiment makes it possible to learn and store information in which the artificial neuron outputs “1” or “0”. In this case, the voltages of the n signal input units 5 may be either analog values or H or L digital values.
[0095]
FIG. 4 is a diagram showing an example of an operation waveform when two signal input units 5 are provided in the circuit shown in FIG. The power supply voltage VDD is 5 V, and the voltage of the voltage terminal 7 a of the learning storage unit 7 is 0 V. When the voltages V1 and V2 of the two signal input units 5 are simultaneously changed from 0V to 5V, as shown in FIG. 4, the voltage VOUT of the output terminal 10 changes from 5V to about 0.5V. Furthermore, when the voltages V1 and V2 of the two signal input units 5 are simultaneously set to 0V and then set to 5V again, the output voltage VOUT becomes about 1.4V from 5V. That is, while the voltage is about 0.5 V at the time of the first input, the voltage drops only to about 1.4 V at the time of the second input. This indicates that the NMISFET 1 is hard to be turned on, and the remanent polarization of the ferroelectric film 108 is the same as learning, storing, and suppressing that the NMISFET 1 is turned on.
[0096]
Further, when a positive voltage such that a voltage of -Vc or more is applied to the ferroelectric film 8 is applied to the polarization electrode 7b of the learning storage unit 7, the remanent polarization of the ferroelectric film 8 changes from -QM to + QM. To + 2QM, and returns to the initial state. When a slightly smaller voltage is applied to the polarization electrode 7b, the amount of polarization of the ferroelectric film 8, which decreases according to the voltage, changes. This can be said to be an operation of resetting the learning storage information of the neuron. Therefore, according to the present embodiment, the operation of simply resetting the learning storage information of the neuron can be performed simply by controlling the voltage of the learning storage unit 7 irrespective of the structure of the NMISFET 1. According to this embodiment, there is no need to electrically insulate the substrate of each MIS type neuron element or to design a very complicated control circuit.
[0097]
Therefore, according to the present embodiment, a semiconductor device which can easily learn and store the output state of each neuron and which functions as a neuron element incorporating a mechanism for easily resetting or weakening the learning and memory can be provided by a simple method. .
[0098]
-First modification example-
Although the MIS type neuron element of the present embodiment has only one learning storage unit 7 for holding learning storage information, it may have a plurality of learning storage units 7.
[0099]
FIG. 5 is a schematic diagram illustrating a configuration of a neuron element that is a semiconductor device according to a first modification of the first embodiment in which a plurality of learning storage units are provided. The neuron element according to this modification includes a polarization memory 7A having a voltage terminal 7Aa receiving a polarization voltage and a polarization electrode 7Ab opposed to the floating gate 4 with a ferroelectric film 8A interposed therebetween. The learning storage unit 7B includes a voltage terminal 7Ba for receiving a voltage and a polarization electrode 7Bb opposed to the floating gate 4 with the ferroelectric film 8B interposed therebetween. Other configurations are the same as those shown in FIG.
[0100]
In the case of this modification, the ratio of the capacitance of the ferroelectric films 8A and 8B interposed between the two learning storage units 7A and 7B and the floating gate 4 may be the same or different. In this modification, the learning storage units 7A and 7B and the ferroelectric films 8A and 8B are arranged at both ends of the floating gate 4. However, the locations where the learning storage units 7A and 7B and the ferroelectric films 8A and 8B are arranged. Does not affect the functions of the learning storage units 7A and 7B.
[0101]
According to this modification, by controlling the learning storage unit 7A and the learning storage unit 7B with independent voltages, polarization control can be performed in multiple stages, and more accurate or diverse learning storage is realized. be able to.
[0102]
Therefore, according to this modified example, it is also possible to provide a semiconductor device which can easily learn and store the output state of each neuron and which functions as a neuron element incorporating a mechanism for easily resetting or weakening the learning and memory by a simple method. it can.
[0103]
-2nd modification-
In this embodiment, a circuit is constructed by combining the NMISFET 1 and the load resistance element 9, but a p-type MIS transistor may be used instead of the load resistance element 9.
[0104]
FIG. 6 is a schematic diagram illustrating a configuration of a neuron element that is a semiconductor device according to a second modification of the first embodiment. The neuron element according to this modification includes a p-channel MIS transistor 11 (PMISFET 11) connected in series to the NMISFET 1, instead of the load resistance element 9 in the structure shown in FIG. The source terminal 12 of the PMISFET 11 is connected to a power supply unit for supplying the power supply voltage VDD, and the drain terminal 13 of the PMISFET 11 is connected to the drain terminal 3 of the NMISFET 1. The output terminal 10 is connected to the drain terminal 3 of the NMISFET 1 and the drain terminal 13 of the PMISFET 11. The floating gate 4 is provided so as to straddle the NMISFET 1 and the PMISFET 11, and a paraelectric film 16 is interposed between the floating gate 4 and the substrate region of the PMISFET 11.
[0105]
According to this modification, the capacitance between the floating gate and the semiconductor substrate is set to C0 in the description of the combination circuit of the NMISFET and the load resistance element, whereas when the p-type MISFET11 is used, the NMISFET1 is used. WhenPMISFETAssuming that the sum of the capacitances between the floating gate 4 and the semiconductor substrate over the semiconductor substrate 11 is C0, the same relationship as the above equation (1) holds.
[0106]
(Second embodiment)
In the first embodiment, the element is designed so that the threshold voltage VTH of the NMISFET 1 is substantially equal to the coercive voltage Vc of the ferroelectric film 8. However, the element is designed by a method different from that of the first embodiment. You can also. In the present embodiment, an element designed by a different method while adopting the same circuit configuration as that of the first embodiment will be described with reference to FIGS. That is, the circuit configuration of the neuron element of the present embodiment is as shown in FIG.
[0107]
FIG. 7 is a diagram illustrating the voltage dependence (hysteresis loop) of the remanent polarization of the ferroelectric film 8 when a method different from that of the first embodiment is employed. For example, the threshold voltage VTH of the NMISFET 1 is smaller than the coercive voltage Vc of the ferroelectric film 8, and the potential VF of the floating gate 4 when the input voltage of the n signal input units 5 takes the maximum value is equal to or lower than the coercive voltage Vc. The element can be designed so that The capacitances of the paraelectric films 5c interposed between the n signal input units 5 and the floating gate 4 may be the same, or may be different from each other for weighting.
[0108]
In the neuron element shown in FIG. 1, when all the input voltages of the n signal input sections 5 take the maximum value, the potential VF of the floating gate 4 becomes larger than the threshold voltage VTH of the NMISFET1, so that the NMISFET1 is turned on. , A current flows between the source terminal 2 and the drain terminal 3, and the NMISFET 1 is turned on. At this time, the resistance between the source terminal 2 and the drain terminal 3 becomes smaller than that of the load resistance element 9, and the output voltage of the output terminal 10 becomes almost 0V. On the other hand, since the coercive voltage Vc of the ferroelectric film 8 is designed to be higher than the threshold voltage VTH of the NMISFET 1, even when the NMISFET 1 is turned on, the polarization state of the ferroelectric film 8 slightly changes, but does not greatly change. Absent.
[0109]
In FIG. 7, when all the input voltages of the n signal input units 5 are 0 V, the potential VF of the floating gate 4 is also 0 V, and the remanent polarization of the ferroelectric film 8 is the first state after initialization. It is at point A. Thereafter, even when all the input voltages of the n signal input units 5 take the maximum value, the potential VF of the floating gate 4 is smaller than the coercive voltage Vc of the ferroelectric film 8, so that the polarization state is changed to the point C. When the input voltages of all the n signal input units 5 return to 0, the polarization state moves to the point B. Therefore, the remanent polarization changes by the remanent polarization difference X between points A and B. As described above, since the remanent polarization is reduced, the NMISFET 1 is changed in a direction in which it is difficult to turn on. Therefore, in order to turn on the NMISFET 1 next, it is necessary that VF is larger by X / (C1 + C2 +... + Cn + CM + C0). That is, the NMISFET 1 is suppressed from being turned on again.
[0110]
If some of the n signal input units 5 do not take the highest voltage, the remanent polarization will be somewhere between points A and C depending on the potential VF of the floating gate 4. Located in. When the voltages of all the signal input units 5 are returned to 0 V, the remanent polarization is located somewhere between the point A and the point B. When all the voltages of the n signal input units 5 change so that the potential VF of the floating gate 4 gradually increases, the remanent polarization when the voltages of all the signal input units 5 are returned to 0 V gradually increases. To become smaller. This is the same as learning reinforcement.
[0111]
On the other hand, if all the voltages of the n signal input units 5 change gradually after the potential VF of the floating gate 4 takes a certain value, the voltages of all the signal input units 5 are returned to 0V. The remanent polarization does not change and learning is not enhanced.
[0112]
In order to further enhance the learning, a negative voltage is applied to the floating gate 4 to the learning storage unit 7 so that a voltage higher than the coercive voltage Vc is applied to both ends of the ferroelectric film 8. The application time may be any time as long as it is equal to or longer than the time required for the polarization inversion of the ferroelectric film 8 to occur. For example, a pulse of about 100 ns during which a voltage equal to or higher than the coercive voltage Vc is applied to both ends of the ferroelectric film 8 may be used. At this time, in the hysteresis characteristics shown in FIG. 7, the voltage applied to both ends of the ferroelectric film 8 is 0 V before the application of the pulse voltage, so that the remanent polarization is somewhere between the points A and B. Located in. During the pulse application, the voltage applied to both ends of the ferroelectric film 8 becomes larger than Vc, so that the polarization state shifts to the point D. After the pulse application, the applied voltage returns to 0 V, so that the polarization state moves to the point E. Initially, if the polarization state is at point A, the remnant polarization changes by Y, and the polarization is greatly increased from positive to negative. Therefore, the NMISFET 1 does not turn on unless the input voltages of the n signal input units 5 are higher. This means that the NMISFET 1 is more difficult to be turned on by the pulse applied to the learning storage unit 7, which is the same value as that the negative learning is strengthened and the suppression is large.
[0113]
Subsequently, a function of performing positive learning will be described. A voltage is applied to the learning storage unit 7 in the same procedure as described above. In this case, a positive voltage is applied to the floating gate 4 to the learning storage unit 7, and the ferroelectric film 8 A voltage higher than the coercive voltage Vc is applied to both ends. The application time can be arbitrarily set as long as it is equal to or longer than the time required for the polarization inversion of the ferroelectric film 8 to occur. For example, a pulse signal in which a voltage of Vc or more is applied to both ends of the ferroelectric film 8 for about 100 ns may be applied to both ends of the ferroelectric film 8. At this time, in the hysteresis characteristic shown in FIG. 7, the voltage applied to both ends of the ferroelectric film 8 is 0 V before the pulse voltage is applied, and therefore the polarization state is located at the point E. During the application of the pulse signal, the voltage applied to both ends of the ferroelectric film 8 exceeds the coercive voltage -Vc, so that the polarization state shifts to the point F. After the application of the pulse signal, since the applied voltage returns to 0 V, the polarization state shifts to point A. Since the polarization state initially at the point E has shifted to the point A, the remanent polarization changes by Y, and the polarization largely changes from negative to positive. Therefore, even if the input voltages of the n signal input units 5 are smaller, the NMISFET 1 is turned on. This means that the NMISFET 1 is more easily turned on by the pulse applied to the learning storage unit 7, which means that positive learning has been performed.
[0114]
Further, if the voltage of the pulse signal at this time is set slightly smaller so that a voltage lower than the coercive voltage Vc is applied to both ends of the ferroelectric film 8, the polarization state at the point E before the application of the pulse signal becomes: During the application of the pulse signal, the operation shifts to the point G. After the application of the pulse signal, the applied voltage returns to 0 V, so that the polarization state shifts to the point H. Since the polarization state initially at the point E has shifted to the point H, the remanent polarization changes by Z, and the negative polarization slightly decreases. Therefore, even if the input voltage of each signal input unit 5 is slightly smaller, the NMISFET 1 is turned on. This means that the NMISFET 1 is slightly more easily turned on by the pulse signal applied to the learning storage unit 7, which means that the positive weak learning has been performed.
[0115]
As described above, according to the present embodiment, by controlling the voltage applied to the learning storage unit 7, learning can be enhanced or suppressed at various rates. According to the present embodiment, it is possible to easily enhance or suppress the learning storage information of the neuron at various rates simply by controlling the voltage of the learning storage unit 7 irrespective of the NMISFET 1. Moreover, according to the present embodiment, it is not necessary to electrically insulate the substrate portion of each MIS-type neuron element or to design a very complicated control circuit.
[0116]
Therefore, by using this embodiment, the output state of each neuron can be easily learned and stored, and a neuron element incorporating a mechanism for easily enhancing and suppressing the learning and storage can be provided by a simple method. Furthermore, by forming an arithmetic circuit by combining the neuron elements, a neuron element can be formed, and a semiconductor application device having a learning function can be realized using the neuron element. Further, it is possible to realize a system that performs advanced operations such as recognition and judgment, that is, an artificial intelligence system, using this semiconductor applied device.
[0117]
In the present embodiment, a circuit is constructed by combining the NMISFET 1 and the load resistance element 9, but a p-type MIS transistor can be used instead of the load resistance element 9 as in the first embodiment.
[0118]
(Third embodiment)
FIG. 8 is a schematic diagram illustrating a configuration of a neuron element and a control circuit that are semiconductor devices according to the third embodiment of the present invention.
[0119]
In the present embodiment, a control circuit is provided in addition to the neuron element in the first embodiment. The control circuit according to the present embodiment includes a logic circuit 21 connected to the output terminal 10 and receiving the first output signal Vout1, and a logic circuit 21 connected to the logic circuit 21 and receiving the second output signal Vout2 output from the logic circuit 21. The logic circuit 22 includes a stage logic circuit 22, an evaluation circuit 23 containing various data, and a pulse signal generation circuit 24 for generating a pulse signal to be supplied to the learning storage unit 7.
[0120]
The basic configuration and operation of the NMISFET 1 in the present embodiment are as described in the first or second embodiment.
[0121]
The first output signal Vout1 output from the output terminal 10 passes through the logic circuit 21, becomes a second output signal Vout2, and is transmitted to the next-stage logic circuit 22. As described in the first embodiment, when the sum of the input values of the n signal input units 5 reaches a certain value, the potential VF of the floating gate 4 exceeds the threshold voltage VTH of the NMISFET1, the NMISFET1 turns on, and the source A current flows between the terminal 2 and the drain terminal 3 to be in a conductive state. When the NMISFET1 turns on, the first output signal Vout1 changes from 1 to 0.
[0122]
Further, the evaluation circuit 23 compares the second output signal Vout2 with the evaluation reference value stored in the evaluation circuit 23, and feeds the resulting evaluation signal Sev back to the logic circuit 21. The evaluation signal Sev is a signal output as a result of evaluating whether or not the second output signal Sout2 is close to the result obtained by the signal output of the entire circuit. The evaluation signal Sev is a signal output from all other neuron elements that require this. Can be supplied to The evaluation signal Sev is a positive voltage signal when the result of the second output signal Vout2 is close to the result (evaluation reference value), for example, and is very different from the result of the second output signal Vout2 (evaluation reference value). It is assumed that the signal is a negative voltage signal in the case of being far from the above, and a signal of 0 V in the middle of the signal. That is, the determination as to whether the learning of the first output signal Vout1 is strengthened or suppressed is made in the logic circuit 21 using the evaluation signal Sev.
[0123]
For example, when the NMISFET 1 is turned on, the first output signal Vout1 is close to 0 V, and the evaluation signal Sev is a positive voltage signal, the logic circuit 21 outputs a positive signal from the logic circuit 21 in order to strengthen the first output signal Vout1. The signal Spt is supplied to the pulse signal generation circuit 24. At this time, the first output signal Vout1 and the positive teacher signal Spt are received from the pulse signal generation circuit 24, and as a learning signal Sln supplied to the learning storage unit 7, a pulse signal of a positive voltage for enhancing learning is provided. Is output. Therefore, a strong negative electric field is applied to both ends of the ferroelectric film 8. Therefore, when the pulse is removed after the positive voltage pulse signal is applied, the remanent polarization of the ferroelectric film 8 becomes negative and its absolute value increases. This means that the NMISFET 1 is easily turned on when a positive input signal is received at the input unit 5. That is, a learning signal that is a positive voltage pulse signalS lnThereby, the NMISFET 1 is easily turned on, which means that positive learning is strengthened. The application time of the learning signal Sln may be longer than the time required for the polarization inversion of the ferroelectric film 8 to occur. For example, the learning signal SIn may be a pulse signal such that the time during which a voltage equal to or higher than the coercive voltage Vc is applied to both ends of the ferroelectric film 8 is about 100 ns.
[0124]
Similarly, when the NMISFET1 is OFF, the first output signal Vout1 is close to the power supply voltage, and the evaluation signal Sev is a positive voltage signal, the logic circuit 21 outputs a positive signal to strengthen the first output signal Vout1. Is supplied to the pulse signal generation circuit 24. The pulse signal generation circuit 24 receives the first output signal Vout1 and the positive teacher signal Spt, and outputs a pulse signal of a negative voltage for enhancing learning as the learning signal Sln to be supplied to the learning storage unit 7. You.
[0125]
On the other hand, when the NMISFET1 is turned on, the first output signal Vout1 is close to 0 V, and the evaluation signal Sev is a negative voltage, the logic circuit 21 outputs a negative teacher signal Snt to weaken the first output signal Vout1. It is supplied to the pulse signal generation circuit 24. At this time, the first output signal Vout1 and the negative teacher signal Snt are received from the pulse signal generation circuit 24, and as a learning signal SIn supplied to the learning storage unit 7, a negative voltage for weakening (suppressing) the learning. Is output. Therefore, a strong positive electric field is applied to both ends of the ferroelectric film 8. Accordingly, when the pulse is removed after the application of the pulse signal of the negative voltage, the remanent polarization of the ferroelectric film 8 becomes positive and its absolute value increases. This means that it becomes difficult for the NMISFET 1 to be turned on when a positive input signal is received at the input unit 5. That is, a learning signal that is a pulse signal of a negative voltageS lnThis means that the NMISFET 1 is hard to be turned ON, and that learning is weakened (suppressed). The application time of the learning signal Sln may be longer than the time required for the polarization inversion of the ferroelectric film 8 to occur. For example, the learning signal SIn may be a pulse signal such that the time during which a voltage equal to or higher than the coercive voltage Vc is applied to both ends of the ferroelectric film 8 is about 100 ns.
[0126]
Similarly, when the NMISFET1 is OFF, the first output signal Vout1 is close to the power supply voltage, and the evaluation signal Sev is a negative voltage signal, the logic circuit 21 outputs a negative signal to weaken the first output signal Vout1. The teacher signal Snt is supplied to the pulse signal generation circuit 24. The pulse signal generation circuit 24 receives the first output signal Vout1 and the negative teacher signal Snt, and outputs a pulse signal of a positive voltage for weakening learning as the learning signal SIn supplied to the learning storage unit 7. .
[0127]
As described above, by controlling the voltage of the learning signal SIn according to the output signals Sout1 and Sout2 from the output terminal 10, the learning can be strengthened or suppressed at various rates as in the second embodiment. Can be.
[0128]
When the evaluation signal Sev is 0 V, the logic circuit 21 does not output the positive teacher signal Spt or the negative teacher signal Snt, so that the learning signal SIn remains at 0 V, and the learning is strengthened or suppressed. Absent.
[0129]
As described above, a positive voltage pulse signal or a negative voltage pulse signal can be used as the learning signal Sln. At that time, the NMISFET1 can be used in the normal operation mode, and there is no need to control the voltage of the substrate region of the NMISFET1.
[0130]
Therefore, according to the neuron element of the present embodiment, learning using the ferroelectric film 8 can be easily enhanced / suppressed without using a complicated control circuit. Therefore, by combining a large number of neuron elements of the present embodiment, the output state of each neuron element can be easily learned and stored, and a neuron element incorporating a mechanism for easily enhancing or weakening the learning storage is provided by a simple method. can do.
[0131]
In the present embodiment, the circuit of the neuron element is constructed by combining the NMISFET 1 and the load resistance element 9. However, as in the second embodiment, a p-type MIS transistor is used instead of the load resistance element 9. You can also. Although the evaluation signal Sev is of three types: positive voltage, negative voltage, and 0 V, the voltage of the learning signal Sln is converted into analog by adjusting the gradation of the voltage of the evaluation signal Sev with an analog value or the number of pulses. It is possible to control and further enhance and suppress learning with high accuracy.
[0132]
(Fourth embodiment)
In the first to third embodiments, examples have been described in which the present invention is mainly applied to an output-suppressing type neuron element. In the present embodiment, however, the present invention is mainly applied to an output enhancement type or an output suppression type. An example in which the present invention is applied to a neuron element of a type that can be selected from an enhanced type will be described.
[0133]
FIG. 9 is a schematic diagram illustrating a configuration of a neuron element that is a semiconductor device according to the fourth embodiment of the present invention.
[0134]
The neuron element of this embodiment includes an n-channel MIS transistor (NMISFET 31) having a source terminal 32, a drain terminal 33, a gate insulating film 36, and a gate electrode 41. The source terminal 32 is grounded together with the substrate region of the NMISFET 31, and the drain terminal 33 is connected to the output terminal 40. The output terminal 40 is connected to a power supply voltage supply unit for supplying the power supply voltage VDD via the load resistance element 39.
[0135]
A ferroelectric film is formed on the gate electrode 41 of the NMISFET 31.38Floating electrodes 34 facing each other are provided. Further, n signal input units 35 capacitively coupled to the floating electrode 34 are provided. The signal input unit 35 includes an input terminal 35a, an input gate electrode 35b connected to the input terminal 35a, and a paraelectric film 35c interposed between the input gate electrode 35b and the floating electrode 34. That is, the input gate electrode 35b and the floating electrode 34 are capacitively coupled by the paraelectric film 35c.
[0136]
The capacitance between the input gate electrode 35b and the floating electrode 34 is determined by the material, thickness and area of the paraelectric film 35c. The capacitance between each input gate electrode 35b and the floating electrode 34 may be the same, or may be different for weighting.
[0137]
Further, a learning storage unit 37 having a voltage terminal 37a for receiving a polarization voltage and an electrode 37b opposed to the floating electrode 34 with a paraelectric material 37c interposed therebetween is provided. Normally, a constant voltage (ground voltage) of 0 V is applied to the voltage terminal 37 a of the learning storage unit 37.
[0138]
Note that, as in the third embodiment, the signal at the output terminal 40 is transmitted to a logic circuit (not shown).
[0139]
Here, as described in the first embodiment, when the sum of the input values of the n signal input units 35 reaches a certain value, the potential VF of the gate electrode 41 exceeds the threshold voltage VTH of the NMISFET 31, and the NMISFET 31 is turned on. Then, a current flows between the source terminal 32 and the drain terminal 33 to be in a conductive state. When the NMISFET 31 is turned on, the voltage of the output terminal 40 changes from the power supply voltage VDD to 0. When the potential VF of the gate electrode 41 becomes the threshold voltage VTH of the NMISFET 31, the capacitance of the ferroelectric film 38 and the gate capacitance of the NMISFET 31 are adjusted so that the coercive voltage Vc is applied to both ends of the ferroelectric film 38. , N signal inputs35Each of the paraelectric films 35c and the capacity of the paraelectric film 37c of the learning storage unit 37 are designed to be optimized. Then, at the same time when the NMISFET 31 is turned on, the polarization of the ferroelectric film 38 is inverted from -QM to + QM, and increases by + 2QM. Therefore, in order to turn on the NMISFET 31 next, the potential VF of the floating electrode 34 may be lower by 2QM / (C1 + C2 +... + Cn + CM + C0). In other words, the remanent polarization of the ferroelectric film 38 learns and stores that the NMISFET 31 has been turned ON, and enhances the output. To reset this learning,Learning storage unitA negative voltage may be applied to the signal input unit 35 at 37.
[0140]
In the present embodiment, the configuration of the output-enhanced type neuron element has been described. However, there is a method of selecting the output-suppressed type or the output-enhanced type by using a wiring or a transistor.
[0141]
FIGS. 10A to 10C respectively show a configuration before switching wiring of a neuron element, which is a semiconductor device according to a modification of the fourth embodiment of the present invention, and a configuration when wiring is performed in an output-suppressing type. FIG. 4 is a schematic diagram showing a configuration when wiring is performed in an output-enhancing type.
[0142]
As shown in FIG. 10A, before the switching wiring, the gate electrode 41 of the NMISFET 31, the floating gate 34, and the two electrodes sandwiching the ferroelectric film 38 are not connected. Also, the learning storage unit37The voltage terminal 37a and the electrode 37b are not connected to each other.
[0143]
One method is, as shown in FIG. 10B, a wiring method in which two electrodes sandwiching the ferroelectric film 38 are connected to the voltage terminal 37a and the electrode 37b of the learning storage unit 37. In other words, the learning storage unit37The ferroelectric film 38 is interposed between the voltage terminals 37a. By connecting in this manner, as in the first embodiment, when a constant voltage of 0 V is applied to the voltage terminal 37a, the learning storage unit 37 has a negative learning function of weakening learning.
[0144]
Another method is a method of wiring two electrodes sandwiching the ferroelectric film 38 so as to connect the gate electrode 41 and the floating electrode 34, as shown in FIG. 10C. In other words, the ferroelectric film 38 is interposed between the gate electrode 41 and the floating electrode 34. With this connection, as in the fourth embodiment, when a constant voltage of 0 V is applied to the voltage terminal 37a, the learning storage unit 37 has a positive learning function to strengthen learning.
[0145]
In this modification, the connection relationship between the ferroelectric film 38, the gate electrode 41, the floating electrode 34, and the learning storage unit 37 is switched by wiring. By providing a switching transistor, the connection can be switched to the connection shown in FIG. 10B or 10C. In that case, the function can be changed during use.
[0292]
【The invention's effect】
According to the present invention, it is possible to provide a semiconductor device functioning as a neuron element, a potential generator, a logic conversion circuit, or the like having a high learning function, a logic conversion function, a load control function, and the like.
[Brief description of the drawings]
FIG. 1 is a schematic diagram illustrating a circuit configuration of a neuron element of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing voltage dependence (hysteresis loop) of remanent polarization of a ferroelectric film.
FIG. 3 is an equivalent circuit diagram when only the capacitor portion of the neuron element according to the first embodiment is extracted.
FIG. 4 is a diagram illustrating an example of an operation waveform when two signal input units are provided in the circuit illustrated in FIG. 1;
FIG. 5 is a schematic diagram illustrating a configuration of a neuron element that is a semiconductor device according to a first modification of the first embodiment in which a plurality of learning storage units are provided.
FIG. 6 is a schematic diagram illustrating a configuration of a neuron element that is a semiconductor device according to a second modification of the first embodiment.
FIG. 7 is a diagram showing the voltage dependence (hysteresis loop) of the remanent polarization of the ferroelectric film when a method different from that of the first embodiment is employed.
FIG. 8 is a schematic diagram illustrating a configuration of a neuron element and a control circuit that are semiconductor devices according to a third embodiment of the present invention.
FIG. 9 is a schematic diagram illustrating a configuration of a neuron element that is a semiconductor device according to a fourth embodiment of the present invention.
FIGS. 10A to 10C respectively show a configuration before switching wiring of a neuron element, which is a semiconductor device according to a modification of the fourth embodiment of the present invention, when wiring is performed in an output suppression type, in order; FIG. 2 is a schematic diagram showing the configuration when the wiring is wired in an enhanced output type.
FIG. 11 is an equivalent circuit diagram of a neuron element according to a second conventional example described in a conventional publication.
FIG. 12 is a table showing, in a table, a charge amount of each unit with respect to an input signal when a negative pulse signal is applied to a control terminal in a conventional example and a logical value of an output signal;
FIG. 13 is a table showing the amount of charge of each part with respect to an input signal when a negative pulse signal having a larger amplitude is applied to a control terminal in a conventional example in a table with a logical value of an output signal Y;
14A and 14B are a timing chart showing a temporal change of a potential of a floating gate of a neuron element according to a conventional example and a temporal change of a voltage applied to a ferroelectric film, respectively. It is a timing chart.
FIG. 15 is a simplified block circuit diagram showing a configuration of a basic unit of the brain.
FIG. 16 is a schematic diagram showing a simplified structure of a νMOS according to a conventional example.
FIG. 17 is a schematic diagram showing a configuration of a conventional neuron element described in a patent publication.
FIG. 18 is a cross-sectional view showing a conventional ferroelectric gate transistor structure described in a patent publication.
FIG. 19 is a diagram showing a correlation between an applied voltage and a tunnel current when electrons tunnel through a thermal silicon oxide film having a thickness of 10 nm.
[Explanation of symbols]
1 NMISFET
2 Source terminal
3 Drain terminal
4 Floating gate
5 Signal input section
5a Input terminal
5b Input gate electrode
5c Paraelectric film
6 Gate insulating film
7 Learning storage unit
7a Voltage terminal
7b Polarizing electrode
8 Ferroelectric film
9 Load resistance element
10 Output terminal
11 PMISFET
12 Source terminal
13 Drain terminal

Claims (10)

A semiconductor layer;
A first insulating film provided on the semiconductor layer;
A first gate electrode provided on the first insulating film;
At least one second gate electrode provided to face the first gate electrode and receiving an input signal;
At least one second insulating film interposed between the first gate electrode and the at least one second gate electrode;
A third gate electrode provided opposite to the first gate electrode;
A ferroelectric film interposed between the first gate electrode and the third gate electrode;
An output unit connected to a part of the semiconductor layer and outputting an output signal in accordance with an input signal input to the at least one second electrode;
According to the polarization characteristics of the ferroelectric film, has a learning function to strengthen or weaken the correlation between the input signal and the output signal ,
A voltage is applied to the third gate electrode in a pulsed manner,
A positive or negative pulse voltage is applied to the third gate electrode with respect to the first gate electrode,
Evaluation means for evaluating an output signal output from the output unit;
A signal generation circuit for generating a signal to be supplied to the third gate electrode according to an evaluation result of the evaluation means;
A semiconductor device further comprising: The semiconductor device according to claim 1,
A semiconductor device, wherein a constant voltage is supplied to the third gate electrode. The semiconductor device according to claim 2,
A semiconductor device, wherein a positive or negative voltage with respect to the potential of the first electrode is applied to the third gate electrode. The semiconductor device according to any one of claims 1 to 3 ,
The absolute value of the coercive voltage for inverting the polarization of the ferroelectric film is smaller than the absolute value of the threshold voltage for allowing a current to flow in a region located below the first gate electrode in the semiconductor layer. A semiconductor device characterized by having a small size. The semiconductor device according to any one of claims 1 to 3 ,
When a maximum input voltage is applied to the at least one second gate electrode within a range in which current flows in a region located below the first gate electrode in the semiconductor layer, the first gate electrode A voltage between the first gate electrode and the third gate electrode does not exceed a coercive voltage of the ferroelectric film. The semiconductor device according to any one of claims 1 to 5 ,
First and second diffusion regions formed in regions of the semiconductor layer located on both sides of the first gate electrode;
A first voltage supply unit connected to the first and second diffusion regions, and a first and second voltage supply unit for supplying first and second voltages having a height difference,
The output unit is connected to the first diffusion region;
A semiconductor device, wherein a resistive member functioning as a resistor is interposed between the output unit and the first voltage supply unit. The semiconductor device according to any one of claims 1 to 6 ,
A semiconductor device which functions as a neuron element of an arithmetic circuit. The semiconductor device according to claim 7 ,
A semiconductor device which functions as a neuron element of a logical operation circuit. The semiconductor device according to claim 8 ,
A semiconductor device, which is arranged in an artificial intelligence system for performing recognition and judgment. The semiconductor device according to any one of claims 1 to 9 ,
The same number of the at least one second gate electrode and the at least one second insulating film are provided, respectively,
A semiconductor device that outputs the output signal according to a plurality of input signals.

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