TWI793278B - Computing cell for performing xnor operation, neural network and method for performing digital xnor operation - Google Patents

Abstract

A computing cell and method for performing a digital XNOR of an input signal and weights are described. The computing cell includes at least one pair of FE-FETs and a plurality of selection transistors. The pair(s) of FE-FETs are coupled with a plurality of input lines and store the weight. Each pair of FE-FETs includes a first FE-FET that receives the input signal and stores a first weight and a second FE-FET that receives the input signal complement and stores a second weight. The selection transistors are coupled with the pair of FE-FETs.

Description

Computational cell for performing exclusive OR operation, neural network and method for performing digital exclusive OR operation

The present invention relates generally to neural networks, and more specifically to a ferroelectric field effect transistor based antimutex or cell that can be used in neuromorphic computing.

Applications involving deep learning Neural Networks (NN) or neuromorphic computing (such as image recognition, natural language processing, and more generally various pattern matching or classification tasks) are rapidly becoming like general-purpose computing As important. The basic computational element, or neuron, of a NN multiplies a set of input signals by a set of weights and sums the products. Thus, neurons perform vector-matrix product or multiply-accumulate (MAC) operations. A NN typically includes a large number of interconnected neurons, each of which performs a MAC operation. Therefore, the operation of NN is computationally intensive.

The performance of the NN can be improved by improving the efficiency of the MAC operation. It would be desirable to store weights locally to reduce dynamic random access memory (DRAM) access power and frequency. It may also be desirable to perform the MAC operation digitally to help reduce noise and process variability. Binarized neurons may be able to meet these goals. Therefore, a binarized weighted antimutual exclusion or network (XNORNet) has been developed.

，或以布林法被表達為sum =2Count(XNOR(w,x))-n 。計數運算對反互斥或表達式的非零結果的數目進行計數，其中n是神經元的輸入的總數。然後，對照偏差（bias）對結果進行定限（threshold），進而得到神經元的高態輸出或低態輸出。整個過程是數位的。因此，不會招致與類比處理相關聯的資訊丟失。In a binarized anti-exclusive OR (XNOR) cell, weights w are mathematically 1 and -1, but are digitally represented as 1 and 0. Likewise, the signal x is mathematically 1 and -1, but is represented digitally by 1 and 0. The result of the multiplication operation p _i = w _i x _i is only positive if both x and w are 1 and both are mathematically -1 (0 in Boolean representation). This is exactly the logical NOT of the exclusive OR operation (inverse exclusive OR). Therefore, the product of individual weights and signals can be expressed as p _i = XNOR ( w _i , x _i ). The complete MAC operation for a given neuron is expressed as

, or expressed as sum = 2Count(XNOR(w,x))-n in Boolean's method. The count operation counts the number of non-zero outcomes of the inverse mutex or expression, where n is the total number of inputs to the neuron. Then, the result is thresholded against the bias (bias), and then the high-state output or low-state output of the neuron is obtained. The whole process is digital. Therefore, no loss of information associated with analog processing is incurred.

However, the use of weighted binarized representations can be a source of information loss. Binarized networks typically use substantially more neurons than analog (or multi-bit digital) networks to achieve the same level of overall accuracy. Significant improvements can be achieved if the weights are ternarized rather than binarized. The ternarization weights take mathematical values -1, 0, and 1. A weight of 0 produces an output of -1 (logical 0) for any combination of inputs. Thus, the output of a ternary demutual exclusive OR gate (also known as "Gated XNOR") is given by:

When performing an exclusive OR operation with the above equation, non-zero weights and all signals from the {-1, 1} domain are mapped to the {0, 1} Bollinger domain. The mapping is performed after branching based on the mathematical value of the weights.

Ternarized networks may provide improved accuracy over binarized networks when using the same number of neurons. Alternatively, a ternarized network can achieve the same level of accuracy as a binarized network, but with a smaller number of neurons. This results in savings in area, power and inferential throughput and latency. Therefore, both binarized digital demutual exclusion or network and ternary digital demutual exclusion or network can be used in applications such as NN. There is a need for an improved anti-mutual exclusion or logic cell to enhance digital binarization NN operations and/or digital ternary NN operations or other logic operations.

According to some embodiments, a computation cell for performing an exclusive OR operation on input signals and weights includes at least one pair of ferroelectric field-effect transistors (FE-FETs), and a plurality of input lines coupling and storing the weight, each pair of FE-FETs in the at least one pair of FE-FETs includes a first FE-FET and a second FE-FET, and the first FE-FET receives the input signal and stores a first weight, the second FE-FET receives the complement of the input signal and stores a second weight; and a plurality of selection transistors coupled to the pair of FE-FETs.

Exemplary embodiments are related to digital computing cells that perform exclusive OR operations and are useful in a variety of fields including, but not limited to, machine learning, artificial intelligence, neuromorphic computing, and neural networks. The methods and systems can be extended to other applications in which logic devices are used. The following description is presented to enable one of ordinary skill in the art to make and use the invention, and is provided in the context of a patent application and its claims. Various modifications to the exemplary embodiments and general principles and features described herein will be readily apparent. The exemplary embodiments are described primarily in terms of specific methods and systems provided in specific implementations. However, in other embodiments, the methods and systems will operate efficiently.

Phrases such as "exemplary embodiment," "one embodiment," and "another embodiment" can refer to the same embodiment or different embodiments as well as multiple embodiments. Embodiments will be described with reference to systems and/or devices having certain components. However, the systems and/or devices may include more or fewer components than shown, and changes may be made in the configuration and type of components without departing from the scope of the invention. Various exemplary embodiments will also be described in the context of particular methods having certain steps. However, the methods and systems operate effectively with other methods having different and/or additional steps and steps in a different order not inconsistent with the exemplary embodiments. Thus, the present invention is not intended to be limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and features described herein.

Unless otherwise indicated herein or clearly contradicted by context, the terms "a and an" and "the (the)" and similar pronouns should be construed to cover both singular and plural forms. Unless otherwise stated, the terms "comprising, including", "having" and "containing" should be construed as open-ended terms (ie, meaning "including, but not limited to).

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It should be noted that the use of any and all examples, or exemplary terms, provided herein is intended merely to better clarify the invention and is not intended to limit the scope of the invention unless otherwise specified. Furthermore, all terms defined in common dictionaries should not be unduly interpreted unless otherwise defined.

The present invention describes a computational cell and method for performing a digital inverse exclusive OR of input signals and weights. The calculation cell includes at least one pair of FE-FETs and a plurality of selection transistors. The one (multiple) pairs of FE-FETs are coupled to a plurality of input lines and store the weights. Each pair of FE-FETs in the at least one pair of FE-FETs includes: a first FE-FET receiving the input signal and storing a first weight; and a second FE-FET receiving a complement of the input signal And store the second weight. The select transistor is coupled to the pair of FE-FETs.

FIG. 1 is a block diagram illustrating an exemplary embodiment of a digital anti-mutex or computation cell 100 . For simplicity, only a portion of the anti-mutex or cell 100 is shown. The calculation cell 100 digitally performs an exclusive OR operation on input signals and weights. Therefore, the computational cell 100 may be considered a neuromorphic computational cell. In addition, the calculation cell 100 can perform a binary demutual exclusive OR operation or a ternary demutual exclusive OR operation.

The computing cell 100 includes at least two ferroelectric field effect transistors (FE-FETs) 110 and 120 , a select transistor 130 and an optional reset transistor 140 . Also shown are input lines 102 and 104 as well as output lines 106 and select lines 108 . Input lines 102 and 104 respectively receive the input signal and its complement for inference operations. Output line 106 provides the result of the exclusive OR operation. For example, if the computation cell 100 is part of a neural network (NN), the selection line 108 may be used to select the computation cell 100 to perform operations on.

The computing cell 100 includes at least two FE-FETs 110 and 120 . In other embodiments, more than two FE-FETs may be used, but at the expense of cell density. In other embodiments, each computing cell includes only two FE-FETs 110 and 120 . Each of FE-FETs 110 and 120 includes a ferroelectric layer (not explicitly shown in FIG. 1 ), which typically resides between two metal layers, and a transistor (eg, a FET), thereby form a ferroelectric capacitor. In alternative embodiments, the ferroelectric layer may replace the gate oxide. The ferroelectric layer stores the weight by the polarization state of the ferroelectric layer. For example, the ferroelectric layer may include lead zirconate titanate (PbZrTi), hafnium zirconium oxide (HfZrO), barium titanate (BaTiO ₃ ), bismuth titanate (B ₁₂ TiO ₂₀ ), germanium telluride (GeTe) and Ba At least one of _x Eu _1-x TiO ₃ , where x is greater than 0 and not greater than 1. In other embodiments, another and/or additional ferroelectric material may be used.

In operation, reset-evaluate logic may be used. Thus, storage nodes 150 may be reset at the beginning of an inference operation (ie, an exclusive OR operation using previously programmed weights). To perform inference operations, an input x and its complement x_bar are provided to FE-FETs 110 and 120 via input lines 102 and 104, respectively. The polarization of the ferroelectric layers within FE-FETs 110 and 120 varies based on the weights programmed into FE-FETs 110 and 120 . During an inference operation, a selective pull-up is performed on the dynamic storage node 150 . Then, the dynamic storage node voltage can be output via the output line 106 to evaluate or provide the result of the exclusive OR operation. Accordingly, FE-FETs 110 and 120 are connected such that output line 106 provides an inverse exclusive OR of input signal x and weight w stored by FE-FETs 110 and 120 . The selection transistor 130 selects the anti-mutually exclusive OR cell 100 for operation. The optional reset transistor 140 can be used to explicitly reset the computation cell 100 to perform a binarization operation, for example. In other embodiments, the reset operation may be performed in another manner. Therefore, the computation cell 100 can be used in a binarization mode or a binarization mode.

Computational cells 100 can efficiently implement exclusive OR operations and can be implemented in a relatively compact manner. Since the operation is digital, problems with analogous exclusive OR operations are reduced or eliminated. For example, the use of digital weights provides stylized robustness for FE-FETs 110 and 120 . Digital operations may also cause less noise for the output 106 . The use of an analog to digital converter (ADC) can be avoided, and power and area can also be saved. The weights are also stored locally in FE-FETs 110 and 120 used as non-volatile memory. Inference operations can be made more efficient and faster. As described below, the computation cell 100 may provide a binary or ternary demutual exclusive OR. Therefore, the computing cell 100 can digitally efficiently and reliably perform the exclusive OR operation.

FIG. 2 is a block diagram illustrating an exemplary embodiment of a portion 180 of a digital neural network. Section 180 can be considered a neuron. Neuron 180 performs a multiply-accumulate (MAC) operation. Neuron 180 illustrates a possible use of computational cell 100 and is not intended to be limiting.

Neuron 180 includes a plurality of computing cells 100-1, 100-2, 100-3, and 100-4 (collectively referred to as computing cells 100), and a bit count and sign block 190 . In this embodiment, it is desired to combine four inputs x1/x1_bar, x2/x2_bar, x3/x3_bar and x4/x4_bar with four weights. Therefore, four compute cells 100 are used to perform four inverse exclusive OR operations. In alternative embodiments, another number of computing cells 100 may be used. Each of computing cells 100-1, 100-2, 100-3, and 100-4 shown in FIG. 2 operates in a similar manner as computing cell 100 shown in FIG. The bit count and sign block 190 counts and subtracts 4 (ie, the number of input signals to neuron 180 ) the number of non-zero results from the four demutes or cells 100 . Then, the result is qualified against the deviation, and then the high state output or the low state output of the neuron 180 is obtained.

Therefore, the neuron 180 using the computation cell 100 can perform a MAC operation. Because neuron 180 uses cells implemented in hardware, neuron 180 operates efficiently. MAC operations can be performed digitally, which avoids problems with analogous exclusive OR operations. As described with reference to FIG. 1 , the exclusive OR operation performed by the compute cell 100 can also be compact, efficient, and run in binarization mode or ternarization mode. Accordingly, the performance of neurons 180 may be improved.

FIG. 3 is a schematic diagram of an exemplary embodiment of a computing cell 100A for performing a digital exclusive OR operation. Computation cell 100A is similar to anti-mutex or cell 100 and may be used in neuron 180 or other applications. Accordingly, portions of computation cell 100A that are similar to components in antimutex or cell 100 are similarly labeled. Thus, anti-mutual exclusion or cell 100A includes input lines 102 and 104, FE-FETs 110A and 120A, select transistors 132 and 134 , output line 106 and select line 108 . Also shown is a dynamic output node 150 and stylized lines 152 and 154 . In the illustrated embodiment, select transistors 132 and 134 are n-FETs. FE-FETs 110A and 120A are shown to include FETs 112 and 122, respectively, and to include ferroelectric capacitors 114 and 124, respectively, having ferroelectric layers. For example, FIG. 4 depicts an exemplary embodiment of a portion of a FE-FET 110A/120A that may be used in a computational cell that performs a digital exclusive OR operation. FE-FET 110A/120A includes FET 112/122 and capacitor 114/124. The dielectric layer 116/126 may include one or more of PbZrTi, HfZrO, _BaTiO3 , _B12TiO20 , _GeTe , and _{BaxEu1 -xTiO3 ,} where x is greater than zero and not greater than one. In some embodiments, the ferroelectric layer 116/126 is incorporated into the first metal (M1) layer. In other embodiments, the ferroelectric layer 116/126 may be incorporated into other layers.

Input lines 102 and 104 carry the input signal x and its complement x_bar, respectively. Input lines 102 and 104 are connected to the sources of FE-FETs 110A and 120A, respectively. The gates of FE-FETs 110A and 120A are connected to programming lines 152 and 154 via select transistors 132 and 134, respectively. The programming lines 152 and 154 respectively provide the programming signal P and its complement P_bar. The drains of the FE-FETs are coupled together and form the dynamic output node 150 . The sources of select transistors 132 and 134 are connected to FE-FETs 110A and 120A, respectively, the drains of select transistors 132 and 134 are connected to programming lines 152 and 154, respectively, and the gates of select transistors 132 and 134 are connected to Select line 108.

As mentioned above, the weights stored in FE-FETs 110A and 120A are determined by the polarization of ferroelectric layers 114 and 124 . These weights can be trained off-chip. For example, if the intended application of the compute cell 100A is inference only (off-chip training), then the erase and program operations are performed infrequently. Thus, FE-FETs 110A and 120A may only be programmed when it is desired to change weights. In some embodiments, for example, to allow for improvements in off-wafer training, this stylization may only occur a few times per year. In alternative embodiments, FE-FETs 110A and 120A may be programmed more or less frequently.

The weights programmed into FE-FETs 110A and 120A depend on whether computation cell 100A is desired to be used in binarized mode or in binarized mode. The states stored in the two FE-FETs 110A and 120A may be complements for non-zero weights or may be equal for zero weights (eg, setting a high Vt state for both). The use of zero weights may occur for ternary operations or zero weights.

To program the weights, the calculation cell 100A is first erased and then programmed. If present in the form of an array, all computational cells 100 in the entire array can first be globally erased, and then individual non-zero bits can be programmed. To erase cell 100A (and all cells in the array), the signals P and P_bar on programming lines 152 and 154 are set low (eg, to ground), and the signals on input lines 102 and 104 are set to The inputs x and x_bar are set to a high state. The output line 106 of the compute cell 100A is allowed to float. The result is that in cell 100A and in the array, there is a negative voltage across ferroelectric capacitor 114 in each FE-FET 110A and ferroelectric capacitor 124 in each FE-FET 120A. At the end of erase, each FE-FET 110A and 120A has a small, zero, or slightly negative voltage at the node of the gates of the primary FETs 112 and 122 in FE-FETs 110A and 120A. This places all FE-FETs 110A and 120A in a low-conductivity state.

FIG. 5 is a stylized timing diagram 200 illustrating an exemplary embodiment of a computational cell performing a digital exclusive OR operation. In the embodiment shown in FIG. 5, the programming lines 152 and 154 are pulsed to a moderately high voltage, such as 2.5 volts (V) to 3 volts. Referring to FIGS. 3 and 5 , the solid line 202 represents the voltage applied to the programmed lines 152 and 154 , and the dotted line 204 represents the input voltage x or x_bar on the input lines 102 and 104 . Dashed line 206 is the voltage at the gates of FETs 112 and 122 of FE-FETs 110A and 120A during the erase process. The applied voltages to the left of vertical line 209 represent applied voltages that can erase FE-FETs 110A and 120A. Wiping is done at line 209 . Thus, just to the right of line 209, the voltage at the node of the gates of FE-FETs 110A and 120A is small. Therefore, both FE-FETs 110A and 120A have been erased to a low gate voltage.

After the erase is complete, FE-FETs 110A and 120A can be programmed. The programmed events set individual bits representing the mathematical weights stored by FE-FETs 110A and 120A. If ternarization is desired, only non-zero weights are programmed. Programming is achieved by grounding signal input lines 102 and 104 (x, x_bar are low) and applying high voltage to programming line 152 (P is high) or programming line 152 (P_bar is high) . Select line 108 is turned on for each computational cell 100A being programmed. A high voltage on programming line 152 or 154 causes a positive voltage to exist across ferroelectric capacitor 114 in each FE-FET 110A or ferroelectric capacitor 124 in each FE-FET 120A, respectively. Therefore, a change in the polarization state is caused. The gate node of each FE-FET is now programmed to a high positive voltage, thereby setting the base FET into an on-state. In FIG. 5, the gate voltage of the final programmed state of FE-FET 110A (which can store weights) is shown by dashed line 207, while the final programmed state of FE-FET 120A (which can store weight complements) is shown by The gate voltage for the ON state is shown by dashed line 208 . Thus, one or both of FE-FETs 110A and 120A can be programmed. In FIG. 5 , the gate voltages 207 and 208 are different. In some embodiments, the resulting voltage difference between the on-state FET and the off-state FET is approximately 500 millivolts (mV). This may correspond to a typical 7 nanometer (nm) node FET. The voltage difference can be increased significantly by improving the ratio of ferroelectric to non-ferroelectric polarization of ferroelectric capacitors 114 and 124 . For example, thicker ferroelectric capacitors/thicker ferroelectric layers 116/126 with stronger ferroelectric polarization may be used. Therefore, erase-program can be used to program weights into FE-FETs 110A and 120A.

To perform inference operations, an input x and its complement x_bar are provided on input lines 102 and 104, respectively. Select line 108 is driven low. Therefore, the gates of FE-FETs 110A and 120A are allowed to float. The gates of FE-FETs 110A and 120A are allowed to float to allow gate voltages to exceed the supply voltage during inference operations and to provide full output swing. It is desirable to minimize or reduce the difference in ferroelectric voltage to suppress read disturbance. The output of the computation cell 100A (the inverse exclusive OR of the input x and the weight) may be generated on the storage node 150 . Therefore, inference operations can be performed. The time for performing inference operations can also be kept small. For example, FIG. 6 is a diagram 210 illustrating the timing of an inference operation of an exemplary embodiment of a computation cell performing a digital exclusive OR operation. Dashed line 212 indicates the transition of input x on input line 102 from a low state to a high state. Dashed line 214 and dotted line 216 indicate the voltages developed on the gates of FE-FETs 110A and 120A (ie, the gates of transistor 112 and the gates of transistor 122 ) during inference operations. As can be seen in Figure 6, settling to the final voltage can occur in less than 0.1 nanoseconds (ns).

Therefore, the computing cell 100A may have improved performance. Compute cell 100A may utilize only two FE-FETs 110A and 120A in combination with two select n-type FETs (nFETs) 132 and 134 . Thus, the computing cell 100A may be compact. Since FE-FETs 110A and 120A can be programmed digitally, the programming can be robust. The weights are stored locally by the polarization of the ferroelectric layer 116/126. Time and power are saved because access weights from off-die DRAM are not required. Since the compute cell 100A can digitally perform an inverse OR (deduction) operation, the output generated on the storage node 150 can exhibit reduced noise compared to an analog implementation. Furthermore, inference operations are performed quickly and efficiently. Compute cell 100A may be robust to read disturbs. The gate nodes (top nodes of ferroelectric capacitors 114 and 124) of each FE-FET float during inference. Thus, the corollary event asserts an extremely small voltage across the ferroelectric capacitor 114/124 itself. Furthermore, this small voltage increment occurs on a much smaller timescale than the ferroelectric polarization response of standard ferroelectric materials. As described above with reference to FIG. 6, the inference time can reasonably be kept below 0.1 nanoseconds. This time scale can be much smaller than the time of ferroelectric response of standard ferroelectric materials. This is because it is expected that the ferroelectric polarization does not change during the inference operation. This response time is about two orders of magnitude faster than the PbZrTi response and at least several orders of magnitude faster than the HfZrO response. Therefore, no change in polarization of the ferroelectric layer 116/126 is expected. Therefore, repeated corollary events may have little effect on the gate node voltages in FE-FETs 110A and 120A. This indicates that the polarization state of the ferroelectric layer 116/126 has not changed. Therefore, inference/read operations may not disturb the programmed states of FE-FETs 110A and 120A.

The calculation cell 100A can also be used in the ternary operation. For ternarization, use the full set of weights {1, 0, -1}. For zero weight, the computation cell 100A is not programmed after the erase described above. In other words, the erase-program operation is simply accomplished by erasing the computing cell 100A. However, there is a possibility that charge accumulation occurs at the storage node 150 due to back and forth. This may occur because the natural discharge rate of dynamic storage node 150 is low compared to the deduced rate when both FE-FETs 110A and 120A are off, which is the case for zero weight. To prevent this charge accumulation from occurring, an explicit reset is performed before each inference of the ternarization operation. In an anti-mutual exclusion or net situation, the initial ground state of x and x_bar of input lines 102 and 104 is sufficient to discharge storage node 150 by FeFET 110A and/or 120A.

In one embodiment, the computing cell 100A may be used without any additional transistors or interconnect lines. In such an embodiment, storage node 150 is discharged through FE-FETs 110A and 120A. However, the conduction of FE-FETs 110A and 120A is increased by applying a high voltage to programming lines 152 and 154, respectively, while select transistors 132 and 134 are on. The increase in gate voltage on FE-FETs 110A and 120A makes normally-off FE-FETs 110A and 120A temporarily more conductive. This higher conductance of FE-FETs 110A and 120A enables storage node 150 to be discharged quickly. While this approach works, a high voltage pulse is applied to the stylized lines 152 and 154 at each inference. This causes increased power and voltage stress on select transistors 132 and 134, which would otherwise be stressed very infrequently. Alternatively, different embodiments of computing cells may be used.

FIG. 7 illustrates another exemplary embodiment of a computation cell 100B for performing a digital exclusive OR operation with an explicit reset operation. Computation cell 100B is similar to antimutex OR cell 100 and computation cell 100A. Therefore, the computational cell 100B can be used in the neuron 180 or other applications. Accordingly, portions of computing cell 100B that are similar to components in cells 100/100A are similarly labeled. Computational cell 100B thus includes input lines 102 and 104 similar to input lines 102 and 104, FE-FETs 110/110A and 120/120A, select transistors 130/132 and 134, output line 106, and select line 108, respectively. FE-FETs 110B and 120B, select transistors 132 and 134 , output line 106 and select line 108 . Also shown is a dynamic output node 150 and stylized lines 152 and 154 similar to those shown in FIG. 3 . Select transistors 132 and 134 are n-FETs. FE-FETs 110B and 120B include FETs 112 and 122, respectively, and include ferroelectric capacitors 114 and 124, respectively, having ferroelectric layers. FETs 112 and 122 and ferroelectric capacitors 114 and 124 are similar to those shown in FIG. 3 . The dielectric layer (not shown in FIG. 7 ) may include one or more of PbZrTi, HfZrO, BaTiO ₃ , B ₁₂ TiO ₂₀ , GeTe, and Ba _x Eu _1-x TiO ₃ , where x is greater than 0 and not greater than 1. Components 102 , 104 , 106 , 108 , 110B, 112 , 114 , 120B, 122 , 124 , 132 , 134 , 150 , 152 , and 154 are similar in structure and function to like-numbered components in FIGS. 2-4 .

The computing cell 100B also includes a reset transistor 140 (which can be an n-FET) and a reset line 142 . Reset transistor 140 has its gate coupled to reset line 142 and its source coupled to ground. To erase FE-FETs 110B and 120B, reset line 142 is set low, programming lines 152 and 154 are pulsed low, and input lines 102 and 104 are set high. For inference/inverse exclusive-or operations, reset FET 140 is turned on by energizing reset line 142 before applying inputs x and x_bar on input lines 102 and 104, respectively. Thus, use of reset transistor 140 discharges storage node 150 . Then, the inputs x and x_bar can be applied, and an inference operation can be performed. Therefore, when the computing cell 100B is used in the ternary mode, the above-mentioned high voltage can be avoided. The choice between using the smaller compute cell 100A with a high voltage applied to the programmed lines 152 and 154 and using the larger compute cell 100B with the reset FET 140 depends on the goals and technical constraints. But do not use high voltage.

8 is a flowchart illustrating an exemplary embodiment of a method for performing an exclusive OR operation using an exemplary embodiment of a hardware cell. For simplicity, some steps may be omitted, performed in another order, and/or combined. Method 300 is also described in the context of demutual exclusion or cells 100/100A/100B. However, method 300 may be used in conjunction with another anti-mutex or computation cell.

By step 302, weights are programmed into FE-FETs 110/110A/110B and 120/120A/120B. Accordingly, step 302 may be performed as described above. For example, step 302 may include erasing the computing cell 100/100A/100B, followed by a programming step. Although shown as part of process 300 , step 302 may be performed well before and disconnected from the remaining steps of method 300 .

Reset line 142 is driven high and then low to energize reset transistor 140 as desired, via step 304 . Step 304 is performed for the computing cell 100B. Alternatively, FE-FETs 110A and 120A may be reset by an applied voltage. By step 306, the signal and its complement are received. Step 306 may include receiving x_value and x_value_bar in input lines 102 and 104, respectively. Inference operations are performed as described above. Then, by step 308, the result of the inverse exclusive OR operation can be forwarded.

Thus, using method 300, antimutex or cells 100, 100A, 100B, and/or similar devices may be used. Accordingly, anti-mutual exclusion or the advantages of one or more of cells 100, 100A, 100B, and/or similar devices may be achieved. A method and system have been described for performing digital de-OR operations using compact FE-FET computation cells 100/100A/100B in binarization mode or ternarization mode. The methods and systems have been described in terms of the exemplary embodiments shown, and those of ordinary skill in the art will readily recognize that changes can be made to the various embodiments and that any changes will be within the scope of the methods and systems described. spirit and range. Accordingly, numerous modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

100: digital anti-mutual exclusion or calculation cell / anti-mutual exclusion or cell / calculation cell 100-1, 100-2, 100-3, 100-4: Computing cells 100A: Computation Cell/Demutual Exclusion or Cell/Cell/Compact FE-FET Computation Cell 100B: Computation Cell / Antimutex or Cell / Compact FE-FET Computation Cell 102, 104: input line/signal input line/component 106:Output line/output/component 108:Select line/component 110, 110A, 120, 120A: FE-FET 110B, 120B: FE-FET/component 112, 122: FET/transistor/component 114, 124: Ferroelectric capacitors/capacitors/ferroelectric layers/components 116, 126: dielectric layer/ferroelectric layer 130:Select Transistor 132, 134: select transistor/select nFET/component 140: reset transistor / reset FET 142: reset line 150:Storage Node/Dynamic Storage Node/Dynamic Output Node/Component 152, 154: Stylized lines/components 180: Part of a digital neural network/neuron 190:Bit Count and Sign Block 200, 210: timing diagram 202: solid line 204, 216: point line 206, 207, 208, 212, 214: dashes 209: vertical line 300: method/process 302, 304, 306, 308: steps P: stylized signal/signal P_bar: Complement/signal of programmed signal x: input/input voltage x1, x1_bar, x2, x2_bar, x3, x3_bar, x4, x4_bar: input x_bar: complement of input/input voltage/input

FIG. 1 is a block diagram illustrating an exemplary embodiment of a digital antimutex or computation cell. FIG. 2 is a block diagram illustrating an exemplary embodiment of a portion of a neural network that includes a plurality of demutual exclusion or computation cells and performs a multiply-accumulate operation. FIG. 3 illustrates an exemplary embodiment of a computation cell for performing a digital exclusive OR operation. Figure 4 illustrates an exemplary embodiment of a portion of a FE-FET that may be used in a computational cell that performs a digital exclusive OR operation. 5 is a stylized timing diagram illustrating an exemplary embodiment of a computation cell performing a digital exclusive OR operation. 6 is a diagram illustrating the timing of an inference operation of an exemplary embodiment of a computation cell performing a digital exclusive OR operation. FIG. 7 illustrates another exemplary embodiment of a computation cell for performing a digital exclusive OR operation. FIG. 8 is a flowchart illustrating an exemplary embodiment of a method for performing an exclusive OR operation using an exemplary embodiment of a compute cell.

100: digital anti-mutual exclusion or calculation cell / anti-mutual exclusion or cell / calculation cell

102, 104: input line/signal input line/component

106:Output line/output/component

108:Select line/component

110, 120: FE-FET

130:Select Transistor

140: reset transistor / reset FET

150:Storage Node/Dynamic Storage Node/Dynamic Output Node/Component

x: input/input voltage

x_bar: complement of input/input voltage/input

Claims (19)

A computational cell for performing an inverse exclusive OR operation on input signals and weights, comprising: at least one pair of ferroelectric field effect transistors coupled to a plurality of input lines and storing the weights, the at least one pair of ferroelectric field effect transistors The transistor includes a first ferroelectric field effect transistor and a second ferroelectric field effect transistor, the first ferroelectric field effect transistor receives the input signal and stores the first weight, and the second ferroelectric field effect transistor receives the input signal The complement of the input signal and store the second weight, the first ferroelectric field effect transistor is coupled with the second ferroelectric field effect transistor to form a dynamic storage node; a plurality of selection transistors, and the at least one pair a ferroelectric field effect transistor coupled; a reset transistor having a reset transistor source, a reset transistor gate and a reset transistor drain, the reset transistor source being connected to the dynamic storage node, The reset transistor gate is coupled to a reset line. The computing cell as described in item 1 of the scope of the patent application, wherein the multiple selection transistors include a first selection transistor and a second selection transistor, and the first selection transistor and the second selection transistor Each of them includes a gate, a source and a drain, the source of the first select transistor is connected to the first gate of the first ferroelectric field effect transistor, the second select transistor The source of the crystal is connected to the second gate of the second ferroelectric field effect transistor, and the gate of the first selection transistor and the gate of the second selection transistor are coupled to Select the line. The computing cell as described in item 2 of the scope of the patent application, wherein the drain of the first selection transistor is coupled to a programming line, and the second selection transistor The drain of is coupled to a programmed complement line. The computing cell as described in item 1 of the scope of the patent application, wherein the first ferroelectric field effect transistor includes a first drain and a first source, and the first source is connected to the plurality of input lines The first input line is coupled, and wherein the second ferroelectric field effect transistor includes a second source and a second drain, and the second source is coupled to a second input line among the plurality of input lines, so The second drain is coupled to the first drain to provide the dynamic storage node. The computing cell as described in item 1 of the scope of the patent application, wherein the first ferroelectric field effect transistor includes a first ferroelectric material, the second ferroelectric field effect transistor includes a second ferroelectric material, and the first ferroelectric field effect transistor includes a second ferroelectric material. A ferroelectric material and the second ferroelectric material include at least one of PbZrTi, HfZrO, BaTiO ₃ , B ₁₂ TiO ₂₀ , GeTe and Ba _x Eu _1-x TiO ₃ , where x is greater than 0 and not greater than 1. The computing cell described in claim 1 of the present invention, wherein the first weight and the second weight are complements of each other when the weight is non-zero and equal when the weight is zero. The computing cell as described in item 1 of the scope of the patent application, wherein the at least one pair of ferroelectric field effect transistors is composed of the first ferroelectric field effect transistor and the second ferroelectric field effect transistor, and the The multiple selection transistors are composed of a first selection transistor and a second selection transistor. A neural network comprising: a plurality of input lines; a plurality of anti-mutually exclusive or cells, each of said plurality of anti-mutually exclusive or cells for performing a digital demutual exclusive OR operation on the input signals and weights, each of the plurality of demutual exclusive OR cells comprising at least one pair of ferroelectric field effect transistors, a plurality of select transistors, and a reset transistor, so The plurality of selection transistors are coupled to the at least one pair of ferroelectric field effect transistors, the reset transistors have a reset transistor source, a reset transistor gate, and a reset transistor drain, and the at least A pair of ferroelectric field effect transistors is coupled to a part of the plurality of input lines and stores the weight, the at least one pair of ferroelectric field effect transistors includes a first ferroelectric field effect transistor and a second ferroelectric field effect transistor, The first ferroelectric field effect transistor receives the input signal and stores a first weight, the second ferroelectric field effect transistor receives a complement of the input signal and stores a second weight, and the first ferroelectric field effect transistor A transistor is coupled to the second FFET to form a dynamic storage node, a source of the reset transistor is connected to the dynamic storage node, and a gate of the reset transistor is coupled to a reset line. The neural network as described in item 8 of the scope of the patent application, wherein the multiple selection transistors include a first selection transistor and a second selection transistor, and the first selection transistor and the second selection transistor Each of them includes a gate, a source and a drain, the source of the first select transistor is connected to the first gate of the first ferroelectric field effect transistor, the second select transistor The source of the crystal is connected to the second gate of the second ferroelectric field effect transistor, and the gate of the first selection transistor and the gate of the second selection transistor are coupled to a selection line, the drain of the first selection transistor is coupled to a programming line, and the drain of the second selection transistor is coupled to a programming complement line, and wherein the at least one pair of iron The electric field effect transistor is composed of the first ferroelectric field effect transistor and the second ferroelectric field effect transistor become. The neural network described in item 9 of the scope of the patent application, wherein the first ferroelectric field effect transistor includes a first drain and a first source, and the first source is connected to the plurality of input lines The first input line is coupled, and wherein the second ferroelectric field effect transistor includes a second drain and a second source, and the second source is coupled to a second input line among the plurality of input lines, so The first drain is coupled to the second drain to form the dynamic storage node. The neural network described in item 10 of the scope of the patent application further includes: a plurality of reset lines, each of the plurality of reset lines is connected with at least one of the plurality of antimutual exclusion or cells or the reset transistor gate coupling. The neural network described in item 8 of the scope of the patent application, wherein the first ferroelectric field effect transistor includes a first ferroelectric material, the second ferroelectric field effect transistor includes a second ferroelectric material, and the first ferroelectric field effect transistor includes a second ferroelectric material. a ferroelectric material and said second ferroelectric material include at least one of PbZrTi, HfZrO, BaTiO ₃ , B ₁₂ TiO ₂₀ , GeTe, and Ba _x Eu _1-x TiO ₃ , where x is greater than zero and not greater than 1, And wherein the first ferroelectric material and the second ferroelectric material are integrated at the first metal layer or higher of the neural network. A method for performing a digital exclusive OR operation comprising: providing an input signal and a complement of the input signal to an exclusive OR cell for performing a digital exclusive OR operation on the input signal and weights The anti-mutual exclusion or cell includes at least one pair of ferroelectric field effect transistors, a plurality of selection transistors and reset transistors, and the plurality of selection transistors are coupled to the at least one pair of ferroelectric field effect transistors , The at least one pair of ferroelectric field effect transistors is coupled to a plurality of input lines and stores the weight, the at least one pair of ferroelectric field effect transistors includes a first ferroelectric field effect transistor and a second ferroelectric field effect transistor, so The first ferroelectric field effect transistor receives the input signal and stores the first weight, the second ferroelectric field effect transistor receives the complement of the input signal and stores the second weight, and the first ferroelectric field effect transistor a crystal coupled to the second ferroelectric field effect transistor to form a dynamic storage node, the reset transistor has a reset transistor source, a reset transistor gate and a reset transistor drain, the reset transistor The source of the transistor is connected to the dynamic storage node, and the gate of the reset transistor is coupled to a reset line. The method described in item 13 of the scope of the patent application, wherein the multiple selection transistors include a first selection transistor and a second selection transistor, and the at least one pair of ferroelectric field effect transistors is controlled by the first ferroelectric field effect transistor and the second ferroelectric field effect transistor, each of the first selection transistor and the second selection transistor includes a gate, a source and a drain, and the first selection The source of the transistor is connected to the first gate of the first ferroelectric field effect transistor, and the source of the second selection transistor is connected to the second gate of the second ferroelectric field effect transistor. gate, the drain of the first selection transistor is coupled to the programming line, the drain of the second selection transistor is coupled to the programming complement line, and the drain of the first selection transistor is coupled to the programming line. The gate and the gate of the second selection transistor are coupled to a selection line, and the method further includes: programming the first weight and the second weight to the first FFET crystal and the second ferroelectric field effect transistor, programming the first weight and the The step of said second weighting further includes: by setting said stylized line to ground, setting said stylized complement line to said ground, setting said select line to high state, setting said plurality of an input line and an input complement line of the input lines are set to the high state to erase the first ferroelectric field effect transistor and the second ferroelectric field effect transistor; and after the erasing step, The second is configured by setting the input line to the ground, setting the input complement line to the ground, setting the select line to the high state, and one of the following Writing to a ferroelectric field effect transistor and said second ferroelectric field effect transistor: applying a pulse to said programmed line, applying a pulse to said programmed complement line, and not writing to said programmed line and said Either of the stylized complement lines applies a pulse. The method according to claim 14, wherein the programming step uses a non-negative voltage. As for the method described in claim 14, wherein the step of providing the input signal further includes: implementing a resetting step and an evaluating step. The method described in item 16 of the scope of patent application, wherein the first ferroelectric field effect transistor includes a first drain and a first source, and the first source is connected to the first of the plurality of input lines Input line coupling, wherein the second ferroelectric field effect transistor includes a second source and a second drain, the second source is coupled to a second input line among the plurality of input lines, and the second A drain is coupled to the first drain to provide the dynamic storage node, and the method further includes: The reset line is pulsed prior to the evaluating step. The method of claim 16, further comprising: prior to said evaluating step, pulsing said stylized line, said stylized complement line, and said select line in a high state. The method described in item 14 of the scope of patent application, wherein the step of providing the input signal further includes: setting the selection line to a low state; while the selection line is in a low state, the input The input signal is provided on a line and the complement of the input signal is provided on the input complement line.

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