JP3659941B2 - Microprocessor and processing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microprocessor having a register cache that caches contents (hereinafter referred to as register values) stored in a register file (register group), and saving (saving) register values between the register file and the register cache. ) And restoration (restore).
[0002]
[Prior art]
Generally, a microprocessor is provided with a register file. The register file stores a plurality of register values. Among the register values, a register value used for an operation in the execution unit of the microprocessor is called a source register.
[0003]
As the source registers used in the instruction set increase, the register file becomes larger. An instruction set is a set of instructions used in a microprocessor. The register file needs to be multi-ported due to the performance requirements of the execution unit. There is a problem of cost increase and performance degradation due to the large register file.
[0004]
As a means for solving this problem, a microprocessor is known in which a register file is reduced in number of ports and a part of the port is restored to a multi-port register cache. Note that the port is the number of source registers that can be simultaneously read and written by some means of the microprocessor.
[0005]
As shown in FIG. 5, the configuration of the microprocessor 50 includes a register file 12 in which a plurality of register values including a plurality of source registers 11 are stored, an instruction, and a source An instruction control / issue unit 14 that issues the address of the register 11 and the destination register that is the result of the operation, an execution unit 16 that receives the instruction and executes the instruction, and a register cache 18 in which the source register 11 is restored And including.
[0006]
However, the task of saving / restoring the register cache occurs due to task switching due to an interrupt or the like. That is, it is necessary to save the contents of the register cache (current task context) to the register file 12. In general, these series of operations are performed after the program execution of the microprocessor 50 is stopped, so that the execution performance of the program is lowered.
[0007]
As a method of reducing a miss penalty, which is the time from saving / restoring of the source register 11 in the register cache 18 to the start of program execution, the register cache 18 from the source register 11 requested by the microprocessor 50 is changed. There is a method of requesting data first / critical data first to be restored. In this method, the source register 11 requested by the microprocessor 50 is first restored. The microprocessor 50 can start executing the program when the restoration to the register cache 18 is started.
[0008]
As shown in FIG. 6, in the request data forward method, data is sequentially restored from the source register 11 requested by the microprocessor 50. Therefore, the following problems occur.
[0009]
Since the order of the source registers 11 requested by the microprocessor 50 does not necessarily match the order of restoration to the register cache 18, the microprocessor 50 may stop again after the program execution is started. For example, there is a possibility of stopping when the source register 11 to be restored is at the end. In FIG. 6, there is a time until the restoration of the source registers R0 and R1 required by the instruction (2). , Stop until the source registers R0, R1 are restored. Further, even when writing to the register cache 18 as the destination register which is the processing result of the source register 11, since the restoration is performed once like the source registers R5 and R6 in FIG. 6, processing is wasted.
[0010]
[Problems to be solved by the invention]
An object of the present invention is to provide a microprocessor and a method for processing a source register that prevent a decrease in the execution performance of a program.
[0011]
[Means for Solving the Problems]
The gist of the microprocessor of the present invention is a register file in which a plurality of register values including a plurality of source registers are stored, an address of a source register that issues an instruction and is processed by the instruction, and processing A unit that issues an address of the destination register that results, a unit that receives the instruction and executes the instruction, a register cache from which the source register is restored, an address of the source register, And a circuit for controlling the restoration of the register and the reading of the source register to the executing unit. By controlling the restoration of the source register and the transmission to the unit to be executed by the controlling circuit, it is possible to perform an operation by an instruction without degrading the execution performance of the program.
[0012]
The source register processing method of the present invention includes a step of issuing an instruction for performing an operation using a source register, an address of a source register used in the instruction, and a destination register resulting from processing by the instruction Issuing the address of the address, restoring the source register of the address to a register cache, transferring the source register to a unit on which the instruction is executed, and executing the instruction. Including.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
The microprocessor and source register processing method of the present invention will be described with reference to the drawings. In this specification and FIGS. 1 to 4, reference numerals R0, R1, R2, R3, R4, R5, R6, and R7 indicate reference numeral 11 or a destination register, respectively.
[0014]
As shown in FIG. 1, the microprocessor 10 of the present invention is used in a register file 12 in which register values including a plurality of source registers 11 are stored, an instruction is issued, and an operation is performed by the instruction. An instruction control / issue unit 14 that issues the address of the source register 11 and the address of the destination register that is the result processed by the instruction, an execution unit 16 that receives the instruction and executes the instruction, and the source register 11 A register cache 18 to be restored and a cache restoration control circuit 20 that receives an address and controls the restoration of the source register 11 and the reading of the source register 11 to the execution unit 16.
[0015]
The source register 11 is a register value used for an operation in the execution unit 16. Also, the destination value is included in the register value.
[0016]
The register cache 18 is also written with the destination register. The destination register is handled in the same manner as the source register 11 stored in the register cache 18 and then restored in the register cache 18.
[0017]
As shown in FIG. 2, the cache restoration control circuit 20 controls a queue 22 that stores the restoration order of the source register 11, and restoration of the source register 11 and reading to the execution unit 16 according to the queue 22. Means 24 and a flag 26 for storing the state of the source register 11 to the register cache 18. The state of the source register 11 stored in the flag 26 includes the restored source register 11 and the destination register after being written.
[0018]
The instruction control / issue unit 14 is an in-order issue / in-order completion scalar processor that issues one instruction at a maximum in one cycle. The instruction control / issue unit 14 and the cache restoration control circuit 20 are connected by a plurality of buses 21. For example, the addresses of two source registers 11 and one destination register are transferred to the cache restoration control circuit 20. The destination register is a processing result in the execution unit 16.
[0019]
Furthermore, the present invention provides a selection circuit 28 for selecting the source register 11 restored in the register cache 18 and the source register 11 stored in the register file 12, and the source file from the register file 12 to the selection circuit 28. A read bus 30 for sending the register 11 and a restoration bus 32 branched from the read bus 30 and connected to the register cache 18 are included. The two registers 30 and 32 can simultaneously send the source register 11 to the selection circuit 28 and the register cache 18.
[0020]
The execution unit 16 and the register cache 18 are connected by a plurality of source register buses 34a and 34b. For example, they are connected by two source / register buses 34a and 34b, and a selection circuit 28 is interposed in one source / register bus 34b. The selection circuit 28 can select the source register 11 stored in the register file 12 or the restored source register 11 in the register cache 18 and send it to the execution unit 16. The selection of the selection circuit 28 is controlled by the cache restoration control circuit 20. Also, a plurality of source registers 11 can be sent simultaneously from the register cache 18 to the execution unit 16 via a plurality of source register buses 34a and 34b.
[0021]
In order to write destination registers to the register cache 18, a destination register bus 36 that connects the execution unit 16 and the register cache 18 is included.
[0022]
The destination register bus 36 may be branched and connected to the register file 12 by the destination register bus 36b. By branching, the destination register which is the processing result of the execution unit 16 can be written to the register cache 18 at the same time as the register file 12. Therefore, the task of saving the source register 11 of the register cache 18 to the register file 12 does not occur at the time of task switching.
[0023]
The register file 12 includes a context pointer (CP) 38 for designating the first address among consecutive register value addresses. This register value includes the source register 11 and the destination register. For example, in the figure, there are eight register values defined by the instruction set, R0 to R7. An arbitrary address indicated by the context pointer 38 is R0, and eight consecutive register values from this R0 are restored to the register cache 18. An arbitrary address indicated by the context pointer 38 is changed when the task is switched.
[0024]
Next, a processing method of the source register 11 using the microprocessor 10 of the present invention will be described. (1) After the task is switched, an address in the register file 12 is designated by the context pointer 38. (2) The instruction control / issue unit 14 issues an instruction and / or issues the address of the source register 11 processed by the instruction and the address of the destination register which is the result of processing by the instruction. (3) Restore the source register 11 of the register file 12 to the register cache 18. (4) The source register 11 of the register file 12 is transferred to the execution unit 16. (5) The execution unit 16 executes the instruction using the transferred source register 11. (6) The instruction operation result is written to the register cache 18 as a destination register. The destination register when performing step (6) is handled in the same manner as the source register 11 after writing to the register cache 18. Further, when the processes (1) to (6) are performed for the first time, the cache restoration control circuit 20 controls to perform (3) and (4) simultaneously. In {circle around (2)}, it is possible to issue only the address first without issuing the instruction and the address simultaneously.
[0025]
Steps (2) to (6) may be repeated any number of times. When the steps (2) to (6) are repeated, A. When the source register 11 used in the execution unit 16 exists in the register cache 18 by the steps (3) and (6), the cache restoration control circuit 20 uses the source register 11 of the register cache 18 as the execution unit. Control to transfer to 16. B. When there is no source register 11 used in the execution unit 16 in the register cache 18, the cache restoration control circuit 20 controls to perform the steps (3) and (4) simultaneously. The cache restoration control circuit 20 can perform the above A and B by controlling the selection circuit 28, the register cache 18, and the register file 12.
[0026]
In the step (6), the destination register may be written to the register file 12 at the same time as the destination register is written to the register cache 18.
[0027]
Further, when the processing is stopped in the step (2), the source register 11 not restored in the register cache 18 or the register value not written in the register cache 18 as the destination register as the processing result of the source register 11 Is restored to the register cache 18.
[0028]
The operation of the cache restoration control circuit 20 in the above process will be specifically described with reference to FIG. The processing in FIG. 2 is processing by the same instruction as the instruction shown in FIG. 6 of the prior art. The value CP of the context pointer 38 is changed from CP1 to CP2 by task switching. The contents of the register cache 18 become invalid. At this time, all the values of the flags 26 of the cache restoration control circuit 20 are also set to “0” (invalid) (state 1).
[0029]
Before the instruction (1) is issued, the address “3” of the source register R3 and the address “4” of the destination register R4 of the instruction (1) are transferred from the instruction control / issue unit 14 to the cache restoration control circuit 20. (State 2). In the cache restoration control circuit 20, the address “3” of the source register R3 is sent to the queue 22, and the flag 26 corresponding to the address “4” of the destination register R4 is set to “1” (valid).
[0030]
When the above operation for command (1) is completed, the same operation is performed for command (2) regardless of whether command (1) is issued. In FIG. 2, the addresses “0” and “1” of the source registers R0 and R1 are sent to the queue 22, and the flag 26 corresponding to the address “5” of the destination register R5 is set to “1” (state 3). . In FIG. 2, the same operation is repeated after the instruction (3) (state 4 and thereafter).
[0031]
The queue 22 stores the address of the source register 11 transferred from the instruction control / issue unit 14. At this time, referring to the corresponding flag 26, if the flag 26 is set to “1”, Not stored in the queue 22.
[0032]
The means 24 for controlling restoration controls restoration of the corresponding source register 11 according to the order of the queue 22. If the relevant source register 11 is requested by the execution unit 16, it is transferred to the execution unit 16 at the same time. To control.
[0033]
When the restoration is completed, the flag 26 corresponding to the address of the source register 11 is set to “1”.
[0034]
When the queue 22 is empty, the flag 26 is referred to from the register value R0, the register value with the flag 26 being “0” is restored, and the flag 26 is set to “1”.
[0035]
If all the flags 26 are set to “1” by the above operation, the restoring operation to the register cache 26 is completed.
[0036]
According to the above embodiment, for example, as shown in FIG. 3, the issue and completion of the instruction (2), (3) or the subsequent instructions are unnecessary as compared with the request data forward method shown in FIG. Because there is no restoration, it can be done quickly. Note that FIG. 3 shows processing by the same instruction as that shown in FIG. 2 or FIG. Since the restoration of the source register 11 and the reading of the source register 11 of the execution unit 16 can be performed in the same cycle, and restoration of the register value corresponding to the destination register can be omitted, the source register 11 can be restored in a short time.
[0037]
FIG. 4 shows another configuration of the present invention. This microprocessor 40 has a plurality of register caches 18. When each register cache 18 is handled as a bank, the microprocessor 40 operates in a bank manner. Restoration can be started immediately by switching banks when switching tasks. That is, the source register 11 is restored to another register cache 18 without saving the source register 11 restored to a certain register cache 18. Further, the restored source register 11 can be saved in the register cache 18 used in the past during the restoration. Therefore, similarly to the configuration of FIG. 1, the processing of the source register 11 can be performed without degrading the program execution performance.
[0038]
As mentioned above, although embodiment of this invention was described, this invention is not limited to said embodiment. In addition, the present invention can be implemented in a mode in which various improvements, modifications, and changes are made based on the knowledge of those skilled in the art without departing from the spirit of the present invention.
[0039]
【The invention's effect】
According to the present invention, after task switching, program execution can be started without waiting for completion of register cache restoration. Further, the program can be continuously executed without depending on the order of the source registers required by the microprocessor. Since the restoration cycle of the entire register cache can be shortened, the execution performance of the program can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram showing a circuit configuration of a microprocessor according to the present invention.
FIG. 2 is a diagram illustrating control of a source register in a cache restoration control circuit.
FIG. 3 is a diagram illustrating a restoration state of a source register in a cash register.
FIG. 4 is a diagram showing another embodiment of the microprocessor, in which a plurality of register caches are provided.
FIG. 5 is a diagram showing a circuit configuration of a conventional microprocessor;
6 is a diagram showing a restored state of the source register in the microprocessor of FIG. 5; FIG.
[Explanation of symbols]
10, 40, 50: Microprocessor 11: Source register 12: Register file 14: Instruction control / issue unit 16: Execution unit 18: Register cache 20: Cache restoration control circuit 21: Address sending bus 22: Queue 24 : Control means 26: Flag 28: Selection circuit 30: Read bus 32: Restore buses 34, 34 a and 34 b: Source register bus 36 and 36 b: Destination register bus 38: Context pointer

Claims (14)

A register file storing a plurality of register values including a plurality of source registers;
A unit that issues an instruction and issues an address of a source register processed by the instruction and an address of a destination register that is processed;
A unit for receiving the instruction and executing the instruction;
A register cache where the source registers are restored;
A microprocessor that receives the address of the source register, and controls the restoration of the source register and the reading of the source register to the executing unit. The circuit to control is
A queue for storing the order of restoration of the source registers;
Means for controlling the restoration of the source register of the register file and reading to the executing unit according to the queue;
A flag for storing a state of a source register of the register cache;
The microprocessor of claim 1 comprising: A circuit for selecting a source register of the register cache and a source register of a register file;
A read bus for sending a source register to a circuit to select from the register file;
3. The microprocessor according to claim 1, further comprising a restoration bus that branches from the read bus and is connected to a register cache. 4. The microprocessor according to claim 3, wherein the execution unit and the register cache are connected by a plurality of source register buses, and the selection circuit is interposed in one of the source register buses. 5. A destination register bus connecting the executing unit and the source register to write a destination register resulting from the source register processed by the executing unit to a register cache. Microprocessor. 6. The microprocessor of claim 5, wherein the destination register bus branches to connect to a register cache and a register file. 7. The microprocessor according to claim 1, further comprising a pointer for designating a first address among consecutive source register addresses in the register file. The microprocessor according to claim 1, wherein the register cache is plural. A method for processing a plurality of source registers stored in a register file comprising:
Issuing an instruction to process the source register;
Issuing the address of the source register processed by the instruction and the address of the destination register resulting from the processing;
Receiving an address of a source register to be processed by the issued instruction and restoring the source register at the address to a register cache;
Receiving the address of the source register processed by the issued instruction and transferring the source register at that address to the unit on which the instruction is executed;
Executing the instructions. The processing method according to claim 9, wherein the restoring step and the transferring step are executed simultaneously. 11. The processing method according to claim 9, further comprising the step of transferring the source register restored by the restoring step to a unit in which the instruction is executed. The processing method according to claim 9, further comprising a step of writing a result processed by the executing step into a register cache. The processing method according to claim 12, wherein the result is written to a register file simultaneously with the writing step. The processing method according to claim 9, further comprising a step of designating a first address among consecutive source register addresses in the register file.

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