JP3658384B2 - MOS type imaging device and camera incorporating the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MOS type image pickup apparatus used for a digital camera or the like and a camera incorporating the same.
[0002]
[Prior art]
The MOS type imaging device is an image sensor that amplifies and reads out a signal of each pixel using an amplifier circuit including a MOS transistor formed in each pixel. In recent years, this type of MOS imaging device, in particular, a so-called CMOS image sensor manufactured by a CMOS (complementary MOS) process has the advantages of low voltage and low power consumption and can be integrated into one chip with peripheral circuits. Attention has been focused on as an image input element for portable devices such as small cameras.
[0003]
In the conventional MOS type imaging device, each circuit in the peripheral circuit region is designed by using a CMOS technology that uses both an n-channel MOS transistor and a p-channel MOS transistor. On the other hand, in the imaging region, all of the MOS transistors constituting each pixel are n-channel MOS transistors. The n-channel MOS transistors constituting this pixel usually have the same structure as the n-channel MOS transistors used in the peripheral circuit region.
[0004]
FIG. 4 is a cross-sectional view showing the structure of a CMOS transistor used in the peripheral circuit region of a conventional MOS imaging device proposed in Patent Document 1 below. An n-type well 26 and a p-type well 25 are formed in the semiconductor substrate 21. A p-channel MOS transistor 22 is formed in the n-type well 26, and an n-channel MOS transistor 23 is formed in the p-type well 25, and the transistors are electrically isolated by an element isolation unit 24. An oxide film 27 formed by a selective oxidation method (LOCOS: local oxidation of silicon) is used for the element isolation portion 24. Further, when further miniaturization proceeds, an oxide film 28 formed by STI (Shallow Trench Isolation) is used for the element isolation portion as shown in FIG.
[0005]
[Patent Document 1]
JP 2002-110953 A
[0006]
[Problems to be solved by the invention]
Since the MOS imaging device includes an amplifier circuit in each pixel as described above, it can amplify a small number of signals and realize high sensitivity. On the other hand, if the leak current leaking into the photodiode is large, it will be amplified, resulting in a problem of large noise.
[0007]
In the conventional MOS type imaging device, as described above, the n-channel MOS transistors constituting the pixels have the same structure as the n-channel MOS transistors used in the peripheral circuit region, that is, the n-channel MOS transistors of the CMOS transistors. Is done. Also, the structure of the element isolation portion between the transistors is the same in the imaging region and the peripheral circuit region.
[0008]
However, CMOS transistors used in the peripheral circuit area have been developed in response to the large trend of semiconductor LSI miniaturization technology, and their production has been tuned mainly for speeding up. Is not paid. For example, in a CMOS transistor as shown in FIG. 4, since the oxide film 27 used for the element isolation portion is formed by thermal oxidation of the substrate 21, about half of the film thickness greatly erodes the substrate 21. Yes. Further, in the CMOS transistor shown in FIG. 5, the oxide film 28 used for the element isolation portion fills the groove formed in the substrate 21, and the entire film thickness erodes the substrate 21. In such an element isolation portion, a large leak current is generated because a large stress is generated in a portion eroded by the oxide film of the substrate. Therefore, when such an element isolation structure of a CMOS transistor is applied to an imaging region as it is, there is a problem that noise due to a leak current becomes very large.
[0009]
An object of the present invention is to provide a MOS type imaging device having a low noise caused by a leakage current and a camera using the MOS type imaging device in order to solve the above-described conventional problems.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a MOS type imaging device of the present invention includes a semiconductor substrate, an imaging region in which a plurality of unit pixels formed on the semiconductor substrate are arranged, and the imaging formed on the semiconductor substrate. A peripheral circuit region including a drive circuit for operating the region, wherein the unit pixel includes a photodiode, a metal-oxide-semiconductor (MOS) transistor, and a first element isolation unit, and the peripheral circuit region includes the drive A MOS-type imaging device including a second element isolation unit that isolates elements in a circuit,
The first element isolation part and the second element isolation part are:
A. An electrically insulating film formed on the substrate so as not to erode the substrate and having a film thickness of 500 nm or less ;
B. A depth of erosion of the substrate of 1 nm or more and 50 nm or less , and an electrical insulating film formed on the substrate that has been subjected to a hydrogen annealing treatment ; and
C. I at least one Der selected from impurity diffusion region formed in said substrate, and said first element isolation portion and the second isolation portion is characterized by the same structure der Rukoto.
[0011]
Next, a camera according to the present invention includes a semiconductor substrate, an imaging region in which a plurality of unit pixels formed on the semiconductor substrate are arranged, and a drive circuit for operating the imaging region formed on the semiconductor substrate. The unit pixel includes a photodiode, a MOS (metal-oxide-semiconductor) transistor, and a first element isolation unit, and the peripheral circuit area isolates elements in the driving circuit. 2 element isolation parts,
The first element isolation part and the second element isolation part are:
A. An electrically insulating film formed on the substrate so as not to erode the substrate and having a film thickness of 500 nm or less ;
B. A depth of erosion of the substrate of 1 nm or more and 50 nm or less , and an electrical insulating film formed on the substrate that has been subjected to a hydrogen annealing treatment ; and
C. I at least one Der selected from impurity diffusion region formed in said substrate, and said first element isolation portion and the second isolation portion incorporates MOS type imaging device Ru same structure der It is characterized by that.
[0012]
In the present invention, the “first element isolation portion” is formed to electrically isolate elements existing in the same pixel.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, the first element isolation part and the second element isolation part are:
A. An electrically insulating film formed on the substrate so as not to erode the substrate,
B. An electrical insulating film formed on the substrate having a depth of eroding the substrate of 1 nm to 50 nm, and
C. Since it is composed of at least one selected from the impurity diffusion regions formed in the substrate, the stress applied to the substrate is reduced, and the leakage current can be suppressed. As a result, noise caused by leakage current can be reduced. In the case of B, when the depth of erosion of the substrate is as shallow as 1 nm or more and 50 nm or less, the stress of the element isolation portion can be reduced and the leakage current can be suppressed.
[0014]
In the MOS imaging device, it is preferable that the impurity diffusion region is formed by ion implantation.
[0015]
In the MOS imaging device, it is preferable that the insulating film has a thickness of 1 nm to 500 nm.
[0016]
In the MOS type imaging device, the first element isolation portion formed so as to be adjacent to the photodiode in the imaging region is constituted by an impurity diffusion region formed in the substrate. It is preferable.
[0017]
In the MOS imaging device, it is preferable that at least a part of the drive circuit is a dynamic circuit. This is because power consumption can be reduced.
[0018]
In the MOS type imaging device, it is preferable that a dark current suppressing layer is formed on a surface layer portion of the photodiode. According to this preferred example, it is possible to suppress a leakage current generated from a defect near the substrate surface on the photodiode.
[0019]
Hereinafter, it demonstrates using drawing.
[0020]
FIG. 2 is a diagram showing an example of the MOS type imaging device of the present invention. This solid-state imaging device includes an imaging region 7 in which a plurality of pixels 6 are arranged one-dimensionally or two-dimensionally, and a peripheral circuit region arranged around the imaging region 7.
[0021]
This MOS type imaging device includes an imaging region 7 in which a plurality of pixels 6 are two-dimensionally arranged on the same semiconductor substrate, a vertical shift register 8 and a horizontal shift register 9 for pixel selection, and the shift register. (Hereinafter, a region other than the imaging region 7, that is, a region including the vertical shift register 8, the horizontal shift register 9, and the timing generation circuit 10 is referred to as a “peripheral circuit region”. "). In the imaging region 7, each pixel 6 includes a photodiode 1 and four MOS transistors, that is, a transfer transistor 2, a reset transistor 3, an amplification transistor 4, and a selection transistor 5. In the peripheral circuit region, the vertical shift register 8, the horizontal shift register 9, and the timing generation circuit 10 are configured using a plurality of MOS transistors.
[0022]
Each pixel 6 constituting the imaging region 7 includes a photodiode 1 and four MOS transistors, that is, a transfer transistor 2, a reset transistor 3, an amplification transistor 4, and a selection transistor 5. The transfer transistor 2 has a photodiode 1 as a source and a drain electrically connected to the gate of the amplification transistor 4. The amplification transistor 4 has a drain electrically connected to the power supply voltage and a source electrically connected to the drain of the selection transistor 5. The reset transistor 2 has a source electrically connected to the drain of the transfer transistor 2 and a drain electrically connected to the power supply voltage. The selection transistor 5 has a source connected to the output line.
[0023]
The role of each transistor will be briefly described. The transfer transistor 2 is a transistor for transferring a signal charge generated by photoelectric conversion by the photodiode 1 to the detection unit (the drain of the transfer transistor 2). The detection unit has a function of accumulating signal charges and inputting a voltage corresponding to the charges to the amplification transistor 4. The amplifying transistor 4 functions to amplify the voltage of the detection unit, and the selection transistor 5 is a switch that extracts the output of the amplifying transistor 4 and functions to select a pixel from which a signal is read. Further, the reset transistor 2 functions to discharge the signal charge accumulated in the detection unit at regular intervals.
[0024]
FIG. 1A and FIG. 1B are cross-sectional views showing an example of a MOS transistor and its peripheral structure. In the MOS transistor 12, a source 14 and a drain 15 which are n-type diffusion regions are formed in a p-type semiconductor substrate 11 (or a p-type well). A gate electrode 17 is formed on the semiconductor substrate 11 corresponding to between the source 14 and the drain 15 via an insulating film 16.
[0025]
Further, as shown in FIGS. 1A and 1B, the MOS transistors 12 are electrically isolated from each other by an element isolation unit 13. The element isolation portion 13 has a structure in which an isolation oxide film 18 is formed on a semiconductor substrate 11 as shown in FIG. 1A or an isolation diffusion in the semiconductor substrate 11 as shown in FIG. It can be set as the structure in which the area | region 19 was formed. Alternatively, a structure in which both the isolation oxide film 18 and the isolation diffusion region 19 are formed may be used. The structure of the element isolation portion will be described in detail later.
[0026]
The photodiode 1 is an n-type diffusion region formed in a p-type semiconductor substrate (or p-type well). As described above, the photodiode constitutes the source of the transfer transistor, and the element isolation portion is formed in the region adjacent to the photodiode, like the sources of the other MOS transistors.
[0027]
Furthermore, it is preferable that a p-type diffusion region is formed as a dark current suppression layer in the surface layer portion of the n-type diffusion region which is a photodiode. In this case, it is preferable that the dark current suppression layer extends to the element isolation portion formed so as to be adjacent to the photodiode. That is, when the element isolation portion is formed of an isolation oxide film, it is preferably extended to below the isolation oxide film. When the element isolation portion is configured of an isolation diffusion region, It is preferable to extend to.
[0028]
In the above description, the case where an n-channel MOS transistor is used as the MOS transistor constituting each pixel is exemplified, but a p-channel MOS transistor can also be used. In this case, the MOS transistor has a structure in which a source and a drain which are p-type diffusion regions are formed in an n-type semiconductor substrate (or an n-type well). The photodiode is composed of a p-type diffusion region, and the dark current suppression layer is composed of an n-type diffusion region.
[0029]
As shown in FIG. 2, the peripheral circuit region includes driving circuits such as a horizontal shift register 8 and a vertical shift register 9 for pixel selection, and a timing generation circuit 10 for supplying pulses necessary for the operation of these shift registers. It is out.
[0030]
In order to reduce the power consumption of this peripheral circuit, the drive circuit is preferably configured using a dynamic circuit. FIG. 3 is a circuit diagram illustrating an example of a dynamic circuit that can be used in the horizontal shift register and the vertical shift register.
[0031]
Normally, a dynamic circuit dynamically retains data in a capacity (20a, 20b, and 20c in FIG. 3). Therefore, if the leakage current is large, the data may be destroyed by the leakage current. However, in the present embodiment, since a structure with a small leakage current is employed as the element isolation portion that isolates the MOS transistors of the drive circuit, such a problem can be reduced.
[0032]
The drive circuit includes a plurality of MOS transistors, and the MOS transistors are electrically separated from each other by an element separation unit. As the structure of the element isolation part, the same structure as the element isolation part in the imaging region can be adopted. That is, a structure in which an isolation oxide film is formed on a semiconductor substrate, a structure in which an isolation diffusion region is formed in the semiconductor substrate, or a structure in which both an isolation oxide film and an isolation diffusion region are formed can be employed. The structure of this element isolation part will be described in detail later.
[0033]
Furthermore, it is preferable that the MOS transistors constituting the pixels in the imaging region and the MOS transistors constituting the drive circuit in the peripheral circuit region all have the same structure. This is because the manufacturing process can be simplified.
[0034]
Next, an element isolation portion between MOS transistors in the imaging region and the peripheral circuit region will be described.
[0035]
As described above, in both the imaging region and the peripheral circuit region, the structure of the element isolation portion is a structure in which an isolation oxide film is formed on a semiconductor substrate (hereinafter referred to as “first embodiment”). Alternatively, a structure in which an isolation diffusion region is formed in a semiconductor substrate (hereinafter referred to as “second embodiment”) is employed.
[0036]
FIG. 1A is a cross-sectional view illustrating an example of an element isolation unit according to the first embodiment. In the element isolation portion 13, an isolation oxide film 18 is formed on the semiconductor substrate 11. The isolation oxide film 18 is a film that does not erode the semiconductor substrate 11 and is, for example, a deposited film formed on a flat surface of the semiconductor substrate. Such an isolation oxide film 18 can be formed by, for example, a CVD method.
[0037]
FIG. 6 is a comparison diagram of leakage current due to the difference in the isolation oxide film.
[0038]
When the thickness of the isolation oxide film 18 is as large as 800 nm as shown in FIG. 6B, the boundary between the isolation oxide film 18 and the source 14 or drain 15 due to the influence of a heat treatment step after the formation of the isolation oxide film 18. Stress concentrates at the end of the isolation oxide film 18 in the region. As a result, the selective oxidation method shown in A of FIG. 6: stress becomes larger than (LOCOS local oxidation of silicon) oxide film 27 formed by the leakage current is increased to 1.3 times. Therefore, by setting the thickness of the isolation oxide film 18 to 500 nm or less , preferably 400 nm or less, and more preferably 250 nm or less, the leakage current at the end of the isolation oxide film 18 is reduced by a selective oxidation method (LOCOS). The leakage current of the oxide film 27 formed by silicon) can be reduced. As shown in FIG. 6C, when the isolation oxide film 18 is 250 nm, it can be reduced by a factor of 0.8.
[0039]
In general, a CMOS LSI or the like has a GND power supply in a unit cell, so that a current may flow from GND to the VDD (for example, 3 V) through the isolation oxide film. It is necessary to improve the breakdown voltage of element isolation by increasing the thickness. However, in the case of an amplifying unit pixel, a GND power supply is not necessarily required in the pixel, so that the isolation oxide film 18 can be made as thin as 4 to 250 nm, and leakage of the isolation oxide film 18 can be reduced.
[0040]
Further, by performing an annealing process in a hydrogen atmosphere after the formation of the isolation oxide film 18, defects caused by stress at the end of the isolation oxide film 18 can be improved, and the leakage current can be further reduced. As shown in E of 6, it was reduced to 0.4 times.
[0041]
Further, FIG. 1A shows an example of an insulating film formed on the substrate so that the isolation oxide film 18 does not erode the semiconductor substrate 11. However, in the experimental results, the isolation oxide film 18 is formed on the semiconductor substrate. When the erosion depth is 50 nm or less, an annealing process is performed in a hydrogen atmosphere to reduce the leakage current as compared with the oxide film 27 formed by a selective oxidation method (LOCOS). As shown in FIG. 6D, the leakage current was reduced by a factor of 0.6.
[0042]
FIG. 1B is a cross-sectional view illustrating an example of the element isolation portion according to the second embodiment. In the element isolation portion 13, an isolation diffusion region 19 is formed in the semiconductor substrate 11. According to the second embodiment, it is possible to obtain a leakage current suppressing effect that is further superior to that of the first embodiment. As the isolation diffusion region 19, a p-type diffusion region is used when the n-channel MOS transistors are separated from each other, and an n-type diffusion region is used when the p-channel MOS transistors are isolated from each other. This isolation diffusion region 19 can be formed, for example, by ion-implanting p-type or n-type impurities into the semiconductor substrate.
[0043]
The impurity concentration and diffusion depth of the isolation diffusion region 19 are not particularly limited as long as the MOS transistor 12 can be electrically isolated. The impurity concentration is, for example, 10 ¹⁴ to 10 ²² cm ⁻³ , preferably 10 ¹⁵ to 10 ²⁰ cm ⁻³ , more preferably 10 ¹⁷ to 10 ²⁰ cm ⁻³ , and the diffusion depth is, for example, more than 0 μm and 7 μm. In the following, it is preferably more than 0 μm and 2 μm or less, more preferably more than 0 μm and 1 μm or less.
[0044]
The element isolation portion may have a structure in which an isolation oxide film and an isolation diffusion region are used together (hereinafter, such a structure is referred to as “third embodiment”). According to such a structure, even when a leak current occurs at the interface between the isolation oxide film and the semiconductor substrate, the leak current can be recombined in the isolation diffusion region, so that a further effect of reducing the leak current can be obtained. It is done.
[0045]
In the imaging region, it is preferable to employ the second embodiment as the structure of the element isolation part adjacent to at least the photodiode. This is because an excellent effect of suppressing leakage current can be obtained. Further, as the structure of the other element isolation portion in the imaging region, the second embodiment can be adopted, but it is particularly preferable to adopt the first embodiment or the third embodiment. This is because high-speed operation of the amplifier circuit in the pixel can be realized.
[0046]
On the other hand, in the peripheral circuit region, it is preferable to adopt the first embodiment or the third embodiment as the structure of the element isolation portion. This is because high-speed operation of the drive circuit can be realized.
[0047]
The structure of the element isolation part in the imaging region and the structure of the element isolation part in the peripheral circuit region can be individually selected from the first embodiment, the second embodiment, and the third embodiment. Below, the suitable example of the combination is given.
[0048]
In the first example, the element isolation part in the imaging region and the element isolation part in the peripheral circuit region have the same structure. In this case, as the structure of the element isolation portion, the second embodiment can be adopted, but it is particularly preferable to adopt the first embodiment or the third embodiment.
[0049]
The second example employs the second embodiment as the structure of the element isolation section in the imaging region, and the first embodiment or the third implementation as the structure of the element isolation section in the peripheral circuit region. The form is adopted. According to such a structure, it is possible to reduce the leakage current that leaks into the photodiode and to increase the speed of the drive circuit.
[0050]
In the third example, in the imaging region, the second embodiment is used as the structure of the element isolation section adjacent to the photodiode, and the first embodiment or the third configuration is used as the structure of the other element isolation section. In the peripheral circuit region, the first embodiment or the third embodiment is employed as the structure of the element isolation portion.
[0051]
According to such a structure, it is possible to reduce the leakage current that leaks into the photodiode and to increase the speed of the drive circuit and the amplifier circuit in the pixel.
[0052]
【The invention's effect】
As described above, according to the MOS type imaging device of the present invention, the noise caused by the leakage current can be reduced by making the element isolation part between the MOS transistors have a specific structure.
[Brief description of the drawings]
FIG. 1A is a cross-sectional view showing an example of an element isolation portion according to a first embodiment of the present invention. (B) is sectional drawing which shows an example of the element separation part which concerns on 2nd Embodiment.
FIG. 2 is a diagram showing a configuration of a MOS type imaging apparatus of the present invention.
FIG. 3 is a circuit diagram showing an example of a dynamic circuit that can be used in the drive circuit of the MOS type imaging device of the present invention.
FIG. 4 is a cross-sectional view showing a structure of a CMOS transistor and an element isolation part constituting a conventional MOS type imaging device.
FIG. 5 is a cross-sectional view showing the structure of a CMOS transistor and an element isolation part constituting a conventional MOS type imaging device.
FIG. 6 is a leakage current comparison diagram due to the difference in the isolation oxide film according to the first embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Photodiode 2, 3, 4, 5 MOS transistor 6 Pixel 7 Imaging area 8 Vertical shift register 9 Horizontal shift register 10 Timing generation circuit 11 Semiconductor substrate 12 MOS transistor 13 Element separation part 14 Source 15 Drain 16 Gate insulating film 17 Gate 18 Isolation oxide film 19 Isolation diffusion region

Claims (12)

A semiconductor substrate;
An imaging region in which a plurality of unit pixels formed on the semiconductor substrate are arranged;
A peripheral circuit region including a drive circuit for operating the imaging region formed on the semiconductor substrate,
The unit pixel includes a photodiode, a MOS (metal-oxide-semiconductor) transistor, and a first element isolation unit.
The peripheral circuit region is a MOS type imaging device including a second element isolation unit that isolates elements in the drive circuit,
The first element isolation part and the second element isolation part are:
A. An electrically insulating film formed on the substrate so as not to erode the substrate and having a film thickness of 500 nm or less ;
B. A depth of erosion of the substrate of 1 nm to 50 nm and an electrical insulating film formed on the substrate that has been subjected to a hydrogen annealing treatment ; and
C. I at least one Der selected from impurity diffusion region formed in said substrate, and, MOS said first element isolation portion and said second element isolation portion is characterized by the same structure der Rukoto Type imaging device.   The MOS type imaging device according to claim 1, wherein the impurity diffusion region is formed by ion implantation. 2. The MOS type image pickup device according to claim 1, wherein a film thickness of the B electrical insulating film is in a range of 1 nm to 500 nm.   The MOS imaging device according to claim 1, wherein at least a part of the drive circuit is a dynamic circuit.   The MOS type imaging device according to claim 1, wherein a surface layer portion of the photodiode has a dark current suppressing layer.   The MOS type imaging device according to claim 1, wherein the first element isolation part and the second element isolation part are formed by annealing in a hydrogen atmosphere. A semiconductor substrate;
An imaging region in which a plurality of unit pixels formed on the semiconductor substrate are arranged;
A peripheral circuit region including a drive circuit for operating the imaging region formed on the semiconductor substrate,
The unit pixel includes a photodiode, a MOS (metal-oxide-semiconductor) transistor, and a first element isolation unit.
The peripheral circuit region includes a second element isolation unit that isolates elements in the drive circuit,
The first element isolation part and the second element isolation part are:
A. An electrically insulating film formed on the substrate so as not to erode the substrate and having a film thickness of 500 nm or less ;
B. A depth of erosion of the substrate of 1 nm to 50 nm and an electrical insulating film formed on the substrate that has been subjected to a hydrogen annealing treatment ; and
C. I at least one Der selected from impurity diffusion region formed in said substrate, and said first element isolation portion and the second isolation portion incorporates MOS type imaging device Ru same structure der A camera characterized by that.   The camera according to claim 7, wherein the impurity diffusion region is formed by ion implantation. The camera according to claim 7, wherein a film thickness of the electrical insulating film of B is in a range of 1 nm to 500 nm. At least partially, camera according to claim 7, which is a dynamic circuit of the drive circuit. Surface portion of the photodiode, camera according to claim 7 having a dark current suppressor layer.   The camera according to claim 7, wherein the first element isolation part and the second element isolation part are formed by annealing in a hydrogen atmosphere.

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