JP3651509B2 - Oxide film etching method and thin film transistor manufacturing method - Google Patents

Oxide film etching method and thin film transistor manufacturing method Download PDF

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Publication number
JP3651509B2
JP3651509B2 JP01608496A JP1608496A JP3651509B2 JP 3651509 B2 JP3651509 B2 JP 3651509B2 JP 01608496 A JP01608496 A JP 01608496A JP 1608496 A JP1608496 A JP 1608496A JP 3651509 B2 JP3651509 B2 JP 3651509B2
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electrode
gate electrode
film
insulating film
gate insulating
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JPH08330272A (en
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則夫 仲山
政幸 堂城
秀雄 平山
隆俊 辻村
篤哉 ▲槙▼田
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International Business Machines Corp
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International Business Machines Corp
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Description

【０００１】
【発明の属する技術分野】
本発明は、金属膜上に酸化膜が被膜され、これら酸化膜および金属膜をエッチングするエッチング方法および薄膜トランジスタの製造方法に関する。
【０００２】
【従来の技術】
近年、大型の画面をもつ液晶表示装置用の薄膜トランジスタ（ＴＦＴ：Thin Film Transistor）アレイが普及しつつある。
【０００３】
ここで、従来の、ゲート線がガラス基板上に位置する逆スタガ型薄膜トランジスタアレイの製造方法を、図３を参照して説明する。
【０００４】
まず、図３（ａ）に示すように、ガラス基板１上に、純アルミニウム、あるいは、数％以下の微量な不純物を含んだアルミニウム（Ａｌ）からなるゲート電極２が配線され、このゲート電極２の表面を陽極酸化などの方法によって酸化アルミニウム（Ａｌ２Ｏ３）とし、第１のゲート絶縁膜３を形成する。
【０００５】
続いて、図３（ｂ）に示すように、これら第１のゲート絶縁膜３を含むガラス基板１上に、たとえば酸化ケイ素膜（ＳｉＯＸ）の第２のゲート絶縁膜４を形成し、アモルファス・シリコン層からなる半導体層５を形成し、この半導体層５上にエッチング・ストッパ用の窒化ケイ素層からなるエッチングストッパ層６を形成する。
【０００６】
その後、図３（ｃ）に示すように、一方のゲート電極２に給電部を形成するための第２のゲート絶縁膜４、第１のゲート絶縁膜３およびゲート電極２の穴穿けを行なう。
【０００７】
さらに、図３（ｄ）に示すように、第２のゲート絶縁膜４上にＩＴＯ（Indium Tin Oxide）からなる画素電極７を形成し、エッチングストッパ層６上に画素電極７に接続されたソース電極８およびドレイン電極９を形成して薄膜トランジスタ10を作製するとともに、穿孔されたゲート電極２、第１のゲート絶縁膜３および第２のゲート絶縁膜４には、給電部となるパッド電極11を装着し、薄膜トランジスタアレイ12が形成される。
【０００８】
ここで、ゲート電極２、第１のゲート絶縁膜３および第２のゲート絶縁膜４の穴穿けの工程について考えると、ＳｉＯＸの第２のゲート絶縁膜４およびＡｌ２Ｏ３の第１のゲート絶縁膜３の穴穿けの後にゲート電極２を残す必要がある。
【０００９】
ところが、第１のゲート絶縁膜３のＡｌ２Ｏ３と、ゲート電極２のＡｌとを選択的にエッチングすることは非常に困難であり、現在はフッ化水素酸を含むエッチング溶液中に浸して、第１のゲート絶縁膜３のＡｌ２Ｏ３を一定時間エッチングし、その後エッチングを停止するという方法で穴穿けしている。
【００１０】
しかし、この方法では場所によりエッチング速度にむらがあること、エッチング速度の再現性に幅があることから、実際の工程ではエッチング時間を長くとる必要がある。したがって、この方法でエッチングを行なうとゲート電極２を均一の厚さで残すことが困難であり、ゲート電極２のＡｌが薄くなったり、あるいは、無くなる場合があり、ゲート電極２に給電部を形成する工程での不良発生の原因となっている。
【００１１】
【発明が解決しようとする課題】
上述のように、図３に示す従来技術では、ゲート電極２に給電部を形成する工程において、ゲート電極２であるＡｌを均一の厚さで残すことが困難であり、パッド電極11との接触不良を引き起こす原因となるおそれがある問題を有している。
【００１２】
本発明は、上記問題点に鑑みなされたもので、金属膜および酸化膜を有するもののエッチングを確実に行なう酸化膜のエッチング方法および薄膜トランジスタの製造方法を提供することを目的とする。
【００１３】
【課題を解決するための手段】
本発明は、アルミニウムを主成分とした金属膜上に、酸化アルミニウムを主成分とした酸化膜が被覆され、これら金属膜および酸化膜を除去する酸化膜のエッチング方法において、前記金属膜をこの金属膜に対向させる対向電極とともに水素イオン濃度指数（ｐＨ）が４以下のエッチング溶液中に浸し、前記金属膜および前記対向電極間に与える電位を、標準水素電極に対し−１．８Ｖの値よりも卑の電位と制御して前記酸化膜を除去し、この酸化膜除去後に前記金属膜および前記対向電極間に与える電位を変化させて前記金属膜の表面を除去する。
【００１４】
そして、前記エッチング溶液は、フッ化水素酸を含む溶液であるため、確実かつ適切に金属膜をエッチングする。
【００１５】
また、本発明は、アルミニウムを主成分としたゲート電極上に、酸化アルミニウムを主成分としたゲート絶縁膜が被覆され、これらゲート電極およびゲート絶縁膜を除去する薄膜トランジスタの製造方法において、前記ゲート電極をこのゲート電極に対向させる対向電極とともに水素イオン濃度指数（ｐＨ）が４以下のエッチング溶液中に浸し、前記ゲート電極および前記対向電極間に与える電位を、標準水素電極に対し−１．８Ｖの値よりも卑の電位と制御して前記ゲート絶縁膜を除去し、このゲート絶縁膜除去後に前記ゲート電極および前記対向電極間に与える電位を変化させて前記ゲート電極の表面を除去し、前記ゲート電極にゲート電極端子を設けるもので、ゲート電極が均質になる。
【００１６】
【発明の実施の形態】
以下、本発明の一実施の形態について、図面に示す薄膜トランジスタの製造方法を参照して説明する。なお、図３に示す従来例と対応する部分には、同一符号を付して説明する。
【００１７】
まず、図１（ａ）に示すように、ガラス基板１上に純アルミニウム（Ａｌ）、あるいは、数％以下の微量な不純物を含んだアルミニウム（Ａｌ）を３０００オングストロームの膜厚でスパッタリングにより蒸着し、パターン化して金属膜のゲート電極２を形成し、続いてゲート電極２のＡｌの表面を陽極酸化により酸化アルミニウム（Ａｌ２Ｏ３）膜としての第１のゲート絶縁膜３で被覆する。
【００１８】
続いて、図１（ｂ）に示すように、これら第１のゲート絶縁膜３を含むガラス基板１上に、たとえば酸化ケイ素膜（ＳｉＯＸ）の第２のゲート絶縁膜４を形成し、アモルファス・シリコン（ａ−ＳｉＯＸ）層の半導体層５を形成し、この半導体層５上にエッチング・ストッパ用の窒化ケイ素層であるエッチングストッパ層６を形成する。
【００１９】
その後に、図１（ｃ）に示すように、ゲート電極２に給電部を形成するために、第１のゲート絶縁膜３および第２のゲート絶縁膜４の穴穿けを行なう。
【００２０】
ここで、この工程で使用する装置について、図２を参照して説明する。
【００２１】
図２に示すように、第１の水槽21に４９％フッ化水素酸水溶液を約２０％含んだ水溶液エッチング溶液22を満たし、この水溶液エッチング溶液22中にゲート電極２、第１のゲート絶縁膜３および第２のゲート絶縁膜４が形成されたガラス基板１および対向電極23を互いに対向させて浸漬させる。なお、第１のゲート絶縁膜３および第２のゲート絶縁膜４の穴穿けを行なわない部分はフォトレジストによって覆われている。
【００２２】
また、第２の水槽24にも第１の水槽21と同様に、４９％フッ化水素酸水溶液を約２０％含んだ水溶液エッチング溶液25を満たし、第１の水槽21および第２の水槽24を塩橋にて接続するとともに、第２の水槽24には参照電極27を浸漬する。
【００２３】
そして、ガラス基板１のゲート電極２、対向電極23および参照電極27をそれぞれ電線28，29，30にてポテンショスタット31に接続し、参照電極27で計測された電位に基づき、ポテンショスタット31にて電位を制御する。なお、ゲート電極２はガラス基板１の周辺部に図示しない電極があり外部に取り出される。
【００２４】
また、エッチングに際しては、ゲート電極２は標準水素電極に対し−３．０Ｖの電位を与えてＡｌを不活態の範囲におく。また、対向電極23には標準水素電極に対し０．０Ｖの電位を与え、この状態で約５分間保持し、ＳｉＯＸの第２のゲート絶縁膜４およびＡｌ２Ｏ３の第１のゲート絶縁膜３を続けてエッチングする。
【００２５】
引き続き、今度はゲート電極２に標準水素電極に対し−１．５Ｖの電位を与えてゲート電極２を活性態の範囲におき、約３０秒間保持し、ガラス基板１を水溶液エッチング溶液22より取り出し、純水にて約５分間洗浄し、窒素雰囲気にて乾燥させる。
【００２６】
次に、図１（ｄ）に示すように、第２のゲート絶縁膜４上にＩＴＯ（Indium Tin Oxide）の画素電極７を形成し、エッチングストッパ層６上に画素電極７に接続されたソース電極８およびドレイン電極９を形成して薄膜トランジスタ10を作製するとともに、穿孔されたゲート電極２、第１のゲート絶縁膜３および第２のゲート絶縁膜４には給電部となるパッド電極11を装着し、薄膜トランジスタアレイ12が形成される。
【００２７】
なお、上記実施の形態ではゲート電極２のＡｌを活性態の範囲におき、約３０秒間保持した後に直ちに水洗したが、ゲート電極２のＡｌを再び不活態の範囲におくような電位、たとえば標準水素電極に対し−３．０Ｖの電位を与えて、一旦エッチングを停止した後に水溶液エッチング溶液22より取り出し、続いて水洗してもよい。
【００２８】
ここで、上述のエッチングについて説明する。
【００２９】
まず、金属元素が電解性の水溶液中で腐食されるか否かの目安としてＰｏｕｒｂａｉｘの電位−ｐＨ平衡図が知られている。そして、ゲート電極２に用いたＡｌについての平衡図を見ると、水素イオン濃度指数ｐＨが４以下で、標準水素電極に対する電位が−１．８Ｖよりも卑（電位ＶがＶ＜−１．８Ｖ）である領域では、Ａｌがイオン化せずに安定に存在する領域（不活態）があることがわかる。そこで、第２のゲート絶縁膜４および第１のゲート絶縁膜３のエッチング工程において、表面がＡｌ２Ｏ３の第１のゲート絶縁膜３で覆われたＡｌのゲート電極２を有するガラス基板１を対向電極23とともにフッ化水素酸を含む水溶液エッチング溶液22中に置き、ゲート電極２のＡｌを不活態の電位に置くことで、ゲート電極２のＡｌの表面をエッチングされない状態に保持することができる。
【００３０】
一方で、ゲート電極２のＡｌ上の第１のゲート絶縁膜３のＡｌ２Ｏ３の表面の電位はＡｌ２Ｏ３が高抵抗の絶縁膜であるため対向電極23の電位によって決まり、対向電極23の電位をＡｌよりも貴の電位でＡｌがイオン化する領域（活性態）にすることにより、Ａｌ２Ｏ３の表面の電位もＡｌが活性態の電位に置くことができる。
【００３１】
また、Ａｌが活性態の電位−ｐＨ領域では、Ａｌ２Ｏ３はＡｌと同様にフッ化水素酸を含むエッチング溶液中でエッチングされることから、この状態にガラス基板１を置くことによりゲート電極２のＡｌ上の第１のゲート絶縁膜３のＡｌ２Ｏ３のみを除去できる。したがって、この場合はエッチング時間を長くとっても、ゲート電極２のＡｌが除去されて薄くなったり、無くなったりすることはない。ただし、この場合、この状態でエッチングを終了させると、Ａｌ／Ａｌ２Ｏ３境界、すなわちゲート電極２および第１のゲート絶縁膜３の境界にはＡｌ２Ｏ３に近い組成の薄膜の残渣が残る。そこで、Ａｌの電位を活性態になるようにしてゲート電極２の表面の薄膜状の残渣の除去を行なう。
【００３２】
【発明の効果】
本発明によれば、金属膜を除去しにくい状態、あるいは、金属膜の表面をエッチングされない状態に保持して酸化膜をエッチングし、対向電極の電位を変化させて金属膜が活性態の電位におくことにより、金属膜を適度にエッチングするため、製品の不良率を低下でき、歩留まりを向上できる。
【図面の簡単な説明】
【図１】 本発明の一実施の形態の薄膜トランジスタアレイの製造工程の一部を示す断面図である。
【図２】 同上ゲート絶縁膜の穴穿け工程に用いるエッチング装置を示す説明図である。
【図３】 従来例の薄膜トランジスタアレイの製造工程の一部を示す断面図である。
【符号の説明】
２ 金属膜としてのゲート電極
３ 酸化膜としての第１のゲート絶縁膜
22 エッチング溶液
23 対向電極 [0001]
BACKGROUND OF THE INVENTION
The present invention relates to an etching method in which an oxide film is coated on a metal film, and etching the oxide film and the metal film, and a method for manufacturing a thin film transistor.
[0002]
[Prior art]
In recent years, a thin film transistor (TFT) array for a liquid crystal display device having a large screen is becoming widespread.
[0003]
Here, a conventional method for manufacturing an inverted staggered thin film transistor array in which gate lines are located on a glass substrate will be described with reference to FIG.
[0004]
First, as shown in FIG. 3A, a gate electrode 2 made of pure aluminum or aluminum (Al) containing a trace amount of impurities of several percent or less is wired on a glass substrate 1, and this gate electrode 2 The first gate insulating film 3 is formed by using aluminum oxide (Al 2 O 3 ) as a surface by anodization or the like.
[0005]
Subsequently, as shown in FIG. 3B, a second gate insulating film 4 made of, for example, a silicon oxide film (SiO x ) is formed on the glass substrate 1 including the first gate insulating film 3, and amorphous. A semiconductor layer 5 made of a silicon layer is formed, and an etching stopper layer 6 made of a silicon nitride layer for etching and stopper is formed on the semiconductor layer 5.
[0006]
Thereafter, as shown in FIG. 3C, the second gate insulating film 4, the first gate insulating film 3, and the gate electrode 2 are formed to form a power feeding portion in one gate electrode 2.
[0007]
Further, as shown in FIG. 3D, a pixel electrode 7 made of ITO (Indium Tin Oxide) is formed on the second gate insulating film 4, and the source connected to the pixel electrode 7 on the etching stopper layer 6 is formed. The thin film transistor 10 is formed by forming the electrode 8 and the drain electrode 9, and a pad electrode 11 serving as a power feeding portion is provided on the perforated gate electrode 2, the first gate insulating film 3 and the second gate insulating film 4. The thin film transistor array 12 is formed by mounting.
[0008]
Here, considering the step of drilling the gate electrode 2, the first gate insulating film 3, and the second gate insulating film 4, the second gate insulating film 4 made of SiO X and the first gate insulating film 4 made of Al 2 O 3 . It is necessary to leave the gate electrode 2 after drilling the gate insulating film 3.
[0009]
However, it is very difficult to selectively etch Al 2 O 3 of the first gate insulating film 3 and Al of the gate electrode 2, and it is currently immersed in an etching solution containing hydrofluoric acid. A hole is formed by etching Al 2 O 3 of the first gate insulating film 3 for a certain time and then stopping the etching.
[0010]
However, in this method, the etching rate varies depending on the location, and the reproducibility of the etching rate varies, so it is necessary to increase the etching time in the actual process. Therefore, when etching is performed by this method, it is difficult to leave the gate electrode 2 with a uniform thickness, and the Al of the gate electrode 2 may be thinned or eliminated. This is a cause of defects in the process.
[0011]
[Problems to be solved by the invention]
As described above, in the prior art shown in FIG. 3, it is difficult to leave Al as the gate electrode 2 with a uniform thickness in the step of forming the power feeding portion on the gate electrode 2, and contact with the pad electrode 11 is difficult. It has a problem that may cause defects.
[0012]
The present invention has been made in view of the above problems, and an object of the present invention is to provide an oxide film etching method and a thin film transistor manufacturing method for reliably etching a metal film and an oxide film.
[0013]
[Means for Solving the Problems]
The present invention relates to a method of etching an oxide film in which an oxide film mainly composed of aluminum oxide is coated on a metal film mainly composed of aluminum, and the metal film is removed from the metal film. Immersion in an etching solution having a hydrogen ion concentration index (pH) of 4 or less together with the counter electrode opposed to the film, and the potential applied between the metal film and the counter electrode is lower than a value of −1.8 V with respect to the standard hydrogen electrode. The oxide film is removed under the control of a base potential, and the surface of the metal film is removed by changing the potential applied between the metal film and the counter electrode after the oxide film is removed.
[0014]
And since the said etching solution is a solution containing hydrofluoric acid, a metal film is etched reliably and appropriately.
[0015]
The present invention also provides a method of manufacturing a thin film transistor in which a gate insulating film mainly composed of aluminum oxide is coated on a gate electrode mainly composed of aluminum, and the gate electrode and the gate insulating film are removed. Is immersed in an etching solution having a hydrogen ion concentration index (pH) of 4 or less together with a counter electrode facing the gate electrode, and a potential applied between the gate electrode and the counter electrode is −1.8 V with respect to a standard hydrogen electrode. controls less noble potential than the value by removing the gate insulating film, the applied to between the gate electrode and the counter electrode by changing the potential to remove the surface of the gate electrode after the gate insulating film is removed, the gate Since the gate electrode terminal is provided on the electrode, the gate electrode becomes uniform.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to a method for manufacturing a thin film transistor shown in the drawings. Note that portions corresponding to those of the conventional example shown in FIG.
[0017]
First, as shown in FIG. 1 (a), pure aluminum (Al) or aluminum (Al) containing a trace amount of impurities of several percent or less is deposited on a glass substrate 1 by sputtering to a thickness of 3000 angstroms. Then, the gate electrode 2 of a metal film is formed by patterning, and then the Al surface of the gate electrode 2 is covered with a first gate insulating film 3 as an aluminum oxide (Al 2 O 3 ) film by anodic oxidation.
[0018]
Subsequently, as shown in FIG. 1B, a second gate insulating film 4 made of, for example, a silicon oxide film (SiO x ) is formed on the glass substrate 1 including the first gate insulating film 3, and amorphous. A silicon (a-SiO x ) layer semiconductor layer 5 is formed, and an etching stopper layer 6, which is a silicon nitride layer for etching stopper, is formed on the semiconductor layer 5.
[0019]
Thereafter, as shown in FIG. 1C, holes are formed in the first gate insulating film 3 and the second gate insulating film 4 in order to form a power feeding portion in the gate electrode 2.
[0020]
Here, the apparatus used in this step will be described with reference to FIG.
[0021]
As shown in FIG. 2, the first water tank 21 is filled with an aqueous solution etching solution 22 containing about 20% of a 49% hydrofluoric acid aqueous solution, and the gate electrode 2 and the first gate insulating film are filled in the aqueous solution etching solution 22. The glass substrate 1 on which the third and second gate insulating films 4 are formed and the counter electrode 23 are immersed so as to face each other. Note that the portions of the first gate insulating film 3 and the second gate insulating film 4 that are not drilled are covered with a photoresist.
[0022]
Similarly to the first water tank 21, the second water tank 24 is filled with an aqueous solution etching solution 25 containing about 20% of a 49% hydrofluoric acid aqueous solution, and the first water tank 21 and the second water tank 24 are provided. While being connected by a salt bridge, a reference electrode 27 is immersed in the second water tank 24.
[0023]
Then, the gate electrode 2, the counter electrode 23 and the reference electrode 27 of the glass substrate 1 are connected to the potentiostat 31 by electric wires 28, 29 and 30, respectively, and based on the potential measured by the reference electrode 27, the potentiostat 31 Control the potential. The gate electrode 2 has an electrode (not shown) in the periphery of the glass substrate 1 and is taken out to the outside.
[0024]
In the etching, the gate electrode 2 applies a potential of −3.0 V to the standard hydrogen electrode to place Al in an inactive range. Further, a potential of 0.0 V is applied to the counter electrode 23 with respect to the standard hydrogen electrode, and this state is maintained for about 5 minutes, and the second gate insulating film 4 made of SiO X and the first gate insulating film made of Al 2 O 3 . The film 3 is subsequently etched.
[0025]
Subsequently, a potential of −1.5 V is applied to the gate electrode 2 with respect to the standard hydrogen electrode to place the gate electrode 2 in the active state and hold for about 30 seconds, and the glass substrate 1 is taken out from the aqueous solution etching solution 22. Wash with pure water for about 5 minutes and dry in a nitrogen atmosphere.
[0026]
Next, as shown in FIG. 1D, an ITO (Indium Tin Oxide) pixel electrode 7 is formed on the second gate insulating film 4, and the source connected to the pixel electrode 7 on the etching stopper layer 6 is formed. The thin film transistor 10 is formed by forming the electrode 8 and the drain electrode 9, and the pad electrode 11 serving as a power feeding portion is attached to the perforated gate electrode 2, the first gate insulating film 3 and the second gate insulating film 4. As a result, the thin film transistor array 12 is formed.
[0027]
In the above embodiment, Al in the gate electrode 2 is placed in the active state and is washed with water immediately after being held for about 30 seconds. However, a potential such that Al in the gate electrode 2 is again in the inactive range, for example, A potential of −3.0 V may be applied to the standard hydrogen electrode to stop the etching once, and then remove from the aqueous solution etching solution 22 and then wash with water.
[0028]
Here, the above-described etching will be described.
[0029]
First, as a measure of whether or not a metal element is corroded in an electrolytic aqueous solution, a potential-pH equilibrium diagram of Paulbaix is known. Then, looking at the equilibrium diagram for the Al used for the gate electrode 2, a hydrogen ion concentration index pH of 4 or less, less noble than the potential -1.8V relative to the standard hydrogen electrode (the potential V is V <-1.8V It can be seen that there is a region (inactive state) where Al does not ionize and exists stably in the region which is). Therefore, in the etching process of the second gate insulating film 4 and the first gate insulating film 3, the glass substrate 1 having the Al gate electrode 2 whose surface is covered with the first gate insulating film 3 of Al 2 O 3 . Is placed in an aqueous solution etching solution 22 containing hydrofluoric acid together with the counter electrode 23, and the Al surface of the gate electrode 2 is kept in an unetched state by placing the Al of the gate electrode 2 at an inactive potential. Can do.
[0030]
On the other hand, the potential of the surface of Al 2 O 3 of the first gate insulating film 3 on the Al of the gate electrode 2 is determined by the potential of the counter electrode 23 because Al 2 O 3 is a high-resistance insulating film. By setting the potential of 23 to a region (active state) in which Al is ionized at a potential nobler than Al, the surface potential of Al 2 O 3 can also be placed at the active potential of Al.
[0031]
In addition, in the potential-pH region where Al is in an active state, Al 2 O 3 is etched in an etching solution containing hydrofluoric acid like Al. Therefore, by placing the glass substrate 1 in this state, the gate electrode Only Al 2 O 3 of the first gate insulating film 3 on 2 Al can be removed. Therefore, in this case, even if the etching time is long, Al in the gate electrode 2 is not removed and does not become thin or disappear. However, in this case, if etching is terminated in this state, a thin film residue having a composition close to Al 2 O 3 is present at the Al / Al 2 O 3 boundary, that is, the boundary between the gate electrode 2 and the first gate insulating film 3. Remain. Therefore, the thin film residue on the surface of the gate electrode 2 is removed by setting the potential of Al to the active state.
[0032]
【The invention's effect】
According to the present invention, the metal film is brought into an active potential by changing the potential of the counter electrode by etching the oxide film while keeping the metal film difficult to remove or keeping the surface of the metal film unetched. In this case, the metal film is appropriately etched, so that the defect rate of the product can be reduced and the yield can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a part of a manufacturing process of a thin film transistor array according to an embodiment of the present invention.
FIG. 2 is an explanatory view showing an etching apparatus used in the step of drilling a gate insulating film.
FIG. 3 is a cross-sectional view showing a part of a manufacturing process of a conventional thin film transistor array.
[Explanation of symbols]
2 Gate electrode as metal film 3 First gate insulating film as oxide film
22 Etching solution
23 Counter electrode

Claims (3)

アルミニウムを主成分とした金属膜上に、酸化アルミニウムを主成分とした酸化膜が被覆され、これら金属膜および酸化膜を除去する酸化膜のエッチング方法において、
前記金属膜をこの金属膜に対向させる対向電極とともに水素イオン濃度指数（ｐＨ）が４以下のエッチング溶液中に浸し、
前記金属膜および前記対向電極間に与える電位を、標準水素電極に対し−１．８Ｖの値よりも卑の電位と制御して前記酸化膜を除去し、
この酸化膜除去後に前記金属膜および前記対向電極間に与える電位を変化させて前記金属膜の表面を除去する
ことを特徴とする酸化膜のエッチング方法。In the method of etching an oxide film in which an oxide film mainly composed of aluminum oxide is coated on a metal film mainly composed of aluminum, and the metal film and the oxide film are removed.
Immerse the metal film in an etching solution having a hydrogen ion concentration index (pH) of 4 or less together with a counter electrode facing the metal film,
Wherein the potential applied between the metal film and the counter electrode, the oxide film is removed by controlling the potential more negative than the value of -1.8V to the standard hydrogen electrode,
A method of etching an oxide film, comprising: removing the surface of the metal film by changing a potential applied between the metal film and the counter electrode after the oxide film is removed. 前記エッチング溶液は、フッ化水素酸を含む溶液である
ことを特徴とする請求項１記載の酸化膜のエッチング方法。 The method for etching an oxide film according to claim 1, wherein the etching solution is a solution containing hydrofluoric acid. アルミニウムを主成分としたゲート電極上に、酸化アルミニウムを主成分としたゲート絶縁膜が被覆され、これらゲート電極およびゲート絶縁膜を除去する薄膜トランジスタの製造方法において、
前記ゲート電極をこのゲート電極に対向させる対向電極とともに水素イオン濃度指数（ｐＨ）が４以下のエッチング溶液中に浸し、
前記ゲート電極および前記対向電極間に与える電位を、標準水素電極に対し−１．８Ｖの値よりも卑の電位と制御して前記ゲート絶縁膜を除去し、
このゲート絶縁膜除去後に前記ゲート電極および前記対向電極間に与える電位を変化させて前記ゲート電極の表面を除去し、
前記ゲート電極にゲート電極端子を設ける
ことを特徴とする薄膜トランジスタの製造方法。In the method of manufacturing a thin film transistor, a gate insulating film mainly composed of aluminum oxide is coated on a gate electrode mainly composed of aluminum, and the gate electrode and the gate insulating film are removed.
Immerse the gate electrode in an etching solution having a hydrogen ion concentration index (pH) of 4 or less together with a counter electrode facing the gate electrode,
Wherein the potential applied between the gate electrode and the counter electrode, to control a potential more negative than the value of -1.8V to the standard hydrogen electrode by removing the gate insulating film,
After removing the gate insulating film, the potential applied between the gate electrode and the counter electrode is changed to remove the surface of the gate electrode,
A method of manufacturing a thin film transistor, wherein a gate electrode terminal is provided on the gate electrode.
JP01608496A 1995-03-27 1996-01-31 Oxide film etching method and thin film transistor manufacturing method Expired - Fee Related JP3651509B2 (en)

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JP6721195 1995-03-27
JP7-67211 1995-03-27
JP01608496A JP3651509B2 (en) 1995-03-27 1996-01-31 Oxide film etching method and thin film transistor manufacturing method

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