JP3641596B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, with the rapid expansion of the market for digital audio cameras and other portable audio devices such as mobile phones, the demand for flash memory is rapidly expanding. At present, the demands for smaller, lighter, and higher functionality of these devices are becoming more and more demanding, and accordingly, the miniaturization, higher integration, lower power supply voltage, and higher reliability of flash memory are increasingly required. It is becoming. In particular, the demand for NAND-type flash memories is growing rapidly because of their high speed and easy integration.
[0003]
In a NAND flash memory, since the power supply voltage is higher than that of a normal MOS transistor, improvement in reliability is indispensable. For example, suppression of erroneous writing during standby and improvement of the breakdown voltage of the select gate transistor are important for improving the reliability of the flash memory.
[0004]
As a measure for improving the reliability, the concentration of the source / drain diffusion layer is lowered. This method is currently the most effective means in terms of improving the breakdown voltage and suppressing erroneous writing.
[0005]
FIG. 8 is a cross-sectional view of a conventional flash memory.
[0006]
As shown in FIG. 8, the tunnel insulating film 3 is formed on the semiconductor substrate 10. A floating gate 2 is formed on the tunnel insulating film 3. A gate insulating film 4 is formed on the floating gate 2. A control gate 1 is formed on the gate insulating film 4. A source region 8 and a drain region 9 are formed in the semiconductor substrate 10 so as to sandwich the tunnel insulating film 3. The source region 8 and the drain region 9 have a low diffusion concentration in order to improve breakdown voltage and suppress erroneous writing.
[0007]
The surfaces of the floating gate 2 and the control gate 1 are covered with an insulating film 5. A side wall insulating film 7 made of silicon nitride is formed on the side wall of the laminated structure including the floating gate 2 and the control gate 1.
[0008]
However, this manufacturing method may cause problems in the electrical characteristics of the device. In the NAND flash memory, a self-aligned contact is formed on the selection gate transistor. At this time, a nitride film is formed on the sidewall insulating film 7 in order to obtain a selection ratio. However, many trap sites are formed in a region in contact with the insulating film 6 located under the side wall insulating film 7. During the flash operation, most of the electrons are exchanged between the floating gate 2 and the semiconductor substrate 10 through the tunnel insulating film 3, but there are also electrons exchanged through the sidewall insulating film 7 and the insulating film 6. To do.
[0009]
Since the sidewall nitride film 7 is made of nitride, a trap site is formed in an interface region with the insulating film 6, and electrons are trapped in the trap site, thereby obtaining an interface state. Since the concentration of the source region 8 and the drain region 9 is low for the reason described above, a depletion layer is formed under the sidewall insulating film 7 of the source region 8 and the drain region 9 by the trapped electrons. Since this depletion layer increases the parasitic resistance, there is a problem that the drain current value is lowered.
[0010]
[Problems to be solved by the invention]
Conventionally, a reduction in diffusion layer concentration has been required from the viewpoint of improving breakdown voltage and preventing erroneous writing. However, a reduction in the diffusion layer concentration has a problem of increasing parasitic resistance due to depletion of the diffusion layer surface due to the interface state under the sidewall nitride film.
[0011]
The present invention has been made to solve the above problems, and prevents the depletion of the diffusion layer surface due to the interface state under the sidewall insulating film, and can improve the breakdown voltage, prevent erroneous writing, and improve the driving force. An object is to provide an apparatus and a method for manufacturing the same.
[0012]
[Means for Solving the Problems]
To achieve the above object, the present invention provides a silicon semiconductor substrate, a tunnel insulating film formed on the silicon semiconductor substrate, a floating gate formed on the tunnel insulating film, and formed on the floating gate. A gate insulating film, a control gate formed on the gate insulating film, an insulating film covering the floating gate and the control gate, and a channel formed in the silicon semiconductor substrate under the tunnel insulating film A source region and a drain region formed in such a manner as to be spaced apart from each other in the silicon semiconductor substrate and the channel region being located therebetween, and at a position facing the floating gate on the source region and the drain region. Undoped silicon semiconductor region, source region and drain A doped silicon semiconductor region formed on the undoped silicon semiconductor region at a position in contact with the undoped silicon semiconductor region, and a silicon nitride film formed on the undoped silicon semiconductor region without being formed on the doped silicon semiconductor region. A semiconductor memory device comprising: I will provide a.
[0014]
The present invention also includes a step of forming a tunnel insulating film on a silicon semiconductor substrate, a step of forming a floating gate on the tunnel insulating film, a step of forming a gate insulating film on the floating gate, and the gate A step of forming a control gate on the insulating film; a step of covering the floating gate, the control gate and the silicon semiconductor substrate with an insulating film; and a source region in the silicon semiconductor substrate using the floating gate and the control gate as a mask. And a step of forming a drain region, a step of exposing a silicon semiconductor substrate surface adjacent to the stacked structure including the floating gate and the control gate, and a step of selectively growing a silicon layer on the exposed surface of the silicon semiconductor substrate. , the controlling Forming a silicon nitride film on the side wall of Rugeto, the silicon which is not covered with the silicon nitride film and the undoped region of the silicon layer facing the floating gate by implanting impurity of the silicon nitride film as a mask And a method of manufacturing a semiconductor memory device, comprising: forming a layer as a doped region.
[0015]
The present invention also includes a step of forming a tunnel insulating film on a silicon semiconductor substrate, a step of forming a floating gate on the tunnel insulating film, a step of forming a gate insulating film on the floating gate, and the gate forming a controls the gate on an insulating film, a step of covering said floating gate, a control gate and the silicon semiconductor substrate over an insulating layer, depositing a silicon layer on the silicon semiconductor substrate over the entire surface, the silicon Etching the layer to leave the silicon layer on the surface of the silicon semiconductor substrate adjacent to the stacked structure comprising the floating gate and the control gate ; forming a silicon nitride film on a side wall of the control gate; and Impurities are implanted using the nitride film as a mask. And simultaneously forming a source region and a drain region while using the silicon layer facing the floating gate as an undoped region and the silicon layer not covered by the silicon nitride film as a doped region. A method for manufacturing a semiconductor memory device is provided.
[0019]
According to the present invention, since the undoped silicon semiconductor region is provided between the silicon nitride film and the silicon semiconductor substrate surface, the distance between the interface state below the silicon nitride film and the silicon substrate surface can be increased. . For this reason, even when the concentration of the source diffusion layer and the drain diffusion layer is low as in a fine flash memory, depletion of the diffusion layer surface due to the interface state below the silicon nitride film can be suppressed. Accordingly, it is possible to suppress a decrease in current driving force accompanying a decrease in diffusion concentration, which becomes more noticeable in a micro flash memory or the like, and it is possible to improve driving voltage while improving breakdown voltage and preventing erroneous writing.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
The details of the present invention will be described below with reference to the illustrated embodiments.
[0021]
(First embodiment)
FIG. 1 is a sectional view showing an element structure of a nonvolatile semiconductor memory device according to the first embodiment of the present invention. Although FIG. 1 shows the configuration of one cell portion, this cell structure can be applied to various memory cell units of NAND type, NOR type, OR type, and AND type.
[0022]
As shown in FIG. 1, a tunnel insulating film 3 is formed on a p-type silicon substrate 10. A floating gate 2 is formed on the tunnel insulating film 3. A gate insulating film 4 is formed on the floating gate 2. A control gate 1 is formed on the gate insulating film 4. The floating gate 2 and the control gate 1 are covered with an insulating film 5 made of coating silicon oxide. A sidewall insulating film 7 made of silicon nitride is formed on the side surface of the control gate 1 via an insulating film 5.
[0023]
A source region 8 and a drain region 9 made of an n-type impurity diffusion layer are formed in a silicon substrate 10 at a position sandwiching a channel region under the tunnel insulating film 3. Regions 17 and 18 made of silicon are formed on the source region 8 and the drain region 9. Of the region made of silicon, the region 18 under the side wall insulating film 7 made of silicon nitride and facing the floating gate 2 is an undoped insulating region. Of the region made of silicon, the region 17 not covered with the sidewall insulating film 7 is a conductive region doped with an n-type impurity. The silicon region 17 is doped by ion implantation using the sidewall insulating film 7 as a mask. Since the sidewall insulating film 7 is masked, the silicon region 18 becomes an undoped region which is not doped with impurities. Thus, it is desirable for maintaining the insulating property that the region 17 is not formed under the sidewall insulating film.
[0024]
In this semiconductor memory device, an undoped silicon region 18 is provided on a silicon substrate 10 under a sidewall insulating film 7 made of a silicon nitride film. As a result, the distance between the interface state existing under the sidewall insulating film 7 and the surface of the silicon substrate 10 can be increased. For this reason, even when the concentrations of the source region 8 and the drain region 9 are low, it is possible to suppress the depletion of the surfaces of the source region 8 and the drain region 9 due to the interface state existing under the sidewall insulating film 7. become.
[0025]
FIG. 2 shows impurity profiles of the source region 8 and the drain region 9. In FIG. 2, a curve indicated by A is a profile of the source region 8 and the drain region 9 of the semiconductor memory device. A curve indicated by B is a profile of the source region 8 and the drain region 9 in the case where the side wall insulating film 7 is formed directly on the semiconductor substrate 10 without the silicon regions 17 and 18.
[0026]
As can be seen from FIG. 2, in the curve indicated by A, the impurity profile is steeper and shallower than the curve indicated by B. Therefore, in the structure of this semiconductor memory device, a shallower junction can be formed, and the leakage current between the source region 8 and the drain region 9 can be suppressed. Furthermore, the breakdown voltage between the source region 8 and the drain region 9 can be improved.
[0027]
Actually, the distance between the sidewall insulating film 7 and the silicon substrate 10 is a design matter and depends on how much parasitic resistance on the surface of the drain region is allowed in the design. Thus, the thickness of the undoped silicon region 18 may be determined.
[0028]
Next, an example of a method for manufacturing the semiconductor memory device of this embodiment will be described with reference to FIG.
[0029]
First, as shown in FIG. 3A, the tunnel insulating film 3 is formed on the p-type silicon substrate 10. Next, the floating gate 2 is formed on the tunnel insulating film 3. Next, a gate insulating film 4 is formed on the floating gate 2. Next, the control gate 1 is formed on the gate insulating film 4.
[0030]
For example, silicon oxide may be used for the tunnel insulating film 3 and the gate insulating film 4. For example, polycrystalline silicon may be used for the floating gate 2 and the control gate. As a method for forming each film, CVD, sputtering, or the like may be used. In addition, this stacked structure may be patterned using a mask or may be shaped using selective growth.
[0031]
Next, as shown in FIG. 3B, the surface of the laminated structure including the floating gate 2 and the control gate 1 is covered with an insulating film 5 made of silicon oxide.
[0032]
Next, as shown in FIG. 3 (c), by ion implantation of the first through the insulating film 5 for the covering, at positions sandwiching the floating gate 2, a source region 8 and a drain region made of n-type impurity diffusion regions 9 is formed.
[0033]
Next, as shown in FIG. 3D, the insulating film 5 on the source region 8 and the drain region 9 is etched to expose the surface of the silicon substrate 10 near the floating gate 2. Next, the silicon layer 11 is selectively epitaxially grown from the exposed surface of the silicon substrate 10.
[0034]
Next, as shown in FIG. 3E, a sidewall insulating film 7 made of silicon nitride is formed on the sidewall of the control gate 1. The sidewall insulating film 7 may be left on the sidewall of the control gate 1 by RIE after silicon nitride is deposited on the entire surface of the silicon substrate 10.
[0035]
Next, as shown in FIG. 3F, a region 17 doped with impurities at a high concentration is formed in the silicon layer 11 by the second shallow ion implantation. At this time, the sidewall insulating film 7 serves as a mask, and the region 18 facing the floating gate 2 becomes an insulating region not doped with impurities. In this manner, the semiconductor memory device shown in FIG. 1 can be formed.
[0036]
In this embodiment, the undoped silicon region 18 is formed under the sidewall insulating film made of silicon nitride. This is because the annealing after the second shallow ion implantation is not performed, or even when annealing is performed, a method using lamp annealing to suppress diffusion as small as possible is used. In this way, a sufficient breakdown voltage can be provided. Further, an undoped silicon region 18 may be formed so as to spread from the bottom to the outside of the sidewall insulating film 7 in order to have a higher breakdown voltage. As a formation method, lithography is added to form a mask larger than the sidewall insulating film 7 and used.
[0037]
(Second Embodiment)
FIG. 4 is a sectional view showing an element structure of a nonvolatile semiconductor memory device according to the second embodiment of the present invention. Although FIG. 4 shows the configuration of one cell portion, this cell structure can be applied to various memory cell units of NAND type, NOR type, OR type, and AND type.
[0038]
The difference between the element structure of the nonvolatile semiconductor memory device according to the second embodiment and the element structure described in the first embodiment is caused by a difference in manufacturing process.
[0039]
As shown in FIG. 4, a tunnel insulating film 3 is formed on a p-type silicon substrate 10. A floating gate 2 is formed on the tunnel insulating film 3. A gate insulating film 4 is formed on the floating gate 2. A control gate 1 is formed on the gate insulating film 4. The floating gate 2 and the control gate 1 are covered with a covering insulating film 5. A sidewall insulating film 7 made of silicon nitride is formed on the side surface of the control gate 1 via an insulating film 5.
[0040]
A region 16 of silicon not doped with impurities is formed on the silicon substrate 10 at a position facing the floating gate 2. Next to the insulating region 16, a silicon region 15 doped with n-type impurities is formed. Thus, it is desirable for maintaining the insulating property that the region 15 is not formed under the sidewall insulating film 7.
[0041]
In the present embodiment, a silicon region is deposited and etched by RIE and left in the vicinity of the gate portion. A sidewall insulating film 7 is formed on the sidewall of the control gate 1 on the silicon region. Thereafter, an impurity is doped to divide into an impurity doped region 15 and an undoped region 16. Thus, the point which shape | molds a silicon area | region by RIE first differs from 1st Embodiment.
[0042]
A source region 8 and a drain region 9 made of an n-type impurity diffusion layer are formed in a silicon substrate 10 at a position sandwiching a channel region under the tunnel insulating film 3. Regions 15 and 16 made of silicon are formed on the source region 8 and the drain region 9. Of the region made of silicon, a region 16 below the side wall insulating film 7 and facing the floating gate 2 is an undoped insulating region. In addition, a region 15 that is not covered with the sidewall insulating film 7 in a region made of silicon is a conductive region doped with an n-type impurity.
[0043]
The source region 8 and the drain region 9 are doped by ion implantation using the sidewall insulating film 7 as a mask simultaneously with the impurity doped region 15 of silicon. Accordingly, the doped region 15 of silicon is doped with impurities of the same conductivity type as the source region 8 and the drain region 9. Since the sidewall insulating film 7 is masked, the silicon region 16 becomes an undoped region which is not doped with impurities.
[0044]
In this semiconductor memory device, an undoped silicon region 16 is provided between the sidewall insulating film 7 and the surface of the silicon substrate 10. As a result, the distance between the interface state existing under the sidewall insulating film 7 and the surface of the silicon substrate 10 can be increased. For this reason, even when the concentrations of the source region 8 and the drain region 9 are low, it is possible to suppress the depletion of the surfaces of the source region 8 and the drain region 9 due to the interface state existing under the sidewall insulating film 7. become.
[0045]
Next, an example of a method for manufacturing the semiconductor memory device of this embodiment will be described with reference to FIG.
[0046]
First, as shown in FIG. 5A, the tunnel insulating film 3 is formed on the p-type silicon substrate 10. Next, the floating gate 2 is formed on the tunnel insulating film 3. Next, a gate insulating film 4 is formed on the floating gate 2. Next, the control gate 1 is formed on the gate insulating film 4.
[0047]
For example, silicon oxide may be used for the tunnel insulating film 3 and the gate insulating film 4. For example, polycrystalline silicon may be used for the floating gate 2 and the control gate. As a method for forming each film, CVD, sputtering, or the like may be used. In addition, this stacked structure may be patterned using a mask or may be shaped using selective growth.
[0048]
Next, as shown in FIG. 5B, the surface of the laminated structure including the floating gate 2 and the control gate 1 is covered with an insulating film 5 made of silicon oxide.
[0049]
Next, as shown in FIG. 5C, a silicon layer 14 is deposited on the entire surface of the silicon substrate 10.
[0050]
Next, as shown in FIG. 5D, the silicon layer 14 is etched by RIE and left in the vicinity of the gate portion.
[0051]
Next, as shown in FIG. 5E, a sidewall insulating film 7 made of silicon nitride is formed on a part of the silicon layer 14 as the sidewall of the control gate 1. The sidewall insulating film 7 may be left on the sidewall of the control gate 1 by RIE after silicon nitride is deposited on the entire surface of the silicon substrate 10.
[0052]
Next, an n-type source region 8 and an n-type drain region 9 are formed by ion implantation. At this time, the silicon region 14 is composed of a region 15 doped with impurities of the same conductivity type as the source region 8 and drain region 9 and a region 16 not doped with impurities and facing the floating gate 2. . In this manner, the semiconductor memory device shown in FIG. 4 can be formed.
[0053]
(Third embodiment)
FIG. 6 is a sectional view showing an element structure of a nonvolatile semiconductor memory device according to the third embodiment of the present invention. Although FIG. 6 shows the configuration of one cell portion, this cell structure can be applied to various memory cell units of NAND type, NOR type, OR type, and AND type.
[0054]
The difference between the element structure of the nonvolatile semiconductor memory device according to the third embodiment and the element structure described in the first and second embodiments is that a region made of a silicon oxide film under a side wall insulating film made of silicon nitride. Is provided.
[0055]
As shown in FIG. 6, a tunnel insulating film 3 is formed on a p-type silicon substrate 10. A floating gate 2 is formed on the tunnel insulating film 3. A gate insulating film 4 is formed on the floating gate 2. A control gate 1 is formed on the gate insulating film 4. The floating gate 2 and the control gate 1 are covered with a covering insulating film 5. A sidewall insulating film 7 made of silicon nitride is formed on the side surface of the control gate 1 via an insulating film 5.
[0056]
A region 20 made of a silicon oxide film is formed on the silicon substrate 10 under a side wall insulating film made of silicon nitride. In the present embodiment, a region 20 made of a silicon oxide film is deposited on the entire surface of the silicon substrate 10 and etched by RIE so as to remain in the vicinity of the gate portion.
[0057]
A source region 8 and a drain region 9 made of an n-type impurity diffusion layer are formed in a silicon substrate 10 at a position sandwiching a channel region under the tunnel insulating film 3. A region 20 made of SiO ₂ is formed on the source region 8 and the drain region 9. The source region 8 and the drain region 9 are doped by ion implantation using a formation region including the floating gate 2 and the control gate 1 as a mask.
In this semiconductor memory device, a region 20 made of a silicon oxide film is provided between the sidewall insulating film 7 and the surface of the silicon substrate 10. As a result, the distance between the interface state existing under the sidewall insulating film 7 and the surface of the silicon substrate 10 can be increased. For this reason, even when the concentrations of the source region 8 and the drain region 9 are low, it is possible to suppress the depletion of the surfaces of the source region 8 and the drain region 9 due to the interface state existing under the sidewall insulating film 7. become.
[0058]
Next, an example of a method for manufacturing the semiconductor memory device of this embodiment will be described with reference to FIG.
[0059]
First, as shown in FIG. 7A, a tunnel insulating film 3 is formed on a p-type silicon substrate 10. Next, the floating gate 2 is formed on the tunnel insulating film 3. Next, a gate insulating film 4 is formed on the floating gate 2. Next, the control gate 1 is formed on the gate insulating film 4.
[0060]
For example, silicon oxide may be used for the tunnel insulating film 3 and the gate insulating film 4. For example, polycrystalline silicon may be used for the floating gate 2 and the control gate. As a method for forming each film, CVD, sputtering, or the like may be used. In addition, this stacked structure may be patterned using a mask or may be shaped using selective growth.
[0061]
Next, as shown in FIG. 7B, the surface of the laminated structure including the floating gate 2 and the control gate 1 is covered with an insulating film 5 made of silicon oxide. Next, the source region 8 and the drain region 9 are formed by ion implantation using the gate structure as a mask.
[0062]
Next, as shown in FIG. 7C, a silicon oxide film 20 is deposited on the entire surface of the silicon substrate 10.
[0063]
Next, as shown in FIG. 7D, the silicon oxide film 20 is etched by RIE and left in the vicinity of the gate portion.
[0064]
Next, as shown in FIG. 7E, a sidewall insulating film 7 made of silicon nitride is formed on a part of the silicon oxide film 20 as a sidewall of the control gate 1. The sidewall insulating film 7 may be left on the sidewall of the control gate 1 by RIE after silicon nitride is deposited on the entire surface of the silicon substrate 10.
In this manner, the semiconductor memory device shown in FIG. 6 can be formed.
[0065]
【The invention's effect】
Even when the concentration of the source region and the drain region is low, depletion of the surface of the diffusion layer due to the interface state existing under the sidewall nitride film can be suppressed, and the driving force is improved while improving the breakdown voltage and preventing erroneous writing. Can do.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 shows an impurity profile of a source region and a drain region when there is no silicon layer between a semiconductor substrate and a sidewall insulating film, and an impurity profile of a source region and a drain region when there is a silicon layer.
FIG. 3 is a cross-sectional view for explaining a manufacturing process of the semiconductor memory device according to the first embodiment;
FIG. 4 is a cross-sectional view of a semiconductor memory device according to a second embodiment of the present invention.
FIG. 5 is a cross-sectional view for explaining a manufacturing process of a semiconductor memory device according to a second embodiment.
FIG. 6 is a cross-sectional view of a semiconductor memory device according to a third embodiment of the present invention.
FIG. 7 is a cross-sectional view for explaining a manufacturing process of a semiconductor memory device according to a third embodiment.
FIG. 8 is a cross-sectional view of a conventional semiconductor memory device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Control gate 2 ... Floating gate 3 ... Tunnel insulating film 4 ... Gate insulating film 5 ... Insulating film 6 ... Insulating film 7 ... Side wall insulating film 8 ... Source region 9 ... Drain region 10 ... Silicon substrate 17 ... Doped silicon Region 18 ... Undoped silicon region 20 ... Silicon oxide film

Claims (3)

  A silicon semiconductor substrate, a tunnel insulating film formed on the silicon semiconductor substrate, a floating gate formed on the tunnel insulating film, a gate insulating film formed on the floating gate, and the gate insulating film A control gate formed in, an insulating film covering the floating gate and the control gate, a channel region formed in the silicon semiconductor substrate under the tunnel insulating film, and spaced apart in the silicon semiconductor substrate, A source region and a drain region formed so that the channel region is located therebetween; an undoped silicon semiconductor region formed at a position facing the floating gate on the source region and the drain region; and the source region and the drain Said undoped silicon half on the region A doped silicon semiconductor region formed at a position in contact with a body region; and a silicon nitride film formed on the undoped silicon semiconductor region without being formed on the doped silicon semiconductor region. Semiconductor memory device. Forming a tunnel insulating film on the silicon semiconductor substrate; forming a floating gate on the tunnel insulating film; forming a gate insulating film on the floating gate; and a control gate on the gate insulating film Forming a source region and a drain region in the silicon semiconductor substrate using the floating gate and the control gate as a mask, and a step of covering the floating gate, the control gate and the silicon semiconductor substrate with an insulating film. a step, a step of exposing the silicon semiconductor substrate surface adjacent to a stack structure including the floating gate and a control gate, a step of selectively growing a silicon layer on the exposed silicon semiconductor substrate surface, the side of the control gate Forming a silicon nitride film, the silicon layer which is not covered with the silicon nitride film and the undoped region of the silicon layer facing the floating gate by implanting impurity of the silicon nitride film as a mask doped A method for manufacturing a semiconductor memory device. Forming a tunnel insulating film on a silicon semiconductor substrate, the tunnel forming a floating gate on the insulating film, forming a gate insulating film on the floating gate, controls the gate insulating film Forming a gate; covering the floating gate, the control gate and the silicon semiconductor substrate with an insulating film; depositing a silicon layer over the entire surface of the silicon semiconductor substrate; etching the silicon layer to A step of leaving the silicon layer on the surface of the silicon semiconductor substrate adjacent to the laminated structure including a floating gate and a control gate ; a step of forming a silicon nitride film on a sidewall of the control gate; and an impurity using the silicon nitride film as a mask By injecting before And a step of simultaneously forming a source region and a drain region while using the silicon layer facing the floating gate as an undoped region and the silicon layer not covered by the silicon nitride film as a doped region. Device manufacturing method.

Images