JP3638136B2 - Lead frame and semiconductor device using the same - Google Patents

Lead frame and semiconductor device using the same Download PDF

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JP3638136B2
JP3638136B2 JP2001398158A JP2001398158A JP3638136B2 JP 3638136 B2 JP3638136 B2 JP 3638136B2 JP 2001398158 A JP2001398158 A JP 2001398158A JP 2001398158 A JP2001398158 A JP 2001398158A JP 3638136 B2 JP3638136 B2 JP 3638136B2
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semiconductor chip
chip mounting
mounting region
lead
lead frame
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JP2003197846A (en
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淳 福井
圭一 辻本
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Mitsui High Tech Inc
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
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  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、リードフレームおよびこれを用いた半導体装置にかかり、特に、樹脂封止体の側面ではなく、底面にリードが露出するように形成された半導体装置に関する。
【０００２】
【従来の技術】
近年、電子機器に装着される半導体装置は、携帯電話、ＰＤＡなどの携帯用端末等に採用されるため、小型化、薄型化、軽量化が求められている。
【０００３】
そしてその小型化、薄型化および軽量化、さらには高集積化を実現すべく、半導体装置の実装においては種々の提案がなされており、リードフレーム、ＴＡＢ（Tape Automated Bonding）テープを使用するＴＢＧＡ、フレキシブルなプリント基板を使用するＰＢＧＡやＣＳＰ（チップサイズパッケージ）と呼ばれる、チップのサイズと同等のウェハスケールＣＳＰ、またはチップサイズよりも若干大きいサイズのＣＳＰなどが開発されている。なかでもＳＯＮ（Small Outline Non-leaded package）、ＱＦＮ（Quad FlatNon-leaded package）と呼ばれる、樹脂封止体の側面ではなく、底面にリードが露出するように形成されたタイプの半導体装置が注目されている。
【０００４】
例えばＱＦＮタイプの半導体装置は図９（ａ）に斜視図および図９（ｂ）に裏面図、図１０に断面図を示すように、リード２は封止樹脂６からなるパッケージの側面には突出することなく、裏面に露呈しており、小型でかつコンパクトな面実装タイプの半導体装置を構成するものである。
【０００５】
このような半導体装置では、半導体チップ4を搭載するための半導体チップ搭載領域（パッド）１が封止樹脂６から露呈しており、リード２と同一面上に形成されている。この構造ではプリント基板１０への装着に際しては、図１２に示すように、プリント基板１０上の回路パターン13は、リード２に対応する個所以外はレジスト１１で被覆されており、このレジスト１１から露呈する回路パターン１３の領域のみが半田１２を介してリード２と接続されている。
【０００６】
この半導体装置は図１１（ａ）乃至（ｅ）にその製造工程図を示すように、図１３に示すような一括モールド（ＭＡＰ：Mold Array Package）タイプのリードフレームを用いて形成される。
【０００７】
すなわちまず図１１（ａ）に示すように、リードフレーム形成用の条材の表面および裏面にパターン形成用のレジストパターン（図示せず）を形成し、これをマスクとして、エッチングを行い、半導体チップを搭載するためのパッド１とこのパッドの周りに先端が位置するように形成されたリード２とを有するリードフレームが形成される。このリードフレームは、図１３に示すように、パッド１がサポートバー7で支持され、全体としては多数のリードフレームが配列された状態で形成される。
【０００８】
このようなリードフレームを用い、図１１（ｂ）に示すように裏面側に樹脂の漏れを防止するためのカバーフィルム3を貼着する。こののち、図１１（ｃ）に示すように半導体チップ4をパッド１上に固着したのち、ワイヤボンディング法を用いて、半導体チップのボンディングパッドとリード2の先端とをボンディングワイヤ５によって接続する。そして一括して樹脂封止を行ない、図１１（ｄ）に示すように封止樹脂６で半導体チップ４およびボンディングワイヤが覆われるように金型（図示せず）内で成型する。
【０００９】
そして最後に、カバーフィルム3を除去し、ダイシングにより個々の半導体装置に分離し、図１１（ｅ）に示すような半導体装置が形成される。
【００１０】
【発明が解決しようとする課題】
しかし、この種の半導体装置には以下のような問題点があった。半導体チップ４を搭載したパッド１全面を封止樹脂６の外部に露出するタイプの場合、封止樹脂６とパッド１との界面に剥離が生じるおそれがあり、またパッケージの反りの一因にもなる。
【００１１】
さらに又図１２に示したように、このような半導体装置を実装するためのプリント基板１０上の回路パターン１３は、リード２に対応する個所以外はレジスト１１で被覆されており、このレジスト１１から露呈する回路パターン１３の領域のみが半田１２を介してリード２と接続されている。
【００１２】
しかしながら図１２に示すように、レジスト１１は厚さが薄いため、露出したパッド１が実装基板１０上の回路パターン１１と電気的に接触してしまうおそれもある。
【００１３】
また、このタイプの半導体装置に置いては、樹脂封止時にリード２およびパッド１の露出面に樹脂漏れが発生するのを防止するため、リードフレームの裏面前面にカバーフィルム３を貼着している。このようなカバーフィルム3は、リードフレームの形状加工後に貼着され、この状態で半導体チップ4の搭載やワイヤボンディングが行なわれるが、これらの工程においては、ヒータプレートなどによりパッド１の下面を支持する必要があるため、パッド１の下面ではカバーフィルム３を除去しなければならないという問題があった。
【００１４】
本発明は前記実情に鑑みてなされたもので、封止樹脂との密着性が良好で、実装時のショート不良のない信頼性の高い半導体装置を提供することを目的とする。
【００１５】
【課題を解決するための手段】
そこで本発明では、半導体チップを搭載する半導体チップ搭載領域と、前記半導体チップ搭載領域から所定の間隔を隔てて形成された複数のリードとを具備し、前記半導体チップ搭載領域は、前記リードの底面よりも上方に底面を有し、かつ前記底面から突出せしめられた少なくとも１つの突出部を有し、前記突出部の先端面が、前記リードの底面と一致するように構成されているリードフレームであって、
前記突出部は、前記半導体チップ搭載領域に、絶縁性部材を介して貼着された柱状突起であることを特徴とすることを特徴とする。
【００１６】
かかる構成によれば、半導体チップ搭載領域は突出部を除いて裏面側も封止樹脂で被覆されることになり、樹脂との接触面積が増大し、樹脂と半導体チップ搭載領域であるパッドとの密着性が向上する。また封止樹脂からなるパッケージの反りも防止される。
【００１７】
また実装基板上の配線パターンと半導体チップ搭載領域との電気的接触が生じる危険性が低減される。またこの突出部を避けるように回路パターンを形成することにより、半導体チップ搭載領域と回路パターンとの電気的接触はほぼ完全に防ぐことが可能となる。また、半導体チップ搭載領域にのみポストを形成しており、リード底面は全面が封止樹脂から露出するようにすることができ、実装面積に影響を与えることなく形成することができるため、実装性も良好である。
【００１８】
さらにリードフレームの裏面にカバーフィルムを貼付した状態で半導体チップの搭載およびワイヤボンディングを行なうに際しても、突出部（ポスト）により半導体チップ搭載領域を支持することができる。
【００１９】
望ましくは、前記半導体チップ搭載領域および前記リードおよび前記突出部は同一の条材を成型加工して一体的に形成されたものであることを特徴とする。かかる構成によれば、上記効果に加え、容易に作業性よく形成される。
【００２０】
望ましくは、前記半導体チップ搭載領域は前記突出部を残してハーフエッチングすることにより形成されたものであることを特徴とする。かかる構成によれば、通常の成型加工において、裏面側マスクを修正するのみでよく、容易にハーフエッチングを行なうのみで形成でき、極めて容易に作業性よく形成される。
【００２１】
望ましくは、前記突出部は、前記半導体チップ搭載領域に、絶縁性部材を介して貼着された柱状体であることを特徴とする。かかる構成によれば、突出部と半導体チップ搭載領域とは別部材で形成され、突出部が絶縁性接着剤などの絶縁性部材を介して前記突出部に固着せしめられるようにすれば、前記突出部は前記半導体チップ搭載領域に搭載される半導体チップと何ら電気的接続をなしておらず、したがって実装基板上の回路パターンに接触したとしても不良を生じることはない。また、この突出部の裏面に酸化膜を形成するなど絶縁処理をしておくようにしてもよい。
【００２２】
望ましくは、前記突出部は、前記半導体チップ搭載領域の中央部に形成された1個の柱状突起からなることを特徴とする。かかる構成によれば、露出面積が小さいため、封止樹脂の剥離防止効果も高くまた、回路パターンとの接触を効果的に防止することができる。
【００２３】
望ましくは、前記突出部は、前記半導体チップ搭載領域の中央部と、前記半導体チップ搭載領域の対角線上とに形成された複数個の突起からなることを特徴とする。かかる構成によれば、上記効果に加え、組み立て実装時の安定性が向上する。
【００２４】
また、前記突出部は、前記半導体チップ搭載領域の中央部と、前記中央部を囲むようにその周辺の複数箇所に形成された複数個の突起からなることを特徴とする。かかる構成によれば、上記効果に加え、組み立て実装時の安定性が向上する。
【００２５】
望ましくは、前記突出部は、前記半導体チップ搭載領域の中央部と、前記中央部を囲むと共に、前記中央部に位置するものよりも径大となるようにその周辺の複数箇所に形成された複数個の突起からなることを特徴とする。突起の形成をハーフエッチングにより行なう場合、突出部を径大とすることにより、エッチングによる形成が容易となる。
【００２６】
さらに、本発明の半導体装置では、表面に、半導体チップを搭載する半導体チップ搭載領域と、前記半導体チップ搭載領域から所定の間隔を隔てて形成された複数のリードと、前記半導体チップ搭載領域に搭載され、前記リードの各ボンディング領域とワイヤボンディングにより接続された半導体チップと、少なくとも前記リードの前記他端部分の底面側が露呈するように前記半導体チップおよび前記リードの先端部分を被覆する封止樹脂とを具備し、前記半導体チップ搭載領域は、前記リードの前記底面よりも上方に底面を有し、かつ前記底面から突出せしめられた少なくとも１つの前記半導体チップ搭載領域に絶縁性部材を介して貼着された柱状突出部を有し、前記突出部の先端面が、前記リードの前記底面と一致するように構成され、前記半導体チップ搭載領域は前記封止樹脂で被覆されており、前記突出部の底面のみが前記封止樹脂から露呈せしめられていることを特徴とする。かかる構成によれば、突出部を除いて半導体チップ搭載領域の裏面側にも封止樹脂が入り込むため密着性が向上し、樹脂抜けが防止され信頼性の高い半導体装置を提供することができる。また封止樹脂からなるパッケージの反りも防止される。
【００２７】
また実装基板上の配線パターンと半導体チップ搭載領域との電気的接触の危険性が低減される。またこの突出部を避けるように回路パターンを形成することにより、半導体チップ搭載領域と回路パターンとの電気的接触はほぼ完全に防ぐことが可能となる。また、半導体チップ搭載領域にのみポストを形成しており、リード底面は全面が封止樹脂から露出するようにすることができ、実装面積に影響を与えることなく形成することができるため、実装性も良好である。
【００２８】
【発明の実施の形態】
以下、本発明の参考例について図面を参照しつつ詳細に説明する。本発明の参考例のリードフレームおよびこれを用いた半導体装置について説明する。図１（ａ）に本発明の第1の実施の形態のリードフレームを用いて形成した半導体装置の斜視図、図１（ｂ）にその裏面図、図２にこのリードフレームの裏面図を示す。
【００２９】
このリードフレームは図12に示したのと同様のＭＡＰタイプのリードフレームであり、半導体チップ搭載領域であるパッド1の裏面側が柱状突起１Ｐを除いてハーフエッチングにより肉薄化されたことを特徴とするもので、他部については図9乃至12に示した従来の半導体装置およびリードフレームと同様に形成されている。
【００３０】
すなわちこの半導体装置は、図１（ａ）および（ｂ）に示すように柱状突起１Ｐの頂面およびリード２が封止樹脂6から露呈せしめられ、パッド1の大部分が封止樹脂６で被覆され、面実装が可能となるように構成されたものである。なおパッド１はサポートバー7によって４方向から支持がなされている。また半導体チップ４とリードとの間はボンディングワイヤ５によって接続されている。
【００３１】
このリードフレームは、板厚０．２ｍｍの銅あるいは鉄−ニッケル製条材をエッチングすることにより形成されたもので、ダイパッド2の周りに、所定の間隔を隔てて多数のリード２を配列したもので、リード1は長さ０．４２ｍｍ、幅０．２３ｍｍであり、パッドは径０．２ｍｍの柱状突起１Ｐを中央部に残して、他の領域は全体にわたって、０．１ｍｍ程度にハーフエッチングにより肉薄化されている。このリードフレームは他の部分については通常のＭＡＰタイプのリードフレームである。
【００３２】
このリードフレームを用いた半導体装置の製造に際しては、図３（ａ）乃至（ｆ）にその製造工程図を示すように、条材をパターンエッチングした後、パッド裏面側の中央部を除く領域のレジストを除去し裏面からハーフエッチングを行うことによって肉薄部の形成を行うが、この例では、裏面側に微細なレジストパターンを残しておくことによって容易に柱状突起１Ｐを形成するものである。
【００３３】
すなわちまず図３（ａ）に示すように、リードフレーム形成用の条材1の表面および裏面にパターン形成用のレジストパターンＲ１，Ｒ２を形成するとともに、肉薄部の突出部を形成すべくパッドの裏面側の中央を除く領域に開口を有するレジストパターンＲ２を形成した点が従来例と異なる点である。他はまったく同様に形成される。
【００３４】
そしてこの状態で、エッチングを行い、図３（ｂ）に示すように、中央部に柱状突起１Ｐを備えた肉薄のパッド１を有するリードフレームが形成される。
【００３５】
このリードフレームのパッド１に、図３（ｃ）に示すように、ポリイミドテープからなるカバーフィルム３を貼着する。
【００３６】
そして図３（ｄ）に示すように、半導体チップ４を搭載し、ワイヤボンディングを行い、図３（ｅ）に示すように、通常の方法で樹脂封止を行い、図３（ｆ）に示すように、カバーフィルム３を剥離し、ダイシングにより個々に分離し、図1（ａ）および（ｂ）に示したような半導体装置を得る。
【００３７】
すなわち通常は図１３に示したようなリードフレームに半導体チップの搭載およびワイヤボンディングを行い、一体的に樹脂封止を行った後、個々の半導体装置に分割する。
【００３８】
このようにして形成された半導体装置によれば、パッド裏面の肉薄部に封止樹脂６が入り込むため樹脂抜けが防止され信頼性の高い半導体装置を提供することができる。またプリント基板などの回路基板への実装が安定かつ容易で信頼性の高い半導体装置を提供することが可能となる。
【００３９】
次に、本発明の第１の実施の形態について説明する。本発明の第１の実施の形態のリードフレームについて説明する。この例では、図４に示すように、肉薄に形成したパッド1Ｓの裏面に絶縁性接着剤8を介して柱状突起１Ｐを貼着したことを特徴とするものである。
他については前記第1の実施の形態とまったく同様に形成する。
【００４０】
かかる構成によれば、柱状突起１Ｐと半導体チップ搭載領域とは別部材で形成され、柱状突起１Ｐが絶縁性接着剤などの絶縁性部材を介して柱状突起１Ｐに固着せしめられているため、柱状突起１Ｐは半導体チップ４と何ら電気的接続をなしておらず、したがって実装基板上の回路パターンに接触したとしても不良を生じることはない。また、この柱状突起１Ｐの裏面に酸化膜を形成するなど絶縁処理をしておくようにしてもよい。
【００４１】
また、リード２についても、半導体チップ搭載領域側の先端部分で他端部分よりも肉薄となるように形成し、少なくともボンディング領域の裏面側で、裏面側に突出する盛り上がり領域を形成し、リードの他端部分の底面と突出部の先端面の高さとが一致するように形成してもよい。
【００４２】
かかる構成によれば、パッドのハーフエッチング工程と同時にリードの肉薄化が可能となり、リードの加工精度も向上し、高精度のパターンを得ることができると共に、盛り上がり領域の形成により、ワイヤボンディングにおけるリードの変形を抑制し、安定した強度でかつ伝送損失が少なく歩留まりの高い半導体装置を提供することが可能となる。
【００４３】
次に、本発明の第２の実施の形態について説明する。本発明の第２の実施の形態の半導体装置について説明する。前記第1の実施の形態では、柱状突起１Ｐは５個形成されているが、この例では、図５に示すように、パッド1の中央部に形成された1個の柱状突起１Ｐからなることを特徴とする。他については第1の実施の形態と同様に形成されている。かかる構成によれば、露出面積がより小さいため、封止樹脂の剥離防止効果も高くまた、回路パターンとの接触を効果的に防止することができる。
【００４４】
次に、本発明の第３の実施の形態について説明する。本発明の第３の実施の形態の半導体装置について説明する。前記第1の実施の形態では、柱状突起１Ｐは５個、前記第３の実施の形態では、１個形成されているが、この例では、図６に示すように、パッド1の中央部および対角線上に形成された計９個の柱状突起１Ｐからなることを特徴とする。他については第1の実施の形態と同様に形成されている。かかる構成によれば、上記効果に加え、組み立て実装時の安定性が向上する。
【００４５】
次に、本発明の第４の実施の形態について説明する。本発明の第４の実施の形態の半導体装置について説明する。前記第４の実施の形態では、柱状突起１Ｐはパッド1の中央部および対角線上に形成されているが、この例では、図７に示すように、パッド1の中央部と、前記中央部を囲むようにその周辺の複数箇所に形成された計９個の突起からなることを特徴とする。かかる構成によれば、上記効果に加え、組み立て実装時の安定性が向上する。
【００４６】
次に、本発明の第５の実施の形態について説明する。本発明の第５の実施の形態の半導体装置について説明する。前記参考例、第３、４の実施の形態では、柱状突起１Ｐは同じ大きさに形成されているが、この例では、図８に示すように、パッド1の中央部と、前記中央部を囲むとともに、中央部に位置するものよりも径大となるようにようにその周辺の複数箇所に形成された計９個の突起からなることを特徴とする。
【００４７】
かかる構成によれば、突起の形成をハーフエッチングにより行なう場合、突出部を径大とすることにより、エッチングによる形成が容易となる。
【００４８】
なお、前記実施の形態では、リードフレームはエッチングにより形成したが、プレス成型の後、ハーフエッチングをするようにしてもよいことはいうまでもない。また、パッドとリードとを別体で形成したものも有効である。加えて、リード長、リード幅、リードの厚さおよび柱状突起の径などについては適宜変更可能である。
【００４９】
【発明の効果】
以上説明してきたように、本発明のリードフレームによれば、突出部を除いて半導体チップ搭載領域の裏面側にも封止樹脂が入り込むため密着性が向上し、樹脂抜け防止が可能で信頼性の高い半導体装置を提供することができる。また封止樹脂からなるパッケージの反りの防止も抑制される。
【００５０】
また本発明の半導体装置によれば、実装基板上の配線パターンと半導体チップ搭載領域との電気的接触の危険性が低減され、またこの突出部を避けるように回路パターンを形成することにより、半導体チップ搭載領域と回路パターンとの電気的接触はほぼ完全に防ぐことが可能となる。
【００５１】
また、本発明の半導体装置は、半導体チップ搭載領域にのみポストが形成されており、リード底面は全面が封止樹脂から露出するようにすることができ、実装面積に影響を与えることなく形成することができるため、実装性も良好である。
【図面の簡単な説明】
【図１】本発明の参考例の半導体装置を示す斜視図および裏面図である。
【図２】本発明の参考例のリードフレームを示す図である。
【図３】本発明の参考例の半導体装置の製造工程図である。
【図４】本発明の第１の実施の形態のリードフレームを示す説明図である。
【図５】本発明の第２の実施の形態の半導体装置を示す裏面図である。
【図６】本発明の第３の実施の形態の半導体装置を示す裏面図である。
【図７】本発明の第４の実施の形態の半導体装置を示す裏面図である。
【図８】本発明の第５の実施の形態の半導体装置を示す裏面図である。
【図９】従来例の半導体装置を示す図である。
【図１０】従来例の半導体装置の断面図である。
【図１１】従来例のリードフレームの製造工程図である。
【図１２】従来例の半導体装置説明図である。
【図１３】ＭＡＰタイプのリードフレームを示す図である。
【符号の説明】
１ パッド
１Ｐ 柱状突起
２ リード
３ カバーフィルム
４ 半導体チップ
５ ボンディングワイヤ
６ 封止樹脂
７ サポートバー
８ 絶縁性接着剤
１０ プリント基板
１１ 回路パターン
１２ 半田
１３ レジスト[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a lead frame and a semiconductor device using the same, and more particularly to a semiconductor device formed such that leads are exposed on the bottom surface rather than the side surface of a resin-sealed body.
[0002]
[Prior art]
2. Description of the Related Art In recent years, a semiconductor device mounted on an electronic device is used for a portable terminal such as a mobile phone and a PDA.
[0003]
Various proposals have been made for mounting semiconductor devices in order to achieve miniaturization, thinning and weight reduction, and high integration. Lead frames, TBGA using TAB (Tape Automated Bonding) tape, A wafer scale CSP equivalent to the chip size, or a CSP slightly larger than the chip size, called a PBGA or CSP (chip size package) using a flexible printed circuit board, has been developed. Of particular note are semiconductor devices of the type called SON (Small Outline Non-leaded package) and QFN (Quad Flat Non-leaded package), where the leads are exposed on the bottom rather than the side of the resin encapsulant. ing.
[0004]
For example, a QFN type semiconductor device has a perspective view in FIG. 9A, a back view in FIG. 9B, and a cross-sectional view in FIG. Therefore, the semiconductor device is exposed on the back surface, and is a small and compact surface mounting type semiconductor device.
[0005]
In such a semiconductor device, a semiconductor chip mounting area (pad) 1 for mounting the semiconductor chip 4 is exposed from the sealing resin 6 and formed on the same surface as the lead 2 . In this structure, when the circuit board 13 is mounted on the printed circuit board 10, the circuit pattern 13 on the printed circuit board 10 is covered with the resist 11 except for portions corresponding to the leads 2 , and is exposed from the resist 11. Only the area of the circuit pattern 13 to be connected is connected to the lead 2 via the solder 12.
[0006]
This semiconductor device is formed using a collective mold (MAP: Mold Array Package) type lead frame as shown in FIG. 13, as shown in FIGS. 11 (a) to 11 (e).
[0007]
That is, first, as shown in FIG. 11A, a resist pattern (not shown) for pattern formation is formed on the front and back surfaces of the strip for lead frame formation, and etching is performed using the resist pattern as a mask. A lead frame is formed which has a pad 1 for mounting a lead and a lead 2 formed so that the tip is positioned around the pad. As shown in FIG. 13, the lead frame is formed in a state where the pad 1 is supported by a support bar 7 and a large number of lead frames are arranged as a whole.
[0008]
Using such a lead frame, as shown in FIG. 11B, a cover film 3 for preventing resin leakage is attached to the back surface side. After that, as shown in FIG. 11C, after the semiconductor chip 4 is fixed on the pad 1, the bonding pad of the semiconductor chip and the tip of the lead 2 are connected by the bonding wire 5 using the wire bonding method. Then, resin sealing is performed collectively, and molding is performed in a mold (not shown) so that the semiconductor chip 4 and the bonding wires are covered with the sealing resin 6 as shown in FIG.
[0009]
Finally, the cover film 3 is removed and separated into individual semiconductor devices by dicing to form a semiconductor device as shown in FIG.
[0010]
[Problems to be solved by the invention]
However, this type of semiconductor device has the following problems. In the case of the type in which the entire surface of the pad 1 on which the semiconductor chip 4 is mounted is exposed to the outside of the sealing resin 6, there is a possibility that peeling occurs at the interface between the sealing resin 6 and the pad 1, and this is also a cause of package warpage Become.
[0011]
Furthermore, as shown in FIG. 12, the circuit pattern 13 on the printed circuit board 10 for mounting such a semiconductor device is covered with a resist 11 except for portions corresponding to the leads 2. Only the region of the exposed circuit pattern 13 is connected to the lead 2 via the solder 12.
[0012]
However, as shown in FIG. 12, since the resist 11 is thin, the exposed pad 1 may be in electrical contact with the circuit pattern 11 on the mounting substrate 10.
[0013]
In addition, in this type of semiconductor device, a cover film 3 is adhered to the front surface of the back surface of the lead frame in order to prevent resin leakage from occurring on the exposed surfaces of the lead 2 and the pad 1 during resin sealing. Yes. Such a cover film 3 is adhered after the lead frame is processed, and in this state, the semiconductor chip 4 is mounted and wire bonding is performed. In these processes, the lower surface of the pad 1 is supported by a heater plate or the like. Therefore, the cover film 3 has to be removed on the lower surface of the pad 1.
[0014]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a highly reliable semiconductor device that has good adhesion to a sealing resin and does not have a short circuit failure during mounting.
[0015]
[Means for Solving the Problems]
Therefore, in the present invention, a semiconductor chip mounting region for mounting a semiconductor chip and a plurality of leads formed at a predetermined interval from the semiconductor chip mounting region are provided, and the semiconductor chip mounting region is a bottom surface of the lead. A lead frame having a bottom surface above and having at least one projecting portion projecting from the bottom surface, wherein a tip surface of the projecting portion coincides with a bottom surface of the lead. There,
The projecting portion is a columnar projection adhered to the semiconductor chip mounting region via an insulating member .
[0016]
According to such a configuration, the semiconductor chip mounting area is covered with the sealing resin on the back side except for the protruding portion, the contact area with the resin is increased, and the resin and the pad that is the semiconductor chip mounting area Adhesion is improved. Further, warpage of the package made of the sealing resin is also prevented.
[0017]
In addition, the risk of electrical contact between the wiring pattern on the mounting substrate and the semiconductor chip mounting area is reduced. Further, by forming the circuit pattern so as to avoid this protruding portion, it is possible to almost completely prevent electrical contact between the semiconductor chip mounting region and the circuit pattern. Also, the post is formed only in the semiconductor chip mounting area, and the entire bottom surface of the lead can be exposed from the sealing resin, so that it can be formed without affecting the mounting area. Is also good.
[0018]
Further, the semiconductor chip mounting region can be supported by the protrusions (posts) when mounting the semiconductor chip and wire bonding with the cover film attached to the back surface of the lead frame.
[0019]
Preferably, the semiconductor chip mounting area, the lead, and the protruding portion are integrally formed by molding the same strip material. According to this configuration, in addition to the above effects, it is easily formed with good workability.
[0020]
Preferably, the semiconductor chip mounting region is formed by half-etching leaving the protruding portion. According to such a configuration, in a normal molding process, it is only necessary to correct the back side mask, it can be easily formed by only half-etching, and it is very easily formed with good workability.
[0021]
Preferably, the protruding portion is a columnar body attached to the semiconductor chip mounting region via an insulating member. According to such a configuration, the protrusion and the semiconductor chip mounting region are formed as separate members, and the protrusion is fixed to the protrusion via an insulating member such as an insulating adhesive. The part is not electrically connected to the semiconductor chip mounted in the semiconductor chip mounting region, and therefore no defect occurs even if it contacts the circuit pattern on the mounting substrate. Further, an insulating process such as forming an oxide film on the back surface of the protruding portion may be performed.
[0022]
Preferably, the protruding portion is formed of a single columnar protrusion formed at a central portion of the semiconductor chip mounting region. According to this configuration, since the exposed area is small, the effect of preventing the sealing resin from peeling off is high, and contact with the circuit pattern can be effectively prevented.
[0023]
Preferably, the projecting portion includes a plurality of protrusions formed at a central portion of the semiconductor chip mounting region and diagonal lines of the semiconductor chip mounting region. According to this configuration, in addition to the above effects, stability during assembly and mounting is improved.
[0024]
In addition, the protruding portion includes a central portion of the semiconductor chip mounting region and a plurality of protrusions formed at a plurality of locations around the central portion so as to surround the central portion. According to this configuration, in addition to the above effects, stability during assembly and mounting is improved.
[0025]
Preferably, the projecting portion surrounds the central portion of the semiconductor chip mounting region and the central portion, and a plurality of protrusions are formed at a plurality of locations around the central portion so as to be larger in diameter than those located in the central portion. It consists of individual protrusions. In the case where the protrusion is formed by half etching, formation by etching is facilitated by increasing the diameter of the protrusion.
[0026]
Furthermore, in the semiconductor device of the present invention, a semiconductor chip mounting area on which a semiconductor chip is mounted, a plurality of leads formed at a predetermined interval from the semiconductor chip mounting area, and the semiconductor chip mounting area are mounted on the surface. A semiconductor chip connected to each bonding region of the lead by wire bonding, and a sealing resin that covers the semiconductor chip and the leading end portion of the lead so that at least the bottom surface side of the other end portion of the lead is exposed The semiconductor chip mounting area has a bottom surface above the bottom surface of the lead, and is attached to at least one of the semiconductor chip mounting areas protruding from the bottom surface via an insulating member. has a columnar protrusion that is, the distal end surface of the projecting portion is configured to match with the bottom surface of the lead, Serial semiconductor chip mounting region is covered with the sealing resin, characterized in that only the bottom surface of the projecting portion is caused to expose from the sealing resin. According to such a configuration, since the sealing resin enters the back surface side of the semiconductor chip mounting region except for the protruding portion, the adhesion is improved, and the semiconductor device can be provided with high reliability by preventing the resin from coming off. Further, warpage of the package made of the sealing resin is also prevented.
[0027]
In addition, the risk of electrical contact between the wiring pattern on the mounting substrate and the semiconductor chip mounting area is reduced. Further, by forming the circuit pattern so as to avoid this protruding portion, it is possible to almost completely prevent electrical contact between the semiconductor chip mounting region and the circuit pattern. Also, the post is formed only in the semiconductor chip mounting area, and the entire bottom surface of the lead can be exposed from the sealing resin, so that it can be formed without affecting the mounting area. Is also good.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, reference examples of the present invention will be described in detail with reference to the drawings. A lead frame of a reference example of the present invention and a semiconductor device using the same will be described. FIG. 1A is a perspective view of a semiconductor device formed using the lead frame according to the first embodiment of the present invention, FIG. 1B is a back view thereof, and FIG. 2 is a back view of the lead frame. .
[0029]
This lead frame is a MAP type lead frame similar to that shown in FIG. 12, and the back side of the pad 1 which is a semiconductor chip mounting region is thinned by half etching except for the columnar protrusion 1P. The other parts are formed in the same manner as the conventional semiconductor device and lead frame shown in FIGS.
[0030]
That is, in this semiconductor device, as shown in FIGS. 1A and 1B, the top surface of the columnar protrusion 1P and the lead 2 are exposed from the sealing resin 6, and most of the pad 1 is covered with the sealing resin 6. Therefore, it is configured so that surface mounting is possible. The pad 1 is supported from four directions by the support bar 7. The semiconductor chip 4 and the lead are connected by a bonding wire 5.
[0031]
This lead frame is formed by etching a copper or iron-nickel strip having a thickness of 0.2 mm, and a large number of leads 2 are arranged around the die pad 2 at a predetermined interval. The lead 1 has a length of 0.42 mm and a width of 0.23 mm. The pad has a columnar protrusion 1P having a diameter of 0.2 mm at the center, and the other regions are half-etched to about 0.1 mm over the entire area. It is thinned. This lead frame is a normal MAP type lead frame for the other parts.
[0032]
When manufacturing a semiconductor device using this lead frame, as shown in FIGS. 3A to 3F, the strip material is subjected to pattern etching, and then the region other than the central portion on the back side of the pad is removed. The thin portion is formed by removing the resist and performing half etching from the back surface. In this example, the columnar protrusion 1P is easily formed by leaving a fine resist pattern on the back surface side.
[0033]
That is, first, as shown in FIG. 3A, the resist patterns R1 and R2 for pattern formation are formed on the front and back surfaces of the strip 1 for forming the lead frame, and the pads are formed so as to form thin projections. The difference from the conventional example is that a resist pattern R2 having an opening in a region excluding the center on the back side is formed. Others are formed in exactly the same way.
[0034]
Then, in this state, etching is performed to form a lead frame having a thin pad 1 having a columnar protrusion 1P at the center as shown in FIG.
[0035]
As shown in FIG. 3C, a cover film 3 made of polyimide tape is attached to the pad 1 of the lead frame.
[0036]
Then, as shown in FIG. 3 (d), the semiconductor chip 4 is mounted, wire bonding is performed, and as shown in FIG. 3 (e), resin sealing is performed by a normal method, as shown in FIG. 3 (f). In this manner, the cover film 3 is peeled off and separated by dicing to obtain a semiconductor device as shown in FIGS. 1 (a) and 1 (b).
[0037]
That is, normally, a semiconductor chip is mounted on a lead frame as shown in FIG. 13 and wire bonding is performed, and after resin sealing is integrally performed, the semiconductor device is divided into individual semiconductor devices.
[0038]
According to the semiconductor device formed as described above, the sealing resin 6 enters the thin portion on the back surface of the pad, so that the resin can be prevented from coming off and a highly reliable semiconductor device can be provided. In addition, it is possible to provide a highly reliable semiconductor device that is stable and easy to mount on a circuit board such as a printed board.
[0039]
Next, a first embodiment of the present invention will be described. A lead frame according to a first embodiment of the present invention will be described. In this example, as shown in FIG. 4, a columnar protrusion 1 </ b> P is attached to the back surface of a thin pad 1 </ b> S via an insulating adhesive 8.
Others are formed in the same manner as in the first embodiment.
[0040]
According to this configuration, the columnar protrusion 1P and the semiconductor chip mounting region are formed as separate members, and the columnar protrusion 1P is fixed to the columnar protrusion 1P via an insulating member such as an insulating adhesive. The protrusion 1P does not make any electrical connection with the semiconductor chip 4, and therefore no defect occurs even if it contacts the circuit pattern on the mounting substrate. Further, an insulating process such as an oxide film may be formed on the back surface of the columnar protrusion 1P.
[0041]
In addition, the lead 2 is also formed so that the tip portion on the semiconductor chip mounting region side is thinner than the other end portion, and a raised region protruding to the back surface side is formed at least on the back surface side of the bonding region. You may form so that the bottom face of an other end part and the height of the front end surface of a protrusion part may correspond.
[0042]
According to such a configuration, the lead can be thinned simultaneously with the half-etching process of the pad, the lead processing accuracy can be improved, a highly accurate pattern can be obtained, and the formation of the raised region leads to lead in wire bonding. Therefore, it is possible to provide a semiconductor device having a stable yield, a low transmission loss, and a high yield.
[0043]
Next, a second embodiment of the present invention will be described. A semiconductor device according to a second embodiment of the present invention will be described. In the first embodiment, five columnar protrusions 1P are formed, but in this example, as shown in FIG. 5, the columnar protrusion 1P is composed of one columnar protrusion 1P formed at the center of the pad 1. It is characterized by. Others are formed in the same manner as in the first embodiment. According to such a configuration, since the exposed area is smaller, the effect of preventing the peeling of the sealing resin is high, and contact with the circuit pattern can be effectively prevented.
[0044]
Next, a third embodiment of the present invention will be described. A semiconductor device according to a third embodiment of the present invention will be described. In the first embodiment, five columnar protrusions 1P are formed, and in the third embodiment, one is formed. In this example, as shown in FIG. It consists of a total of nine columnar protrusions 1P formed on a diagonal line. Others are formed in the same manner as in the first embodiment. According to this configuration, in addition to the above effects, stability during assembly and mounting is improved.
[0045]
Next, a fourth embodiment of the present invention will be described. A semiconductor device according to a fourth embodiment of the present invention will be described. In the fourth embodiment, the columnar protrusion 1P is formed on the central portion and diagonal line of the pad 1, but in this example, as shown in FIG. 7, the central portion of the pad 1 and the central portion are It is characterized by comprising a total of nine protrusions formed at a plurality of locations around the periphery so as to surround. According to this configuration, in addition to the above effects, stability during assembly and mounting is improved.
[0046]
Next, a fifth embodiment of the present invention will be described. A semiconductor device according to a fifth embodiment of the present invention will be described. In the reference example, the third and fourth embodiments, the columnar protrusions 1P are formed to have the same size, but in this example, as shown in FIG. It is characterized by comprising a total of nine protrusions formed at a plurality of locations around the periphery so as to be larger in diameter than the one located in the central portion.
[0047]
According to such a configuration, when the protrusion is formed by half etching, the protrusion can be easily formed by increasing the diameter.
[0048]
In the above embodiment, the lead frame is formed by etching, but it goes without saying that half-etching may be performed after press molding. It is also effective to form the pads and leads separately. In addition, the lead length, lead width, lead thickness, columnar protrusion diameter, and the like can be changed as appropriate.
[0049]
【The invention's effect】
As described above, according to the lead frame of the present invention, the sealing resin enters the back side of the semiconductor chip mounting area except for the protruding portion, so that the adhesion is improved and the resin can be prevented from coming off and reliable. A semiconductor device with a high level can be provided. Further, it is possible to suppress the warpage of the package made of the sealing resin.
[0050]
Further, according to the semiconductor device of the present invention, the risk of electrical contact between the wiring pattern on the mounting substrate and the semiconductor chip mounting area is reduced, and the circuit pattern is formed so as to avoid this protruding portion, so that the semiconductor Electrical contact between the chip mounting area and the circuit pattern can be prevented almost completely.
[0051]
In the semiconductor device of the present invention, the post is formed only in the semiconductor chip mounting region, and the entire bottom surface of the lead can be exposed from the sealing resin, and is formed without affecting the mounting area. Therefore, mountability is also good.
[Brief description of the drawings]
FIGS. 1A and 1B are a perspective view and a rear view showing a semiconductor device according to a reference example of the invention. FIGS.
FIG. 2 is a view showing a lead frame according to a reference example of the present invention.
FIG. 3 is a manufacturing process diagram of a semiconductor device according to a reference example of the invention;
FIG. 4 is an explanatory diagram illustrating a lead frame according to the first embodiment of this invention.
FIG. 5 is a back view showing the semiconductor device according to the second embodiment of the present invention;
FIG. 6 is a back view showing a semiconductor device according to a third embodiment of the present invention.
FIG. 7 is a back view showing a semiconductor device according to a fourth embodiment of the present invention.
FIG. 8 is a back view showing a semiconductor device according to a fifth embodiment of the present invention.
FIG. 9 is a diagram illustrating a conventional semiconductor device.
FIG. 10 is a cross-sectional view of a conventional semiconductor device.
FIG. 11 is a manufacturing process diagram of a conventional lead frame.
FIG. 12 is an explanatory diagram of a conventional semiconductor device.
FIG. 13 is a diagram showing a MAP type lead frame.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Pad 1P Columnar protrusion 2 Lead 3 Cover film 4 Semiconductor chip 5 Bonding wire 6 Sealing resin 7 Support bar 8 Insulating adhesive 10 Printed circuit board 11 Circuit pattern 12 Solder 13 Resist

Claims (6)

半導体チップを搭載する半導体チップ搭載領域と、前記半導体チップ搭載領域から所定の間隔を隔てて形成された複数のリードとを具備し、前記半導体チップ搭載領域は、前記リードの底面よりも上方に底面を有し、かつ前記底面から突出せしめられた少なくとも１つの突出部を有し、前記突出部の先端面が、前記リードの底面と一致するように構成されているリードフレームであって、
前記突出部は、前記半導体チップ搭載領域に、絶縁性部材を介して貼着された柱状突起であることを特徴とするリードフレーム。 A semiconductor chip mounting region for mounting the semiconductor chip; and a plurality of leads formed at a predetermined interval from the semiconductor chip mounting region, the semiconductor chip mounting region being a bottom surface above the bottom surface of the lead And has at least one projecting portion projected from the bottom surface, and a leading end surface of the projecting portion is configured to coincide with the bottom surface of the lead ,
The lead frame according to claim 1, wherein the protrusion is a columnar protrusion attached to the semiconductor chip mounting region via an insulating member. 前記突出部は、前記半導体チップ搭載領域の中央部に形成された1個の柱状突起からなることを特徴とする請求項１に記載のリードフレーム。2. The lead frame according to claim 1 , wherein the protruding portion is formed of a single columnar protrusion formed at a central portion of the semiconductor chip mounting region. 前記突出部は、前記半導体チップ搭載領域の中央部と、前記半導体チップ搭載領域の対角線上とに形成された複数個の突起からなることを特徴とする請求項１に記載のリードフレーム。2. The lead frame according to claim 1, wherein the protruding portion includes a plurality of protrusions formed at a central portion of the semiconductor chip mounting region and on a diagonal line of the semiconductor chip mounting region. 前記突出部は、前記半導体チップ搭載領域の中央部と、前記中央部を囲むようにその周辺の複数箇所に形成された複数個の突起からなることを特徴とする請求項１または２に記載のリードフレーム。3. The projection according to claim 1, wherein the protruding portion includes a central portion of the semiconductor chip mounting region and a plurality of protrusions formed at a plurality of locations around the central portion so as to surround the central portion. Lead frame. 前記突出部は、前記半導体チップ搭載領域の中央部と、前記中央部を囲むと共に、前記中央部に位置するものよりも径大となるようにその周辺の複数箇所に形成された複数個の突起からなることを特徴とする請求項１または２に記載のリードフレーム。The projecting portion surrounds the central portion of the semiconductor chip mounting region and the central portion, and a plurality of protrusions formed at a plurality of locations around the central portion so as to be larger in diameter than those located in the central portion. The lead frame according to claim 1 or 2, characterized by comprising: 表面に、半導体チップを搭載する半導体チップ搭載領域と、前記半導体チップ搭載領域から所定の間隔を隔てて形成された複数のリードと、前記半導体チップ搭載領域に搭載され、前記リードの各ボンディング領域とワイヤボンディングにより接続された半導体チップと、少なくとも前記リードの前記他端部分の底面側が露呈するように前記半導体チップおよび前記リードの先端部分を被覆する封止樹脂とを具備し、前記半導体チップ搭載領域は、前記リードの前記底面よりも上方に底面を有し、かつ前記底面から突出せしめられた少なくとも１つの前記半導体チップ搭載領域に絶縁性部材を介して貼着された柱状突出部を有し、前記突出部の先端面が、前記リードの前記底面と一致するように構成され、前記半導体チップ搭載領域は前記封止樹脂で被覆されており、前記突出部の底面のみが前記封止樹脂から露呈せしめられていることを特徴とする半導体装置。A semiconductor chip mounting region for mounting a semiconductor chip on the surface, a plurality of leads formed at a predetermined interval from the semiconductor chip mounting region, and each bonding region of the leads mounted on the semiconductor chip mounting region, A semiconductor chip connected region by wire bonding; and a sealing resin that covers the semiconductor chip and a tip portion of the lead so that at least a bottom surface side of the other end portion of the lead is exposed. Has a bottom surface above the bottom surface of the lead, and has a columnar protrusion attached to at least one semiconductor chip mounting region protruding from the bottom surface via an insulating member , The front end surface of the projecting portion is configured to coincide with the bottom surface of the lead, and the semiconductor chip mounting region is Is covered with a resin, the semiconductor device characterized by only the bottom surface of the projecting portion is caused to expose from the sealing resin.
JP2001398158A 2001-12-27 2001-12-27 Lead frame and semiconductor device using the same Expired - Fee Related JP3638136B2 (en)

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