JP3633174B2 - Synchronous detection demodulator - Google Patents

Description

【０００８】
（数１）においてｊは虚数単位である。
判定部９は、ベースバンド信号Ｉｋ、Ｑｋから（表１）、（表２）に示す規則によりシンボルの判定を行い、判定位相φｋを出力する。（表１）は偶数シンボルを示し、（表２）は奇数シンボルを示す。
【０００９】
【表１】

【００１０】
【表２】

【００１１】
差動復号部１０は、１シンボルの遅延器１１および減算器１２から成り、判定部９からの出力信号を（表３）に示す規則により変換する。
【００１２】
【表３】

【００１３】
具体的には、（表３）中括弧で示すようにπ／４、π／２等の位相を３ビットで表現し、減算器１２は２の補数による演算を行い、減算器１２の出力信号を（表３）に示す規則により変換することにより、差動復号部１０は上記構成で（表３）の変換を実施する。遅延器４１、４２は非同期ベースバンド信号Ｉ´ｋ、Ｑ´ｋを１シンボル遅延させ、逆変調部５は遅延器４１、４２からの１シンボル前の非同期ベースバンド信号の位相を１シンボル前の判定位相だけ減じる。リミッタ６は逆変調部５の出力信号を（数２）に示す演算により変換する。
【００１４】
【数２】

【００１５】
ローパスフィルタ７は逆変調部５からリミッタ６を介して得られた再生ベースバンド搬送波信号から雑音を低減させる。
【００１６】
図５は図４の同期検波復調装置を構成するフィルタを示す機能ブロック図である。図５において、７１は減算器、７２は入力信号をα倍する定数倍器、７３は加算器、７４は１シンボル遅延させる遅延器である。なお、定数倍器７２において倍率αは０≦α＜１の範囲で設定され、０でフィルタ作用がなくなり、１に近付くほど狭帯域となる。
【００１７】
次に、図４の同期検波復調装置について、その動作を説明する。
分配器１への入力中間周波信号は（数３）で示される。
【００１８】
【数３】

【００１９】
（数３）において、ｔｋ、φｋ、Ａｋは第ｋシンボルのそれぞれ中心時刻、変調位相、振幅である。π／４シフトＱＰＳＫでは（表３）に示す規則により変調位相が決まるので、φ０＝０とおけば、φｋはｋが偶数のときには０、π／２、π、３π／２のいずれかを、奇数のときにはπ／４、３π／４、５π／４、７π／４のいずれかをとる。（数３）のωは搬送波の角周波数で、局部発振器２５の角周波数に等しい。θは搬送波の局部発振器２５の出力信号に対する位相差で、電波の伝播距離、フェージング等により変化する。入力中間周波信号は準同期検波部２により直交成分および同相成分の非同期ベースバンド信号へ変換される。さらに、準同期検波部２から出力される非同期ベースバンド信号はＡ／Ｄ変換器３１および３２によってシンボル毎にサンプリングされ、（数４）で示す非同期ベースバンド信号となる。
【００２０】
【数４】

【００２１】
これら直交成分および同相成分の信号の組を複素数で表すと、（数５）のようになる。
【００２２】
【数５】

【００２３】
逆変調部５には１シンボル前の非同期ベースバンド信号と１シンボル前の判定位相信号とが入力される。判定部９における判定が誤らなかったと仮定すれば、判定位相は変調位相φｋ−１と一致し、逆変調部５は（数６）に示す演算を行い、Ｉ´ｃｋ、Ｑ´ｃｋを出力する。
【００２４】
【数６】

【００２５】
よってリミッタ６は、複素数表現でｅｘｐ［ｊθ］なる信号を出力する。フェージング等によるθの変化が十分遅ければｅｘｐ［ｊθ］は定数だからローパスフィルタ７をそのまま通過し、（数７）に示す再生ベースバンド搬送波信号Ｉｃｋ、Ｑｃｋを得る。
【００２６】
【数７】

【００２７】
複素乗算部８は（数１）の演算により（数８）に示すベースバンド信号Ｉｋ、Ｑｋを出力する。
【００２８】
【数８】

【００２９】
判定部９は（表１）、（表２）の規則により判定位相信号を出力するので、その信号の示す判定位相は変調位相φｋに一致する。差動復号部１０は（数９）に示す値を得る。
【００３０】
【数９】

【００３１】
これにより差動復号部１００では、（表３）の規則に従いデータが復号されるとともに、１シンボル前の判定位相を示す判定位相信号が逆変調部５へ出力される。
【００３２】
【発明が解決しようとする課題】
しかしながら、上記従来の同期検波復調装置では、ローパスフィルタ７の過渡応答により、受信開始直後の再生ベースバンド搬送波信号が搬送波の位相θへ収束するまで時間がかかり、雑音が無視できる十分な受信信号レベルであってもシンボル判定誤りが生じる。また、高速なフェージングを受けた受信信号に対しては、搬送波の位相θの変動に対し、ローパスフィルタ７の帯域が狭いと追従できない。したがって、上記収束や搬送波位相の追従を速めるためローパスフィルタ（再生ベースバンド搬送波信号用ローパスフィルタ）７の帯域をある程度広くせざるを得ず、その結果、再生ベースバンド搬送波の搬送波電力対雑音電力比（Ｃ／Ｎ）が低くなり、ビット誤り率特性が理論特性より劣化するという問題点を有していた。
【００３３】
この同期検波復調装置では、再生ベースバンド搬送波信号用ローパスフィルタの帯域を狭くしても過渡応答が生じないことが要望されている。
【００３４】
本発明は、再生ベースバンド搬送波信号用ローパスフィルタの帯域を狭くしても過渡応答が生ぜず、シンボル誤りが生じない同期検波復調装置を提供することを目的とする。
【００３５】
【課題を解決するための手段】
この課題を解決するために本発明による同期検波復調装置は、デジタルデータにより位相変調または周波数変調された受信信号を受信信号の搬送波とは非同期である局部発振信号により直交検波し、同相成分および直交成分から成る第１のベースバンド信号を出力する準同期検波部と、第１のベースバンド信号から同相成分および直交成分から成る搬送波信号を再生する搬送波再生部と、搬送波再生部から出力される信号を入力するフィルタと、フィルタから出力される同相成分および直交成分から成る再生搬送波信号により第１のベースバンド信号を複素乗算し、同相成分および直交成分から成る第２のベースバンド信号を出力する複素乗算部と、第２のベースバンド信号からシンボルを判定し、判定されたシンボルの位相を示す判定位相信号を出力する判定部と、判定位相信号を入力してデータを復号する差動復号部とを有する同期検波復調装置であって、差動復号部が、判定位相信号と固定された特定位相を示す固定位相信号とを切り換える切換え器を有し、同期検波器として動作させる場合には、第１のベースバンド信号を１シンボル遅延させた信号を切換え器によって得られた位相で逆変調する逆変調型搬送波再生を搬送波再生部に行わせると共にフィルタを低域通過特性に設定し且つ切換え器を判定位相信号側に切り換え、遅延検波器として動作させる場合には、第１のベースバンド信号を１シンボル遅延させた信号を切換え器によって得られた位相で逆変調する逆変調型搬送波再生を搬送波再生部に行わせると共にフィルタをスルー特性に設定し且つ切換え器を固定位相信号側に切り換えるように構成したものである。
【００３６】
これにより、再生ベースバンド搬送波信号用ローパスフィルタの帯域を狭くしても過渡応答が生ぜず、シンボル誤りが生じない同期検波復調装置が得られる。
【００３７】
【発明の実施の形態】
本発明の請求項１に記載の発明は、デジタルデータにより位相変調または周波数変調された受信信号を受信信号の搬送波とは非同期である局部発振信号により直交検波し、同相成分および直交成分から成る第１のベースバンド信号を出力する準同期検波部と、第１のベースバンド信号から同相成分および直交成分から成る搬送波信号を再生する搬送波再生部と、搬送波再生部から出力される信号を入力するフィルタと、フィルタから出力される同相成分および直交成分から成る再生搬送波信号により第１のベースバンド信号を複素乗算し、同相成分および直交成分から成る第２のベースバンド信号を出力する複素乗算部と、第２のベースバンド信号からシンボルを判定し、判定されたシンボルの位相を示す判定位相信号を出力する判定部と、判定位相信号を入力してデータを復号する差動復号部とを有する同期検波復調装置であって、差動復号部が、判定位相信号と固定された特定位相を示す固定位相信号とを切り換える切換え器を有し、同期検波器として動作させる場合には、第１のベースバンド信号を１シンボル遅延させた信号を切換え器によって得られた位相で逆変調する逆変調型搬送波再生を搬送波再生部に行わせると共にフィルタを低域通過特性に設定し且つ切換え器を判定位相信号側に切り換え、遅延検波器として動作させる場合には、第１のベースバンド信号を１シンボル遅延させた信号を切換え器によって得られた位相で逆変調する逆変調型搬送波再生を搬送波再生部に行わせると共にフィルタをスルー特性に設定し且つ切換え器を固定位相信号側に切り換えることとしたものであり、受信開始時には切換え器から固定位相信号が出力されて遅延検波モードで動作し、受信開始後の数シンボル受信後においては切換え器から判定位相信号が出力されて同期検波モードへ切り換えられるという作用を有する。
【００３８】
請求項２に記載の発明は、デジタルデータにより位相変調または周波数変調された受信信号を受信信号の搬送波とは非同期である局部発振信号により位相検波して第１のベースバンド位相信号を出力する位相検波部と、第１のベースバンド位相信号から搬送波位相信号を再生する搬送波再生部と、搬送波再生部から出力される搬送波位相信号を入力するフィルタと、フィルタから出力される再生搬送波位相信号により第１のベースバンド位相信号を減算して第２のベースバンド位相信号を出力する減算器と、第２のベースバンド位相信号からシンボルを判定し、判定されたシンボルの位相を示す判定位相信号を出力する判定部と、判定位相信号と固定された特定位相を示す固定位相信号とを切り換える切換え器を有し、同期検波器として動作させる場合には、第１のベースバンド位相信号を１シンボル遅延させた信号を判定位相信号側に切り換えられた切換え器によって得られた判定位相で減算する逆変調型搬送波再生を搬送波再生部に行わせると共にフィルタを低域通過特性に設定し、遅延検波器として動作させる場合には、第１のベースバンド位相信号を１シンボル遅延させた信号を固定位相信号側に切り換えられた切換え器によって得られた固定位相で減算する逆変調型搬送波再生を搬送波再生部に行わせると共にフィルタをスルー特性に設定する差動復号部とを有することとしたものであり、再生搬送波位相信号を出力するフィルタにおいては遅延検波モード時の最終シンボル位相を再生搬送波の初期位相として狭帯域フィルタ動作が開始されるという作用を有する。
【００３９】
請求項３に記載の発明は、請求項１に記載の発明において、搬送波再生部が遅延器を有し、遅延器がシンボルクロックで駆動されるラッチ回路又はシンボルクロックにより更新されるメモリから成ることとしたものであり、各部のデータがシンボルクロックに同期して更新されるという作用を有する。
【００４０】
請求項４に記載の発明は、請求項１又は２に記載の発明において、切換え器に代えて、シンボルクロックで駆動されるラッチ回路又はシンボルクロックにより更新されるメモリを備えることとしたものであり、シンボルクロックの入力を接続または停止することにより差動復号部が判定位相信号または固定位相信号を出力するという作用を有する。
【００４１】
請求項５に記載の発明は、請求項２に記載の発明において、フィルタの出力信号をシンボルクロックで差分した差分値を時間的に平均化する平均化回路と、平均化回路の出力信号によりフィルタの出力信号を補正する補正回路とを有し、補正回路の出力信号を再生搬送波位相信号とすることとしたものであり、受信信号の搬送波周波数に誤差が生じた場合でも再生搬送波の位相が補正されるという作用を有する。
【００４２】
請求項６に記載の発明は、請求項１に記載の準同期検波部、搬送波再生部、フィルタおよび複素乗算部のダイバーシティ枝分の複数組と、各複素乗算部から出力される第２のベースバンド信号を選択または合成した信号からシンボルを判定し、判定されたシンボルの位相を判定位相信号として出力する判定部と、請求項１に記載の差動復号部とを有することとしたものであり、受信開始時には切換え器から固定位相信号が出力されて遅延検波モードで動作し、受信開始後の数シンボル受信時においては切換え器から判定位相信号が出力されて同期検波モードへ切り換えられるという作用を有すると共に、ダイバーシティ受信がなされ、フェージングの影響が抑制されるという作用を有する。
【００４３】
請求項７に記載の発明は、請求項２に記載の準同期検波部、搬送波再生部、フィルタおよび複素乗算部のダイバーシティ枝分の複数組と、各複素乗算部から出力される第２のベースバンド位相信号を選択または合成した信号からシンボルを判定し、判定されたシンボルの位相を判定位相信号として出力する判定部と、請求項２に記載の差動復号部とを有することとしたものであり、再生搬送波位相信号を出力するフィルタにおいては遅延検波モード時の最終シンボル位相を再生搬送波の初期位相として狭帯域フィルタ動作が開始されるという作用を有すると共に、ダイバーシティ受信がなされ、フェージングの影響が抑制されるという作用を有する。
【００４４】
以下、本発明の実施の形態について、図１〜図３、図５を用いて説明する。
（実施の形態１）
図１は、本発明の実施の形態１による同期検波復調装置を示すブロック図である。図１において、分配器１、準同期検波部２、逆変調部５、リミッタ６、ローパスフィルタ７、複素乗算部８、判定部９、遅延器１１、減算器１２、ミキサ２１、２２、ローパスフィルタ２３、２４、局部発振器２５、Ａ／Ｄ変換器３１、３２、遅延器４１、４２は図４と同様のものであるので、同一符号を付し、説明は省略する。１３は切換え器としてのスイッチ、１００は差動復号部である。
【００４５】
図１に示すように、差動復号部１００は、１シンボルの遅延器１１、遅延器１１の入力を切り換えるスイッチ１３および減算器１２から成り、判定部９から出力される判定位相信号を同期検波モード動作時に（表３）に示す規則により変換する。また、上記遅延器４１、４２、逆変調部５、リミッタ６は搬送波再生部を構成する。なお、遅延器１１、４１、４２、７４（図５）は遅延線等の遅延素子を用いることもできるが、シンボルクロックで駆動されるラッチ回路あるいはシンボルクロックにより更新されるメモリなどにより構成することもでき、このようなデジタル信号処理および回路の集積化に適した構成とすることは好適な対策である。
【００４６】
以上のように構成された同期検波復調装置について、その動作を説明する。分配器１への入力中間周波信号は（数３）で表現される。この（数３）で示す中間周波信号は、準同期検波部２により、直交成分および同相成分の非同期ベースバンド信号へ変換され、さらにＡ／Ｄ変換器３１、３２によってシンボル毎にサンプリングされ、（数４）で示す非同期ベースバンド信号（第１のベースバンド信号）Ｉ´ｋ、Ｑ´ｋとなる。これら直交成分および同相成分の信号の組を複素数で表すと（数５）のようになる。以上の動作は従来装置における動作と同様である。
【００４７】
まず受信開始時から説明する。受信開始時すなわちバースト受信の先頭部分ではスイッチ１３がＤ側に接続されていて、遅延器１１の出力が０になるとともにローパスフィルタ７の定数倍器７２（図５）の倍率αが０に設定される。このとき、逆変調部５には１シンボル前の非同期ベースバンド信号Ｉ´ｋ−１、Ｑ´ｋ−１および判定位相としての０（つまり固定位相）が入力されているので、逆変調部５の出力信号は入力信号と等しくなる。また、ローパスフィルタ７はαが０に設定されているので、ローパスフィルタ７の入力信号はそのまま出力される。すなわちローパスフィルタ７はスルー状態である。従って、ローパスフィルタ７の出力信号すなわち再生ベースバンド搬送波信号Ｉｃｋ、Ｑｃｋは（数１０）で示すものとなる。
【００４８】
【数１０】

【００４９】
よって、複素乗算部１００の出力信号（第２のベースバンド信号）の値は（数１１）となり、本復調装置は遅延検波器として動作する。
【００５０】
【数１１】

【００５１】
判定部９は、（表２）の奇数シンボルに対する規則により判定位相信号を出力するので、雑音などによる誤りがなければ、上記信号の示す判定位相ψｋは（数９）に一致する。差動復号部１００は判定位相ψｋの信号をそのまま出力し、（表３）の規則に従いデータが復号される。
【００５２】
この状態で適当なシンボル数を受信し、例えばバーストのプリアンブル期間中にスイッチ１３をＣ側へ切り換え、ローパスフィルタ７の定数倍器７２のαに適当な値を設定し、同期検波モードに切り換える。スイッチ１３がＣ側に接続されると、図１の構成は図４の構成と同一となり、本復調装置は同期検波器として動作する。このように検波モードを切り換えてもローパスフィルタ７の出力信号には過渡応答は生じない。以下、遅延検波モードから同期検波モードへの遷移過程において、第Ｌシンボルの復調データ出力直後でスイッチ１３がＤ側からＣ側へ切り換えられたとして説明する。切換え直前（ｋ＝Ｌ）のローパスフィルタ７の出力信号の値は（数１２）で示される。
【００５３】
【数１２】

【００５４】
このとき遅延器１１の入力値としては（数１３）で示す判定部９の出力値が設定されている。
【００５５】
【数１３】

【００５６】
次のシンボルでスイッチ１３がＣ側へ切り換えられると、遅延器１１の出力値として（数１３）の値が遅延されて現れる。これを（数１４）に示す。
【００５７】
【数１４】

【００５８】
よって逆変調部５の出力値は（数１５）の値となり、リミッタ６の出力値すなわちローパスフィルタ７の入力値は（数１６）の値となる。
【００５９】
【数１５】

【００６０】
【数１６】

【００６１】
このように雑音や干渉が無ければ、検波モードが切り換わる前後でローパスフィルタ７の入力値は変化しない。よって減算器７１（図５）の出力は０となり、αを０以外の適当な値に設定しても過渡応答は生じない。
【００６２】
ところで、以後同期検波モードにおいては、判定位相は変調位相に対して（数１７）で示す関係となり、変調位相に対して一定のオフセットが生じる。
【００６３】
【数１７】

【００６４】
しかし、π／４シフトＱＰＳＫは差動符号化変調であるから差動復号部１００の出力信号として（数１８）の値の出力信号が現れるので、判定誤りは生じない。
【００６５】
【数１８】

【００６６】
なお、本実施の形態ではスイッチ１３は遅延器１１の入力側に配置したが、その出力側に配置しても良い。この場合は切換えが１シンボル遅延する。また、本実施の形態ではスイッチ１３により判定位相を０の固定位相に切り換えることにより遅延検波器として動作するが、遅延器１１が例えばラッチ回路によって構成される場合にはスイッチ１３を用いずに同ラッチ回路のクロックを停止し、データ更新を停止すれば足りる。このとき遅延器１１の出力位相は例えばπ等の特定のシンボル点位相に固定されるため、再生搬送波および同期ベースバンド信号の位相、判定部９の出力の判定位相に上記固定されたシンボル点位相分のオフセットが生じることになる。しかし、図１から明らかなように減算器１２によりそのオフセットは相殺されるので、全く同様の出力値が得られる。このような構成とすればスイッチ１３は不要であり、構成が簡単になる。
【００６７】
以上のように本実施の形態によれば、本復調装置を同期検波器として動作させる場合には、第１のベースバンド信号を１シンボル遅延させた信号を判定位相信号側Ｃへ切り換えられた切換え器１３によって得られた位相（判定位相）で逆変調する逆変調型搬送波再生を搬送波再生部４１、４２、５、６に行わせると共にフィルタ７を低域通過特性に設定し、遅延検波器として動作させる場合には、第１のベースバンド信号を１シンボル遅延させた信号を固定位相信号側Ｄへ切り換えられた切換え器１３によって得られた０の位相（固定位相）で逆変調する逆変調型搬送波再生を搬送波再生部４１、４２、５、６に行わせると共にフィルタ７をスルー特性に設定するようにしたことにより、バースト受信の先頭部では遅延検波モードとし、続いて同期検波モードへ切り換えることによりローパスフィルタ７で過渡応答が生じないようにすることができるので、ローパスフィルタ７の帯域を狭くしても過渡応答によって生じるシンボル誤りが生じないようにすることができる。
【００６８】
（実施の形態２）
図２は、本発明の実施の形態２による同期検波復調装置を示すブロック図である。図２において、分配器１、準同期検波部２、遅延器１１、減算器１２、ミキサ２１、２２、ローパスフィルタ２３、２４、局部発振器２５、Ａ／Ｄ変換器３１、３２、遅延器４１、差動復号部１００は図１と同様のものであるので、同一符号を付し、説明は省略する。３３はアークタンジェント変換部（ｔａｎ−１変換部）、５０は逆変調部、７０はローパスフィルタ、８０は減算器、９０は判定部である。上記遅延器４１、逆変調部５０は搬送波再生部を構成する。
【００６９】
以上のように構成された同期検波復調装置について、その機能、動作等について説明する。アークタンジェント変換部３３は、（数４）の値の入力信号を（数１９）に示される非同期ベースバンド位相φｋ＋θの信号（第１のベースバンド位相信号）に変換するものであり、例えば読出し専用メモリによるルックアップテーブル方式などで構成することができる。図２の分配器１、準同期検波部２、Ａ／Ｄ変換器３１、３２およびアークタンジェント変換部３３は位相検波部を構成する。判定部９０は減算器８０の出力信号（第２のベースバンド位相信号）を実施の形態１の場合と同様に（表３）に示す規則で判定し、判定位相ψｋの信号を出力する。逆変調部５０は、遅延器４１から出力される１シンボル前の非同期ベースバンド位相を１シンボル前の判定位相だけ減じ、再生ベースバンド搬送波位相として出力する。
【００７０】
ローパスフィルタ７０は、逆変調部５０から出力される再生ベースバンド搬送波位相から雑音を低減させるためのものであり、図５の１系統で構成される。
【００７１】
【数１９】

【００７２】
このように、準同期検波後の直交・同相成分２チャネルの信号を処理せず、一旦位相情報に変換して処理することで、図１における複素乗算部８や逆変調部５が不要で、複素乗算処理が単なる減算処理となる。また、図１におけるリミッタ６が不要で、構成が簡単になる。さらに、これらの信号処理の全て又は一部をデジタルシグナルプロセッサで行う場合には演算速度の低いものを使うことができる。
【００７３】
なお、局部発振器２５の発振周波数と入力中間周波信号の搬送波周波数との誤差が生じた場合にはθがｋに比例して増加または減少するため、検波モードが切り換わる前後でローパスフィルタ７０の入力信号はシンボル当たりθの変化分だけのずれが生じる。このような場合は上記誤差を検出する回路、たとえばローパスフィルタ７０の出力値である再生ベースバンド搬送波位相の差分値を検出し、数シンボルにわたって平均する平均化回路（図示せず）を設けることができる。
【００７４】
すなわち、前のバースト受信で上記差分値を検出しておき、遅延検波モードから同期検波モードへの検波モード切換え時に補正回路（図示せず）により遅延器７４（図５）の入力値を補正すれば同様にローパスフィルタ７０の過渡応答は生じない。またフェージングが高速な場合には、遅延検波の方が同期検波よりも特性が優れているので、たとえば自動車電話などの場合には、移動体の速度を検出し、移動速度が一定値以上の場合には同期検波に切り換えることを禁止することもできる。
【００７５】
また、本実施の形態ではスイッチ１３は遅延器１１の入力側に配置したが、その出力側に配置しても良い。また、本実施の形態ではスイッチ１３により判定位相を０の固定位相に切り換えたが、実施の形態１の場合と同様に遅延器１１が例えばラッチ回路によって構成される場合には、同ラッチ回路のクロックを停止し、データ更新を停止すれば遅延検波器として動作し、スイッチ１３が不要で、構成が簡単になる。
【００７６】
以上のように本実施の形態によれば、同期検波器として動作させる場合には、第１のベースバンド位相信号を１シンボル遅延させた信号を判定位相信号側に切り換えられた切換え器１３によって得られた判定位相で減算する逆変調型搬送波再生を搬送波再生部４１、５０に行わせると共にフィルタ７０を低域通過特性に設定し、遅延検波器として動作させる場合には、第１のベースバンド位相信号を１シンボル遅延させた信号を固定位相信号側に切り換えた切換え器１３によって得られた固定位相で減算する逆変調型搬送波再生を搬送波再生部４１、５０に行わせると共にフィルタ７０をスルー特性に設定するようにしたことにより、再生搬送波位相信号を出力するフィルタ７０においては遅延検波モード時の最終シンボル位相を再生搬送波の初期位相として狭帯域フィルタ動作を開始することができるので、ローパスフィルタ７０で過渡応答が生じないようにすることができ、ローパスフィルタ７０の帯域を狭くしても過渡応答によって生じるシンボル誤りが生じないようにすることができる。
【００７７】
（実施の形態３）
図３は、本発明の実施の形態３による同期検波復調装置を示すブロック図である。図３において、分配器１、準同期検波部２、逆変調部５、リミッタ６、ローパスフィルタ７、複素乗算部８、判定部９、遅延器１１、減算器１２、スイッチ（切換え器）１３、ミキサ２１、２２、ローパスフィルタ２３、２４、局部発振器２５、Ａ／Ｄ変換器３１、３２、遅延器４１、４２、差動復号部１００は図１と同様のものであるので、同一符号を付し、説明は省略する。図３の同期検波装置が図１と異なる点は、図３が２種類の第２のベースバンド信号Ｉｋ、Ｑｋを生成している点である。つまり２つの複素乗算部８は第２のベースバンド信号Ｉｋ、Ｑｋを判定部９へ出力する。
【００７８】
図３に示すような構成とすることで本同期検波復調装置はダイバーシチ受信機にも適用できる。すなわち判定部９および差動復号部１００以外の部分をダイバーシチ枝数組（図３では２組）だけ有する構成とし、判定部９において複素演算部８の出力を各ダイバーシチ枝の受信電解強度に応じて選択または合成して判定する構成とすればよい。このようにダイバーシチ受信とすれば、フェージングに対する受信特性が改善される。
【００７９】
なお、図３では図１の同期検波復調装置の複素乗算部８までの構成を２組（２系統）使用した場合について説明したが、これを図２の同期検波復調装置の減算器８０までの構成を２組（２系統）使用することとしても良い。また、本実施の形態では上記構成２組の場合について説明したが、上述したようにダイバーシチ枝数に応じた組数とすることもできる。
【００８０】
以上のように本実施の形態によれば、図１の判定部９および差動復号部１００以外の部分又は図２の判定部９０および差動復号部１００以外の部分をダイバーシチ枝数組だけ有するようにしたことにより、ローパスフィルタ７又は７０で過渡応答が生じないようにして狭い帯域のローパスフィルタ７又は７０であってもシンボル誤りが生じないようにすることができると共に、ダイバーシチ受信としてフェージングに対する受信特性を改善することができる。
【００８１】
【発明の効果】
以上のように本発明の同期検波復調装置によれば、受信開始時には切換え器から固定位相信号を出力して遅延検波モードで動作させ、受信開始時から数シンボル受信した後においては切換え器から判定位相信号を出力して同期検波モードへ切り換えることができるので、ローパスフィルタで過渡応答が生じないようにすることができ、ローパスフィルタの帯域を狭くしても過渡応答によって生じるシンボル誤りが生じないようにすることができるという有利な効果が得られる。
【００８２】
また、再生搬送波位相信号を出力するフィルタにおいては遅延検波モード時の最終シンボル位相を再生搬送波の初期位相として狭帯域フィルタ動作を開始することができるので、ローパスフィルタで過渡応答が生じないようにすることができ、ローパスフィルタの帯域を狭くしても過渡応答によって生じるシンボル誤りが生じないようにすることができるという有利な効果が得られる。
【００８３】
さらに、搬送波再生部が遅延器を有し、遅延器がシンボルクロックで駆動されるラッチ回路又はシンボルクロックにより更新されるメモリから成ることにより、ラッチ回路又はメモリという簡単な構成で各部のデータをシンボルクロックに同期して更新することができるという有利な効果が得られる。
【００８４】
さらに、切換え器に代えて、シンボルクロックで駆動されるラッチ回路又はシンボルクロックにより更新されるメモリを備えることにより、シンボルクロックの入力を接続または停止することにより差動復号部が判定位相信号または固定位相信号を出力することができるので、判定位相または固定位相の発生を簡単な構成で実現できるという有利な効果が得られる。
【００８５】
さらに、フィルタの出力信号をシンボルクロックで差分した差分値を時間的に平均化する平均化回路と、平均化回路の出力信号によりフィルタの出力信号を補正する補正回路とを有し、補正回路の出力信号を再生搬送波位相信号とすることにより、受信信号の搬送波周波数に誤差が生じた場合でも再生搬送波の位相を補正できるという有利な効果が得られる。
【００８６】
さらに、準同期検波部、搬送波再生部、フィルタおよび複素乗算部をダイバーシティ枝分の複数組設けたことにより、受信開始時には切換え器から固定位相信号を出力して遅延検波モードで動作させ、受信開始時から数シンボル受信した後においては切換え器から判定位相信号を出力して同期検波モードへ切り換えることができると共にダイバーシチ受信動作が可能となるので、ローパスフィルタの帯域を狭くしても過渡応答によって生じるシンボル誤りが生じないようにすることができると共にフェージングの影響を抑制することができるという有利な効果が得られる。
【図面の簡単な説明】
【図１】本発明の実施の形態１による同期検波復調装置を示すブロック図
【図２】本発明の実施の形態２による同期検波復調装置を示すブロック図
【図３】本発明の実施の形態３による同期検波復調装置を示すブロック図
【図４】従来の同期検波復調装置を示すブロック図
【図５】図４の同期検波復調装置を構成するフィルタを示す機能ブロック図
【符号の説明】
１ 分配器
２ 準同期検波部
５、５０ 逆変調部
６ リミッタ
７、２３、２４、７０ ローパスフィルタ
８ 複素乗算部
９、９０ 判定部
１１、４１、４２、７４ 遅延器
１２、７１、８０ 減算器
１３ スイッチ（切換え器）
２１、２２ ミキサ
２５ 局部発振器
３１、３２ Ａ／Ｄ変換器
７２ 定数倍器
７３ 加算器
１００ 差動復号部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a synchronous detection / demodulation apparatus that demodulates a transmission signal that is phase-modulated or frequency-modulated by a digital signal mainly to wirelessly transmit digital data.
[0002]
[Prior art]
In recent years, digitization of wireless communication is progressing in the field of mobile communication typified by automobile telephones from the viewpoints of confidentiality factories, compatibility with ISDN networks and computers, and effective use of frequency resources. In digital mobile radio communication, for example, as specified in the radio wave system development center standard RCRSTD-27 or RCRSTD-28, which is a standard for digital cellular telephones or digital cordless telephones in Japan, there are differences in modulation methods. Π / 4 shift QPSK, which is a kind of dynamic coding phase shift keying (hereinafter referred to as “differential PSK”), is called a time slot having a fixed time width on one carrier frequency as a multiple access system. Time division multiple access (hereinafter referred to as “TDMA”) in which communication is performed by dividing into units and allocating two or more radio channels in time division is often used.
[0003]
In a receiving unit of a digital radio apparatus using differential PSK, a delay detection method or a synchronous detection method is used as a demodulation method. The synchronous detection method is slightly more complicated than the delay detection method, but has excellent bit error rate characteristics. For example, a synchronous detection / demodulation device of π / 4 shift QPSK is disclosed in Japanese Patent Laid-Open No. 6-90262. Has been. The synchronous detection demodulator needs a sine wave having a phase equal to the carrier wave of the received signal, that is, a regenerated carrier wave, and includes a circuit for generating this, that is, a carrier wave regenerating circuit. As a specific carrier recovery circuit, for example, a circuit using an inverse modulator is disclosed in JP-A-5-260106. In addition, a demodulator based on synchronous detection is often used in the form of orthogonal demodulation of a signal obtained by converting a received signal, which is an input signal, to a low carrier frequency by a heterodyne mixing circuit, that is, an intermediate frequency signal using a reproduced carrier signal. However, today, as shown in the conventional example and embodiment of the above-mentioned JP-A-6-90262, quasi-synchronous detection, that is, quadrature detection is performed by a local oscillation signal whose frequency is the same as that of the carrier wave of the received signal and whose phase is asynchronous. A method of once converting to baseband and demodulating it by digital signal processing is often used.
[0004]
FIG. 4 is a block diagram showing a conventional synchronous detection and demodulation apparatus, and shows a π / 4 shift QPSK synchronous detection and demodulation apparatus. In FIG. 4, 1 is a distributor, 2 is a quasi-synchronous detection unit, 21 and 22 are mixers, 23 and 24 are low-pass filters, 25 is a local oscillator, 31 and 32 are A / D converters, and 41 and 42 are delay devices. 5 is an inverse modulation unit, 6 is a limiter, 7 is a low-pass filter (low-pass filter for reproduction baseband carrier signal), 8 is a complex multiplication unit, 9 is a determination unit, 10 is a differential decoding unit, 11 is a delay unit, 12 Is a subtractor.
[0005]
The function and operation of the synchronous detection / demodulation apparatus configured as described above will be described. The intermediate frequency signal input to the distributor 1 is a signal that is phase-modulated or frequency-modulated with digital data. The distributor 1 distributes the input intermediate frequency signal.
[0006]
The quasi-synchronous detection unit 2 includes mixers 21 and 22 and low-pass filters 23 and 24 that extract only baseband components, and performs quadrature detection using a local oscillation signal from a local oscillator 25 having a frequency equal to the carrier frequency of the input intermediate frequency signal. To do. The A / D converters 31 and 32 convert the baseband signal from the quasi-synchronous detection unit 2 into a digital signal. The A / D converter samples the baseband signal at the center of the symbol period once for each symbol. The complex multiplier 8 indicates the asynchronous baseband signals (first baseband signals) I′k and Q′k from the A / D converters 31 and 32 as reproduction baseband carrier signals Ick and Qck (Equation 1). The baseband signals (second baseband signals) Ik and Qk are converted by complex calculation.
[0007]
[Expression 1]

[0008]
In (Equation 1), j is an imaginary unit.
The determination unit 9 determines a symbol from the baseband signals Ik and Qk according to the rules shown in (Table 1) and (Table 2), and outputs a determination phase φk. (Table 1) shows even symbols, and (Table 2) shows odd symbols.
[0009]
[Table 1]

[0010]
[Table 2]

[0011]
The differential decoding unit 10 includes a one-symbol delay unit 11 and a subtracter 12, and converts the output signal from the determination unit 9 according to the rules shown in (Table 3).
[0012]
[Table 3]

[0013]
Specifically, as shown by the braces in (Table 3), the phase of π / 4, π / 2, etc. is expressed by 3 bits, and the subtractor 12 performs an operation with 2's complement, and the output signal of the subtractor 12 Is converted according to the rules shown in (Table 3), the differential decoding unit 10 performs the conversion shown in (Table 3) with the above configuration. The delay units 41 and 42 delay the asynchronous baseband signals I′k and Q′k by one symbol, and the inverse modulator 5 sets the phase of the asynchronous baseband signal one symbol before from the delay units 41 and 42 one symbol previous. Decrease only the judgment phase. The limiter 6 converts the output signal of the inverse modulation unit 5 by the calculation shown in (Expression 2).
[0014]
[Expression 2]

[0015]
The low-pass filter 7 reduces noise from the reproduced baseband carrier signal obtained from the inverse modulator 5 via the limiter 6.
[0016]
FIG. 5 is a functional block diagram showing a filter constituting the synchronous detection demodulator of FIG. In FIG. 5, 71 is a subtracter, 72 is a constant multiplier that multiplies an input signal by α, 73 is an adder, and 74 is a delay device that delays one symbol. In the constant multiplier 72, the magnification α is set in a range of 0 ≦ α <1, and when 0, there is no filter action, and the closer to 1, the narrower the band.
[0017]
Next, the operation of the synchronous detection demodulator of FIG. 4 will be described.
An input intermediate frequency signal to the distributor 1 is represented by (Equation 3).
[0018]
[Equation 3]

[0019]
In (Equation 3), tk, φk, and Ak are the center time, the modulation phase, and the amplitude of the k-th symbol, respectively. In π / 4 shift QPSK, the modulation phase is determined by the rule shown in (Table 3). Therefore, if φ0 = 0, φk is any one of 0, π / 2, π, and 3π / 2 when k is an even number. When the number is an odd number, one of π / 4, 3π / 4, 5π / 4, and 7π / 4 is taken. Ω in (Expression 3) is an angular frequency of the carrier wave, and is equal to the angular frequency of the local oscillator 25. θ is the phase difference of the carrier wave with respect to the output signal of the local oscillator 25, and varies depending on the propagation distance of radio waves, fading, and the like. The input intermediate frequency signal is converted by the quasi-synchronous detection unit 2 into an asynchronous baseband signal having a quadrature component and an in-phase component. Further, the asynchronous baseband signal output from the quasi-synchronous detection unit 2 is sampled for each symbol by the A / D converters 31 and 32, and becomes an asynchronous baseband signal represented by (Equation 4).
[0020]
[Expression 4]

[0021]
When a set of signals of these quadrature components and in-phase components is represented by complex numbers, (Formula 5) is obtained.
[0022]
[Equation 5]

[0023]
The inverse modulation unit 5 receives an asynchronous baseband signal one symbol before and a determination phase signal one symbol before. If it is assumed that the determination by the determination unit 9 is not erroneous, the determination phase coincides with the modulation phase φk−1, and the inverse modulation unit 5 performs the calculation shown in (Equation 6) and outputs I′ck and Q′ck. .
[0024]
[Formula 6]

[0025]
Therefore, the limiter 6 outputs a signal exp [jθ] in complex number expression. If the change in θ due to fading or the like is sufficiently slow, exp [jθ] is a constant, so it passes through the low-pass filter 7 as it is to obtain reproduced baseband carrier signals Ick and Qck shown in (Equation 7).
[0026]
[Expression 7]

[0027]
The complex multiplier 8 outputs baseband signals Ik and Qk shown in (Equation 8) by the operation of (Equation 1).
[0028]
[Equation 8]

[0029]
Since the determination unit 9 outputs the determination phase signal according to the rules of (Table 1) and (Table 2), the determination phase indicated by the signal matches the modulation phase φk. The differential decoding unit 10 obtains the value shown in (Equation 9).
[0030]
[Equation 9]

[0031]
As a result, the differential decoding unit 100 decodes data in accordance with the rules of (Table 3) and outputs a determination phase signal indicating the determination phase of one symbol before to the inverse modulation unit 5.
[0032]
[Problems to be solved by the invention]
However, in the conventional synchronous detection / demodulation device described above, due to the transient response of the low-pass filter 7, it takes time until the reproduced baseband carrier signal immediately after the start of reception converges to the phase θ of the carrier, and a sufficient received signal level at which noise can be ignored. Even so, a symbol determination error occurs. Also, a received signal that has undergone high-speed fading cannot follow the fluctuation of the phase θ of the carrier wave if the band of the low-pass filter 7 is narrow. Therefore, the band of the low-pass filter (reproduced baseband carrier signal low-pass filter) 7 has to be widened to some extent in order to accelerate the convergence and tracking of the carrier phase, and as a result, the carrier power to noise power ratio of the reproduced baseband carrier (C / N) becomes low, and the bit error rate characteristic deteriorates from the theoretical characteristic.
[0033]
In this synchronous detection demodulator, it is desired that a transient response does not occur even if the band of the low-pass filter for the reproduction baseband carrier wave signal is narrowed.
[0034]
SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronous detection / demodulation apparatus in which a transient response does not occur even if a band of a low-pass filter for a reproduction baseband carrier wave signal is narrowed, and a symbol error does not occur.
[0035]
[Means for Solving the Problems]
In order to solve this problem, the synchronous detection demodulator according to the present invention performs quadrature detection on a received signal that is phase-modulated or frequency-modulated by digital data using a local oscillation signal that is asynchronous with the carrier wave of the received signal. A quasi-synchronous detection unit that outputs a first baseband signal composed of components, a carrier recovery unit that recovers a carrier signal composed of in-phase and quadrature components from the first baseband signal, and a signal output from the carrier recovery unit And a complex that multiplies the first baseband signal by the reproduced carrier signal composed of the in-phase component and the quadrature component output from the filter, and outputs the second baseband signal composed of the in-phase component and the quadrature component. A determination phase for determining a symbol from the multiplier and the second baseband signal and indicating a phase of the determined symbol And a differential decoding unit that receives a determination phase signal and decodes data, and the differential decoding unit has a fixed specific phase fixed to the determination phase signal. In the case of having a switching device that switches between the fixed phase signal shown and operating as a synchronous detector, the inverse modulation that reversely modulates the signal obtained by delaying the first baseband signal by one symbol with the phase obtained by the switching device When the carrier wave recovery unit performs the carrier wave recovery unit, the filter is set to a low-pass characteristic, and the switch is switched to the determination phase signal side to operate as a delay detector, the first baseband signal is set to one symbol. Inverts the delayed signal with the phase obtained by the switcher, and causes the carrier recovery unit to perform inverse modulation type carrier recovery, sets the filter to the through characteristic, and fixes the switcher Those configured to switch the phase signal side.
[0036]
Thereby, even if the band of the low-pass filter for the reproduced baseband carrier signal is narrowed, a transient detection does not occur and a synchronous detection / demodulation device in which no symbol error occurs is obtained.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
In the first aspect of the present invention, a received signal phase-modulated or frequency-modulated by digital data is quadrature-detected by a local oscillation signal that is asynchronous with the carrier wave of the received signal, and a first signal comprising an in-phase component and a quadrature component is obtained. A quasi-synchronous detection unit that outputs one baseband signal, a carrier recovery unit that recovers a carrier signal composed of an in-phase component and a quadrature component from the first baseband signal, and a filter that receives a signal output from the carrier recovery unit A complex multiplier that complex-multiplies the first baseband signal by the recovered carrier signal composed of the in-phase component and the quadrature component output from the filter, and outputs the second baseband signal composed of the in-phase component and the quadrature component; A determination unit that determines a symbol from the second baseband signal and outputs a determination phase signal indicating a phase of the determined symbol; A synchronous detection demodulator having a differential decoding unit that receives a constant phase signal and decodes data, wherein the differential decoding unit switches between a determination phase signal and a fixed phase signal indicating a fixed specific phase In the case of operating as a synchronous detector, an inverse modulation type carrier recovery that reversely modulates a signal obtained by delaying the first baseband signal by one symbol with the phase obtained by the switch is provided to the carrier recovery unit. When the filter is set to the low-pass characteristic and the switch is switched to the judgment phase signal side to operate as a delay detector, a signal obtained by delaying the first baseband signal by one symbol is Let the carrier recovery unit perform inverse modulation type carrier recovery that performs inverse modulation with the obtained phase, set the filter to the through characteristic, and switch the switch to the fixed phase signal side. At the start of reception, a fixed phase signal is output from the switch and operates in the delay detection mode. After receiving several symbols after the start of reception, a determination phase signal is output from the switch and enters the synchronous detection mode. It has the effect of being switched.
[0038]
According to a second aspect of the present invention, a phase of a received signal that is phase-modulated or frequency-modulated by digital data is detected by a local oscillation signal that is asynchronous with a carrier wave of the received signal, and a first baseband phase signal is output. A detection unit, a carrier recovery unit that recovers the carrier phase signal from the first baseband phase signal, a filter that receives the carrier phase signal output from the carrier recovery unit, and a recovered carrier phase signal output from the filter. A subtractor that subtracts one baseband phase signal to output a second baseband phase signal, and determines a symbol from the second baseband phase signal, and outputs a determination phase signal indicating the phase of the determined symbol It operates as a synchronous detector with a switching unit that switches between a determination unit that performs and a determination phase signal and a fixed phase signal that indicates a fixed specific phase In this case, the carrier recovery unit performs inverse modulation type carrier recovery in which a signal obtained by delaying the first baseband phase signal by one symbol is subtracted by the determination phase obtained by the switch switched to the determination phase signal side. When the filter is set to a low-pass characteristic and is operated as a delay detector, the signal obtained by delaying the first baseband phase signal by one symbol is switched to the fixed phase signal side. In the filter for outputting the recovered carrier phase signal, the carrier recovery unit performs the reverse modulation type carrier recovery that subtracts with a fixed phase and sets the filter to the through characteristic. The narrowband filter operation is started with the final symbol phase in the delay detection mode as the initial phase of the regenerated carrier wave.
[0039]
According to a third aspect of the present invention, in the first aspect of the present invention, the carrier recovery unit includes a delay unit, and the delay unit includes a latch circuit driven by a symbol clock or a memory updated by the symbol clock. The data of each part is updated in synchronization with the symbol clock.
[0040]
According to a fourth aspect of the present invention, in the first or second aspect of the present invention, in place of the switch, a latch circuit driven by a symbol clock or a memory updated by the symbol clock is provided. The differential decoding unit outputs the determination phase signal or the fixed phase signal by connecting or stopping the input of the symbol clock.
[0041]
According to a fifth aspect of the present invention, in the second aspect of the invention, an averaging circuit that temporally averages a difference value obtained by subtracting the output signal of the filter with a symbol clock, and a filter based on the output signal of the averaging circuit. And a correction circuit for correcting the output signal of the correction signal, and the output signal of the correction circuit is used as a reproduced carrier phase signal, and the phase of the reproduced carrier is corrected even if an error occurs in the carrier frequency of the received signal. Has the effect of being
[0042]
According to a sixth aspect of the present invention, there are provided a plurality of sets of diversity branches of the quasi-synchronous detection unit, the carrier wave recovery unit, the filter and the complex multiplication unit according to the first aspect, and a second base output from each complex multiplication unit. A determination unit that determines a symbol from a signal obtained by selecting or combining band signals and outputs a phase of the determined symbol as a determination phase signal, and the differential decoding unit according to claim 1 is provided. The fixed phase signal is output from the switch at the start of reception and operates in the delay detection mode, and the decision phase signal is output from the switch at the time of reception of several symbols after the reception is started and the operation is switched to the synchronous detection mode. In addition, the diversity reception is performed, and the influence of fading is suppressed.
[0043]
According to a seventh aspect of the present invention, there is provided a plurality of sets of diversity branches of the quasi-synchronous detection unit, the carrier wave recovery unit, the filter and the complex multiplication unit according to the second aspect, and a second base output from each complex multiplication unit A determination unit that determines a symbol from a signal obtained by selecting or combining band phase signals and outputs the phase of the determined symbol as a determination phase signal, and the differential decoding unit according to claim 2. In addition, the filter that outputs the regenerated carrier phase signal has the effect that the narrow band filter operation is started with the final symbol phase in the delay detection mode as the initial phase of the regenerated carrier wave, and diversity reception is performed, which has the effect of fading. It has the effect of being suppressed.
[0044]
Embodiments of the present invention will be described below with reference to FIGS. 1 to 3 and FIG.
(Embodiment 1)
FIG. 1 is a block diagram showing a synchronous detection demodulator according to Embodiment 1 of the present invention. In FIG. 1, distributor 1, quasi-synchronous detection unit 2, inverse modulation unit 5, limiter 6, low pass filter 7, complex multiplication unit 8, determination unit 9, delay unit 11, subtractor 12, mixers 21 and 22, low pass filter 23 and 24, the local oscillator 25, the A / D converters 31 and 32, and the delay units 41 and 42 are the same as those in FIG. Reference numeral 13 denotes a switch as a switch, and reference numeral 100 denotes a differential decoding unit.
[0045]
As shown in FIG. 1, the differential decoding unit 100 includes a one-symbol delay unit 11, a switch 13 that switches the input of the delay unit 11, and a subtractor 12, and synchronously detects a determination phase signal output from the determination unit 9. Conversion is performed according to the rules shown in (Table 3) during mode operation. The delay units 41 and 42, the inverse modulation unit 5 and the limiter 6 constitute a carrier recovery unit. The delay units 11, 41, 42, and 74 (FIG. 5) can use delay elements such as delay lines, but are configured by a latch circuit driven by a symbol clock or a memory updated by a symbol clock. A configuration suitable for such digital signal processing and circuit integration is a suitable measure.
[0046]
The operation of the synchronous detection and demodulation apparatus configured as described above will be described. An input intermediate frequency signal to the distributor 1 is expressed by (Equation 3). The intermediate frequency signal shown in (Equation 3) is converted into a quadrature component and in-phase component asynchronous baseband signal by the quasi-synchronous detector 2, and further sampled for each symbol by the A / D converters 31 and 32. Asynchronous baseband signals (first baseband signals) I′k and Q′k expressed by Equation 4). When a set of signals of these quadrature components and in-phase components is represented by a complex number, (Formula 5) is obtained. The above operation is the same as that in the conventional apparatus.
[0047]
First, a description will be given from the start of reception. At the start of reception, that is, at the beginning of burst reception, the switch 13 is connected to the D side, the output of the delay device 11 becomes 0, and the magnification α of the constant multiplier 72 (FIG. 5) of the low-pass filter 7 is set to 0. Is done. At this time, the inverse modulation unit 5 is input with the asynchronous baseband signals I′k−1 and Q′k−1 one symbol before and 0 (that is, a fixed phase) as the determination phase. Output signal is equal to the input signal. Further, since α is set to 0 in the low-pass filter 7, the input signal of the low-pass filter 7 is output as it is. That is, the low-pass filter 7 is in a through state. Therefore, the output signals of the low-pass filter 7, that is, the reproduction baseband carrier signals Ick and Qck are expressed by (Equation 10).
[0048]
[Expression 10]

[0049]
Therefore, the value of the output signal (second baseband signal) of the complex multiplier 100 is (Equation 11), and the present demodulator operates as a delay detector.
[0050]
[Expression 11]

[0051]
Since the determination unit 9 outputs a determination phase signal according to the rule for odd symbols in (Table 2), if there is no error due to noise or the like, the determination phase ψk indicated by the signal matches (Equation 9). The differential decoding unit 100 outputs the signal of the determination phase ψk as it is, and the data is decoded according to the rule of (Table 3).
[0052]
In this state, an appropriate number of symbols is received. For example, during the preamble period of the burst, the switch 13 is switched to the C side, an appropriate value is set in α of the constant multiplier 72 of the low-pass filter 7, and the synchronous detection mode is switched. When the switch 13 is connected to the C side, the configuration of FIG. 1 is the same as the configuration of FIG. 4, and the demodulator operates as a synchronous detector. Thus, even if the detection mode is switched, a transient response does not occur in the output signal of the low-pass filter 7. In the following description, it is assumed that the switch 13 is switched from the D side to the C side immediately after the output of the demodulated data of the Lth symbol in the transition process from the delay detection mode to the synchronous detection mode. The value of the output signal of the low-pass filter 7 immediately before switching (k = L) is expressed by (Equation 12).
[0053]
[Expression 12]

[0054]
At this time, as the input value of the delay device 11, the output value of the determination unit 9 shown in (Equation 13) is set.
[0055]
[Formula 13]

[0056]
When the switch 13 is switched to the C side at the next symbol, the value of (Equation 13) appears as an output value of the delay device 11 after being delayed. This is shown in (Formula 14).
[0057]
[Expression 14]

[0058]
Therefore, the output value of the inverse modulation unit 5 is a value of (Expression 15), and the output value of the limiter 6, that is, the input value of the low-pass filter 7, is a value of (Expression 16).
[0059]
[Expression 15]

[0060]
[Expression 16]

[0061]
If there is no noise or interference in this way, the input value of the low-pass filter 7 does not change before and after the detection mode is switched. Therefore, the output of the subtractor 71 (FIG. 5) becomes 0, and no transient response occurs even if α is set to an appropriate value other than 0.
[0062]
By the way, in the synchronous detection mode thereafter, the determination phase has a relationship represented by (Equation 17) with respect to the modulation phase, and a certain offset occurs with respect to the modulation phase.
[0063]
[Expression 17]

[0064]
However, since π / 4 shift QPSK is differential encoding modulation, an output signal having a value of (Equation 18) appears as an output signal of the differential decoding unit 100, so that a determination error does not occur.
[0065]
[Expression 18]

[0066]
In the present embodiment, the switch 13 is disposed on the input side of the delay device 11, but may be disposed on the output side thereof. In this case, switching is delayed by one symbol. In this embodiment, the switch 13 operates as a delay detector by switching the determination phase to a fixed phase of 0. However, when the delay device 11 is configured by a latch circuit, for example, the switch 13 is not used. It is sufficient to stop the clock of the latch circuit and stop the data update. At this time, since the output phase of the delay unit 11 is fixed to a specific symbol point phase such as π, for example, the phase of the reproduced carrier wave and the synchronous baseband signal and the symbol point phase fixed to the determination phase of the output of the determination unit 9 An offset of minutes will occur. However, as apparent from FIG. 1, since the offset is canceled by the subtracter 12, the same output value can be obtained. With such a configuration, the switch 13 is unnecessary and the configuration is simplified.
[0067]
As described above, according to the present embodiment, when the demodulator is operated as a synchronous detector, a signal obtained by delaying the first baseband signal by one symbol is switched to the determination phase signal side C. Carrier modulation units 41, 42, 5, 6 perform inverse modulation type carrier wave regeneration that is inversely modulated with the phase (determination phase) obtained by the detector 13, and the filter 7 is set to a low-pass characteristic to serve as a delay detector. In the case of operation, an inverse modulation type that reverse-modulates a signal obtained by delaying the first baseband signal by one symbol with a phase of 0 (fixed phase) obtained by the switcher 13 switched to the fixed phase signal side D. By causing the carrier recovery units 41, 42, 5, and 6 to perform carrier recovery and setting the filter 7 to the through characteristic, a delay detection mode is set at the beginning of burst reception. Since by switching to the synchronous detection mode can be made to a transient response in low pass filter 7 does not occur, it is possible to prevent the occurrence symbol errors caused by the transient response even by narrowing the band of the low pass filter 7.
[0068]
(Embodiment 2)
FIG. 2 is a block diagram showing a synchronous detection demodulator according to Embodiment 2 of the present invention. 2, distributor 1, quasi-synchronous detection unit 2, delay unit 11, subtractor 12, mixers 21 and 22, low-pass filters 23 and 24, local oscillator 25, A / D converters 31 and 32, delay unit 41, Since the differential decoding unit 100 is the same as that in FIG. 1, the same reference numerals are given and description thereof is omitted. 33 is an arctangent conversion unit (tan-1 conversion unit), 50 is an inverse modulation unit, 70 is a low-pass filter, 80 is a subtractor, and 90 is a determination unit. The delay device 41 and the inverse modulation unit 50 constitute a carrier wave recovery unit.
[0069]
The function and operation of the synchronous detection / demodulation apparatus configured as described above will be described. The arc tangent conversion unit 33 converts the input signal of the value of (Equation 4) into a signal (first baseband phase signal) of the asynchronous baseband phase φk + θ shown in (Equation 19). A look-up table method using a memory can be used. The distributor 1, the quasi-synchronous detector 2, the A / D converters 31 and 32, and the arctangent converter 33 in FIG. 2 constitute a phase detector. The determination unit 90 determines the output signal (second baseband phase signal) of the subtractor 80 according to the rules shown in (Table 3) as in the first embodiment, and outputs a signal of the determination phase ψk. The inverse modulation unit 50 subtracts the asynchronous baseband phase one symbol before output from the delay unit 41 by the determination phase one symbol before and outputs it as a reproduction baseband carrier phase.
[0070]
The low-pass filter 70 is for reducing noise from the reproduction baseband carrier wave phase output from the inverse modulator 50, and is composed of one system in FIG.
[0071]
[Equation 19]

[0072]
As described above, the quadrature / in-phase component two-channel signal after quasi-synchronous detection is not processed, but once converted into phase information and processed, the complex multiplication unit 8 and the inverse modulation unit 5 in FIG. The complex multiplication process is simply a subtraction process. Further, the limiter 6 in FIG. 1 is unnecessary, and the configuration is simplified. Furthermore, when all or part of the signal processing is performed by a digital signal processor, one having a low calculation speed can be used.
[0073]
When an error occurs between the oscillation frequency of the local oscillator 25 and the carrier frequency of the input intermediate frequency signal, θ increases or decreases in proportion to k, and therefore, the input of the low-pass filter 70 before and after the detection mode is switched. The signal is shifted by a change of θ per symbol. In such a case, a circuit for detecting the error, for example, an averaging circuit (not shown) for detecting the difference value of the reproduction baseband carrier phase, which is the output value of the low-pass filter 70, and averaging over several symbols is provided. it can.
[0074]
That is, the difference value is detected in the previous burst reception, and the input value of the delay unit 74 (FIG. 5) is corrected by a correction circuit (not shown) when the detection mode is switched from the delay detection mode to the synchronous detection mode. Similarly, the transient response of the low-pass filter 70 does not occur. Also, when fading is fast, delay detection has better characteristics than synchronous detection.For example, in the case of a car phone, the speed of the moving object is detected and the moving speed is above a certain value. It is also possible to prohibit switching to synchronous detection.
[0075]
In the present embodiment, the switch 13 is arranged on the input side of the delay device 11, but may be arranged on the output side thereof. In the present embodiment, the determination phase is switched to a fixed phase of 0 by the switch 13, but when the delay device 11 is constituted by a latch circuit, for example, as in the first embodiment, the latch circuit If the clock is stopped and the data update is stopped, it operates as a delay detector, the switch 13 is unnecessary, and the configuration is simplified.
[0076]
As described above, according to the present embodiment, when operating as a synchronous detector, a signal obtained by delaying the first baseband phase signal by one symbol is obtained by the switcher 13 switched to the determination phase signal side. When the carrier wave recovery units 41 and 50 perform the inverse modulation type carrier wave recovery to be subtracted by the determined determination phase and set the filter 70 to the low-pass characteristic and operate as a delay detector, the first baseband phase The carrier wave regenerators 41 and 50 perform reverse modulation type carrier wave regeneration that subtracts the signal obtained by delaying the signal by one symbol with the fixed phase obtained by the switcher 13 that switches to the fixed phase signal side, and the filter 70 has a through characteristic. As a result of the setting, in the filter 70 that outputs the recovered carrier phase signal, the final symbol phase in the delay detection mode is set to the recovered carrier wave. Since the narrowband filter operation can be started as the initial phase, it is possible to prevent the low-pass filter 70 from generating a transient response, and even if the band of the low-pass filter 70 is narrowed, a symbol error caused by the transient response does not occur. Can be.
[0077]
(Embodiment 3)
FIG. 3 is a block diagram showing a synchronous detection demodulator according to Embodiment 3 of the present invention. In FIG. 3, a distributor 1, a quasi-synchronous detection unit 2, an inverse modulation unit 5, a limiter 6, a low pass filter 7, a complex multiplication unit 8, a determination unit 9, a delay unit 11, a subtractor 12, a switch (switching unit) 13, The mixers 21 and 22, the low-pass filters 23 and 24, the local oscillator 25, the A / D converters 31 and 32, the delay units 41 and 42, and the differential decoding unit 100 are the same as those in FIG. The description is omitted. 3 differs from FIG. 1 in that FIG. 3 generates two types of second baseband signals Ik and Qk. That is, the two complex multipliers 8 output the second baseband signals Ik and Qk to the determination unit 9.
[0078]
By adopting the configuration as shown in FIG. 3, the present synchronous detection demodulator can also be applied to a diversity receiver. In other words, the part other than the determination unit 9 and the differential decoding unit 100 is configured to have only a number of diversity branch sets (two sets in FIG. 3). It may be configured to be selected or combined and determined. With diversity reception in this way, the reception characteristics against fading are improved.
[0079]
3 illustrates the case where two sets (two systems) of the configuration up to the complex multiplication unit 8 of the synchronous detection demodulator of FIG. 1 are used, this is applied to the subtracter 80 of the synchronous detection demodulator of FIG. Two sets (two systems) of configurations may be used. In the present embodiment, the case of the above-described two sets of configurations has been described. However, as described above, the number of sets according to the number of diversity branches may be used.
[0080]
As described above, according to the present embodiment, a portion other than determination unit 9 and differential decoding unit 100 in FIG. 1 or a portion other than determination unit 90 and differential decoding unit 100 in FIG. By doing so, it is possible to prevent a transient response from occurring in the low-pass filter 7 or 70 so that a symbol error does not occur even in the low-pass filter 7 or 70 having a narrow band. Reception characteristics can be improved.
[0081]
【The invention's effect】
As described above, according to the synchronous detection demodulator of the present invention, at the start of reception, a fixed phase signal is output from the switch to operate in the delay detection mode, and after receiving several symbols from the start of reception, the switch determines Since the phase signal can be output and switched to the synchronous detection mode, a transient response can be prevented from being generated by the low-pass filter, and even if the band of the low-pass filter is narrowed, a symbol error caused by the transient response does not occur. The advantageous effect that it can be achieved is obtained.
[0082]
In addition, in the filter that outputs the regenerated carrier phase signal, the narrowband filter operation can be started with the final symbol phase in the delay detection mode as the initial phase of the regenerated carrier wave, so that no transient response is generated in the low-pass filter. Thus, even if the band of the low-pass filter is narrowed, an advantageous effect that symbol errors caused by transient response can be prevented can be obtained.
[0083]
Further, the carrier recovery unit includes a delay unit, and the delay unit is configured by a latch circuit driven by a symbol clock or a memory updated by a symbol clock, so that data of each unit can be symbolized with a simple configuration of a latch circuit or a memory. An advantageous effect that the update can be performed in synchronization with the clock is obtained.
[0084]
In addition, by providing a latch circuit driven by a symbol clock or a memory updated by the symbol clock instead of the switch, the differential decoding unit can determine or fix the determination phase signal by connecting or stopping the input of the symbol clock. Since the phase signal can be output, it is possible to obtain an advantageous effect that the generation of the determination phase or the fixed phase can be realized with a simple configuration.
[0085]
And an averaging circuit that temporally averages a difference value obtained by subtracting the output signal of the filter with the symbol clock, and a correction circuit that corrects the output signal of the filter with the output signal of the averaging circuit. By making the output signal a reproduced carrier phase signal, an advantageous effect is obtained that the phase of the reproduced carrier can be corrected even if an error occurs in the carrier frequency of the received signal.
[0086]
Furthermore, by providing multiple sets of quasi-synchronous detectors, carrier recovery units, filters, and complex multipliers for the diversity branch, at the start of reception, a fixed phase signal is output from the switch to operate in the delayed detection mode, and reception starts. After receiving several symbols from the time, a decision phase signal can be output from the switch to switch to the synchronous detection mode, and diversity reception operation is possible, so even if the band of the low-pass filter is narrowed, it is caused by a transient response An advantageous effect is obtained that it is possible to prevent the occurrence of symbol errors and to suppress the influence of fading.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a synchronous detection demodulator according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a synchronous detection demodulator according to a second embodiment of the present invention.
FIG. 3 is a block diagram showing a synchronous detection demodulator according to a third embodiment of the present invention.
FIG. 4 is a block diagram showing a conventional synchronous detection demodulator.
5 is a functional block diagram showing a filter constituting the synchronous detection demodulator of FIG. 4;
[Explanation of symbols]
1 Distributor
2 Quasi-synchronous detector
5, 50 Inverse modulation section
6 Limiter
7, 23, 24, 70 Low-pass filter
8 Complex multiplier
9, 90 judgment part
11, 41, 42, 74 delay device
12, 71, 80 Subtractor
13 switch
21, 22 Mixer
25 Local oscillator
31, 32 A / D converter
72 constant multiplier
73 Adder
100 Differential decoding unit

Claims (7)

Quasi-synchronous detection that outputs a first baseband signal composed of an in-phase component and a quadrature component by performing quadrature detection on a received signal that is phase-modulated or frequency-modulated with digital data using a local oscillation signal that is asynchronous with the carrier wave of the received signal. A carrier reproduction unit that reproduces a carrier signal composed of an in-phase component and a quadrature component from the first baseband signal, a filter that inputs a signal output from the carrier recovery unit, and an in-phase output from the filter A complex multiplier that complex-multiplies the first baseband signal by a reproduced carrier signal composed of a component and a quadrature component, and outputs a second baseband signal composed of an in-phase component and a quadrature component; and the second baseband signal A determination unit that determines a symbol from the output and outputs a determination phase signal indicating a phase of the determined symbol; and A synchronous detection demodulator having a differential decoding unit that receives a phase signal and decodes data, wherein the differential decoding unit switches between the determination phase signal and a fixed phase signal indicating a fixed specific phase In the case of having a switch and operating as a synchronous detector, the reverse modulation type carrier recovery for reversely modulating the signal obtained by delaying the first baseband signal by one symbol with the phase obtained by the switch When the carrier is regenerated, the filter is set to a low-pass characteristic, and the switch is switched to the decision phase signal side to operate as a delay detector, the first baseband signal is delayed by one symbol. The carrier wave regenerator performs the demodulation type carrier wave regeneration that demodulates the generated signal with the phase obtained by the switch, and the filter is set to the through characteristic. Synchronous detection demodulation device characterized by switching said switching device to the stationary phase signal side. A phase detector that outputs a first baseband phase signal by detecting a phase of a received signal phase-modulated or frequency-modulated by digital data with a local oscillation signal that is asynchronous with a carrier wave of the received signal; A carrier wave regenerator for regenerating a carrier wave phase signal from a baseband phase signal, a filter for inputting a carrier wave phase signal output from the carrier wave regenerator, and the first baseband by a regenerated carrier wave phase signal output from the filter A subtractor that subtracts the phase signal and outputs a second baseband phase signal; and a determination unit that determines a symbol from the second baseband phase signal and outputs a determination phase signal indicating the phase of the determined symbol And a switching device for switching between the determination phase signal and a fixed phase signal indicating a fixed specific phase as a synchronous detector In the case of generating the reverse modulation type carrier wave reproduction, the signal obtained by delaying the first baseband phase signal by one symbol is subtracted by the determination phase obtained by the switching unit switched to the determination phase signal side. When the filter is set to a low-pass characteristic and is operated as a delay detector, the signal obtained by delaying the first baseband phase signal by one symbol is placed on the fixed phase signal side. A differential decoding unit that causes the carrier recovery unit to perform inverse modulation type carrier recovery for subtracting at a fixed phase obtained by the switched switcher, and sets the filter to a through characteristic. Synchronous detection demodulator. 2. The synchronous detection demodulator according to claim 1, wherein the carrier recovery unit includes a delay unit, and the delay unit includes a latch circuit driven by a symbol clock or a memory updated by the symbol clock. 3. The synchronous detection demodulator according to claim 1, further comprising a latch circuit driven by a symbol clock or a memory updated by the symbol clock instead of the switch. An averaging circuit that temporally averages a difference value obtained by subtracting the output signal of the filter with a symbol clock, and a correction circuit that corrects the output signal of the filter with the output signal of the averaging circuit, The synchronous detection demodulator according to claim 2, wherein the output signal of the correction circuit is a reproduced carrier phase signal. A signal obtained by selecting or combining a plurality of sets of diversity branches of the quasi-synchronous detection unit, the carrier recovery unit, the filter, and the complex multiplication unit according to claim 1 and the second baseband signal output from each complex multiplication unit A synchronous detection / demodulation apparatus comprising: a determination unit that determines a symbol from the determination unit, and outputs a phase of the determined symbol as a determination phase signal; and the differential decoding unit according to claim 1. A plurality of sets of diversity branches of the quasi-synchronous detection unit, the carrier recovery unit, the filter, and the complex multiplication unit according to claim 2 and the second baseband phase signal output from each complex multiplication unit are selected or synthesized. A synchronous detection demodulator comprising: a determination unit that determines a symbol from a signal and outputs the phase of the determined symbol as a determination phase signal; and the differential decoding unit according to claim 2.

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