JP3612486B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a method for manufacturing a semiconductor device constituting a semiconductor integrated circuit having a thin film transistor formed over an insulating surface. In the present invention, the insulating surface refers to an insulating substrate, an insulating film formed thereon, or an insulating film formed on a semiconductor or metal material. The present invention particularly relates to an integrated circuit using a metal material mainly composed of aluminum as a gate electrode / wiring material, and includes a semiconductor integrated circuit such as an active matrix circuit used for a liquid crystal display or the like. How to make About.
[0002]
[Prior art]
Conventionally, a thin film transistor (TFT) has been manufactured using a self-alignment method (self-alignment method) with the aid of single crystal semiconductor integrated circuit technology. In this method, a gate electrode is formed on a semiconductor film via a gate insulating film, and impurities are introduced into the semiconductor film using the gate electrode as a mask. As a means for introducing impurities, a thermal diffusion method, an ion implantation method, a plasma doping method, or a laser doping method is used.
[0003]
Conventionally, a TFT uses silicon whose conductivity is increased by doping using a single crystal semiconductor integrated circuit technology as a gate electrode material. This has high heat resistance and was an ideal material for high temperature processing. However, in recent years, it has become clear that using silicon gates is not appropriate.
The first is that the conductivity is low. This has not been conspicuous in devices with a relatively small area until now, but as the liquid crystal display has increased in size, the active matrix circuit has also increased in size, and the design rule (the width of the gate wiring) has been deferred. Became prominent.
[0004]
The second problem is related to the substrate material. As the device becomes larger, the substrate material used is not an expensive material with high heat resistance such as quartz or silicon wafer, but Corning 7059 glass or NH techno. It has become necessary to use inexpensive materials that are inexpensive but inferior in heat resistance, such as glass silicate glass such as NA-35 and NA-45. Since the heat treatment of at least 650 ° C. is necessary for forming the silicon gate, it is not appropriate to use such a material as a substrate.
[0005]
Because of these problems, it has been necessary to use aluminum gate instead of silicon gate. In this case, pure aluminum may be used, but since the heat resistance is extremely inferior, usually a small amount of a material such as silicon, copper, or scandium (Sc) is added. Nevertheless, since aluminum has a problem in terms of heat resistance, for example, thermal annealing cannot be used for activation of impurities after a doping process using accelerated ions such as ion implantation, as in laser irradiation. Light annealing was used. Even at that time, the light intensity, etc., to be irradiated so that the aluminum gate was not damaged by the light irradiation was severely restricted.
[0006]
Aluminum with a mirror surface itself reflects light over a wide wavelength range from ultraviolet to infrared. For example, in flash lamp annealing, the duration of light irradiation is long, so the light absorbed by the silicon film, etc. The temperature of the silicon film increased, and it was transferred to the aluminum by heat conduction, and the aluminum melted and deformed. Similar problems occur with laser annealing and with continuous-wave laser irradiation. In the case of irradiation with an extremely short pulsed laser, the light absorbed by the silicon film was used only for annealing the silicon film, and aluminum could be used without increasing the temperature.
[0007]
FIG. 4 shows a manufacturing process of a thin film transistor having an aluminum gate based on the above idea. First, a base insulating film 402 is deposited over a substrate 401, and island-shaped crystalline semiconductor regions 403 and 404 are formed. Then, an insulating film 405 functioning as a gate insulating film is formed so as to cover this. (Fig. 4 (A))
[0008]
Then, the gate electrodes / wirings 406 and 407 are formed using a material mainly composed of aluminum. (Fig. 4 (B))
Next, an impurity (for example, phosphorus (P) or boron (B)) is implanted in a self-aligned manner by means such as ion implantation or ion doping using the gate electrodes / wirings 406 and 407 as a mask, thereby forming an impurity region. 408 and 409 are formed. Here, since phosphorus is implanted into the impurity region 408 and boron is implanted into the impurity region 408, the former is assumed to be N-type and the latter is assumed to be P-type. (Fig. 4 (C))
[0009]
Thereafter, the region into which the impurity is introduced is activated by irradiating a pulse laser beam from the upper surface. (Fig. 4 (D))
Finally, an interlayer insulator 411 is deposited, contact holes are formed in the respective impurity regions, and electrodes / wirings 412 to 416 connected thereto are formed, thereby completing the thin film transistor. (Fig. 4 (E))
[0010]
[Problems to be solved by the invention]
However, in the method described above, the boundary between the impurity region and the channel formation region (the portion sandwiched between the impurity regions in the semiconductor region immediately below the gate electrode) (for example, indicated by 410 in FIG. 4D) is Since it was not subjected to sufficient treatment in the process, it was found that it was electrically unstable, and problems such as an increase in leakage current occurred when used for a long time, resulting in a decrease in reliability.
That is, as is apparent from the process, after the gate electrode is formed, impurities are not introduced and laser irradiation is not performed, so that the crystallinity of the channel formation region is not substantially changed.
[0011]
On the other hand, the impurity region adjacent to the channel formation region initially has the same crystallinity as the channel formation region, but the crystallinity is destroyed in the process of impurity introduction. The impurity region is recovered by a later laser irradiation process, but it is difficult to reproduce the same state as the original crystallinity, and in particular, the portion of the impurity region that contacts the active region may become a shadow during laser irradiation. Highly active and cannot be fully activated. That is, the crystallinity of the impurity region and the active region is discontinuous, so that trap levels are likely to occur. In particular, when a method of irradiating high-speed ions is adopted as an impurity introduction method, the impurity ions wrap around under the gate electrode portion due to scattering and destroy the crystallinity of that portion. The area under the gate electrode portion cannot be activated by a laser or the like, with the gate electrode portion being a shadow.
[0012]
The same applies to the gate insulating film. That is, the gate insulating film on the channel formation region maintains the initial state, whereas the gate insulating film on the impurity region changes greatly due to the process of impurity introduction, laser irradiation, etc. Many trap levels were generated.
[0013]
One method for solving this problem is to activate by irradiating with light such as laser from the back side. In this method, since the gate wiring is not shaded, the boundary between the active region and the impurity region is sufficiently activated. However, in this case, it is necessary for the substrate material to transmit light, and it is difficult for many glass substrates to transmit ultraviolet light of 300 nm or less. For example, a KrF excimer laser (wavelength excellent in mass productivity) 248 nm) is not available.
[0014]
Further, in such a laser irradiation process, although aluminum is instantaneous, it is heated to a high temperature to cause an abnormal growth (hillock) of aluminum crystals. In particular, the abnormal growth in the vertical direction caused a short circuit with the upper wiring.
In addition, there is another problem when the ion doping method is used as the impurity doping method. The ion doping method refers to a gas containing impurities to be doped (for example, phosphine (PH for PH). ₃ ), Diborane (B ₂ H ₆ )) Is discharged, and the generated ions are extracted and irradiated at a high voltage.
[0015]
This method is simpler than the ion implantation method and is suitable for large-area processing, but does not separate the mass, so that various ions are irradiated. In particular, hydrogen ions are irradiated in a very large amount, both atomic and molecular. When such hydrogen ions are present in the gate insulating film in the vicinity of the gate electrode (the gate insulating film above the region 410 in FIG. 4), the characteristics are changed by voltage application. In particular, the method shown in FIG. 4 has a problem in that it cannot perform a treatment for sufficiently releasing hydrogen injected into the gate insulating film.
[0016]
The present invention has been made in view of such problems, and proposes a method of manufacturing a highly reliable thin film transistor by achieving continuity of crystallinity between an active region and an impurity region. It is an object to propose a high-performance thin film semiconductor integrated circuit in which various thin film transistors are integrated.
[0017]
[Means for solving problems]
The present invention activates not only the impurity region and the gate insulating film but also the channel formation region by a thermal annealing treatment or a light annealing treatment that irradiates light energy emitted from a powerful light source such as a laser or a flash lamp. To solve the above problem.
[0018]
The basic configuration of the present invention is as follows. First, a material functioning as a mask for forming an impurity region is formed over an island-shaped semiconductor region having crystallinity, and a doping impurity is introduced into the semiconductor film by means of ion doping or the like using the material as a mask. . The material to be used as a mask is an insulating material containing an organic material such as polyimide or silicon oxide or silicon nitride, and the conductive material is a metal such as aluminum, tantalum, or titanium, or nitride. Conductive metal nitrides such as tantalum and titanium nitride are preferred. When it is desired to avoid direct contact between the semiconductor region and the mask, a silicon oxide or silicon nitride film may be formed therebetween.
[0019]
Next, the mask is removed, and an insulating film functioning as a gate insulating film is formed. Thereafter, thermal annealing or light annealing treatment improves not only the activation of the doped impurities, but also the interface characteristics between the gate insulating film and the channel forming region and the characteristics between the channel forming region and the impurity region. In this case, light annealing alone or heat annealing alone or light annealing and heat annealing may be used in combination.
In the thermal annealing treatment, the annealing temperature is set to 650 ° C. or lower. In addition, when a laser is used in the optical annealing treatment, various excimer lasers such as a KrF laser (wavelength 248 nm), a XeCl laser (308 nm), an ArF laser (193 nm), a XeF laser (353 nm), an Nd: YAG laser ( 1064 nm) and the second, third, and fourth harmonics thereof, a carbon dioxide laser, an argon ion laser, a copper vapor laser, and the like may be used.
[0020]
Incoherent light sources are also inexpensive and easy to use. For example, a xenon lamp, a krypton arc lamp, a halogen lamp, and the like. In these light treatments, not only irradiation from the upper side of the semiconductor region but also irradiation from the back surface can be performed from both the upper and back surfaces.
In addition, in these thermal annealing or optical annealing treatments, an atmosphere containing a halogen element (an atmosphere containing hydrogen chloride, chlorine, ethylene trichloride, hydrogen fluoride, fluorine, nitrogen trifluoride, etc.) or an oxidizing atmosphere It is effective when performed in an atmosphere containing oxygen, various nitrogen oxides, ozone, or the like.
[0021]
When forming the gate electrode, the relationship between the gate electrode and the impurity region can be either an offset gate or an overlap gate. If the offset gate is used, the leakage current of the TFT can be reduced. However, in the case of the offset gate, since the current when the TFT is turned on is small, it is disadvantageous in terms of operation speed. Therefore, the offset gate is usually used only for the switching TFT and sampling TFT of the pixel of the active matrix circuit. Other logic circuits should have a slight overlap gate. Overlap gates are disadvantageous in high-speed operation because of the presence of parasitic capacitance, but there is no problem in driving as much as an active matrix circuit.
[0022]
If all or part of the gate electrodes / wirings thus formed are anodized on the top and side surfaces to form an aluminum oxide film having a high withstand voltage, a short circuit with the upper wiring can be prevented. . In particular, in an active matrix circuit having many wiring crossings, if an anodized film is formed on the upper surface in this way, an interlayer short circuit can be prevented. Further, since aluminum oxide has a high dielectric constant, a capacitor (capacitor) can be formed between the upper wiring and the upper wiring. Anodization is usually performed electrochemically in an electrolytic solution, but it goes without saying that it may be performed in a reduced-pressure plasma atmosphere as in the known plasma anodization method.
[0023]
[Action]
In the present invention, when performing thermal annealing or optical annealing for activating the doped impurities, the gate electrode / wiring is not formed. Therefore, the conventional self-aligned doping as shown in FIG. In comparison, the allowable range of thermal annealing and optical annealing is widened. For example, it becomes possible to use thermal annealing or flash lamp annealing that could not be used in the prior art.
In the thermal annealing process, the impurity region, the channel formation region, and the gate insulating film are heated evenly, so that no discontinuity occurs at the boundary between them. Similarly, even in the case of the optical annealing treatment, there is no discontinuity due to the shadow because there is no gate electrode.
[0024]
Further, when light annealing or thermal annealing is performed in an atmosphere containing halogen or an oxidizing atmosphere, an effect of substituting hydrogen atoms remaining in the gate insulating film or the semiconductor region is recognized. A high electric field is generated in the gate insulating film and the channel formation region, and if hydrogen atoms exist in the form of silicon-hydrogen or oxygen-hydrogen at that time, the hydrogen is released by the electric field, resulting in a change in characteristics over time. . When halogen, particularly fluorine or chlorine, is present instead of hydrogen, the silicon-halogen and oxygen-halogen bond is very strong and does not easily dissociate, thus stabilizing the characteristics.
[0025]
In addition, when ion doping is used as an impurity doping means, ion doping is performed without the gate insulating film, so that hydrogen ions are not implanted into the gate insulating film, and extremely stable characteristics are obtained. can get.
Further, in a circuit having an intersection, if the upper surface and side surfaces of the gate electrode are anodized, a short circuit with the upper wiring due to generation of hillocks can be prevented. In particular, it is a feature of aluminum that an anodic oxide film having a high electrical withstand voltage can be obtained, which is a feature that cannot be achieved by conventional silicon gates.
[0026]
【Example】
Example 1 FIG. 1 shows this example. This embodiment shows a process of forming a thin film transistor circuit having an intersection on an insulating substrate. The substrate 101 is a glass substrate, for example, a non-alkali borosilicate glass substrate such as Corning 7059. A silicon oxide film 102 was deposited thereon as a base oxide film. As a deposition method of the silicon oxide film, for example, a sputtering method or a chemical vapor deposition method (CVD method) can be used. Here, a film was formed by a plasma CVD method using TEOS (tetra-ethoxy-silane) and oxygen as material gases. The substrate temperature was 200 to 400 ° C. The thickness of the underlying silicon oxide film was 500 to 2000 mm.
[0027]
Next, an amorphous silicon film was deposited. As a method for depositing the amorphous silicon film, a plasma CVD method or a low pressure CVD method is used. Here, monosilane (SiH ₄ ) As a material gas, an amorphous silicon film was deposited by plasma CVD. The thickness of the amorphous silicon film was 1000-15000 mm. Then, this film was crystallized by annealing at 600 ° C. for 72 hours. The crystalline silicon film thus obtained was etched to form island silicon regions 103.
[0028]
Thereafter, a silicon nitride film having a thickness of 1000 to 6000 mm, for example, 3000 mm, was formed on the entire surface by plasma CVD. This thickness is chosen to be sufficient to function as a mask during doping. Then, the silicon nitride film was etched to form a doping mask 104. (Fig. 1 (A))
[0029]
In this state, boron ions were doped by an ion doping method. This is diborane (B ₂ H ₆ The ions obtained by discharging a gas diluted with hydrogen are extracted at a high voltage and irradiated onto the substrate. The accelerating voltage of ions is changed depending on the thickness of the silicon region. Typically, 10 to 30 kV is appropriate when the silicon region is 1000 mm. In this embodiment, the voltage is 20 kV. Also, the dose amount is 1 × 10 ¹⁴ ~ 6 × 10 ¹⁵ Atom / cm ² For example, 5 × 10 ¹⁴ Atom / cm ² It was. Thus, the P-type impurity region 105 was formed. Incidentally, the range of the impurity region shown in the figure is nominal, and it goes without saying that there is actually a wraparound due to ion scattering or the like. (Fig. 1 (B))
[0030]
Next, the photoresist mask 104 was removed, and a silicon oxide film 106 functioning as a gate insulating film was formed to a thickness of 800 to 1500 mm, for example, 1200 mm. Here, the same manufacturing method as that of the base silicon oxide film 102 is employed. Then, annealing was performed at 600 ° C. for 12 to 48 hours, for example, 24 hours, thereby activating the doped impurities and improving the interface characteristics between the gate insulating film and the silicon region. In this step, excess hydrogen could be released from the gate insulating film 106. (Figure 1 (C))
[0031]
Thereafter, an aluminum film (containing 1 to 5% by weight of silicon) having a thickness of 3000 to 8000 mm, for example, 5000 mm is formed by sputtering, and this is etched to form aluminum gate electrodes / wirings 107, 108, and 109. Formed. At this time, the gate electrode 108 was offset. The offset width x was set to 0.3 to 2 μm. Further, since the gate wiring 109 was formed on the impurity region, it did not function as the gate electrode of the TFT but functioned as one electrode of the capacitor. Further, the gate wiring 107 is electrically connected to the other gate electrodes / wirings 108 and 109. (Figure 1 (D))
[0032]
Then, the gate electrodes / wirings 107 to 109 were subjected to anodic oxidation through current, and dense anodic oxide (aluminum oxide) films 110, 111, and 112 were formed on the surfaces and side surfaces thereof to a thickness of 1000 to 2500 mm. In anodic oxidation, the substrate is immersed in an ethylene glycol solution of 1 to 5% citric acid adjusted to about pH = 7 with ammonia, all the gate wirings of the active matrix circuit are used as positive electrodes, and the applied voltage is 1 to 5 V / This was done by boosting in minutes.
[0033]
The anodic oxide film thus formed is referred to as a barrier type anodic oxide and has an excellent breakdown voltage. As the breakdown voltage, 80% of the maximum applied voltage is guaranteed. Since the anodic oxide on the gate electrode is for preventing a short circuit with the upper wiring, an appropriate thickness may be selected for that purpose. In addition, since the side surface of the gate electrode is retracted by this anodic oxidation step, the offset width is slightly expanded to y (> x). (Figure 1 (E))
[0034]
Thereafter, a silicon oxide film 113 having a thickness of 2000 to 10,000 mm, for example, 5000 mm was formed as an interlayer insulator by plasma CVD using TEOS as a material gas, and contact holes were formed in the silicon oxide film 113. Then, a multilayer film of a material such as a metal, for example, a titanium nitride film having a thickness of 1000 mm and an aluminum film having a thickness of 5000 mm was formed, and this was etched to form an electrode / wiring 114 in the impurity region. The upper wiring 114 intersects with the gate wiring 107 as shown in the figure. However, since the intersection 115 includes the anodic oxide 110 in addition to the interlayer insulator 113, defects such as upper and lower shorts are suppressed. (Fig. 1 (F))
[0035]
Finally, a silicon nitride film 116 having a thickness of 2000 to 6000 mm, for example, 3000 mm, is formed as a passivation film by plasma CVD, and this and the silicon oxide film 113 are etched to form a contact hole for the impurity region 105. . Then, a transparent conductive film (for example, indium tin oxide film) was formed and etched to form a pixel electrode 117. (Fig. 1 (G))
[0036]
Through the above steps, a P-channel TFT 118 having an offset gate structure could be formed. In addition, a capacitor 119 (which has the gate insulating film 106 as a dielectric) can be formed adjacent to the TFT 118. In this embodiment, a TFT 118 represents a TFT used as a switching element or a sampling TFT of a pixel of an active matrix circuit.
[0037]
Embodiment 2 FIG. 2 shows this embodiment. This example is the same as Example 1 up to the doping step, except that a catalyst element for promoting crystallization is added at the time of crystallization of amorphous silicon. Therefore, the steps up to the doping step are shown in FIG. See and (B).
First, an amorphous silicon film having a thickness of 300 to 1000 mm, for example, 500 mm, was formed on a substrate on which a base oxide film was formed in the same manner as in Example 1. Then, after forming a thin nickel acetate film or nickel film on the surface, amorphous silicon was crystallized by annealing at 500 to 580 ° C. for 2 to 8 hours in a nitrogen or argon atmosphere. At this time, nickel functions as a catalyst for promoting crystallization. The crystalline silicon film thus obtained was etched to form island silicon regions.
[0038]
Thereafter, a silicon oxide film having a thickness of 1000 to 6000 mm, for example, 3000 mm, was formed on the entire surface by plasma CVD. Then, this silicon oxide film was etched to form a doping mask. The region for forming the N-channel TFT was covered with a photoresist mask.
In this state, boron ions were doped by an ion doping method. Diborane diluted with hydrogen as a doping gas (B ₂ H ₆ ) Was used. The acceleration voltage of ions was 5 to 30 kV, for example, 10 kV. The dose is 1 × 10 ¹⁴ ~ 6 × 10 ¹⁵ Atom / cm ² For example, 2 × 10 ¹⁴ Atom / cm ² It was. Thus, P-type impurity regions 202 and 203 were formed.
[0039]
Similarly, phosphorus ions were doped by an ion doping method. The doping gas is hydrogen diluted phosphine (PH ₃ ). The acceleration voltage of ions was 5 to 30 kV, for example, 10 kV. The dose is 1 × 10 ¹⁴ ~ 6 × 10 ¹⁵ Atom / cm ² For example, 5 × 10 ¹⁴ Atom / cm ² It was. In this way, an N-type impurity region 201 was formed.
[0040]
Next, the masks 201 to 203 were removed, and a silicon oxide film 204 functioning as a gate insulating film was formed to a thickness of 800 to 1500 mm, for example, 1200 mm. Then, irradiation with a KrF excimer laser (wavelength 248 nm) activated the doped impurities and improved the interface characteristics between the gate insulating film and the silicon region. The energy of the laser is 250 to 450 mJ / cm. ² The appropriate number of shots was 2 to 50 shots. Further, when the substrate was heated to 250 to 550 ° C. during laser irradiation, it could be activated more effectively.
[0041]
Since the energy density and the number of shots depend on the silicon film, an optimum one may be selected in accordance with characteristics such as the density, crystallinity, and doping amount of the silicon film to be used. Typically, phosphorus is doped with a dose of 2 × 10 ¹⁴ Atom / cm ² , Substrate temperature 250 ° C, laser energy 300mJ / cm ² A sheet resistance of 500 to 1000 Ω / □ was obtained. As is apparent from the figure, in this embodiment, the boundary between the impurity region and the active region is also irradiated by the laser, so that the reliability due to the deterioration of the boundary portion which has become a problem in the conventional manufacturing process (see FIG. 4). Sexual decline was significantly reduced.
[0042]
It should be noted that when crystallization is performed using a catalyst element such as nickel as in this example, it is observed that regions in an amorphous silicon state are left behind. The remaining amorphous silicon region could be completely crystallized.
In this embodiment, since the gate insulating film is formed after the ion doping process, the gate insulating film does not contain excessive hydrogen, and if excessive hydrogen is present, It was removed by the laser irradiation process. For this reason, characteristic variation (deterioration) was suppressed.
After this step, thermal annealing may be performed again at 500 to 600 ° C. (Fig. 2 (A))
[0043]
Thereafter, an aluminum film (containing 0.1 to 0.5% by weight of scandium) having a thickness of 3000 to 8000 mm, for example, 5000 mm was formed by sputtering. In a later step (porous anodic oxide forming step), an anodic oxide film having a thickness of about 100 to 300 mm may be formed on the aluminum surface in order to improve the adhesion between the aluminum film and the photoresist mask. In that case, the substrate may be immersed in an ethylene glycol solution of 1 to 5% citric acid adjusted to about pH = 7 with ammonia, and a voltage of 5 to 20 V may be applied to the entire aluminum film.
[0044]
Next, this was etched to form aluminum gate electrodes / wirings 205, 206, 207 and 208. At this time, the gate electrodes / wirings 205, 206, and 207 are all overlapped with the impurity regions 201, 202, and 203 by about 1 μm. Further, since the gate wiring 208 was formed on the impurity region, it did not function as the gate electrode of the TFT but functioned as one electrode of the capacitor. In this state, the gate electrodes 205 and 206 are completely electrically insulated from the gate electrodes 207 and 208. The photoresist masks 209, 210, 211, and 212 used in the patterning / etching process were left as they were. (Fig. 2 (B))
[0045]
Then, porous anodic oxides 213 and 214 were formed on the side surfaces of the gate electrode by applying a current to the gate electrodes / wirings 207 and 208 in an electrolytic solution. This anodizing step was performed using 3 to 20% of an acidic aqueous solution of citric acid or succinic acid, phosphoric acid, chromic acid, sulfuric acid or the like. In this case, a thick anodic oxide of 0.5 μm or more, for example, 2 μm, was formed at a low voltage of about 10 to 30V. The width of the anodic oxide depended on the anodic oxidation time. At this time, no current was applied to the gate electrodes / wirings 205 and 206, so no anodic oxidation occurred. (Fig. 2 (C))
[0046]
As a result, the gate electrodes 205 to 207 initially overlap each other by about 1 μm with respect to the impurity region. However, only the gate electrode 207 is retreated by 2 μm due to anodic oxidation. In other words, the offset state was 1 μm. Thus, the offset width can be controlled stably by utilizing anodization.
[0047]
Thereafter, the photoresist masks 209 to 212 were removed, and the region other than the active matrix circuit was covered with the photoresist 215 again. Then, the gate electrodes / wirings 212 and 213 are anodized through current, and a dense barrier type anodic oxide (aluminum oxide) coating is formed on the inside of the porous anodic oxides 213 and 214 and the upper surfaces of the gate electrodes / wirings 207 and 208. 216 and 217 were formed with a thickness of 1000 to 2500 mm. In anodization, the substrate is immersed in an ethylene glycol solution of 1 to 5% citric acid adjusted to about pH = 7 with ammonia, all the gate wirings of the active matrix circuit are used as positive electrodes, and the applied voltage is 1 to 5 V / This was done by boosting in minutes. It should be noted that the areas other than the active matrix circuit area were masked with a photoresist 215 and were electrically insulated from the active matrix circuit, so that anodization was not performed. (Fig. 2 (D))
[0048]
Thereafter, the photoresist 215 was removed, and a silicon oxide film 218 having a thickness of 2000 to 1000 例 え ば, for example, 5000 と し て was formed as an interlayer insulator by plasma CVD using TEOS as a material gas, and a contact hole was formed in this. Then, an aluminum film having a thickness of 5000 mm was formed, and this was etched to form electrodes / wirings 219 to 224 in the impurity region and the gate wiring. Although the figure shows a state in which a contact is formed on the gate electrode on the silicon region, in practice, a contact is formed on the gate wiring other than the silicon region. (Figure 2 (E))
[0049]
Finally, a silicon nitride film 225 having a thickness of 2000 to 6000 mm, for example, 3000 mm, is formed as a passivation film by plasma CVD, and this and the silicon oxide film 218 are etched to form a contact hole in the impurity region 203. . Then, a transparent conductive film (for example, an indium tin oxide film) was formed and etched to form a pixel electrode 226. (Fig. 2 (F))
[0050]
Through the above steps, an N-channel TFT 227 and P-channel TFTs 228 and 229 can be formed. Further, a capacitor 230 (which has the gate insulating film 204 as a dielectric) can be formed adjacent to the TFT 229. In this embodiment, the TFT 229 represents a TFT used for a pixel switching element or a sampling TFT of an active matrix circuit, and the TFTs 227 and 228 represent TFTs used for other logic circuits.
[0051]
FIG. 5 shows a block diagram in the case where an active matrix circuit constituted by using the TFT shown in this embodiment, a driver circuit thereof, and other circuits are formed on a substrate 504. The TFTs 227 and 228 shown in this embodiment are used for logic circuits of the X / Y decoder / driver, CPU, and various memories. On the other hand, the TFT 229 is used as a pixel switching TFT 501 of an active matrix circuit, a sampling TFT of a driver circuit, and matrix elements of various memories. The capacitor 230 is used as an auxiliary capacitor 503 of the pixel cell 502 of the active matrix circuit or a storage element of various memory circuits.
[0052]
Example 3 This example is shown in FIG. First, a base silicon oxide film was formed on a substrate (Corning 7059), and an island-shaped amorphous silicon film was formed to a thickness of 300 to 1000 mm, for example, 500 mm. Then, the amorphous silicon film was crystallized by laser irradiation.
[0053]
The laser uses a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec), and the energy density of the laser is 250 to 450 mJ / cm. ² It was. During the laser irradiation, the substrate was heated to 350 to 450 ° C. The number of laser shots was 2 to 10 shots. Since the energy density, the number of shots, and the temperature of the laser depend on the film quality of the amorphous silicon film, optimal values may be selected depending on the film quality. In this embodiment, a pulse laser is used, but a continuous wave laser such as an argon ion laser may be used. The crystalline silicon film thus obtained was etched to form island silicon regions.
[0054]
Thereafter, a 500 nm thick silicon nitride film 301 was deposited on the entire surface by plasma CVD. Subsequently, a silicon oxide film having a thickness of 3000 mm was formed on the entire surface by plasma CVD. Then, this silicon oxide film was etched to form doping masks 302, 303, and 304. Further, a region for forming the N-channel TFT was covered with a photoresist mask 305.
[0055]
In this state, boron ions were doped by an ion doping method. Diborane diluted with hydrogen as a doping gas (B ₂ H ₆ ) Was used. The acceleration voltage of ions was 10 to 50 kV, for example, 20 kV. The acceleration voltage needs to be increased as much as the silicon nitride film 301 exists. The dose is 1 × 10 ¹⁴ ~ 6 × 10 ¹⁵ Atom / cm ² For example, 3 × 10 ¹⁵ Atom / cm ² It was. Thus, P-type impurity regions 306 and 307 were formed. (Fig. 3 (A))
[0056]
After removing the photoresist mask 305, phosphorus ions were doped again by an ion doping method. The doping gas is hydrogen diluted phosphine (PH ₃ ). The acceleration voltage of ions was 10 to 50 kV, for example, 20 kV. The dose is 1 × 10 ¹⁴ ~ 6 × 10 ¹⁵ Atom / cm ² For example, 1 × 10 ¹⁵ Atom / cm ² It was. At this time, phosphorus was implanted into the entire surface. However, since the dose amount of phosphorus is smaller than the dose amount of boron in the previous doping, the conductivity type of the P-type impurity regions 306 and 307 formed earlier is still P.sub.2. It was a mold. In this way, an N-type impurity region 309 was formed. (Fig. 3 (B))
[0057]
Next, the photoresist mask 308 and the masks 302 to 304 and the silicon nitride film 301 were removed, and a silicon oxide film 310 functioning as a gate insulating film was formed to a thickness of 800 to 1500 mm, for example, 1200 mm. Then, by instantaneously irradiating the halogen lamp light, the doped impurities were activated and the interface characteristics between the gate insulating film and the silicon region were improved.
[0058]
The intensity of light emitted from the lamp was adjusted so that the temperature on the single crystal silicon wafer of the monitor was between 800 and 1300 ° C, typically between 900 and 1200 ° C. Specifically, the temperature of the thermocouple embedded in the silicon wafer was monitored, and this was fed back to the infrared light source. The temperature increase was constant, the speed was 50 to 200 ° C./second, and the temperature decrease was 20 to 100 ° C. by natural cooling.
[0059]
In particular, intrinsic or substantially intrinsic amorphous silicon is well absorbed by visible light, particularly light with a wavelength of less than 0.5 μm, and can convert light into heat, but the light of the present invention is 0.5-4 μm. Irradiate light of wavelength. This wavelength can be crystallized intrinsic or substantially intrinsic (phosphorus or boron is 10 ¹⁷ cm ^-3 Can effectively absorb light and convert it into heat. Further, far-infrared light having a wavelength of 10 μm or more is absorbed by the glass substrate and heated, but when the wavelength of 4 μm or less is most, heating of the glass is extremely small. That is, a wavelength of 0.5 to 4 μm is effective for further crystallizing the crystallized silicon film.
[0060]
As is clear from the figure, in this example, since light was irradiated from above and below the substrate, the decrease in reliability due to the deterioration of the boundary portion that was a problem in the conventional manufacturing process (see FIG. 4) was significantly reduced. did. (Figure 3 (C))
Thereafter, thermal annealing was performed at a temperature of 500 to 600 ° C. for 2 to 48 hours, for example, at 550 ° C. for 4 hours. Then, an aluminum film (containing 1 to 5% by weight of scandium) having a thickness of 3000 to 8000 mm, for example, 5000 mm is formed by sputtering, and this is etched to form aluminum gate electrodes / wirings 311, 312, 313. 314 was formed.
[0061]
At this time, as in Example 2, the region other than the active matrix circuit was covered with the photoresist 315, and the gate electrodes / wirings 313 and 314 were anodized through current, and the aluminum oxide film had a thickness of 1000 to 2500 mm, Barrier-type anodic oxide films were formed on the top and side surfaces of the gate electrodes / wirings 313 and 314.
[0062]
At this time, the gate electrodes / wirings 311 and 312 overlap with the impurity regions 309 and 306. On the other hand, the gate electrode / wiring 303 is offset, but unlike the second embodiment, one of the impurity regions 307 (the one that forms the pixel electrode) is offset and the other is the overlap. I did it. Further, since the gate wiring 314 was formed on the impurity region, it did not function as the gate electrode of the TFT but functioned as one electrode of the capacitor. (Fig. 3 (D))
[0063]
Thereafter, the photoresist 315 was removed, and a silicon oxide film 316 having a thickness of 5000 mm was formed as an interlayer insulator by a plasma CVD method using TEOS as a material gas, and a contact hole was formed therein. Then, an aluminum film having a thickness of 5000 mm was formed and etched to form electrodes / wirings 317 to 322 in the impurity region and the gate wiring. (Figure 3 (E))
[0064]
Finally, a silicon nitride film 323 having a thickness of 3000 mm was formed as a passivation film by plasma CVD, and this and the silicon oxide film 316 were etched to form a contact hole in the impurity region 307. Then, a transparent conductive film (for example, indium tin oxide film) was formed and etched to form a pixel electrode 324. (Fig. 3 (F))
[0065]
Through the above steps, an N-channel TFT 325 and P-channel TFTs 326 and 327 can be formed. In addition, a capacitor 328 (which has the gate insulating film 310 as a dielectric) can be formed adjacent to the TFT 327. In this embodiment, the TFT 327 represents a TFT used for a pixel switching element or a sampling TFT of an active matrix circuit, and the TFTs 325 and 326 represent TFTs used for other logic circuits.
[0066]
【The invention's effect】
According to the present invention, it was possible to form a thin film semiconductor integrated circuit with few defects that constitutes a gate electrode / wiring with a material mainly composed of aluminum. Although the TFT according to this example is based on a low-temperature process of 650 ° C. or less, it has excellent reliability and has little deterioration. Specifically, even when the source was grounded and left for 10 hours or more with a potential of +20 V or more or −20 V or less applied to one or both of the drain and gate, the transistor characteristics were not significantly affected. As described above, the present invention is an industrially useful invention.
[Brief description of the drawings]
FIG. 1 shows an embodiment of the present invention. (See Example 1)
FIG. 2 shows an embodiment of the present invention. (See Example 2)
FIG. 3 shows an embodiment of the present invention. (See Example 3)
FIG. 4 shows an example of a conventional technique.
FIG. 5 shows a block diagram of an integrated circuit using the present invention.
[Explanation of symbols]
101 ..... PCB
102 .... Base oxide film
103 ... Island-like semiconductor region
104 ..... Doping mask
105 ... P-type impurity region
106 ..... Gate insulating film
108 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Gate electrode
107, 109 ... Gate wiring
110, 111, 112 ... anodic oxide coating
113 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Interlayer insulator
114 ... upper wiring and electrodes
115 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Wiring intersection
116 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Passivation film
117 ..... Pixel electrode
118 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ P-channel TFT
119 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Capacity

Claims (3)

An amorphous silicon film is formed on the insulating surface,
Forming a film containing nickel on the amorphous silicon film;
Annealing the amorphous silicon film to form a crystalline silicon film;
Patterning the crystalline silicon film to form a first crystalline silicon film, a second crystalline silicon film, and a third crystalline silicon film;
Forming a first mask, a second mask, and a third mask on the first crystalline silicon film, the second crystalline silicon film, and the third crystalline silicon film, respectively;
An N-type impurity is added to a part of the first crystalline silicon film by the first mask;
Adding a P-type impurity to a part of the second crystalline silicon film and the third crystalline silicon film by the second mask and the third mask;
Removing the first mask, the second mask, and the third mask;
Forming a gate insulating film on the first crystalline silicon film, the second crystalline silicon film, and the third crystalline silicon film;
First crystalline silicon film in which the N-type impurity is added, a second crystalline silicon film where the P-type impurity is added, a third crystalline silicon film, and annealing the gate insulating film And
Via the gate insulating film, a first gate electrode above the first crystalline silicon film, a second gate electrode above the second crystalline silicon film, and above the third crystalline silicon film Forming a third gate electrode and a gate wiring insulated from each other ;
The first gate electrode overlaps the region of the first crystalline silicon film to which the N-type impurity is added via the gate insulating film,
The second gate electrode overlaps the region of the second crystalline silicon film to which the P-type impurity is added via the gate insulating film,
The third gate electrode does not overlap the region of the third crystalline silicon film to which the P-type impurity is added via the gate insulating film,
An auxiliary capacitance is formed by the region to which the P-type impurity is added in the gate wiring, the gate insulating film, and the third crystalline silicon film,
A first thin film transistor having the first crystalline silicon film, a gate insulating film, and a first gate electrode, and a second thin film transistor having the second crystalline silicon film, the gate insulating film, and the second gate electrode A logic circuit is formed, and a switching element of a pixel is formed by a third thin film transistor having the third crystalline silicon film, a gate insulating film, and a third gate electrode Manufacturing method. An amorphous silicon film is formed on the insulating surface,
Forming a film containing nickel on the amorphous silicon film;
Annealing the amorphous silicon film to form a crystalline silicon film;
Patterning the crystalline silicon film to form a first crystalline silicon film, a second crystalline silicon film, and a third crystalline silicon film;
Forming a first mask, a second mask, and a third mask on the first crystalline silicon film, the second crystalline silicon film, and the third crystalline silicon film, respectively;
An N-type impurity is added to a part of the first crystalline silicon film by the first mask;
Adding a P-type impurity to a part of the second crystalline silicon film and the third crystalline silicon film by the second mask and the third mask;
Removing the first mask, the second mask, and the third mask;
Forming a gate insulating film on the first crystalline silicon film, the second crystalline silicon film, and the third crystalline silicon film;
First crystalline silicon film in which the N-type impurity is added, the P-type second crystalline silicon film doped with an impurity of the third crystalline silicon film, and the gate insulating film a halogen element Annealing in an atmosphere containing
Via the gate insulating film, a first gate electrode above the first crystalline silicon film, a second gate electrode above the second crystalline silicon film, and above the third crystalline silicon film Forming a third gate electrode and a gate wiring insulated from each other ;
The first gate electrode overlaps the region of the first crystalline silicon film to which the N-type impurity is added via the gate insulating film,
The second gate electrode overlaps the region of the second crystalline silicon film to which the P-type impurity is added via the gate insulating film,
The third gate electrode does not overlap the region of the third crystalline silicon film to which the P-type impurity is added via the gate insulating film,
An auxiliary capacitance is formed by the region to which the P-type impurity is added in the gate wiring, the gate insulating film, and the third crystalline silicon film,
A first thin film transistor having the first crystalline silicon film, a gate insulating film, and a first gate electrode, and a second thin film transistor having the second crystalline silicon film, the gate insulating film, and the second gate electrode A logic circuit is formed, and a switching element of a pixel is formed by a third thin film transistor having the third crystalline silicon film, a gate insulating film, and a third gate electrode Manufacturing method. An amorphous silicon film is formed on the insulating surface,
Forming a film containing nickel on the amorphous silicon film;
Annealing the amorphous silicon film to form a crystalline silicon film;
Patterning the crystalline silicon film to form a first crystalline silicon film, a second crystalline silicon film, and a third crystalline silicon film;
Forming a first mask, a second mask, and a third mask on the first crystalline silicon film, the second crystalline silicon film, and the third crystalline silicon film, respectively;
An N-type impurity is added to a part of the first crystalline silicon film by the first mask;
Adding a P-type impurity to a part of the second crystalline silicon film and the third crystalline silicon film by the second mask and the third mask;
Removing the first mask, the second mask, and the third mask;
Forming a gate insulating film on the first crystalline silicon film, the second crystalline silicon film, and the third crystalline silicon film;
First crystalline silicon film in which the N-type impurity is added, the P-type second crystalline silicon film doped with an impurity of the third crystalline silicon film, and oxidizing the gate insulating film Annealing in the atmosphere of
Via the gate insulating film, a first gate electrode above the first crystalline silicon film, a second gate electrode above the second crystalline silicon film, and above the third crystalline silicon film Forming a third gate electrode and a gate wiring insulated from each other ;
The first gate electrode overlaps the region of the first crystalline silicon film to which the N-type impurity is added via the gate insulating film,
The second gate electrode overlaps the region of the second crystalline silicon film to which the P-type impurity is added via the gate insulating film,
The third gate electrode does not overlap the region of the third crystalline silicon film to which the P-type impurity is added via the gate insulating film,
An auxiliary capacitance is formed by the region to which the P-type impurity is added in the gate wiring, the gate insulating film, and the third crystalline silicon film,
A first thin film transistor having the first crystalline silicon film, a gate insulating film, and a first gate electrode, and a second thin film transistor having the second crystalline silicon film, the gate insulating film, and the second gate electrode A logic circuit is formed, and a switching element of a pixel is formed by a third thin film transistor having the third crystalline silicon film, a gate insulating film, and a third gate electrode Manufacturing method.

Images