JP3587595B2 - Image conversion device - Google Patents

Description

と表される。また、（４） 式の読み出しアドレスｈｍｙ がＹ２信号の位相であるときには、Ｙ１信号のサンプル点でのＣＢ信号のデータ、つまり、Ｙ２信号より３小さいアドレス（計算されたｈｍｙ より３小さいアドレス）のＣＢ信号を読み出す。よって、
【００１８】
【数７】

となる。
【００１９】
ＣＲ信号を読み出すためのアドレスを（ｈｍｒ，ｖｍｙ） とすると、（４） 式の読み出しアドレスｈｍｙ がＹ１信号の位相の時は、ＣＲ信号はＹ１信号より１大きいアドレスにあるので、
【００２０】
【数８】

となり、同様に、Ｙ２信号の位相になるときは、Ｙ２信号より１小さいアドレスのＣＲ信号を読み出すので、
【００２１】
【数９】

となる。Ｙ２信号位相での読み出し例を図５に示す。図５に示すＣＢ，ＣＲ はＹ１と同一の（Ｈ，Ｖ） で読み出しアドレスを計算して、最後にオフセットが加算される。以上から分かるように、Ｙ，ＣＢ，ＣＲ の読み出しアドレスは、Ｙ，ＣＢ，ＣＲ が多重されていない場合の座標系で幾何学変換式Ｆｘ，Ｆｙ を計算し、Ｆｘを２倍、すなわち、２Ｆｘ にし、Ｙ，ＣＢ，ＣＲ の各信号に対して、表１に示すオフセットを加算することにより求めることができる。読み出しアドレスがＹ１信号の位相またはＹ２信号の位相のいずれであるかは、幾何学変換式Ｆｘに基づき生成されたアドレスの整数部のＬＳＢ により判定することができる。表１に示すＬＳＢ は幾何学変換式Ｆｘに基づき生成されたアドレスの整数部のＬＳＢ である。
【００２２】
【表１】

【００２３】
実際には、出力信号（出力映像）も多重された形式であるので、幾何学変換式Ｆｘ，Ｆｙ の計算を、図６に示すように、ＣＢ，Ｙ１，ＣＲ信号の期間は、Ｙ１信号で計算したＦｘをホールドし、Ｙ２信号の期間はＹ２信号のＦｘを計算するというようにする。このようにすることにより、上述した原理をそのまま適用することができる。
【００２４】
次に、多重信号の補間処理について説明する。図２に示すような近傍４画素値による４点補間を用いる場合を例にとる。読み出しアドレスの水平値（ｈ） の小数部をｐとし、読み出しアドレスの垂直値（ｖ） の小数部をｑとした場合、求めたい画素値Ｇは
【００２５】
【数１０】

と表される。補間係数ｐ，ｑ は前記Ｆｘ，Ｆｙ に基づき生成されたアドレスの小数部であるが、これはＹ信号の補間係数であり、ＣＢ，ＣＲ 信号の補間処理をする場合は、係数ｐを変換する必要がある。その理由は、ＣＢ，ＣＲ 信号は１画素おきにしかサンプルがないため、４点補間に用いられる画素の関係がＹ信号とは異なるからである。この様子を図７に示す。変換後の補間係数をｐ’とする。ＣＢ，ＣＲ 信号の補間係数は、例えば、読み出しアドレスの位相がＹ１信号と同位相（ｈ整数部のＬＳＢ が０）であった場合、図７（ａ） から分かるように、
【００２６】
【数１１】
ｐ’ ＝ ｐ／２ …（９）
となる。また。位相がＹ２信号と同位相（ｈ整数部のＬＳＢ が１）であった場合、補間係数ｐ’は、図７（ｂ） から分かるように、
【００２７】
【数１２】
ｐ’ ＝ （１＋ｐ）／２ …（１０）
となる。補間係数ｐ’の切り替えを表２に示す。
【００２８】
【表２】

【００２９】
図１は本発明の第１の実施の形態を示す。図１において、１０は帯域制限回路であり、幾何学変換時の再サンプルによる折り返しを防止するために帯域制限を行うものである。帯域制限回路１０は映像信号の多重タイミングに合わせて係数を切り替えることが可能な構成とする。すなわち、多重信号のタイミング（ＣＢ，Ｙ１，ＣＲ，Ｙ２） ごとに異なる係数でフィルタ演算を行うものとする。２０は書き込みアドレス発生回路であり、クロックごとに水平値が１ずつ増加し、ラインごとに垂直値が１ずつ増加する、いわゆるリニアなアドレスを発生するものである。３１ないし３４はメモリであり、帯域制限回路１０により帯域制限された映像信号が、書き込みアドレス発生回路２０からのアドレスに従って書き込まれており、Ｇ１からＧ４までの画素に対応させてある。４０は読み出しアドレス発生回路であり、メモリ３１〜３４の読み出しアドレスを幾何学変換式に基づいて発生するものである。５０は４点補間回路であり、メモリ３１〜３４から読み出された画素値に対して、図２に示すような近傍４画素値による４点補間を行うものである。
【００３０】
このように構成したので、入力の映像信号は帯城制限回路１０により帯域制限され、得られた信号は、クロックごとに水平値が１ずつ増加し、ラインごとに垂直値が１ずつ増加する、いわゆるリニアなアドレスでメモリ３１〜３４に書き込まれる。そして、メモリ３１〜３４上の映像データは、読み出しアドレス発生回路４０により幾何学変換式に基づいて発生されたアドレスから読み出される。読み出しアドレス発生回路４０により発生される読み出しアドレス値は小数を含んでおり、必ずしも入力映像の標本点に一致しないので、図２に示すような近傍４画素値による４点補間を用いている。読み出しアドレスの水平値（ｈ） の小数部をｐとし、読み出しアドレスの垂直値（ｖ） の小数部をｑとした場合、求めたい画素値Ｇは
【００３１】
【数１３】

と表される。
【００３２】
図９は図１に示す読み出しアドレス回路４０の構成を示す。図９において、５０は図１の４点補間回路５０と同一部分を示す。９０１はアドレス計算回路であり、非多重形式の信号を幾何学変換する際のアドレス（ｈ，ｖ） を計算するものである。９０２はビットシフタであり、アドレス計算回路９０１により計算されたアドレスデータのうち水平方向のアドレスの整数部を上位へ１ビットシフトするものである。ビットシフタ９０２によりアドレスが２倍され、２ｈが得られる。９０３はオフセット回路であり、図１０に示すように構成されており、アドレス計算回路９０１のｈ整数部のＬＳＢ に基づき、タイミング回路９０４からの信号に合わせて、ＣＢ，Ｙ１，ＣＲ，Ｙ２ のオフセットを出力するものである。９０５は補間アドレス回路であり、Ｇ１，Ｇ２，Ｇ３，Ｇ４ 相当する画素のアドレスをそれぞれ計算するものである。
【００３３】
次に、動作を説明する。非多重形式の信号を幾何学変換する際のアドレス（ｈ，ｖ） がアドレス計算回路９０１により計算され、得られたアドレスデータのうちｈ方向のアドレスはビットシフタ９０２により上位へ１ビットシフトされる。よって、アドレスが２倍され、２ｈが得られる。そして、読み出しアドレスがＹ１の位相か、Ｙ２の位相かが、アドレス計算回路９０１のｈ整数部のＬＳＢ で判定され、判定結果に基づき、オフセットが切り換えられる。すなわち、ｈ整数部のＬＳＢ が０の場合には、スイッチ素子１００３がセレクタ１００１側に切り換えられ、ＣＢ，Ｙ１，ＣＲ，Ｙ２ のそれぞれの多重タイミングに合わせて、セレクタ１００１によりそれぞれ０，１，２，１が選択され出力される。一方、ｈ整数部のＬＳＢ が１の場合には、スイッチ素子１００３がセレクタ１００２側に切り換えられ、ＣＢ，Ｙ１，ＣＲ，Ｙ２ のそれぞれの多重タイミングに合わせて、セレクタ１００２によりそれぞれ−２，１，０，１が選択され出力される。そして、切り換えられたオフセット回路１００３出力が加算され、多重形式の読み出しアドレスが計算される。多重タイミングに合わせたオフセット回路１００３出力は、表１の通りである。
【００３４】
拡大率が１．０ の場合、２．０ の場合の各回路の出力を図８（ｂ），（ｃ） に示す。このようなタイミングで読み出し、アドレスの計算が行われる。図８（ａ） において、アドレスの更新のタイミングでは、Ｕの期間は同一の読み出しアドレス値となることを示し、黒の三角形はアドレス値の更新のタイミングを示す。図８（ｂ），（ｃ） おいて、ビットシフタの出力値は、アドレス計算回路出力の整数部を２倍した値になっており、補間アドレス回路出力値はビットシフタ出力値とオフセット回路出力値を加算した結果になっている。
【００３５】
補間アドレス回路９０５では、Ｇ１画素のアドレスからＧ２，Ｇ３，Ｇ４に相当する画素のアドレスをそれぞれ計算する。これらのアドレスはＧ１画素の読み出しアドレスを（ｈｍ，ｖｍ） とすると、
Ｇ２用アドレス（ｈｍ＋α， ｖｍ ）
Ｇ３用アドレス（ｈｍ， ｖｍ＋１）
Ｇ４用アドレス（ｈｍ＋α， ｖｍ＋１）
となる。Ｙ１，Ｙ２（輝度信号） のタイミングでは、α＝２であり、ＣＢ，ＣＲ（色信号） のタイミングでは、α＝４である。
【００３６】
４点補間回路５０の構成を示す図１１を参照して４点補間回路の動作を説明する。４点補間回路５０では、Ｇ１，Ｇ２，Ｇ３，Ｇ４ 画素と、読み出しアドレスの小数部（ｐ、ｑ）を用いて、式（１） により補間画素を計算する。その際、ＣＢ，ＣＲ（色信号） のタイミングでは、読み出しアドレスのｈ整数部のＬＳＢ によって、ｐを表２のｐ’のように変換して補間計算をする。すなわち、読み出しアドレスのｈ整数部のＬＳＢ が０である場合には、スイッチ素子１１０３がセレクタ１１０１側に切り換えられ、ＣＢ，Ｙ１，ＣＲ，Ｙ２ のそれぞれの多重タイミングに合わせて、セレクタ１１０１によりそれぞれｐ／２ ，ｐ ，ｐ／２ ，ｐ が選択される。一方、ｈ整数部のＬＳＢ が１の場合には、スイッチ素子１１０３がセレクタ１１０２側に切り換えられ、ＣＢ，Ｙ１，ＣＲ，Ｙ２ のそれぞれの多重タイミングに合わせて、セレクタ１１０２によりそれぞれ（１＋ｐ）／２ ，ｐ ，（１＋ｐ）／２ ，ｐ が選択される。補間係数ｐ’と、読み出しアドレスの垂直値（ｖ） の小数部ｑを用いて、次の式、すなわち、
【００３７】
【数１４】
Ｇ ＝ Ｇ１（１−ｐ’）（１−ｑ） ＋ Ｇ２＊ｐ’（１−ｑ） ＋ Ｇ３（１−ｐ’）ｑ ＋ Ｇ４＊ｐ’＊ｑ
から、加重加算回路１１０４により画素値Ｇが求められる。
【００３８】
本実施の形態では、上記のように構成したので、多重信号のまま幾何学変換処理を行うことができ、多重信号を各チャンネルに分ける回路が不要になり、また、チャンネルごとに補間回路を用意する必要がなくなる。
【００３９】
本実施の形態では、Ｇ１からＧ４までの画素ごとに４つのメモリを用いた例を説明したが、１つのメモリで共用し、１つのメモリからの各画素の読み出しを、入力信号の標本化周波数の４倍で行うようにしても、同様の効果を奏することができる。
【００４０】
本実施の形態では、多重形式の映像信号の例を説明したが、非多重形式の映像信号を幾何学変換処理することもできる。
【００４１】
【発明の効果】
以上説明したように、本発明によれば、上記のように構成したので、（１） 多重されたコンポーネント映像信号を分離することなく幾何学変換処理を行うことができ、（２） 多重されていない映像信号も同一の回路構成で処理できるなどの特徴を有しており、従来よりも全体的に大幅な回路規模縮小を図ることができ効率的である。
【図面の簡単な説明】
【図１】本発明の一実施の形態を示すブロック図である。
【図２】４点補間を説明するための説明図である。
【図３】ＩＴＵ−Ｒ ＢＴ．６５６で勧告されている多重映像信号の伝送フォーマットを示す図である。
【図４】Ｙ信号を例に幾何学変換の原理を説明するための説明図である。
【図５】多重信号を例に幾何学変換の原理を説明するための説明図である。
【図６】アドレス計算方法を説明するための説明図である。
【図７】多重タイミングに合わせた補間係数の切り換えを説明するための説明図である。
【図８】読み出しアドレス処理を説明するための説明図である。
【図９】図１に示す読み出しアドレス発生回路４０の構成を示すブロック図である。
【図１０】図９に示すオフセット回路９０３の構成を示すブロック図である。
【図１１】図１に示す４点補間回路５０の構成を示すブロック図である。
【図１２】従来の幾何学変換装置を示すブロック図である。
【符号の説明】
１０ 帯域制限回路
２０ 書き込みアドレス発生回路
３１ Ｇ１メモリ
３２ Ｇ２メモリ
３３ Ｇ３メモリ
３４ Ｇ４メモリ
４０ 読み出しアドレス発生回路
５０ ４点補間回路
９０１ アドレス計算回路
９０２ ビットシフタ
９０３ オフセット回路
９０４ タイミング回路
９０５ 補間アドレス回路
１００１，１００２，１１０１，１１０２ セレクタ
１００３，１１０３ スイッチ素子
１１０４ 加重加算回路[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image conversion device for performing a geometric conversion process on a time-division multiplexed video signal.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a geometric conversion process of a multiplex standard TV signal is performed by a geometric conversion device as shown in FIG. The multiplexed (multiplexed) luminance signal and chrominance signal are divided into separate channels (demultiplex) by a demultiplexer 1201, and the luminance signal Y and the color signals CB, CR are stored in the memories 1203, 1204, and 1205, respectively. Then, according to the geometric transformation, Y, CB, and CR are read from the memories 1203, 1204, and 1205 according to the integer part of the addresses (integer part and decimal part) generated by the read address circuit 1206, respectively. The signals are supplied to interpolation circuits 1207, 1208, and 1209. In the interpolation circuits 1207, 1208, and 1209, the Y, CB, and CR signals obtained by performing the interpolation processing in accordance with the decimal part of the addresses (integer part and decimal part) generated by the read address circuit 1206 are multiplexed. 1210.
[0003]
[Problems to be solved by the invention]
As described above, the conventional device requires a circuit for separating and synthesizing the luminance signal Y and the color signals CB and CR, that is, the demultiplexer 1201 and the multiplexer 1210. In addition, a circuit for performing image interpolation processing, that is, interpolation circuits 1207, 1208, and 1209, is required, which is not efficient.
[0004]
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide an image conversion device capable of performing a geometric conversion process with a smaller circuit configuration.
[0005]
[Means for Solving the Problems]
According to the first aspect of the present invention, a store means, a write address generating means for generating a linear write address of the store means, and a linear address of the store means generated by the write address generating means are time-division multiplexed. Writing means for sequentially writing the digital component video signals, an address generating means for generating an address on the storing means based on a geometric conversion formula, and two-dimensionally interpolating a pixel value of the address generated by the address generating means. An image conversion device comprising interpolation means, wherein the address generation means uses a transmission format defined by ITU-R BT.656 from a vertical component and a horizontal component of output pixel coordinates and a geometric conversion formula. An address calculation circuit for calculating the address of the Y signal among the CB, Y, and CR signals which have been time-division multiplexed; A timing circuit that outputs an identification signal indicating which signal type is used at the clock timing based on the signal and the clock, an identification signal from the timing circuit, and an address of the Y signal calculated by the address calculation circuit. An offset circuit for extracting an addition coefficient determined from the value of the LSB of the integer part of the horizontal component of the horizontal component from the addition coefficient obtained in advance, and an integer part of the horizontal component of the address of the Y signal calculated by the address calculation circuit as 2 A multiplying bit shifter, an adding circuit for adding the output of the bit shifter and the output of the offset circuit, an output of the adding circuit, a vertical component of the address of the Y signal calculated by the address calculating circuit, and the timing An interpolation signal for generating an address of pixel data constituting a two-dimensional interpolation filter from an identification signal from the circuit. Characterized in that a less circuit.
[0006]
In the invention as set forth in claim 1, the interpolating means is configured to determine the signal type from the timing circuit and the LSB value of an integer part of a horizontal component of the address of the Y signal calculated by the address calculation circuit. A calculating circuit for calculating an interpolation coefficient p ′ from a value p of a decimal part of a horizontal component; and a two-dimensional interpolation filter constituent pixel data read from the storage means in accordance with an address generated by the interpolation address circuit. An interpolation filter for performing two-dimensional arithmetic processing based on the filter coefficient calculated from p ′ and the value q of the decimal part of the vertical component from the address calculation circuit can be provided.
[0007]
According to the first aspect of the present invention, the storing means can include four memories of a G1 memory, a G2 memory, a G3 memory, and a G4 memory for writing digital data of the same content respectively, and the interpolation address circuit includes: A circuit that generates an address of the video signal G1 from the output of the adder circuit and the vertical component of the address of the Y signal calculated by the address calculation circuit, and outputs the address to the G1 memory; A circuit for adding a specific value to generate an address of a video signal G3 of the same type vertically adjacent to the video signal G1 and outputting the same to the G3 memory; Of the same type of video adjacent to the video signal G1 horizontally behind the video signal G1. A signal generated as an address of the signal G2 and output to the G2 memory, and a specific value selected based on an identification signal from the timing circuit are added to the address of the video signal G1 to generate a horizontal signal of the video signal G3. A circuit that generates an address of the same type of video signal G4 adjacent to the rear and outputs the same to the G4 memory, and the interpolation filter includes video signals G1 and G2 that are output data from the four memories. , G3 and G4 as inputs, and the four data as pixel data constituting a two-dimensional interpolation filter from the interpolation coefficient p ′ and the value q of the decimal part of the vertical component of the address of the Y signal.
G = G1 (1-p ') (1-q) + G2 * p' (1-q) + G3 (1-p ') q + G4 * p' * q
Can be provided with a circuit for calculating the interpolation data G by the calculation expression represented by
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
The principle of the geometric transformation according to the present invention will be described. First, for simplicity of description, a description will be given of an example of a non-multiplexed Y signal. When the input Y signal is written to the memory at a linear address and read to the output screen, it is read at the address generated based on the geometric transformation formula. Assuming that the geometric transformation formula is Fx, Fy, the coordinates (address) on the memory are (h, v), and the coordinates on the output screen are (H, V), (h, v) and (H, V) The relationship is
[0012]
(Equation 3)
h = Fx (H, V)
v = Fy (H, V) (2)
It can be expressed as. That is, the pixel at the position (H, V) on the output screen is read from the address (h, v) in the memory. However, since (h, v) may not coincide with the input sample point, in such a case, a four-point interpolation process is performed. By doing so, geometric transformation can be performed. This is shown in FIG.
[0013]
Next, a method of writing the multiplexed Y, CB, and CR into a memory as a multiplexed signal and separately reading the Y, CB, and CR signals from the memory will be described. The multiplex signal referred to here is ITU-R BT. A signal having a format as shown in FIG. In the format, the signal type is uniquely determined by the horizontal synchronization signal and the clock. When the coordinates (address) of the Y signal on the memory are (hmy, vmy) and the coordinates on the output screen are (H, V), the address (hmy, vmy) from which the Y signal is read is (hmy, vmy). And (h, v) shown in FIG.
(Equation 4)
hmy = 2h + 1
vmy = v (3)
Therefore, using equation (2),
[0015]
(Equation 5)
hmy = 2Fx (H, V) +1
vmy = Fy (H, V) (4)
It is expressed as Since the signal is not multiplexed in the v direction and multiplexing processing does not need to be considered, only the h direction will be described below.
[0016]
Assuming that the address for reading the CB signal is (hmb, vmy), if the read address hmy in the expression (4) has the phase of the Y1 signal, the CB signal is an address one smaller than the Y1 signal.
[0017]
(Equation 6)

It is expressed as When the read address hmy in the equation (4) is the phase of the Y2 signal, the data of the CB signal at the sample point of the Y1 signal, that is, the address of the address 3 smaller than the Y2 signal (the address 3 smaller than the calculated hmy). Read the CB signal. Therefore,
[0018]
(Equation 7)

It becomes.
[0019]
Assuming that the address for reading the CR signal is (hmr, vmy), when the read address hmy in the equation (4) has the phase of the Y1 signal, the CR signal is located at an address one greater than the Y1 signal.
[0020]
(Equation 8)

Similarly, when the phase of the Y2 signal is reached, the CR signal of the address smaller than the Y2 signal by 1 is read out.
[0021]
(Equation 9)

It becomes. FIG. 5 shows an example of reading at the Y2 signal phase. CB and CR shown in FIG. 5 calculate the read address with the same (H, V) as Y1, and finally the offset is added. As can be seen from the above, the read address of Y, CB, CR is obtained by calculating the geometric transformation formula Fx, Fy in the coordinate system when Y, CB, CR is not multiplexed, and doubling Fx, that is, 2Fx And the offsets shown in Table 1 are added to the Y, CB, and CR signals. Whether the read address is the phase of the Y1 signal or the phase of the Y2 signal can be determined by the LSB of the integer part of the address generated based on the geometric transformation formula Fx. LSB shown in Table 1 is the LSB of the integer part of the address generated based on the geometric transformation formula Fx.
[0022]
[Table 1]

[0023]
Actually, since the output signal (output video) is also in a multiplexed format, the calculation of the geometric transformation formulas Fx and Fy is performed by using the Y1 signal during the periods of the CB, Y1 and CR signals as shown in FIG. The calculated Fx is held, and during the period of the Y2 signal, the Fx of the Y2 signal is calculated. By doing so, the above-described principle can be applied as it is.
[0024]
Next, the multiplex signal interpolation processing will be described. An example in which four-point interpolation using four neighboring pixel values as shown in FIG. 2 is used will be described. When the decimal part of the horizontal value (h) of the read address is p and the decimal part of the vertical value (v) of the read address is q, the pixel value G to be obtained is
(Equation 10)

It is expressed as The interpolation coefficients p and q are the decimal part of the address generated based on the Fx and Fy. These are the interpolation coefficients of the Y signal. When the interpolation processing of the CB and CR signals is performed, the coefficient p is converted. There is a need. The reason is that the CB and CR signals have samples only every other pixel, and the relationship of the pixels used in the four-point interpolation is different from that of the Y signal. This is shown in FIG. The interpolation coefficient after the conversion is defined as p ′. As can be seen from FIG. 7A, the interpolation coefficients of the CB and CR signals are, for example, when the phase of the read address is the same as that of the Y1 signal (LSB of the h integer part is 0).
[0026]
(Equation 11)
p ′ = p / 2 (9)
It becomes. Also. When the phase is the same as that of the Y2 signal (LSB of the h integer part is 1), the interpolation coefficient p ′ is, as can be seen from FIG.
[0027]
(Equation 12)
p ′ = (1 + p) / 2 (10)
It becomes. Table 2 shows the switching of the interpolation coefficient p '.
[0028]
[Table 2]

[0029]
FIG. 1 shows a first embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a band limiting circuit which limits the band in order to prevent aliasing due to re-sampling during geometric transformation. The band limiting circuit 10 is configured to be able to switch the coefficient in accordance with the multiplex timing of the video signal. That is, it is assumed that the filter operation is performed with different coefficients for each timing (CB, Y1, CR, Y2) of the multiplex signal. Reference numeral 20 denotes a write address generation circuit that generates a so-called linear address in which the horizontal value increases by one for each clock and the vertical value increases by one for each line. Reference numerals 31 to 34 denote memories in which video signals band-limited by the band-limiting circuit 10 are written in accordance with the address from the write address generation circuit 20, and correspond to pixels G1 to G4. A read address generation circuit 40 generates a read address of the memories 31 to 34 based on a geometric conversion formula. Reference numeral 50 denotes a four-point interpolation circuit that performs four-point interpolation on the pixel values read from the memories 31 to 34 by using four neighboring pixel values as shown in FIG.
[0030]
With this configuration, the input video signal is band-limited by the band limiter 10, and the resulting signal has a horizontal value that increases by one for each clock and a vertical value that increases by one for each line. The data is written to the memories 31 to 34 at a so-called linear address. Then, the video data on the memories 31 to 34 is read from the address generated by the read address generation circuit 40 based on the geometric conversion formula. Since the read address value generated by the read address generation circuit 40 includes a decimal number and does not always coincide with the sample point of the input video, four-point interpolation using four neighboring pixel values as shown in FIG. 2 is used. If the decimal part of the horizontal value (h) of the read address is p and the decimal part of the vertical value (v) of the read address is q, the pixel value G to be obtained is
(Equation 13)

It is expressed as
[0032]
FIG. 9 shows a configuration of the read address circuit 40 shown in FIG. In FIG. 9, reference numeral 50 denotes the same part as the four-point interpolation circuit 50 of FIG. An address calculation circuit 901 calculates an address (h, v) when geometrically transforming a non-multiplexed signal. A bit shifter 902 shifts the integer part of the address in the horizontal direction in the address data calculated by the address calculation circuit 901 by one bit to the upper side. The address is doubled by the bit shifter 902 to obtain 2h. Reference numeral 903 denotes an offset circuit, which is configured as shown in FIG. 10, and based on the LSB of the h integer part of the address calculation circuit 901, offsets CB, Y1, CR, and Y2 in accordance with a signal from the timing circuit 904. Is output. Reference numeral 905 denotes an interpolation address circuit for calculating addresses of pixels corresponding to G1, G2, G3, and G4.
[0033]
Next, the operation will be described. An address (h, v) at the time of geometrically converting a non-multiplexed signal is calculated by an address calculation circuit 901, and the address in the h direction of the obtained address data is shifted upward by one bit by a bit shifter 902. Therefore, the address is doubled, and 2h is obtained. Whether the read address is the phase of Y1 or the phase of Y2 is determined by the LSB of the h integer part of the address calculation circuit 901, and the offset is switched based on the determination result. That is, when the LSB of the integer part of h is 0, the switch element 1003 is switched to the selector 1001 side, and the selector 1001 sets the switch elements 1003 to 0, 1, 2 according to the respective multiplex timings of CB, Y1, CR, and Y2. , 1 are selected and output. On the other hand, when the LSB of the h integer part is 1, the switch element 1003 is switched to the selector 1002 side, and -2, 1, and 2 are respectively selected by the selector 1002 in accordance with the respective multiplex timings of CB, Y1, CR, and Y2. 0 and 1 are selected and output. Then, the output of the switched offset circuit 1003 is added, and a multiplexed read address is calculated. The output of the offset circuit 1003 according to the multiplex timing is as shown in Table 1.
[0034]
FIGS. 8B and 8C show outputs of the respective circuits when the enlargement ratio is 1.0 and 2.0. At such a timing, reading and address calculation are performed. In FIG. 8A, at the timing of updating the address, the period of U indicates that the read address value is the same, and the black triangle indicates the timing of updating the address value. 8B and 8C, the output value of the bit shifter is a value obtained by doubling the integer part of the output of the address calculation circuit, and the output value of the interpolation address circuit is the output value of the bit shifter and the output value of the offset circuit. It is the result of addition.
[0035]
The interpolation address circuit 905 calculates the addresses of the pixels corresponding to G2, G3, and G4 from the address of the G1 pixel. Assuming that the read address of the G1 pixel is (hm, vm),
G2 address (hm + α, vm)
G3 address (hm, vm + 1)
G4 address (hm + α, vm + 1)
It becomes. At the timing of Y1, Y2 (luminance signal), α = 2, and at the timing of CB, CR (color signal), α = 4.
[0036]
The operation of the four-point interpolation circuit will be described with reference to FIG. The four-point interpolation circuit 50 calculates the interpolation pixel by the equation (1) using the G1, G2, G3, and G4 pixels and the decimal part (p, q) of the read address. At this time, at the timing of CB, CR (color signal), the interpolation calculation is performed by converting p into p ′ in Table 2 using the LSB of the h integer part of the read address. In other words, when the LSB of the h integer part of the read address is 0, the switch element 1103 is switched to the selector 1101 side, and the selector 1101 sets each of p and b according to the multiplex timing of CB, Y1, CR, and Y2. / 2, p, p / 2, p are selected. On the other hand, when the LSB of the h integer part is 1, the switch element 1103 is switched to the selector 1102 side, and each of (1 + p) / 2 is adjusted by the selector 1102 in accordance with the multiplex timing of CB, Y1, CR, and Y2. , P, (1 + p) / 2, p are selected. Using the interpolation coefficient p ′ and the decimal part q of the vertical value (v) of the read address, the following equation:
[0037]
[Equation 14]
G = G1 (1-p ') (1-q) + G2 * p' (1-q) + G3 (1-p ') q + G4 * p' * q
, The pixel value G is obtained by the weighted addition circuit 1104.
[0038]
In the present embodiment, since the configuration is performed as described above, the geometric conversion processing can be performed without changing the multiplexed signal, and a circuit for dividing the multiplexed signal into each channel becomes unnecessary, and an interpolation circuit is prepared for each channel. You don't have to.
[0039]
In this embodiment, an example in which four memories are used for each of the pixels G1 to G4 has been described. However, one memory is used in common, and reading of each pixel from one memory is performed based on the sampling frequency of the input signal. The same effect can be obtained even if the operation is performed four times as large as.
[0040]
In this embodiment, an example of a multiplexed video signal has been described. However, a non-multiplexed video signal can be subjected to geometric conversion processing.
[0041]
【The invention's effect】
As described above, according to the present invention, with the above-described configuration, (1) the geometric conversion process can be performed without separating the multiplexed component video signals, and (2) the multiplexed component video signals are multiplexed. It has such a feature that no video signal can be processed with the same circuit configuration, and the overall circuit size can be greatly reduced as compared with the conventional one, which is efficient.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is an explanatory diagram for explaining four-point interpolation;
FIG. 3 shows ITU-R BT. FIG. 6 is a diagram illustrating a transmission format of a multiplexed video signal recommended in 656.
FIG. 4 is an explanatory diagram for explaining the principle of geometric transformation using a Y signal as an example.
FIG. 5 is an explanatory diagram for explaining the principle of geometric transformation using a multiplexed signal as an example.
FIG. 6 is an explanatory diagram for explaining an address calculation method.
FIG. 7 is an explanatory diagram for explaining switching of interpolation coefficients in accordance with multiplex timing.
FIG. 8 is an explanatory diagram for describing a read address process.
FIG. 9 is a block diagram showing a configuration of a read address generation circuit 40 shown in FIG.
FIG. 10 is a block diagram showing a configuration of an offset circuit 903 shown in FIG.
11 is a block diagram showing a configuration of a four-point interpolation circuit 50 shown in FIG.
FIG. 12 is a block diagram showing a conventional geometric transformation device.
[Explanation of symbols]
10 Band limiter 20 Write address generator 31 G1 memory 32 G2 memory 33 G3 memory 34 G4 memory 40 Read address generator 50 4-point interpolation circuit 901 Address calculation circuit 902 Bit shifter 903 Offset circuit 904 Timing circuit 905 Interpolation address circuits 1001, 1002 , 1101, 1102 selector 1003, 1103 switch element 1104 weighted addition circuit

Claims (3)

Store means,
Write address generating means for generating a linear write address of the store means;
Writing means for sequentially writing time-division multiplexed digital component video signals to the linear address of the storing means generated by the writing address generating means;
Address generation means for generating an address on the storage means based on a geometric transformation formula;
Interpolating means for two-dimensionally interpolating the pixel value of the address generated by the address generating means,
The address generating means includes:
From the vertical and horizontal components of the output pixel coordinates and the geometric transformation formula, the address of the Y signal of the CB, Y, and CR signals time-division multiplexed in the transmission format defined by ITU-R BT.656 is used. An address calculation circuit for calculating,
A timing circuit that outputs an identification signal indicating which signal type is used at the clock timing based on the horizontal synchronization signal and the clock;
An offset circuit for extracting an addition coefficient determined from the identification signal from the timing circuit and the LSB value of the integer part of the horizontal component of the address of the Y signal calculated by the address calculation circuit from the addition coefficient obtained in advance; ,
A bit shifter for doubling an integer part of a horizontal component of an address of the Y signal calculated by the address calculation circuit;
An output circuit for adding the output of the bit shifter and the output of the offset circuit;
An interpolation address circuit for generating an address of two-dimensional interpolation filter constituting pixel data from an output of the addition circuit, a vertical component of an address of the Y signal calculated by the address calculation circuit, and an identification signal from the timing circuit; An image conversion device comprising: In claim 1, the interpolation means comprises:
Based on the signal type from the timing circuit and the value of the LSB of the integer part of the horizontal component of the address of the Y signal calculated by the address calculation circuit, an interpolation coefficient p ′ is calculated from the value p of the decimal part of the horizontal component. A calculation circuit for calculating,
The two-dimensional interpolation filter constituent pixel data read from the storage means in accordance with the address generated by the interpolation address circuit is calculated from the interpolation coefficient p 'and the value q of the decimal component of the vertical component from the address calculation circuit. An image conversion device comprising: an interpolation filter that performs two-dimensional arithmetic processing based on a selected filter coefficient. In claim 1,
The storing means includes four memories of a G1 memory, a G2 memory, a G3 memory and a G4 memory for writing digital data having the same contents to each other,
The interpolation address circuit,
A circuit for generating an address of the video signal G1 from an output of the adder circuit and a vertical component of the address of the Y signal calculated by the address calculation circuit, and outputting the address to the G1 memory;
A circuit for adding a specific value to the address of the video signal G1 to generate an address of a video signal G3 of the same type vertically adjacent to the video signal G1 and outputting the same to the G3 memory;
A specific value selected based on the identification signal from the timing circuit is added to the address of the video signal G1 to generate an address of a video signal G2 of the same type that is adjacent to the video signal G1 horizontally and rearward. A circuit for outputting to the G2 memory;
A specific value selected based on the identification signal from the timing circuit is added to the address of the video signal G1 to generate an address of a video signal G4 of the same type which is horizontally adjacent to the video signal G3, and A circuit for outputting to a G4 memory,
The interpolation filter is
The data of the video signals G1, G2, G3, and G4, which are output data from the four memories, are input, and the four data are used as constituent pixel data of a two-dimensional interpolation filter. From the value q of the decimal part of the vertical component,
G = G1 (1-p ') (1-q) + G2 * p' (1-q) + G3 (1-p ') q + G4 * p' * q
An image conversion device comprising: a circuit for calculating interpolation data G by a calculation expression represented by:

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