JP3581666B2 - Information processing equipment - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a memory control method for an information processing device such as a personal computer and a workstation.
[0002]
[Prior art]
2. Description of the Related Art In recent years, information processing apparatuses such as personal computers and workstations have been steadily becoming smaller and more sophisticated. The processing power of microprocessors, the core of these information processing devices, is rapidly improving, supported by advances in semiconductor process technology, and products that exhibit high performance at high operating frequencies while maintaining low power consumption have appeared. I've been. With such a rapid increase in processor capacity, a memory that can support the processor is required. Therefore, a synchronous dynamic RAM (hereinafter, referred to as a synchronous DRAM) has appeared as a new memory device that bridges the difference between the processor capability and the memory capability.
[0003]
The synchronous DRAM device performs an operation of reading data from the DRAM every clock period in synchronization with a given driving clock, and has a feature that it can cope with a high-speed operation frequency of a microprocessor. As a current product specification, a synchronous DRAM device that can support a driving clock frequency of 100 MHz (one clock of 10 ns) has been commercialized.
[0004]
As for this type of memory control system, for example, a "memory interface" disclosed in Japanese Patent Publication No. Sho 60-3699 is known.
[0005]
[Problems to be solved by the invention]
When a synchronous DRAM device is applied to a memory system of an information processing device, it is necessary to consider the input / output buffer performance of a memory control LSI and the variation in characteristics of the DRAM element due to a change in an operating environment such as temperature and power supply voltage. . The characteristic variation of the DRAM element due to the change of the operating environment is an obstacle in deriving the high-speed operation performance of the synchronous DRAM, and the driving clock frequency of the current practical memory system is 33 MHz (1 clock 30 ns). ). Therefore, at present, the high-speed read performance of the synchronous DRAM cannot be fully utilized.
[0006]
SUMMARY OF THE INVENTION It is an object of the present invention to provide an information processing apparatus capable of reading data from a synchronous DRAM using a high-frequency driving clock signal regardless of a change in an operating environment.
[0007]
[Means for Solving the Problems]
According to the present invention, in order to solve the above-described problem, a storage unit that outputs data every one clock period in synchronization with an input clock signal,
A control unit that inputs the clock signal to the storage unit and performs at least a process of receiving the data;
A first wiring for passing the clock signal from the control unit to a storage unit;
A second wiring that transfers the data from the storage unit to a control unit;
A third wiring that branches a clock signal sent to the storage unit by the first wiring and returns the branched clock signal to the control unit;
An information processing apparatus is provided inside the control unit, the information processing device including a temporary storage unit that captures and temporarily stores data transferred by the data wiring at the timing of the clock signal pulled back by the third wiring.
[0008]
[Action]
In the present invention, the clock immediately before being passed to the storage unit is pulled back by the third wiring, and data is taken in at the timing of this clock. The data output by the storage unit in synchronization with the drive clock and passed to the control unit, and the pull-back clock pulled back by the third wiring both include a wiring delay and a delay by the internal circuit of the control unit. Have been. These delays fluctuate due to changes in the environment. However, since both the data and the pull-back clock include these delays, the data and the pull-back clock fluctuate in the same tendency due to changes in the environment. . Therefore, it is possible to reduce the variation width of the difference between the two delay times. Therefore, data output in synchronization with the driving clock can be always taken in at the same timing regardless of a change in environment, so that the clock frequency can be increased. This makes it possible to configure an information processing device capable of extracting data at high speed from the storage unit.
[0009]
【Example】
Hereinafter, an information processing apparatus according to an embodiment of the present invention will be described with reference to the drawings.
[0010]
First, the configuration of the information processing apparatus according to the present embodiment will be described with reference to FIGS. 6 and 2A.
[0011]
As shown in FIG. 6, the information processing apparatus 1001 according to the present embodiment includes a CPU 1011, a memory bus control unit 1012, and a main memory 1013. The memory bus control unit 1012 is connected to a bus 1014. In addition, an input / output processing unit 1015, an auxiliary storage device control unit 1016, a drawing display control unit 1017, and a display memory 1023 are connected to the bus 1014. An external keyboard 1018, mouse 1019, and communication device 1024 are connected to the input / output processing unit 1015. Further, the compact disk 1020 and the hard disk 1021 are connected to the auxiliary storage device control unit 1016, and the display 1022 is connected to the drawing display processing unit 1017.
[0012]
As shown in FIG. 2A, the main memory 1013 includes a synchronous DRAM device 102. The memory bus control unit 1012 includes a memory control LSI 101 which is a circuit for controlling data input / output of the synchronous DRAM element 102. In the present embodiment, the memory control LSI 101 is configured by one LSI, but it is not necessarily required to be one LSI, and the memory control LSI 101 is combined with an input / output controller that controls input / output with the CPU 1011. You can also.
[0013]
As shown in FIG. 2A, the memory control LSI 101 includes a clock generation unit 103, an output buffer 104, input buffers 202 and 107, and a latch. The output buffer 104 and the input buffers 202 and 107 are circuits for delaying and outputting a signal for a predetermined time. Although not shown in FIG. 2, in addition, the row address strobe signal (RAS) 2003, column address strobe signal (CAS) 2004, and write enable signal (WE) 2005 of FIG. 7 are generated. And a circuit for transferring data received from the CPU 1011 to the synchronous DRAM 102. The memory control LSI 101 includes at least pins 2011, 2012, and 2013 for inputting and outputting these signals.
[0014]
The synchronous DRAM device 102 is a DRAM device that operates in synchronization with the rising edge of the drive clock signal 112. FIG. 7 shows the timing of reading data from the synchronous DRAM device 102. The synchronous DRAM device 102 generates a row address strobe signal (RAS) 2003, a column address strobe signal (CAS) 2004, and a write enable signal (WE) 2005 at the rising edge of the drive clock signal (CLK) 112. Determine the value. The RAS signal indicates the fetch timing of the row address, and the CAS signal is the signal indicating the fetch timing of the column address. As shown in FIG. 7, synchronous DRAM device 102 continuously outputs data output signal 2006 in synchronization with CLK 112. In a synchronous DRAM device capable of supporting a driving clock signal with a frequency of 100 MHz, the access time from the rising edge of the driving clock signal to the output of new data is 9 ns, and new data can be read every 10 ns. ing.
[0015]
In the present embodiment, the drive clock signal 112 given by the memory control LSI 101 to the synchronous DRAM 102 is returned to the memory control LSI 101 and used as the latch clock signal 114. Therefore, the wiring 2017 is branched from the middle of the wiring 2016 connecting the pin 2011 of the memory control LSI 101 and the clock pin 112 of the synchronous DRAM device 102, and the branched wiring 2017 is again transferred from the pin 2012 of the memory control LSI 101 to the memory control LSI 101. The input is made inside the LSI 101.
[0016]
The operation of the information processing apparatus according to the present embodiment when the CPU 1011 reads data from the main memory 1013 will be described.
[0017]
The CPU 1011 instructs the memory / bus control unit 1012 to read data from the main memory 1013. The memory control LSI 101 in the memory bus control unit 1012 generates the internal clock signal 111 in the clock generation unit 103 in the memory control LSI 101. The internal clock signal 111 is output from the pin 2011 to the outside via the output buffer 104, and is input from the clock pin 2014 as the drive clock (CLK) 112 of the synchronous DRAM device 102 via the wiring 2016. The memory control LSI 101 inputs the RAS 2003 and the CAS 2004 to the synchronous DRAM device 102. Synchronous DRAM element 102 determines RAS 2003 and CAS 2004 starting from the rising edge of drive clock signal 112 and outputs new memory data 115 from data output pin 2015. The memory data 115 is input from the pin 2013 of the memory control LSI 101 via the wiring 2018. Then, the read data 113 is input to the data latch 108 in the memory control LSI 101 via the input buffer 107.
[0018]
In addition, the driving clock signal 112 is pulled back to the data latch 108 by the wiring 2017 branched from the wiring 2016, and is input from the pin 2012 as the pull-back clock 201. The pullback clock 201 is input to the data latch 108 via the input buffer 202 as a latch clock signal 114. The data latch 108 latches the read data 113 at the rising edge timing of the latch clock signal 114. Then, data is transferred to the CPU 1011 at another timing corresponding to the clock of the CPU 1011. Alternatively, it is transferred to the input / output processing unit 1015, the auxiliary storage device control unit 1016, and the drawing display processing unit 1017 via the bus 1014 according to the instruction of the CPU 1011. The transferred data is communicated externally from the communication device 1014, stored on the compact disk 1021 or the like, or displayed on the display 1022, for example.
[0019]
As described above, in the present embodiment, the drive clock signal 112 supplied to the synchronous DRAM 102 is returned to the memory control LSI 101 and used as the latch clock signal 114. The difference between the delay from the drive clock of the read data 113 and the delay from the drive clock of the latch clock signal 114 is the difference between the wiring delays 106 and 203 and the difference between the delays 202 and 207 of the input buffer. However, since these delays both change with the same tendency with respect to changes in the operating environment such as the ambient temperature, the change in the difference between the delay of the read data 113 and the delay of the latch clock signal 114 due to the operating environment is very small. Become. Therefore, as shown in FIG. 2B, the relationship between the read data 113 and the latch clock signal 114 is kept substantially constant at the maximum and minimum values of the drive clock delay. In order to always latch data at the same timing, the clock cycle needs to be larger than the difference between the delay of the read data 113 and the delay of the latch clock signal 114. In the configuration of this embodiment, this difference is Since it is very small, it can be made smaller than the minimum period that the synchronous DRAM device 102 can support. Accordingly, the drive clock signal 112 can be set to the maximum clock frequency that can be supported by the synchronous DRAM device, and it is possible to realize a page cycle of 1 address / 1 clock that maximizes the function of the synchronous DRAM device. Become.
[0020]
Another embodiment of the present invention will be described with reference to FIG. FIG. 3 shows another embodiment of the memory control LSI in the embodiment of FIG.
[0021]
The memory control LSI 2101 in FIG. 3 includes a clock generation unit 103, a system sequencer 301, a memory read sequencer 302, a read data path 303, a burst data buffer 304, and a selector 305.
[0022]
The clock generation unit 103 receives a signal input from the CPU via the pin 2246 and the input buffer 2248, and generates a reference clock 2118. The reference clock 2118 is output from the pin 2131 via the output buffer 2106, and is input to the synchronous DRAM element 102 as the drive clock 2115 via the wiring 2115. The reference clock 2118 is input to the system sequencer 301 via the clock buffer 2136. The system sequencer 301 generates the CAS 2119. The CAS 2119 is output from the pin 2132 via the output buffer 2107, and is input to the synchronous DRAM device 102 via the wiring 2242. The synchronous DRAM device 102 outputs data 2117 in synchronization with the drive clock 2115. In this embodiment, four data D0, D1, D2, and D3 are output. The data 2117 passes through a wiring 2245, a pin 2135, an input buffer 2111, undergoes an error check or the like in a read data path 303, and is input as input data 2112 to a burst data buffer 304.
[0023]
On the other hand, the drive clock 2115 is pulled back to the memory read sequencer 302 via the input buffer 2108 by the pin 2133 and the wiring 2243. In addition, the CAS 2116 is pulled back through the input buffer 2109 by the wiring 2244 and the pin 2134. The memory read sequencer 302 determines the retrieved CAS input 2113 based on the retrieved clock 2114 and outputs the signal 114 every clock after two clocks of the CAS input 2113 have elapsed. According to the timing of the signal 114, the data D0, D1, D2, and D3 are stored in four buffers 2102, 2103, 2104, and 2105 of the burst data buffer 304 provided for the length of the continuous access.
[0024]
At the timing of the reference clock 2118, the system sequencer 301 outputs a signal every clock after five clocks of the CAS 2119 have elapsed. In response to this signal, the selector 305 switches and sequentially outputs the data of the buffers 2102 to 2105. The data 2120 is output from the pin 2247 via the output buffer 2249.
[0025]
In this embodiment, by providing two terminals, the pin 2133 and the pin 2134, in the memory control LSI, the fetch timing of the burst data buffer 304 can be determined based on the recovered clock 2114. The delay 2301 of the recovered clock 2114 from the drive clock 2115 and the delay of the read data input to the read data path from the drive clock 2115 are both delays caused by the wiring and the input buffer. Therefore, even if the delay 2302 of the drive clock 2118 from the reference clock 2118 greatly fluctuates due to fluctuations in the operating environment such as ambient temperature, both of the above-mentioned two delays are affected by fluctuations in the operating environment such as ambient temperature. Change in the same tendency. Therefore, the change in the difference between the two delays due to the change in the operating environment is very small. Thus, even if the cycle of the drive clock is reduced, data can always be stored in the buffer at the same timing. Therefore, the frequency of the drive clock can be set to the maximum frequency that the synchronous DRAM device can support, and high-speed reading can be performed.
[0026]
Another embodiment of the present invention will be described with reference to FIG.
[0027]
The difference between the embodiment of FIG. 5 and the embodiment shown in FIG. 3 is that, in the memory control LSI 101, the drive clock and CAS are not transmitted from the outside of the memory control LSI 101 but from the memory control LSI 101 via the bidirectional buffers 501 and 502. This means that the data is returned to the memory read sequencer 302 immediately before the output.
[0028]
In the configuration of FIG. 5, the clock returned to the memory read sequencer 302 and the CAS returned include the delay of the input / output buffers 501 and 502. Accordingly, the difference in delay from the memory data is small, and the frequency of the drive clock can be increased as in the embodiment of FIG. However, unlike the embodiment of FIG. 3, in the embodiment of FIG. 5, the recovered clock and the recovered CAS do not include the wiring delay between the memory control LSI 101 and the synchronous DRAM device 102. It is necessary to set the maximum frequency of the drive clock lower than in the third embodiment. On the other hand, the embodiment of FIG. 5 has the advantage that the pins 2133 and 2134 of the memory control LSI 101 of FIG. 3 are unnecessary, and the number of pins of the memory control LSI 101 can be reduced.
[0029]
Next, a comparative example for comparison with the above-described embodiment will be described with reference to FIG.
[0030]
FIG. 1 is a diagram showing an example of a memory system when the same control is performed on a synchronous DRAM as that of a general non-synchronous DRAM. In the memory system shown in FIG. 1A, the internal clock signal 111 generated by the clock generation unit 103 in the memory control LSI 101 is output from the pin 3001 to the outside via the output buffer 104, and the driving clock of the synchronous DRAM 102 The signal 112 is connected to the pin 3002. The synchronous DRAM 102 outputs new data starting from the rising edge of the drive clock signal 112. The memory data 115 is output from a pin 3003 of the synchronous DRAM 102, is connected to a pin 3004 of the memory control LSI 101, and is connected as a read data 113 to the data latch 108 in the memory control LSI 101 via the input buffer 107. The data latch 108 latches the read data 113 at the rising edge timing of the latch clock signal 114, which is the internal clock signal 111 passed through the clock buffer 109.
[0031]
Here, the drive clock signal 112 has a delay due to the output buffer 104 and the wiring load 105 on the board with respect to the internal clock signal 111, and the read data 113 has the memory data 115 output with respect to the output on the board A delay due to the wiring load 106 and the input buffer 107 is added. The latch clock signal 114 is delayed from the internal clock signal 111 by the clock buffer 109.
[0032]
The delay of the drive clock signal 112 (delay caused by the output buffer 104 and the wiring load 105) and the delay of the read data 113 (delay caused by the wiring load 106 and the input buffer 107) starting from the internal clock signal 111 are added to the delay of the synchronous DRAM 102. The value obtained by adding the access time (9 ns for a 100 MHz product) is empirically about 30 ns (typical value). In the memory system of FIG. 1, the delay value of the latch clock signal 114 starting from the internal clock signal 111 is adjusted in advance according to the delay value so that the read data 113 can be latched at the maximum and minimum delays. Needed. The adjustment of the delay value of the latch clock signal 114 has been performed by adjusting the delay value of the clock buffer 109.
[0033]
However, as shown in FIG. 1B, when the difference between the maximum value and the minimum value of the delay of the read data 113 starting from the internal clock signal 111 exceeds one clock period of the drive clock signal 112 given to the synchronous DRAM 102. Since the synchronous DRAM 102 outputs one data only for one clock period of the drive clock signal 112, it is impossible to design to take in data every clock. For example, even if the synchronous DRAM 102 of 100 MHz (access time 9 ns) is used, when the typical value of the delay is about 30 ns, the difference between the maximum value and the minimum value is empirically about 30 ns. Cannot be made shorter than 30 ns.
[0034]
As described above, when an actual memory system is configured by the control method of FIG. 1 as a comparative example, the difference between the maximum value and the minimum value of the delay of the drive clock signal 112 limits the operating frequency of the entire memory system. However, the high speed of the synchronous DRAM 102 cannot be utilized.
[0035]
On the other hand, in the information processing apparatus of the embodiment shown in FIGS. 2, 3 and 5 of the present invention, the clock used for the latch and the data to be latched regardless of the difference between the maximum value and the minimum value of the delay of the drive clock. And the delay difference is always small, so that the frequency of the drive clock can be increased.
[0036]
In the above-described embodiment, a synchronous DRAM is used as the main memory 1013 of the information processing apparatus in FIG. 6, and the memory control LSI of the memory / bus control unit 1012 for controlling the DRAM is configured as shown in FIGS. 2, 3, and 5. However, the configurations shown in FIGS. 2, 3, and 5 are applicable to any case where a synchronous DRAM is adopted. For example, when a synchronous DRAM device is used for the display memory 1023 in FIG. In order to absorb a difference in data transfer speed between the bus 1014 and the communication device 1024 or between the bus 1014 and an auxiliary storage device such as the hard disk 1021 and the compact disk 1020, the auxiliary storage device control unit 1016 and the The memory control method of the present invention is also applicable to a case where the input / output control unit 1015 has a buffer memory employing a synchronous DRAM.
[0037]
【The invention's effect】
Since the present invention is configured as described above, the relationship between the data and the latch clock can be kept substantially constant regardless of the magnitude of the delay of the drive clock of the synchronous DRAM, and the high speed of the synchronous DRAM can be maintained. Thus, it is possible to realize a page cycle of 1 address / 1 clock utilizing the characteristics.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a memory system of a comparative example, and FIG. 1B is a timing chart.
2A and 2B are a block diagram and a timing chart, respectively, showing a configuration of a portion for performing memory control of the information processing apparatus according to the embodiment of the present invention;
FIG. 3 is a block diagram illustrating a configuration of a portion that performs memory control of an information processing apparatus according to another embodiment of the present invention.
FIG. 4 is a timing chart showing the operation of the embodiment of FIG.
FIG. 5 is a block diagram showing a configuration of a portion that performs memory control of an information processing apparatus according to yet another embodiment of the present invention.
FIG. 6 is a block diagram showing the overall configuration of an information processing apparatus according to one embodiment of the present invention.
FIG. 7 is a timing chart showing the timing at the time of reading data from the synchronous DRAM of the information processing apparatus according to one embodiment of the present invention.
[Explanation of symbols]
101: Memory control LSI, 102: Synchronous DRAM, 103: Clock generator, 104: Output buffer, 105: Wiring load, 106: Wiring load, 107: Input buffer, 108: Data latch, 109: Clock buffer, 111 ... Internal clock, 112: drive clock, 113: read data, 114: latch clock, 115: memory data, 201: pullback clock, 202: input buffer, 203: wiring load, 301: system sequencer, 302: memory read sequencer, 303 .., Read data path, 304, burst data buffer, 305 selector, 501, bidirectional buffer, 502, bidirectional buffer, 1001, information processing device, 1011, CPU, 1012, memory bus control unit, 1013, main memory, 1014 … Ba Reference numeral 1015: Input / output control unit, 1016: Auxiliary storage device control unit, 1017: Drawing display control unit, 1018: Keyboard, 1019: Mouse, 1020: Compact disk, 1021: Hard disk, 1022: Display, 1023: Display memory, 1024 …Communication device

Claims (5)

An information processing apparatus capable of mounting a memory that outputs data in synchronization with a clock signal,
Having a memory control device for controlling the memory,
The memory control device,
A clock output terminal for outputting a clock signal to be supplied to the memory,
A data input terminal for inputting data output by the memory,
A data buffer for latching data input from the data input terminal in synchronization with a clock signal,
A first bidirectional buffer for supplying a clock signal to the clock output terminal and the data buffer;
A CAS output terminal for outputting a CAS signal to be supplied to the memory;
A second bidirectional buffer for supplying a CAS signal to the CAS output terminal and the data buffer ;
The data buffer latches data input from the data input terminal in synchronization with a clock signal according to a CAS signal,
The first bidirectional buffer comprises:
A first buffer for supplying a clock signal to the clock output terminal;
A second buffer that supplies a clock signal output from the first buffer and input to the clock output terminal to the data buffer,
The second bidirectional buffer comprises:
A third buffer for supplying a CAS signal to the CAS output terminal;
An information processing apparatus, comprising: a fourth buffer that supplies a CAS signal output from the third buffer and input to the CAS output terminal to the data buffer. The information processing device according to claim 1 ,
The data buffer includes a plurality of data storage units, and sequentially stores data sequentially input from the data input terminal into each of the plurality of data storage units in synchronization with a clock signal according to a CAS signal. Characteristic information processing device. The information processing device according to claim 1 or 2 ,
The information processing apparatus according to claim 1, wherein the memory control device further includes a CAS signal generation unit that generates a CAS signal synchronized with a clock signal and supplies the CAS signal to the second bidirectional buffer. The information processing apparatus according to claim 3 , wherein
The information processing apparatus according to claim 1, wherein the memory control device further includes a clock generation unit that generates a clock signal and supplies the clock signal to the first bidirectional buffer and the CAS signal generation unit. The information processing apparatus according to claim 1 , wherein:
The memory control device is provided in a rendering display processing unit,
The information processing apparatus, wherein the memory is a display memory used by the drawing display processing unit.

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