JP5418291B2 - Memory controller and information processing apparatus - Google Patents

Description

  The present application relates to a memory controller that performs data transfer with a memory outside a chip, and an information processing apparatus.

  There is a memory controller that performs data transfer with an external memory such as an SDRAM (Synchronous Dynamic Random Access Memory) that outputs data in synchronization with an input clock signal. The memory controller supplies a clock signal to a memory outside the chip and receives data. With respect to such a memory controller, a configuration is known in which data from a memory is captured using a feedback clock signal obtained by pulling back a clock signal input to the memory.

JP 2001-290698 A

  In the memory controller, read data read from the memory is transferred to an internal clock signal used in the memory controller so that the internal logic circuit can process the read data. Here, since the feedback clock signal used for reading the read data has a delay with respect to the internal clock signal, it is asynchronous with the internal clock signal. For this reason, data transfer from a feedback clock signal to an internal clock signal is realized by temporarily holding read data using a FIFO (First In, First Out) memory.

  An example is shown in FIG. The memory controller 100 controls data input / output between a memory outside the chip and an internal logic circuit. An internal clock signal ACLK generated by a clock generation unit (not shown) and used inside the memory controller 100 is supplied to the memory and pulled back to the memory controller 100 as a feedback clock signal FBCLK. Since the feedback clock signal FBCLK passes through the outside of the chip, it has a delay 112 with respect to the internal clock signal ACLK. The counter start signal generation circuit 101 outputs a counter start signal PSP in synchronization with the internal clock signal ACLK. The counter start signal PSP is input to the three-stage register 106. The counter start signal PSP is fed back to the memory controller 100 as the feedback counter start signal FBPSP via the outside of the chip in the same manner as the feedback clock signal FBCLK. Therefore, the delay 111 of the feedback counter start signal FBPSP with respect to the counter start signal PSP has a correlation with the delay 112 of the feedback clock signal FBCLK with respect to the internal clock signal ACLK.

  The counter circuit 107 is a free-run counter that is enabled by a feedback counter start signal FBPSP and performs a count operation in synchronization with the feedback clock signal FBCLK. The three-stage register 106 to which the counter start signal PSP is input is, for example, three flip-flops that latch data in synchronization with the internal clock signal ACLK. The counter circuit 108 is a free-run counter that is enabled by a counter start signal PSP input via a three-stage register 106 and performs a count operation in synchronization with the internal clock signal ACLK.

  Register group 104 includes three flip-flops FF0, FF1, and FF2, and stores read data MRD read from the memory in synchronization with feedback clock signal FBCLK. The selector 103 in the previous stage of the register group 104 designates the storage position of the read data MRD from among the flip-flops FF0, FF1, and FF2 included in the register group 104 according to the count value of the counter circuit 107. Further, when the selector 105 in the subsequent stage of the register group 104 takes out the read data MRD from the register group 104, the take-out position of the read data MRD is set to the flip-flops FF0, FF1, and FF2 according to the count value of the counter circuit 108. Specify from among. That is, the configuration including the counter circuit 107, the selector 103, the register group 104, the counter circuit 108, and the selector 105 functions as a FIFO memory having the counter circuit 107 and the selector 103 as a write pointer and the counter circuit 108 and the selector 105 as a read pointer. To do.

  The data capture control circuit 102 outputs a read enable signal RDEN using the internal clock signal ACLK as an operation clock. The read data MRD extracted from the register group 104 via the selector 105 is input to the AND gate 109 together with the read enable signal RDEN. The flip-flop 110 latches the output of the AND gate 109 in synchronization with the internal clock signal ACLK. The output of the flip-flop 110 is processed by the internal logic circuit as the read data output QRD.

  The operation of the conventional example having the above configuration will be described with reference to FIG. FIG. 2 is an example of a timing chart when the cycle of the internal clock signal ACLK is 7.4 ns and the delay 112 of the feedback clock signal FBCLK with respect to the internal clock signal ACLK is about 4.6 ns. In FIG. 2, RP is the number of the flip-flop designated by the counter circuit 108 and the selector 105 among the flip-flops FF0, FF1, and FF2 of the register group 104, that is, the value of the read pointer. Similarly, WP is the number of the flip-flop designated by the counter circuit 107 and the selector 103 among the flip-flops FF0, FF1, and FF2 included in the register group 104, that is, the value of the write pointer.

  When the counter start signal PSP is output from the counter start signal generation circuit 101, the counter circuit 108 is enabled via the three-stage register 106. As a result, the read pointer value RP starts to change after a certain cycle (here, 3 cycles) starting from the counter start signal PSP. In addition, as described above, the delay 111 of the feedback counter start signal FBPSP with respect to the counter start signal PSP has a correlation with the delay 112 of the feedback clock signal FBCLK with respect to the internal clock signal ACLK. Therefore, the feedback counter start signal FBPSP is delayed from the counter start signal PSP in the same manner as the feedback clock signal FBCLK is delayed from the internal clock signal ACLK. When the feedback counter start signal FBPSP is taken into the counter circuit 107 at the rising edge of the feedback clock signal FBCLK, the value WP of the write pointer starts to change.

  Based on a read command (a) issued from the internal logic circuit, Da1, Da2, Da3, Da4 are read from the memory as read data MRD, and a read enable signal RDEN is output from the data fetch control circuit 102 at a predetermined timing. Is done. In synchronization with the feedback clock signal FBCLK, the read data MRD is taken into the register group 104 according to the value WP of the write pointer. Thereby, the data Da1 is stored in the flip-flop FF2, the data Da2 is stored in the flip-flop FF0, the data Da3 is stored in the flip-flop FF1, and the data Da4 is stored in the flip-flop FF2.

  While the read enable signal RDEN is being output, the read data MRD extracted from the register group 104 according to the read pointer value RP is latched by the flip-flop 110 in synchronization with the internal clock signal ACLK. As a result, the data Da1, Da2, Da3, and Da4 become the read data output QRD synchronized with the internal clock signal ACLK. In this way, the transfer of the read data MRD to the internal clock signal ACLK is started after four cycles from the issue of the read command (a), and the operation is continued in the same manner thereafter.

  When data transfer from the feedback clock signal FBCLK to the internal clock signal ACLK is performed using a FIFO memory, it is necessary to know the value of the delay 112 outside the chip to some extent in order to determine the operation timing of the write pointer with respect to the read pointer. Become. On the other hand, in the conventional example shown in FIG. 1, the counter start signal PSP is taken in as the feedback counter start signal FBPSP via the outside of the chip in the same manner as the feedback clock signal FBCLK. Thereby, the value of the delay 112 is estimated from the delay 111 correlated with the delay 112, and the temporal relationship between the read pointer and the write pointer is determined. Therefore, there is an advantage that the development can proceed even when the delay outside the chip cannot be grasped at the design stage.

  However, the conventional example shown in FIG. 1 requires a terminal for outputting the counter start signal PSP to the outside and a terminal for feeding back the feedback counter start signal FBPSP to the inside, resulting in an increase in the number of terminals. For this reason, it may not be possible to employ a chip with a limited number of terminals.

  An object of the present application is to provide a memory controller and an information processing apparatus that can reliably transfer data without adding a terminal.

  A memory controller disclosed in the present application is a memory controller that supplies an internal clock signal to an external memory and performs data transfer with the memory, and read data read from the memory is input to the memory. A register group that stores the internal clock signal in synchronization with a feedback clock signal that is fed back, and a storage location of the read data is specified in synchronization with the feedback clock signal when the read data is taken into the register group And a read pointer that designates the read data extraction position in synchronization with the internal clock signal when the read data is extracted from the register group, and is supplied to the memory Masking a part of the internal clock signal to the read pointer Adjusting the operation timing of the site pointers.

  According to the disclosed memory controller and information processing apparatus, it is possible to reliably transfer data without adding a terminal.

It is a circuit block diagram which shows a prior art example. It is a timing chart which shows operation | movement of a prior art example. It is a circuit block diagram of a 1st embodiment. It is a circuit block diagram which shows the specific example of a counter start signal & mask signal generation circuit. It is a state transition diagram which shows operation | movement of a control state machine. It is a timing chart which shows operation | movement of 1st Embodiment. It is a circuit block diagram of a 2nd embodiment. It is a timing chart which shows operation | movement of a counter start signal & mask signal generation circuit. It is a state transition diagram which shows operation | movement of an external clock observation module. It is a timing chart which shows operation of a 2nd embodiment.

  FIG. 3 is a circuit block diagram of the first embodiment. FIG. 3 mainly shows a part related to the read control of the memory controller 200A, and a part thereof is omitted in view of easy viewing. An internal clock signal ACLK generated by a clock generation unit (not shown) is supplied as an operation clock to each unit in the memory controller 200A. The command buffer 201 is a buffer that receives a command from the logic side, and receives a control signal from the internal logic circuit. The address buffer 202 is a buffer that receives an address from the logic side, and receives an address ADD from the internal logic circuit. The memory control module 203 generates command information for the memory based on the information in the command buffer 201 and the address buffer 202. The memory control module 203 issues a start signal START immediately after the operation of the memory controller 200A starts to start the operation of the transfer FIFO 208, and issues an original signal RE_SOURCE during a read operation to fetch data from the transfer FIFO 208. Control to do. The memory command generation circuit 204 outputs a memory control signal and a memory address MADD, and transmits command information of the memory control module 203 to the memory.

  The mode setting register 205 is a register for setting the issuance timing of the counter start signal PSP, the read enable signal RDEN, and the mask signal CLKMASK based on the mode setting information MODE. The counter start signal & mask signal generation circuit 206 generates the counter start signal PSP and the mask signal CLKMASK at a timing set based on the value of the mode setting register 205 in accordance with the start signal START issued from the memory control module 203. Issue. The data fetch control circuit 207 adds a delay based on the value of the mode setting register 205 to the original signal RE_SOURCE issued from the memory control module 203, and generates a read enable signal RDEN.

  In the transfer FIFO 208, the counter start signal PSP is input to the enable terminal of the counter circuit 210 and also input to the enable terminal of the counter circuit 212 via the three-stage register 209. The three-stage register 209 is, for example, three flip-flops that latch data in synchronization with the internal clock signal ACLK, similarly to the three-stage register 106 in the conventional example of FIG. The counter circuit 210 is a free-run counter that is enabled by the counter start signal PSP and performs a count operation in synchronization with the feedback clock signal FBCLK. The counter circuit 212 is a free-run counter that is enabled by a counter start signal PSP input via a three-stage register 209 and performs a count operation in synchronization with the internal clock signal ACLK. The external data synchronization register group 211 includes, for example, three flip-flops similarly to the register group 104 in the conventional example of FIG. 1, and stores read data MRD read from the memory in synchronization with the feedback clock signal FBCLK. To do.

  Although not shown in FIG. 3, the transfer FIFO 208 has selectors at the front and rear stages of the register group 211, respectively. The preceding selector designates the storage location of the read data MRD from among the flip-flops of the register group 211 according to the count value of the counter circuit 210. Further, when the read selector MDR takes out the read data MRD from the register group 211, it designates the read data MRD take-out position from the flip-flops of the register group 211 according to the count value of the counter circuit 212. That is, the transfer FIFO 208 functions as a FIFO memory in which the count value of the counter circuit 210 is a write pointer value and the count value of the counter circuit 212 is a read pointer value.

  The read data buffer 213 is enabled by the read enable signal RDEN, synchronizes the read data MRD acquired from the transfer FIFO 208 with the internal clock signal ACLK, and transfers it to the internal logic circuit as the read data output RDATA. The read data buffer 213 can be realized by, for example, a configuration including the AND gate 109 and the flip-flop 110 in the conventional example of FIG.

  An internal clock signal ACLK used inside the memory controller 200A is supplied to the memory via the AND gate 214 and is pulled back to the memory controller 200A as a feedback clock signal FBCLK. Since the feedback clock signal FBCLK passes through the outside of the chip, it has a delay 215 with respect to the internal clock signal ACLK. Since internal clock signal ACLK is input to AND gate 214 together with mask signal CLKMASK, it is masked according to the L level output of mask signal CLKMASK and fed back as feedback clock signal FBCLK.

  FIG. 4 is a circuit block diagram showing a specific example of the counter start signal & mask signal generation circuit 206. The start signal START issued from the memory control module 203 (see FIG. 3) is input to the flip-flop 12 via the AND gate 11 whose one input is fixed to the H level. The flip-flop 12 latches the start signal START input via the AND gate 11 in synchronization with the internal clock signal ACLK, and outputs a counter start enable signal PSP_EN. The control state machine 13 receives the counter start enable signal PSP_EN, the value DL of the mode setting register 205 (see FIG. 3), and the internal clock signal ACLK, and outputs the counter start signal PSP and the mask enable signal CLKMSK_EN. The AND gate 15 outputs a logical product signal of the mask enable signal CLKMSK_EN and the counter start enable signal PSP_EN inverted by the inverter 14 as the mask signal CLKMASK.

  FIG. 5 is a state transition diagram showing the operation of the control state machine 13, which is a specific example described in a hardware description language. In the RESET state, a value obtained by adding 1 to the value DL of the mode setting register 205 is given as a predetermined value DL_NUM.

  In the STANDBY state, “000” is substituted into the 3-bit register MASK_CNT. “0” is assigned to the 1-bit register corresponding to the counter start signal PSP. “1” is assigned to a 1-bit register corresponding to the mask enable signal CLKMSK_EN. When the start signal START is issued and the value of the 1-bit register corresponding to the counter start enable signal PSP_EN becomes “1”, the control state machine 13 shifts to the MASK state.

  In the MASK state, the value of the 3-bit register MASK_CNT is added bit by bit. “0” is assigned to the 1-bit register corresponding to the counter start signal PSP. “0” is assigned to a 1-bit register corresponding to the mask enable signal CLKMSK_EN. When the value of the 3-bit register MASK_CNT added bit by bit reaches a predetermined value DL_NUM, the control state machine 13 transits to the FINAL state through the LASTMASK state.

  In the LASTMASK state, the value of the 3-bit register MASK_CNT is held. “1” is assigned to a 1-bit register corresponding to the counter start signal PSP. “0” is assigned to a 1-bit register corresponding to the mask enable signal CLKMSK_EN.

  In the final state, the value of the 3-bit register MASK_CNT is held. “1” is assigned to a 1-bit register corresponding to the counter start signal PSP. “1” is assigned to a 1-bit register corresponding to the mask enable signal CLKMSK_EN.

  The operation of the first embodiment having the above configuration will be described with reference to FIG. FIG. 6 is an example of a timing chart when the cycle of the internal clock signal ACLK is 7.4 ns and the delay 215 of the feedback clock signal FBCLK with respect to the internal clock signal ACLK is 3.7 ns. In FIG. 6, RP and WP indicate the read pointer value and the write pointer value, respectively, as in FIG.

  In the STANDBY state, the counter start signal PSP is at L level, so the transfer FIFO 208 waits for operation. Further, since the mask signal CLKMASK is at the H level, the internal clock signal ACLK is fed back as the feedback clock signal FBCLK without being masked.

  When the start signal START issued from the memory control module 203 immediately after the operation of the memory controller 200A starts is taken into the flip-flop 12 (see FIG. 4) in synchronization with the internal clock signal ACLK, the counter start enable signal PSP_EN is output. . When the value of the 1-bit register corresponding to the counter start enable signal PSP_EN becomes “1”, the control state machine 13 shifts to the MASK state as described above (see FIG. 5).

  In the MASK state, the counter start signal PSP is at L level, so the transfer FIFO 208 continues to wait for operation. Since mask signal CLKMASK is at L level, internal clock signal ACLK is masked and fed back as feedback clock signal FBCLK. When the value of the 3-bit register MASK_CNT added one bit at a time reaches the predetermined value DL_NUM, the control state machine 13 transitions to the LASTMASK state as described above (see FIG. 5).

  In the LASTMASK state, the counter start signal PSP becomes H level, so that the counter circuit 210 is enabled in the transfer FIFO 208 and the counter circuit 212 is also enabled via the three-stage register 209. Since mask signal CLKMASK is at L level, internal clock signal ACLK is masked and fed back as feedback clock signal FBCLK. In the final state, the counter start signal PSP is at the H level, so that the transfer FIFO 208 continues to operate. Further, since the mask signal CLKMASK is at the H level, the internal clock signal ACLK is fed back as the feedback clock signal FBCLK without being masked.

  Therefore, the write pointer value WP, which is the count value of the counter circuit 210, starts to change as the mask period of the internal clock signal ACLK fed back as the feedback clock signal FBCLK ends. Also, the read pointer value RP, which is the count value of the counter circuit 212, starts to change after a certain cycle (here, 3 cycles) after the counter start signal PSP becomes H level.

  As described above, in the first embodiment, the counter start signal & mask signal generation circuit 206 provides a sufficiently long mask period for the internal clock signal ACLK supplied to the memory, and issues the counter start signal PSP during the mask period. . As a result, the asynchronousness between the internal clock signal ACLK and the feedback clock signal FBCLK can be absorbed, and the operation timing of the write pointer with respect to the read pointer can be adjusted in the transfer FIFO 208. Further, since the mask period and the issuance timing of the counter start signal PSP can be changed according to the value of the mode setting register 205, the adjustment can be performed according to the delay 215 of the feedback clock signal FBCLK with respect to the internal clock signal ACLK.

  FIG. 7 is a circuit block diagram of the second embodiment. In the second embodiment, portions corresponding to those in the first embodiment are denoted by the same reference numerals, description thereof is omitted, and differences from the first embodiment will be mainly described. The memory controller 200B includes an external clock observation module 216. The external clock observation module 216 observes the feedback clock signal FBCLK using the quadruple clock signal X4ACLK having a frequency four times that of the internal clock signal ACLK as an operation clock, and outputs a write pointer enable signal WP_EN. The counter circuit 210 is enabled by a write pointer enable signal WP_EN.

  FIG. 8 is an example of a timing chart showing the operation of the counter start signal & mask signal generation circuit 206 in the second embodiment. The basic configuration of the counter start signal & mask signal generation circuit 206 is the same as that in the first embodiment. As shown in FIG. 8, in the second embodiment, the counter start signal & mask signal generation circuit 206 always sets the mask period of the internal clock signal ACLK to one cycle.

  FIG. 9 is a state transition diagram showing the operation of the external clock observation module 216, which is a specific example described in a hardware description language. As described above, the external clock observation module 216 uses the quadruple clock signal X4ACLK as an operation clock. When returning from the RESET state, the external clock observation module 216 shifts to the FBCHECK1 state in synchronization with the quadruple clock signal X4ACLK. Then, the external clock observation module 216 proceeds in order of FBCHECK 1 → FBCHECK 2 → FBCHECK 3 → FBCHECK 4 unless the value of the 1-bit register corresponding to the feedback clock signal FBCLK becomes “1”.

  Even in the FBCHECK4 state, when the value of the 1-bit register corresponding to the feedback clock signal FBCLK does not become “1”, the external clock observation module 216 shifts to the WP_EN_ACT state. In the WP_EN_ACT state, the external clock observation module 216 outputs a write pointer enable signal WP_EN. In this way, the external clock observation module 216 outputs the write pointer enable signal WP_EN when the feedback clock signal FBCLK does not become H level for four cycles of the quadruple clock signal X4ACLK.

  The operation of the second embodiment having the above configuration will be described with reference to FIG. When the internal clock signal ACLK is masked for one cycle by the counter start signal & mask signal generation circuit 206, the mask information is transmitted to the feedback clock signal FBCLK, and the feedback clock signal FBCLK is missing for one cycle. Since the feedback clock signal FBCLK does not become H level for 4 cycles of the quadruple clock signal X4ACLK, the external clock observation module 216 outputs the write pointer enable signal WP_EN as described above. As a result, the counter circuit 210 is enabled and the value WP of the write pointer starts to change in synchronization with the feedback clock signal FBCLK.

  Thus, in the second embodiment, the counter start signal & mask signal generation circuit 206 masks the internal clock signal ACLK supplied to the memory for one cycle. The external clock observation module 216 observes the feedback clock signal FBCLK using the quadruple clock signal X4ACLK as an operation clock, and outputs a write pointer enable signal WP_EN when mask information is detected. Thereby, also in the second embodiment, the asynchronousness between the internal clock signal ACLK and the feedback clock signal FBCLK can be absorbed, and the operation timing of the write pointer with respect to the read pointer can be adjusted in the transfer FIFO 208. Further, since the issuance timing of the counter start signal PSP can be changed according to the value of the mode setting register 205, adjustment according to the delay 215 of the feedback clock signal FBCLK with respect to the internal clock signal ACLK can be performed. Further, the external clock observation module 216 can reliably detect the mask information by using the quadruple clock signal X4ACLK.

  As described above in detail, according to the first and second embodiments, the internal clock signal ACLK supplied to the memory is masked so that the internal clock signal ACLK and the feedback clock signal FBCLK are asynchronous. Can be absorbed and stable data can be captured. According to the first and second embodiments, it is possible to reliably transfer data without adding a terminal.

  Needless to say, the present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the spirit of the present invention.

  For example, in the second embodiment, the case where the external clock observation module 216 uses the quadruple clock signal X4ACLK has been described, but the present invention is not limited to this. The external clock observation module 216 may use a high-speed clock signal multiplied by 4 or more.

  In the above embodiment, the register group 211 of the transfer FIFO 208 includes, for example, three flip-flops. However, it is needless to say that the present invention is not limited to this.

  The present invention can also be realized as an information processing apparatus including the memory controller and the memory described above.

  The internal clock signal ACLK and the feedback clock signal FBCLK are examples of the internal clock signal and the feedback clock signal, respectively. The register group 211 is an example of a register group. The counter circuit 210 and the selector are examples of a write pointer. The counter circuit 212 and the selector are examples of read pointers. The transfer FIFO 208 is an example of a FIFO memory. The counter start signal PSP is an example of a start signal. The quadruple clock signal X4ACLK is an example of a high-speed clock signal. The external clock observation module 216 is an example of an observation module.

200A, 200B Memory controller 205 Mode setting register 206 Counter start signal & mask signal generation circuit 207 Data capture control circuit 208 Transfer FIFO
210, 212 Counter circuit 211 Register group 213 Read data buffer 216 External clock observation module ACLK Internal clock signal FBCLK Feedback clock signal MRD Read data PSP Counter start signal X4ACLK Quadruple clock signal

Claims (6)

A memory controller for supplying an internal clock signal to an external memory and performing data transfer with the memory;
A group of registers for storing read data read from the memory in synchronization with a feedback clock signal obtained by feeding back the internal clock signal input to the memory;
A write pointer that specifies the storage location of the read data in synchronization with the feedback clock signal when the read data is taken into the register group;
A read pointer for designating the read data extraction position in synchronization with the internal clock signal when the read data is extracted from the register group;
FIFO memory including
A part of the internal clock signal supplied to the memory is masked, and the operation timing of the write pointer with respect to the read pointer is adjusted. The memory controller according to claim 1, wherein an activation signal for activating the read pointer and the write pointer is output during a mask period of the internal clock signal supplied to the memory. The memory controller according to claim 2, further comprising a mode setting register that sets an output timing of the mask period and the activation signal. An observation module for observing the feedback clock signal, using a high-speed clock signal having an integer multiple of the internal clock signal as an operation clock;
The memory controller according to claim 1, wherein the write pointer is activated in response to detection of a mask portion of the internal clock signal supplied to the memory. The memory controller according to claim 4, wherein the high-speed clock signal is a quadruple clock signal having a frequency four times that of the internal clock signal. A memory that outputs data in synchronization with the input clock signal;
A memory controller for supplying an internal clock signal to the memory and transferring data with the memory;
An information processing apparatus comprising:
The memory controller is
A group of registers for storing read data read from the memory in synchronization with a feedback clock signal obtained by feeding back the internal clock signal input to the memory;
A write pointer that specifies the storage location of the read data in synchronization with the feedback clock signal when the read data is taken into the register group;
A read pointer for designating the read data extraction position in synchronization with the internal clock signal when the read data is extracted from the register group;
FIFO memory including
An information processing apparatus comprising: masking a part of the internal clock signal supplied to the memory and adjusting an operation timing of the write pointer with respect to the read pointer.

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