JP3577290B2 - Nonvolatile semiconductor memory device - Google Patents

Description

【０４０２】
第１２の実施例では、すでに述べた様々な利点に加えて、次のような追加の利点も得られる。
【０４０３】
図６１は、図６０に示したワード線ＷＬ００ないしＷＬ０７およびＷＬ１０ないしＷＬ１７とローカルデコーダ１４６４の出力線ＷＬ０ないしＷＬ７との間の接続態様を示す半導体基板上のレイアウト図である。図６１を参照して、各ワード線ＷＬ００ないしＷＬ０７およびＷＬ１０ないしＷＬ１７は、第２ポリシリコン層により形成される。一方、ローカルデコーダ１４６４の各出力線は、第１アルミ配線層により形成される。各ワード線と対応する出力信号線との間の接続は、スルーホールを介して行なわれる。図６１に示した接続態様は、図６０に示した回路図においても示されていることが指摘される。
【０４０４】
図６０および図６１に示した接続態様を用いることにより、ワード線とローカルデコーダの出力線との間の接続が簡単化され、したがって配線密度が低下され、その結果高い集積度が得られる。
【０４０５】
図６２は、図６０に示した２つのメモリセル１４９１および１４９２の間の分離を示す断面構造図である。図６０に示したメモリセル１４９１および１４９２は、それぞれのセクタにおいて他方のセクタに最も近い位置に置かれている。これらのトランジスタ１４９１および１４９２を分離するため、図６２に示すように、半導体基板内に分離酸化膜１４９０が形成される。２つの隣接するトランジスタ１４９１および１４９２を分離するために必要となる分離酸化膜１４９０の幅Ｗｃは、図６３に示すようなフィールドシールドのためのトランジスタ１４９５および１４９６を用いる場合と比較して少なくて足りる。すなわち、図６３に示した例では、分離のためのトランジスタ１４９５および１４９６を形成するのみ大きな幅Ｗｄが必要となるが、分離酸化膜１４９０を用いることによりより少ない幅Ｗｃで近接する２つのトランジスタ１４９１および１４９２を分離することができる。これにより、より高い集積度が得られる。
【０４０６】
図６４は、第１２の実施例において用いられるワード線電圧制御回路およびプリデコーダの回路図である。図６４に示したワード線電圧制御回路１４７０は、図５９において簡単化のために省略されている。
【０４０７】
図６４を参照して、ワード線電圧制御回路１４７０は、ＶＰＰ発生器１４７１と、ＶＢＢ発生器１４７２と、電圧検出器１４７３と、インバータ１４７４と、ＶＰＰスイッチング回路１４７５と、ＶＰＰスイッチング回路１４７６と、ＣＭＯＳトランスミッションゲート１４７７および１４７８とを含む。
【０４０８】
プリデコーダ１４５２は、ＣＭＯＳトランスミッションゲートを構成するＰＭＯＳトランジスタ１４８１およびＮＭＯＳトランジスタ１４８２を含む。
【０４０９】
図６４に示したワード線電圧制御回路１４７０およびプリデコーダ１４５２において、消去動作，プログラム動作および読出動作を実行するため前述の表１に示した電圧が与えられる。
【０４１０】
一般に、フラッシュメモリのメモリセルのしきい電圧の分布を検査するため、テストのための外部電圧ＶＥＷが与えられる。図６４に示されるように、テストモード動作において、外部電圧ＶＥＷは、ワード線電圧制御回路１４７０におけるＣＭＯＳトランスミッションゲート１４７８およびプリデコーダ１４５２におけるＣＭＯＳトランスミッションゲート（トランジスタ１４８１および１４８２により構成される）を介して図６０に示したワード線ＷＬ００ないしＷＬ１７に与えられる。外部電圧ＶＥＷの電圧経路がＣＭＯＳ回路のみにより構成されているので、ＭＯＳトランジスタのしきい電圧による電圧の損失が生じない。言い換えると、より広い範囲で変化する外部電圧ＶＥＷを電圧レベルの変化なしにワード線に与えることができ、所望のテストが行なわれ得る。
【０４１１】
（１３） 第１３実施例
図６５はこの発明に従った不揮発性半導体記憶装置の第１３実施例の模式図である。半導体基板８０はメモリトランジスタ領域と周辺領域とに分けられている。メモリトランジスタ領域には、メモリトランジスタ８７ａ、８７ｂ、８７ｃ、８７ｄが間を隔てて形成されている。半導体基板８０の主表面のうち、メモリトランジスタ領域には、ｎ型のソース領域８４ａ、８４ｂ、ｎ型のドレイン領域８５ａ、８５ｂが間を隔てて形成されている。ソース領域８４ａはメモリトランジスタ８７ａと８７ｂのソース領域となり、ソース領域８４ｂはメモリトランジスタ８７ｃと８７ｄのソース領域となる。
【０４１２】
またドレイン領域８５ａはメモリトランジスタ８７ｂと８７ｃのドレイン領域となり、ドレイン領域８５ｂはメモリトランジスタ８７ｄのドレイン領域となる。なお８８はコントロールゲートを示し、８９はフローティングゲートを示している。
【０４１３】
半導体基板８０の主表面のうち、メモリトランジスタ領域には、ｎ型のソース／ドレイン領域８３ａ、８３ｂを有するセレクトゲートトランジスタ８６が形成されている。ソース／ドレイン領域８３ｂはメモリトランジスタ８７ａのドレイン領域の役割もしている。
【０４１４】
メモリトランジスタ８７ａ、８７ｂ、８７ｃ、８７ｄ上には多結晶シリコンからなる副ビット線９０が形成されている。副ビット線９０はソース／ドレイン領域８３ｂと接続されている。副ビット線９０から分岐した分岐線９１ａはドレイン領域８５ａと接続され、分岐線９１ｂはドレイン領域８５ｂと接続されている。副ビット線９０上にはアルミニウムからなる主ビット線９２が形成されている。主ビット線９２は、ソース／ドレイン領域８３ａに接続されている。
【０４１５】
半導体基板８０中にはメモリトランジスタ領域を囲むようにｐウェル領域８２が形成されており、ｐウェル領域８２を囲むようにｎウェル領域８１が形成されている。周辺領域にはＭＯＳトランジスタ９３が形成されている。この発明に従った不揮発性半導体記憶装置のさらに詳細な説明を第１４実施例を用いて行なう。
【０４１６】
（１４） 第１４実施例
図６６（ａ）はこの発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の一部の断面図である。ｐ型シリコン基板２０１にはｐウェル領域２１０が間を隔てて形成されている。ｐウェル領域２１０上には、メモリトランジスタ２５０〜２５７、２６１、２６２、セレクトゲートトランジスタ２５９、２６０が形成されている。ｐウェル領域２１０には、各メモリトランジスタのｎ型のソース領域２２３、ｎ型のドレイン領域２２４が形成されている。２４９はｎ型の不純物領域を示している。
【０４１７】
各メモリトランジスタ、セレクトゲートトランジスタはシリコン酸化膜２４７で覆われている。ソース領域２２３上はシリコン酸化膜２４７によって塞がれている。これに対しドレイン領域２２４および不純物領域２４９上はシリコン酸化膜で塞がれていない。各メモリトランジスタはフローティングゲート２１９およびコントロールゲート２２０を備えている。
【０４１８】
メモリトランジスタ２５０〜２５７の各ドレイン領域２２４は１本の副ビット線２２７ａによって電気的に接続されている。メモリトランジスタ２６１、２６２のドレイン領域２２４は１本の副ビット線２２７ｂによって電気的に接続されている。不純物領域２４９は接続導電層２４８と電気的に接続されている。また、フィールド酸化膜２０６上にはダミーゲート２４２を有するダミーゲートトランジスタ２５８が形成されている。ダミーゲートトランジスタの詳細は後で説明する。
【０４１９】
副ビット線２２７ａおよび２２７ｂ上には層間絶縁膜２４５が形成され、層間絶縁膜２４５上には主ビット線２３３が形成されている。主ビット線２３３は接続導電層２４８と電気的に接続されている。主ビット線２３３上には層間絶縁膜２４６が形成され、層間絶縁膜２４６上にはアルミニウム配線２３８が間を隔てて形成されている。
【０４２０】
一方、シリコン基板２０１中にはｐウェル領域２１０を覆うようにｎウェル領域２０７が形成されている。
【０４２１】
図６６（ｂ）は図６６（ａ）に示すメモリトランジスタの等価回路図である。８個のメモリトランジスタの各ドレイン領域は副ビット線と接続され、ソース領域はソース線に接続されている。選択ゲート１によって主ビット線と副ビット線との導通／遮断が行なわれる。ワード線１〜８はコントロールゲートのことである。
【０４２２】
図６７は、この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタの断面構造図である。ｐウェル領域２１０とフローティングゲート２１９との間にはゲート酸化膜２１３が形成され、フローティングゲート２１９とコントロールゲート２２０の間にはＯＮＯ膜２１５が形成されている。
【０４２３】
次にこの発明に従った不揮発性半導体記憶装置の第１４実施例の動作を図６６（ｂ）と図６７を用いて説明する。まず消去動作について説明する。従来例で説明したＮＯＲ型およびＮＡＮＤ型は電子を引き抜くことにより消去状態にしていたが、この第１４実施例では電子を注入することにより消去状態にしている。すなわち、メモリトランジスタ２５０〜２５７を一括消去する場合、主ビット線２３３をフローティング状態に保ち、セレクトゲートトランジスタ２５９をＯＦＦする。これにより副ビット線２２７ａもフローティング状態となる。そしてソース線およびｐウェル領域２１０ａに−１０Ｖ程度の電圧を印加する。そして、ワード線１〜ワード線８に１０Ｖ程度の電圧を印加する。これにより図６７の▲２▼に示すようにチャネル領域にある電子がトンネル効果の１つであるチャネルＦＮ現象によってフローティングゲート２１９に注入される。これが消去状態“１”でありＶｔｈの値は〜６Ｖ程度である。
【０４２４】
次に書込動作について説明する。たとえばメモリトランジスタ２５７を書込状態“０”にするとき、セレクトゲートトランジスタ２５９をＯＮし、主ビット線２３３に５Ｖ程度の電圧を印加する。これにより副ビット線２２７ａの電圧も５Ｖ程度になる。そしてｐウェル領域２１０ａを接地電位に保ち、ソース線をＯＰＥＮにする。さらに、ワード線８に−１０Ｖ程度の電圧を印加し、ワード線１〜ワード線７は接地電位に保つ。これにより、図６７の▲１▼に示すように、メモリトランジスタ２５７のフローティングゲート２１９に蓄積された電子はトンネル効果の１つであるドレインＦＮ現象によってドレイン領域２２４に引き抜かれる。これによりメモリトランジスタ２５７が書込状態“０”となり、このときＶｔｈの値は１Ｖ程度になる。
【０４２５】
次に読出動作を説明する。たとえばメモリトランジスタ２５７を読出すとき、セレクトゲートトランジスタ２５９をＯＮし、主ビット線２３３に１Ｖ程度の電圧を印加する。そしてソース線およびｐウェル領域２１０ａを接地電位に保つ。そしてワード線８に３〜５Ｖ程度の電圧を印加し、ワード線１〜ワード線７を接地電位にする。このときメモリトランジスタ２５７が消去状態“１”のときはチャネルが形成されずビット線に電流が流れない。これに対し書込状態“０”のときはチャネルが形成されビット線に電流が流れる。これにより書込状態／消去状態の判定を行なう。
【０４２６】
この第１４実施例ではｐウェル領域２１０に負の電圧を印加させている。ｐウェル領域２１０の周りにはｎウェル領域２０７があるので、負の電圧を印加してもｐウェル領域２１０とｎウェル領域２０７とは逆バイアス状態となり、ｐウェル領域２１０に電圧を印加しても周辺回路形成領域に電圧が印加されることはない。
【０４２７】
また、消去動作のとき、ｐウェル領域に負の電圧を印加し、ワード線に正の電圧を印加することにより、最大電圧の値を小さくしながらも、ｐウェル領域２１０とコントロールゲート２２０間の電位差を相対的に大きくし、チャネルＦＮ効果を起こすことを可能にしている。
【０４２８】
また、図６６（ａ）に示すようにメモリトランジスタ２５０〜２５７の各ドレイン領域２２４には副ビット線２２７ａが接続されている。このため読出動作の際には読出電流を多くとることができるのでＮＡＮＤ型に比べて読出動作を高速に行なえる。
【０４２９】
さらに、図６７に示すように書込動作をドレインＦＮを用いているので、チャネルホットエレクトロンを用いる場合に比べ高い効率で書込動作を行なうことができ、これにより消費電力の低減を図れる。
【０４３０】
次に図６６（ａ）に示す構造の平面的配置状態を説明する。図６８はコントロールゲート２２０を形成した状態までにおける平面図である。図６８をＡ−Ａ線で切断した状態が、図６６（ａ）においてコントロールゲート２２０までの状態を示している。コントロールゲート２２０、選択ゲート２３４、ダミーゲート２４２、ソース線２２３ａは縦方向に延びている。ソース線２２３ａは図６６（ａ）に示すソース領域２２３をつなげたものである。フィールド酸化膜２０６とドレイン領域２２４が交互に形成されている。なお、選択ゲート２３４上にある配線層（メモリトランジスタのコントロールゲートにあたる）は図示を省略している。
【０４３１】
図６９は図６８の上に副ビット線２２７ａ、２２７ｂを形成した状態を示している。ソース線２２３ａは配線層２４１と電気的に接続されている。配線層２４１は副ビット線２２７ａ、２２７ｂと同時に形成されたものである。
【０４３２】
また、選択ゲート２３４はポリパッド２３６と電気的に接続されている。ポリパッド２３６も副ビット線２２７ａ、２２７ｂと同時に形成されたものである。なお、副ビット線２２７ａ、２２７ｂとドレイン領域２２４とのコンタクトは図示が省略されている。また、接続導電層２４８と不純物領域２４９とのコンタクトも図示が省略されている。
【０４３３】
図７０は図６９の上に主ビット線２３３を形成した状態を示している。主ビット線２３３は接続導電層２４８と電気的に接続されている。アルミ電極２３７ａ、２３７ｂ、２３７ｃ、２３７ｄは主ビット線２３３と同時に形成されたものである。アルミ電極２３７ａは一方のポリパッド２３６と電気的に接続され、アルミ電極２３７ｂは他方のポリパッド２３６と電気的に接続されている。アルミ電極２３７ｃは配線層２４１と電気的に接続されている。またアルミ電極２３７ｄはダミーゲート２４２と電気的に接続されている。
【０４３４】
図７１は図７０の上にアルミ配線２３８ａ〜２３８ｇを形成した状態を示している。アルミ配線２３８ａはアルミ電極２３７ａと電気的に接続され、アルミ配線２３８ｂはアルミ電極２３７ｂと電気的に接続され、アルミ配線２３８ｅはアルミ電極２３７ｃと電気的に接続され、アルミ配線２３８ｆ、２３８ｇはアルミ電極２３７ｂと電気的に接続されている。
【０４３５】
次に、この発明に従った不揮発性半導体記憶装置の第１４実施例の全体の構成および動作の第１〜第７の例を表２を参照しながら説明する。
【０４３６】
この不揮発性半導体記憶装置に含まれるメモリセルマトリックスは、以下に説明するように複数のセクタに分割されている。表２には、選択されたセクタ内のメモリセル（メモリトランジスタ）および非選択のセクタ内のメモリセル（メモリトランジスタ）への電圧印加条件が示される。表２において、Ｖｄはドレイン電圧、Ｖｇはコントロールゲート電圧、Ｖｓはソース電圧、Ｖｂｂはウェル電圧を示す。
【０４３７】
【表２】

【０４３８】
＜１＞ 第１の例
（ａ） 不揮発性半導体記憶装置の全体の構成
図７２は、第１の例による不揮発性半導体記憶装置の全体の構成を示すブロック図である。
【０４３９】
メモリセルマトリックス７０はセクタＳＥ１，ＳＥ２に分割されている。メモリセルマトリックス７０は、セクタＳＥ１，ＳＥ２にそれぞれ対応するセレクトゲートＳＧ１，ＳＧ２を含む。メモリセルマトリックス７０はＰウェル領域７１内に形成される。
【０４４０】
メモリセルマトリックス７０には２つの主ビット線ＭＢ０，ＭＢ１が配列される。主ビット線ＭＢ０，ＭＢ１はそれぞれＹゲート７２内のＹゲートトランジスタＹＧ０，ＹＧ１を介してセンスアンプ５２および書込回路５３に接続される。
【０４４１】
主ビット線ＭＢ０に対応して２つの副ビット線ＳＢ０１，ＳＢ０２が設けられ、主ビット線ＭＢ１に対応して２つの副ビット線ＳＢ１１，ＳＢ１２が設けられる。
【０４４２】
副ビット線ＳＢ０１，ＳＢ１１に交差するようにワード線ＷＬ０，ＷＬ１が配列され、副ビット線ＳＢ０２，ＳＢ１２に交差するようにワード線ＷＬ２，ＷＬ３が配列される。
【０４４３】
副ビット線ＳＢ０１，ＳＢ０２，ＳＢ１１，ＳＢ１２とワード線ＷＬ０〜ＷＬ３との交点にはそれぞれメモリセル（メモリトランジスタ）Ｍ００〜Ｍ０３，Ｍ１０〜Ｍ１３が設けられる。メモリセルＭ００，Ｍ０１，Ｍ１０，Ｍ１１はセクタＳ１に含まれ、メモリセルＭ０２，Ｍ０３，Ｍ１２，Ｍ１３はセクタＳＥ２に含まれる。
【０４４４】
各メモリセルのドレインは対応する副ビット線に接続され、コントロールゲートは対応するワード線に接続され、ソースはソース線ＳＬに接続される。
【０４４５】
セレクトゲートＳＧ１はセレクトゲートトランジスタＳＧ０１，ＳＧ１１を含み、セレクトゲートＳＧ２はセレクトゲートトランジスタＳＧ０２，ＳＧ１２を含む。副ビット線ＳＢ０１，ＳＢ０２はそれぞれセレクトゲートトランジスタＳＧ０１，ＳＧ０２を介して主ビット線ＭＢ０に接続され、副ビット線ＳＢ１１，ＳＢ１２はそれぞれセレクトゲートトランジスタＳＧ１１，ＳＧ１２を介して主ビット線ＭＢ１に接続される。
【０４４６】
アドレスバッファ５８は、外部から与えられるアドレス信号を受け、Ｘアドレス信号をＸデコーダ５９に与え、Ｙアドレス信号をＹデコーダ５７に与える。Ｘデコーダ５９は、Ｘアドレス信号に応答して複数のワード線ＷＬ０〜ＷＬ３のうちいずれかを選択する。Ｙデコーダ５７は、Ｙアドレス信号に応答して複数の主ビット線ＭＢ０，ＭＢ１のいずれかを選択する選択信号を発生する。
【０４４７】
Ｙゲート７２内のＹゲートトランジスタは、それぞれ選択信号に応答して主ビット線ＭＢ０，ＭＢ１をセンスアンプ５２および書込回路５３に接続する。
【０４４８】
読出時には、センスアンプ５２が、主ビット線ＭＢ０または主ビット線ＭＢ１上に読出されたデータを検知し、データ入出力バッファ５１を介して外部に出力する。
【０４４９】
書込時には、外部から与えられるデータがデータ入出力バッファ５１を介して書込回路５３に与えられ、書込回路５３はそのデータに従って主ビット線ＭＢ０，ＭＢ１にプログラム電圧を与える。
【０４５０】
高電圧発生回路５４，５５は外部から電源電圧Ｖｃｃ（たとえば５Ｖ）を受け、高電圧を発生する。負電圧発生回路５６は外部から電源電圧Ｖｃｃを受け、負電圧を発生する。ベリファイ電圧発生回路６０は、外部から与えられる電源電圧Ｖｃｃを受け、ベリファイ時に、選択されたワード線に所定のベリファイ電圧を与える。ウェル電位発生回路６１は、消去時に、ｐウェル領域７１に負電圧を印加する。ソース制御回路６２は、消去時に、ソース線ＳＬに高電圧を与える。セレクトゲートデコーダ６３は、アドレスバッファ５８からのアドレス信号の一部に応答して、セレクトゲートＳＧ１，ＳＧ２を選択的に活性化する。
【０４５１】
書込／消去制御回路５０は、外部から与えられる制御信号に応答して、各回路の動作を制御する。
【０４５２】
（ｂ） 不揮発性半導体記憶装置の動作
次に、不揮発性半導体記憶装置のセクタ消去動作、書込動作および読出動作を表１を参照しながら説明する。
【０４５３】
（ｉ） セクタ消去動作
ここでは、セクタＳＥ１を一括消去するものと仮定する。まず、書込／消去制御回路５０にセクタ一括消去動作を指定する制御信号が与えられる。それにより、高電圧発生回路５５および負電圧発生回路５６が活性化される。
【０４５４】
高電圧発生回路５５はＸデコーダ５９に高電圧（１０Ｖ）を与える。Ｘデコーダ５９は、セクタＳＥ１のワード線ＷＬ０，ＷＬ１に高電圧（１０Ｖ）を印加し、セクタＳＥ２のワード線ＷＬ２，ＷＬ３に０Ｖを印加する。負電圧発生回路５６はＹデコーダ５７およびウェル電位発生回路６１に負電圧を与える。Ｙデコーダ５７はＹゲート７２内のＹゲートトランジスタＹＧ０，ＹＧ１に負電圧を印加する。それにより、主ビット線ＭＢ０，ＭＢ１はフローティング状態になる。ソース制御回路６２はソース線ＳＬをフローティング状態にする。また、ウェル電位発生回路６１はｐウェル領域７１に負電圧（−８Ｖ）を印加する。セレクトゲートデコーダ６３はセレクトゲートＳＧ１，ＳＧ２をオフ状態にする。
【０４５５】
このようにして、選択セクタＳＥ１内のメモリセルおよび非選択セクタＳＥ２内のメモリセルに、表２の（Ｅ１）に示されるように電圧が印加される。その結果、セクタＳＥ１内のすべてのメモリセルは消去される。
【０４５６】
（ｉｉ） 書込動作
ここでは、メモリセルＭ００をプログラムするものと仮定する。すなわち、メモリセルＭ００にデータ“０”を書込み、メモリセルＭ１０はデータ“１”を保持する。
【０４５７】
まず、書込／消去制御回路５０に、プログラム動作を指定する制御信号が与えられる。それにより、高電圧発生回路５４および負電圧発生回路５６が活性化される。
【０４５８】
負電圧発生回路５６はＸデコーダ５９に負電圧を与える。Ｘデコーダ５９は、アドレスバッファ５８から与えられるＸアドレス信号に応答してワード線ＷＬ０を選択し、選択されたワード線ＷＬ０に負電圧（−８Ｖ）を印加し、非選択のワード線ＷＬ１〜ＷＬ３に０Ｖを印加する。
【０４５９】
高電圧発生回路５４はＹデコーダ５７、書込回路５３およびセレクトゲートデコーダ６３に高電圧を与える。まず、外部からデータ入出力バッファ５１を介してデータ“０”が書込回路５３に与えられ、ラッチされる。Ｙデコーダ５７は、アドレスバッファ５８から与えられるＹアドレス信号に応答してＹゲート７２内のＹゲートトランジスタＹＧ０に高電圧を印加し、ＹゲートトランジスタＹＧ１に０Ｖを印加する。それにより、ＹゲートトランジスタＹＧ０がオンする。
【０４６０】
書込回路５３はＹゲートトランジスタＹＧ０を介して主ビット線ＭＢ０にデータ“０”に対応するプログラム電圧（５Ｖ）を印加する。また、セレクトゲートデコーダ６３は、セレクトゲートＳＧ１をオン状態にし、セレクトゲートＳＧ２をオフ状態にする。それにより、副ビット線ＳＢ０１，ＳＢ１１がそれぞれ主ビット線ＭＢ０，ＭＢ１に接続される。ソース制御回路６２は、ソース線ＳＬをフローティング状態にする。ウェル電位発生回路６１はｐウェル領域７１に０Ｖを印加する。
【０４６１】
このようにして、メモリセルＭ００に、表２の（Ｐ１）の左欄に示されるように電圧が印加される。その結果、メモリセルＭ００のしきい値電圧が下降する。
【０４６２】
一定時間（たとえば１ｍ秒）経過後、外部からデータ入出力バッファ５１を介してデータ“１”が書込回路５３に与えられ、ラッチされる。Ｙデコーダ５７は、アドレスバッファ５８から与えられるＹアドレス信号に応答してＹゲート７２内のＹゲートトランジスタＹＧ１に高電圧を印加し、ＹゲートトランジスタＹＧ０に０Ｖを印加する。それにより、ＹゲートトランジスタＹＧ１がオンする。書込回路５３は、ＹゲートトランジスタＹＧ１を介して主ビット線ＭＢ１にデータ“１”に対応する０Ｖを印加する。
【０４６３】
このようにして、メモリセルＭ１０に、表２の（Ｐ１）の右欄に示されるように電圧が印加される。その結果、メモリセルＭ１０のしきい値電圧は高いまま維持される。
【０４６４】
（ｉｉｉ） 読出動作
ここでは、メモリセルＭ００からデータを読出すものと仮定する。まず、書込／消去制御回路５０に、読出動作を指定する制御信号が与えられる。
【０４６５】
Ｘデコーダ５９は、アドレスバッファ５８から与えられるＸアドレス信号に応答してワード線ＷＬ０を選択し、それに３Ｖを印加する。このとき、ワード線ＷＬ１〜ＷＬ３は０Ｖに保たれる。セレクトゲートデコーダ６３は、セレクトゲートＳＧ１をオン状態にし、セレクトゲートＳＧ２をオフ状態にする。Ｙデコーダ５７は、アドレスバッファ５８から与えられるＹアドレス信号に応答してＹゲート７２内のＹゲートトランジスタＹＧ０をオンさせる。ソース制御回路６２はソース線ＳＬを接地する。
【０４６６】
このようにして、選択されたメモリセルＭ００に、表２の（Ｒ１）の左欄に示されるように電圧が印加される。それにより、Ｍ００の内容が“１”であれば主ビット線ＭＢ０に読出電流が流れる。この読出電流がセンスアンプ５２により検知され、データ入出力バッファ５１を介して外部に出力される。このとき、非選択のメモリセルには、表２の（Ｒ１）の右欄に示されるように電圧が印加される。
【０４６７】
＜２＞ 第２の例
（ａ） 不揮発性半導体記憶装置の全体の構成
図７３は、第２の例による不揮発性半導体記憶装置の全体の構成を示すブロック図である。
【０４６８】
図７３の不揮発性半導体記憶装置が図７２の不揮発性半導体記憶装置と異なるのは、負電圧発生回路５６が消去時にソース制御回路６２に負電圧を与える点である。
【０４６９】
他の部分の構成は、図７２に示される構成と同様である。
（ｂ） 不揮発性半導体記憶装置の動作
第２の例の不揮発性半導体記憶装置の書込動作および読出動作は第１の例と同様である。また、セクタ一括消去動作では、ソース制御回路６２によりソース線ＳＬに負電圧（−８Ｖ）が印加される点が第１の例と異なる。
【０４７０】
一括消去時に、選択セクタ内のメモリセルには、表２の（Ｅ２）の左欄に示されるように電圧が印加され、非選択セクタ内のメモリセルには表２の（Ｅ２）の右欄に示されるように電圧が印加される。
【０４７１】
＜３＞ 第３の例
（ａ） 不揮発性半導体記憶装置の全体の構成
図７４は、第３の例による不揮発性半導体記憶装置の全体の構成を示すブロック図である。
【０４７２】
第３の例の不揮発性半導体記憶装置が第１の例の不揮発性半導体記憶装置と異なるのは次の点である。ソース制御回路６２の代わりにソースデコーダ１０２が設けられる。また、負電圧発生回路５６はＹデコーダ５７の代わりにセレクトゲートデコーダ６３およびソースデコーダ１０２に負電圧を与える。
【０４７３】
セクタＳＥ１内のメモリセルＭ００，Ｍ０１，Ｍ１０，Ｍ１１のソースはソース線ＳＬ１に接続され、セクタＳＥ２内のメモリセルＭ０２，Ｍ０３，Ｍ１２，Ｍ１３のソースはソース線ＳＬ２に接続される。ソースデコーダ１０２の出力端子はソース線ＳＬ１，ＳＬ２に接続される。
【０４７４】
（ｂ） 不揮発性半導体記憶装置の動作
第３の例の不揮発性半導体記憶装置の書込動作および読出動作は第１の例と同様である。セクタ一括消去動作では、ソースデコーダ１０２が、選択セクタに対応するソース線をフローティング状態にし、非選択セクタに対応するソース線に負電圧（−８Ｖ）を印加する。たとえば、セクタＳＥ１の一括消去時には、ソース線ＳＬ１がフローティング状態にされ、ソース線ＳＬ２に−８Ｖが印加される。
【０４７５】
このようにして、選択セクタ内のメモリセルには、表２の（Ｅ３）の左欄に示されるように電圧が印加され、非選択セクタ内のメモリセルには表２の（Ｅ３）の右欄に示されるように電圧が印加される。
【０４７６】
その結果、非選択セクタ内のメモリセルのデータを安定に保護しつつ、選択セクタ内のメモリセルを一括消去することができる。
【０４７７】
＜４＞ 第４の例
（ａ） 不揮発性半導体記憶装置の全体の構成
図７５は、第４の例による不揮発性半導体記憶装置の全体の構成を示すブロック図である。
【０４７８】
第４の例の不揮発性半導体記憶装置が図７４に示す第３の例の不揮発性半導体記憶装置と異なるのは次の点である。負電圧発生回路５６は、消去時にウェル電位発生回路６１のみに負電圧を与え、セレクトゲートデコーダ６３およびソースデコーダ１０２には負電圧を与えない。
【０４７９】
（ｂ） 不揮発性半導体記憶装置の動作
第４の例の不揮発性半導体記憶装置の書込動作および読出動作は第１の例と同様である。
【０４８０】
一括消去動作時には、ソースデコーダ１０２が、選択セクタに対応するソース線をフローティング状態にし、非選択セクタに対応するソース線に０Ｖを印加する。たとえば、セクタＳＥ１の一括消去時には、ソース線ＳＬ１がフローティング状態にされ、ソース線ＳＬ２には０Ｖが印加される。
【０４８１】
このようにして、選択セクタ内のメモリセルには、表２の（Ｅ４）の左欄に示されるように電圧が印加され、非選択セクタ内のメモリセルには、表２の（Ｅ４）の右欄に示されるように電圧が印加される。
【０４８２】
その結果、非選択セクタ内のメモリセルのデータを安定に保護にしつつ、選択セクタ内のメモリセルを一括消去することができる。
【０４８３】
＜５＞ 第５の例
（ａ） 不揮発性半導体記憶装置の全体の構成
図７６は、第５の例による不揮発性半導体記憶装置の全体を構成を示すブロック図である。
【０４８４】
第５の例の不揮発性半導体記憶装置が図７５に示す第４の例の不揮発性半導体記憶装置と異なるのは次の点である。２つの負電圧発生回路５６ａ、５６ｂが設けられている。負電圧発生回路５６ａはウェル電位発生回路６１、セレクトゲートデコーダ６３およびソースデコーダ１０２に負電圧を与える。負電圧発生回路５６ｂはＸデコーダ５９に負電圧を与える。他の部分の構成は図７５に示される構成と同様である。
【０４８５】
（ｂ） 不揮発性半導体記憶装置の動作
第５の例の不揮発性半導体記憶装置の書込動作および読出動作は第１の例と同様である。
【０４８６】
セクタ一括消去動作時には、ソースデコーダ１０２が、選択セクタに対応するソース線をフローティング状態にし、非選択セクタに対応するソース線に−４Ｖを印加する。たとえば、セクタＳＥ１の一括消去時には、ソース線ＳＬ１がフローティング状態にされ、ソース線ＳＬ２には−４Ｖが印加される。
【０４８７】
このようにして、選択セクタ内のメモリセルには、表２の（Ｅ５）の左欄に示されるように電圧が印加され、非選択セクタ内のメモリセルには、表２の（Ｅ５）に示されるように電圧が印加される。
【０４８８】
その結果、非選択セクタ内のメモリセルのデータを安定に保護しつつ、選択セクタ内のメモリセルを一括消去することができる。
【０４８９】
＜６＞ 第６の例
第６の例による不揮発性半導体記憶装置の全体の構成は、図７４に示される構成と同様である。また、第６の例の不揮発性半導体記憶装置の書込動作および読出動作は、第１の例と同様である。
【０４９０】
一括消去動作時には、ソースデコーダ１０２が、選択セクタに対応するソース線に−８Ｖを印加し、非選択セクタに対応するソース線に０Ｖを印加する。たとえば、セクタＳＥ１の一括消去時には、ソース線ＳＬ１に−８Ｖが印加され、ソース線ＳＬ２に０Ｖが印加される。
【０４９１】
このようにして、選択セクタ内のメモリセルには、表２の（Ｅ６）の左欄に示されるように電圧が印加され、非選択セクタ内のメモリセルには、表２の（Ｅ６）の右欄に示されるように電圧が印加される。
【０４９２】
その結果、非選択セクタ内のメモリセルのデータを安定に保護しつつ、選択セクタ内のメモリセルを一括消去することができる。
【０４９３】
＜７＞ 第７の例
第７の例による不揮発性半導体記憶装置の全体の構成は、図７６に示される構成と同様である。また、第７の例の不揮発性半導体記憶装置の書込動作および読出動作は、第１の例と同様である。
【０４９４】
セクタ一括消去動作時には、ソースデコーダ１０２が、選択セクタに対応するソース線に−８Ｖを印加し、非選択セクタに対応するソース線に−４Ｖを印加する。たとえば、セクタＳＥ１の選択時には、ソース線ＳＬ１に−８Ｖが印加され、ソース線ＳＬ２に−４Ｖが印加される。
【０４９５】
このようにして、選択セクタ内のメモリセルに、表２の（Ｅ７）の左欄に示されるように電圧が印加され、非選択セクタ内のメモリセルに、表２の（Ｅ７）の右欄に示されるように電圧が印加される。
【０４９６】
その結果、非選択セクタ内のメモリセルのデータを安定に保護しつつ、選択セクタ内のメモリセルを一括消去することができる。
【０４９７】
＜８＞ 各例の利点
第１および第２の例では、非選択セクタが基板からある程度ディスターブを受けるが、ソースデコーダは不要であり、負電圧発生回路は１つだけでよい。
【０４９８】
第３の例では、非選択セクタが基板から受けるディスターブは小さい。また、負電圧発生回路は１つだけでよい。さらに、消去時のソースの接合耐圧は低くてよい。ただし、ソースデコーダが必要である。
【０４９９】
第４および第６の例では、非選択セクタが基板から受けるディスターブは最も小さい。また負電圧発生回路は１つだけでよい。ただし、ソースデコーダが必要であり、ソースの接合耐圧が８Ｖだけ必要である。
【０５００】
第５および第７の例では、非選択セクタが基板から受けるディスターブはやや小さく、ソースの接合耐圧も〜４Ｖと小さくてよい。ただし、ソースデコーダが必要であり、２つの負電圧発生回路が必要である。
【０５０１】
次に、図６６（ａ）に示すこの発明に従った不揮発性半導体記憶装置の第１４実施例の製造方法について、図７７〜図９５を用いて説明する。図７７〜図９５は、上記の構造を有する不揮発性半導体記憶装置の製造方法における第１工程〜第１９工程を示す断面図である。
【０５０２】
まず図７７を参照して、ｐ型シリコン基板２０１主表面に、３００Å程度の膜厚を有する下敷き酸化膜２０２を形成する。そして、この下敷き酸化膜２０２上に、ＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｕｒ Ｄｅｐｏｓｉｔｉｏｎ）法を用いて、５００Å程度の膜厚の多結晶シリコン膜２０３を形成する。この多結晶シリコン膜２０３上に、ＣＶＤ法などを用いて、１０００Å程度のシリコン窒化膜２０４を形成する。そして、このシリコン窒化膜２０４上に、素子分離領域を露出するようにレジスト２０５を形成する。このレジスト２０５をマスクとして異方性エッチングを行なうことによって、素子分離領域上のシリコン窒化膜２０４および多結晶シリコン膜２０３をエッチングする。
【０５０３】
その後、レジスト２０５を除去し、シリコン窒化膜２０４をマスクとして用いて選択酸化を行なうことによって、図７８に示されるように、フィールド酸化膜２０６を形成する。そして、上記の多結晶シリコン膜２０３およびシリコン窒化膜２０４を除去する。
【０５０４】
次に、図７９に示されるように、メモリトランジスタ領域および周辺回路領域の一部に、３．０ＭｅＶ，２．０×１０１３ｃｍ−３の条件で、リン（Ｐ）をイオン注入する。そして、１０００℃の温度で１時間の不純物ドライブを行なう。それにより、ｎウェル２０７が形成される。その後、図８０に示されるように、メモリセル形成領域を覆うようにレジスト２０９を形成し、このレジスト２０９をマスクとして用いて、リン（Ｐ）を１．２ＭｅＶ，１．０×１０１３ｃｍ−３の条件でイオン注入し、さらに、リン（Ｐ）を１８０ＫｅＶ，３．５×１０１２ｃｍ−３の条件でイオン注入する。それにより、周辺回路領域の一部にｎウェル（図示せず）が形成される。
【０５０５】
次に、図８１を参照して、メモリトランジスタ領域に、７００ＫｅＶ，１．０×１０１３ｃｍ−３の条件でボロン（Ｂ）をイオン注入し、さらに１８０ＫｅＶ，３．５×１０１２ｃｍ−３の条件でボロン（Ｂ）をイオン注入する。それにより、ｐウェル２１０が形成される。
【０５０６】
そして、各メモリトランジスタのしきい値電圧制御のための不純物注入を行なった後、図８２を参照して、ｐ型シリコン基板２０１主表面上全面に、熱酸化処理を施すことによって１５０Å程度の膜厚のゲート絶縁膜２１１を形成する。そして、このゲート絶縁膜２１１上における選択ゲートトランジスタ（後述）形成領域を覆うようにレジスト２１２を形成する。このレジスト２１２をマスクして用いて、エッチングを行なうことによって上記のゲート絶縁膜２１１の選択ゲートトランジスタ形成領域以外の部分を除去する。
【０５０７】
上記のレジスト２１２を除去し、再び熱酸化処理を施すことによって、ｐ型シリコン基板２０１上全面に１００Å程度の膜厚のゲート絶縁膜２１３を形成する。それにより、選択ゲートトランジスタ形成領域には、約２５０Å程度の膜厚を有するゲート絶縁膜２１１，２１３が形成されることになる。そして、このゲート絶縁膜２１１，２１３上に、ＣＶＤ法などを用いて第１の多結晶シリコン膜２１４を１２００Å程度の膜厚に形成する。そして、この第１の多結晶シリコン膜厚２１４上に、所定形状（この場合であれば紙面に垂直方向に断続的に複数のレジストパターンが形成される）のレジスト２１２ａを堆積し、このレジスト２１２ａをマスクとして用いて第１の多結晶シリコン膜２１４をエッチングする。
【０５０８】
その後、図８４に示されるように、上記の第１の多結晶シリコン膜２１４上に、ＣＶＤ法などを用いて１００Å程度の膜厚の高温酸化膜を形成し、この高温酸化膜上にＣＶＤ法などを用いてシリコン窒化膜を１００Å程度の厚みに形成し、さらにこのシリコン窒化膜上にＣＶＤ法を用いて１５０Å程度の厚みの高温酸化膜を形成する。それにより、ＯＮＯ膜２１５が形成される。
【０５０９】
次に、図８５を参照して、上記のＯＮＯ膜２１５上に、ＣＶＤ法を用いて、不純物が導入された多結晶シリコン層を１２００Å程度の厚みに形成する。そしてこの多結晶シリコン層上にスパッタリング法を用いて、タングステンシリサイド（ＷＳｉ）層を１２００Å程度の厚みに形成する。これらにより、コントロールゲート電極となる導電層２１６が形成される。この導電層２１６上にＣＶＤ法を用いて、２０００Å程度の膜厚を有する高温酸化膜２１７を形成する。そして、メモリトランジスタ領域および周辺部のトランジスタ形成領域上に位置する高温酸化膜２１７上に、レジスト２１８を形成し、このレジスト２１８をマスクとしてエッチングを行なうことによって、周辺回路で用いるトランジスタの電極を形成する。
【０５１０】
次に、図８６を参照して、上記の高温酸化膜２１７上に、図８６において横方向に断続的にレジスト２１８ａを形成する。そして、このレジスト２１８ａをマスクとして用いて、高温酸化膜２１７、導電膜２１６、ＯＮＯ膜２１５、第１の多結晶シリコン膜２１４をエッチングする。それにより、フローティングゲート電極２１９およびコントロールゲート電極２２０が形成される。
【０５１１】
次に、図８７（ａ）を参照して、図８６に示される状態のフラッシュメモリ上に、さらにレジスト２２１を塗布し、メモリトランジスタのソース領域となる部分を露出させるようにこのレジスト２２１をパターニングする。図８７（ｂ）は、図８７（ａ）に示される状態のフラッシュメモリの一部平面を示す平面図である。そして、図８７（ｂ）におけるＢ−Ｂ線に沿って見た断面が、図８７（ａ）に示されることになる。このようにパターニングされたレジスト２２１をマスクとして用いて、ドライエッチングを行なうことによってソース領域上に形成されているフィールド酸化膜２０６を除去する。
【０５１２】
そして、レジスト２１８ａ，２１１を除去した後、図８８に示されるように、選択ゲートトランジスタのみを露出させるようにレジストパターン２２１ａを形成する。そして、このレジストパターン２２１ａをマスクとして用いて、リン（Ｐ）を６０ＫｅＶ，３．０×１０１３ｃｍ−３の条件でイオン注入する。それにより、選択ゲートトランジスタのソース／ドレイン領域２２３，２２４を形成する。そして、上記のレジスト２２１ａを除去する。
【０５１３】
その後、図８９を参照して、選択ゲートトランジスタとなるトランジスタを覆い他のメモリセルを露出するようにレジストパターン２２１ｂを形成する。そして、このレジスト２２１ｂをマスクとして用いて、３５ＫｅＶ，５．５×１０１５ｃｍ−３の条件で、砒素（Ａｓ）をイオン注入する。それにより、メモリトランジスタのソース／ドレイン領域およびソース線が形成されることになる。そして、レジスト２２１ｂを除去する。
【０５１４】
次に、図９０を参照して、メモリトランジスタ領域に、ＣＶＤ法を用いて、２０００Å程度の膜厚を有する高温酸化膜を形成する。そして、この高温酸化膜を異方性エッチングすることによって、選択ゲートトランジスタの側壁あるいはメモリトランジスタの側壁にサイドウォール２２５を形成する。そして、このサイドウォール２２５をマスクとして用いて、３５ＫｅＶ，４．０×１０１５ｃｍ−３の条件で、砒素（Ａｓ）をイオン注入する。それにより、周辺部のトランジスタのソース／ドレイン領域を形成する。
【０５１５】
その後、図９１を参照して、メモリトランジスタ領域に、ＴＥＯＳ（Ｔｅｔｒａ ｅｔｈｙｌ ｏｒｔｈｏ Ｓｉｌｉｃａｔｅ）膜などからなるシリコン酸化膜２２６を堆積する。そして、３０分程度の酸化膜のシンタ処理を行なう。そして、図９２に示すように、このシリコン酸化膜２２６を異方性エッチングすることによって、サイドウォール２２５ａが形成されることになる。このサイドウォール２２５ａの形成によって、メモリセルにおけるソース領域は、シリコン酸化膜によって覆われることになる。
【０５１６】
次に、図９３を参照して、ＣＶＤ法などを用いて、２０００Å程度の膜厚を有する多結晶シリコン層を形成し、この多結晶シリコン層に不純物を導入することによって導電性をもたせる。この多結晶シリコン層上に所定形状のレジスト２２８を塗布し、このレジスト２２８をマスクとしてパターニングすることによって副ビット線２２７が形成される。
【０５１７】
次に、図９４を参照して、上記のレジスト２２８を除去した後、副ビット線２２７上に、ＣＶＤ法を用いてＴＥＯＳ膜などからなるシリコン酸化膜２２９を形成する。このシリコン酸化膜２２９の膜厚は、１５００Å程度である。このシリコン酸化膜２２９上に、ＣＶＤ法などを用いて、膜厚５００Å程度のシリコン窒化膜２３０を形成する。そして、このシリコン窒化膜２３０上に、ＣＶＤ法などを用いて１００００Å程度の膜厚を有するＢＰＴＥＯＳ膜などからなるシリコン酸化膜２３１を形成する。その後、８５０℃程度の熱処理によりリフローを行ない、ＨＦ等によりＢＰＴＥＯＳ膜を５０００Å程度エッチバックする。そして、このシリコン酸化膜２３１上に所定形状のレジスト２３２を堆積し、このレジスト２３２をマスクとして用いて、シリコン酸化膜２２９，２３１およびシリコン窒化膜２３０をエッチングする。それにより、副ビット線２２７と後の工程で形成される主ビット線２３３との接続のためのコンタクトホール２３３ａが形成されることになる。
【０５１８】
次に、図９５を参照して、上記のコンタクトホール２３３ａ内に、ＣＶＤ法およびエッチバック法を用いて、タングステンプラグ２３３ｂを形成する。そして、このタングステンプラグ２３３ｂ上およびシリコン酸化膜２３１上に、スパッタリング法などを用いて、５０００Å程度の膜厚を有するアルミニウム合金層を形成する。そして、このアルミニウム合金層上に所定形状のレジスト２３２ａを堆積し、このレジスト２３２ａをマスクとしてアルミニウム合金層をパターニングすることによって主ビット線２３３が形成される。その後、レジスト２３２ａを除去し、この主ビット線上に層間絶縁層を形成する。そして、スルーホール形成工程を経てこの層間絶縁層上にさらにアルミニウム配線層を形成する。それにより、図６６（ａ）に示される不揮発性半導体装置が形成されることになる。
【０５１９】
次に、この発明に従った不揮発性半導体記憶装置の第１４実施例のセレクトゲートコンタクト部の製造方法について、図９６〜図１００を用いて説明する。図９６〜図１００は、図６８におけるＣ−Ｃ線に沿って見た断面を示す図である。
【０５２０】
まず、図９６を参照して、上記の実施例と同様の工程を経て、高温酸化膜２１７までを形成する。選択ゲートトランジスタはといえば、その上層に形成されるアルミニウム配線層２３８とコンタクトホールを介して接続される。したがって、その接続部には、コンタクトホールが形成されることになる。このコンタクト部が図９７に示されている。図９７を参照して、上記のように高温酸化膜２１７を堆積した後、エッチングを行なうことによってコンタクト部における高温酸化膜２１７および導電膜２１６を除去する。それにより、コンタクトホール２５１が形成される。
【０５２１】
そして、図９８を参照して、ＣＶＤ法などを用いてＴＥＯＳ膜などからなる酸化膜を全面に形成した後、異方性エッチングを行なうことによって、コンタクトホール２５１の側壁にシリコン酸化膜２３５を残存させる。このとき、このサイドウォールとなるシリコン酸化膜２３５の形成時に、第１の多結晶シリコン膜２１４上のＯＮＯ膜２１５もエッチングされるため、第１の多結晶シリコン膜２１４は露出している。
【０５２２】
次に、図９９を参照して、コンタクトホール２５１に多結晶シリコンからなるポリパッド２３６を形成し、同時に副ビット線２２７を形成する。その後、図１００に示されるように、ポリパッド２３６上および副ビット線２２７上に層間絶縁膜２４５を形成する。そして、この層間絶縁膜２４５におけるポリパッド２３６上に位置する部分に、コンタクトホール２５１ａを形成し、このコンタクトホール２５１ａにアルミ電極２３７を形成する。このとき、このアルミ電極２３７の形成と同時に、主ビット線２３３が形成される。このように、選択ゲートトランジスタのコンタクト部にポリパッド２３６を形成することによって、このコンタクト部におけるアスペクト比を小さくすることができ、かつパターンの重ね合わせのマージンを増大することが可能となる。
【０５２３】
以上のようにして主ビット線２３３およびアルミニウム電極２３７が形成された後は、上記の実施例と同様の工程を経て不揮発性半導体記憶装置が形成されることになる。
【０５２４】
次に、図１０１〜図１０６を用いて、この発明に基づく不揮発性半導体記憶装置の第１４実施例のソース線コンタクト部の製造方法について説明する。図１０１は、図７０に示された不揮発性半導体記憶装置の一部を示す平面図である。まず図１０１を参照して、ソース線２２３ａは、ソース線コンタクト部２３９において、コンタクト部以外のソース線２２３ａの幅Ｗ２よりも大きい幅Ｗ１を有するように形成されている。一方、この形状を反映して、ドレイン領域の幅は、ソース線コンタクト部２３９に挟まれる部分においては、Ｗ４と小さく、それ以外の部分では、このＷ４より大きいＷ３の幅を有している。このような幅の違いを利用して、本実施例においては、ソース線コンタクト部２３９のコンタクトホール形成と、ドレインコンタクト部２４０におけるコンタクトホール形成とは同時に行なおうとするものである。
【０５２５】
以下に、図１０２〜図１０６を用いて、詳しく説明する。図１０２（Ｉ）は、図１０１におけるＤ−Ｄ線に沿った見た断面を示す図である。図１０２（ＩＩ）は、図１０１におけるＥ−Ｅ線に沿って見た断面を示す図である。以下、図１０３〜図１０６においても同様とする。
【０５２６】
まず、図１０２を参照して、メモリトランジスタにおけるフローティングゲート電極２１９、ＯＮＯ膜２１５、コントロールゲート電極２２０および高温酸化膜２１７を上記の実施例と同様の工程を経て形成する。このとき、（Ｉ）図においては、ソース部の間隔がドレイン部の間隔よりも広くなっており、（ＩＩ）図においては、ドレイン部の間隔がソース部の間隔よりも広くなっている。
【０５２７】
このような状態のメモリトランジスタに、図１０３に示されるように、上記の実施例と同様の方法でサイドウォール２２５を形成する。そして、サイドウォール２２５上に、図１０４に示されるように、さらに酸化膜２２６を堆積する。
【０５２８】
その後、図１０５（Ｉ）を参照して、上記の酸化膜２２６に異方性エッチングを施すことによって、ソース線コンタクト部２３９に、コンタクトホール２３９ａを形成する。このとき、ソース部の幅がドレイン部の幅よりも広いため、ソース部の方がエッチングされやすくなり、ソース部においてはコンタクトホール２３９ａが形成されるが、ドレイン部においてはコンタクトホールが形成されない。
【０５２９】
一方、図１０５（ＩＩ）を参照して、この場合であれば、ドレイン部の方がソース部よりも幅が広くなっているため、上記の場合と同様の考え方で、ドレイン部のみにコンタクトホール２４０ａが形成されることになる。このようにして、コンタクトホール２３９ａおよび２４０ａが同時に形成された後、図１０６に示されるように、メモリトランジスタ上に多結晶シリコンなどからなる副ビット線２２７および配線層２４１が形成されることになる。
【０５３０】
以上のように、この実施例によれば、ソース線２２３ａの幅の違いおよびドレイン部の幅の違いを利用して、ソース線コンタクト部２３９の形成とドレインコンタクト部２４０の形成とを同時に行なうことが可能となる。また、それぞれのコンタクトホール形成のためのマスクも必要としないため、工程の簡略化および製造コストの低減が可能となる。
【０５３１】
（１５） 第１５実施例
次に、図１０７を用いて、この発明に従った不揮発性半導体記憶装置の第１５実施例について説明する。図１０７（ａ）は、ダミーメモリトランジスタを形成しない場合の副ビット線２２７形成後の不揮発性半導体記憶装置の断面図であり、図１０７（ｂ）は、ダミーメモリトランジスタを形成した場合、つまり不揮発性半導体記憶装置の第１５実施例の断面図である。まず図１０７（ａ）を参照して、副ビット線２２７の一方端は選択ゲートトランジスタ２３４上で切れており、他方端は、フィールド酸化膜２０６上で切れている。このような場合には、コンタクトエッチング時などにフィールド酸化膜２０６が膜減りし、分離特性が劣化するといった問題点がある。
【０５３２】
そこで、第１５実施例においては、このフィールド酸化膜２０６上にダミーメモリトランジスタ２４２ｂを形成している。それにより、素子間の分離耐圧を劣化させることなくかつ副ビット線２２７における段差も低減することが可能となる。このように、第１５実施例においては、ダミーメモリトランジスタ２４２ｂをフィールド酸化膜２０６上に形成したが、図１０７（ｂ）に示されるように、ダミーメモリトランジスタ２４２ａを、ｐ型シリコン基板２０１上に直接形成してもよい。それにより、ダミーゲート２４２とｐ型シリコン基板２０１との間でＦＮトンネリングを用いて電子の注入を行なうことが可能となる。それにより、フィールドシールド効果を持たせることが可能となる。また、このダミーメモリトランジスタ２４２ａを挟む副ビット線２２７を用いて、チャネルホットエレクトロンによってダミーゲート２４２に電子を注入することも可能である。それによっても、上記の場合と同様のフィールドシールド効果が期待できる。
【０５３３】
（１６） 第１６実施例
次に、図１０８〜図１１９を用いて、この発明に従った不揮発性半導体記憶装置の第１６実施例について説明する。図１０８は、この発明に従った第１６実施例における不揮発性半導体記憶装置のメモリトランジスタ部の部分断面図である。図１０９は、図６９におけるＦ−Ｆ線に沿ってみた断面に対応する断面図である。図１１０〜図１１９は、本実施例における不揮発性半導体記憶装置の製造工程の第１０工程〜第１９工程を示す断面図である。
【０５３４】
前述の各実施例においては、ソース領域上に位置するフィールド酸化膜２０６をエッチング除去し、この状態でソース領域に砒素（Ａｓ）などを注入することによってソース線を形成していた。しかし、この場合には、次に説明するような問題点が考えられる。フィールド酸化膜２０６直下には、素子間の分離特性を向上させるために、予めボロン（Ｂ）などがフィールド酸化膜２０６越しに注入されている。したがって、上記のように、フィールド酸化膜２０６をエッチングした後にソース線形成のための砒素（Ａｓ）を注入した場合には、フィールド酸化膜２０６越しに予め注入されているボロン（Ｂ）と、ソース線形成のために注入された砒素（Ａｓ）とがオーバラップする部分が生じることとなる。それにより、その重なる部分において、キャリア濃度が相殺され、ソース耐圧が低くなるといった問題点が考えられる。
【０５３５】
そこで、本実施例においては、ソース線形成のために、各ソース領域を電気的に接続するような不純物の導入された多結晶シリコンなどからなる配線層を形成することとしている。それにより、フィールド酸化膜２０６上にその配線層を形成することができるため、ソース線形成領域上に位置するフィールド酸化膜２０６を取除く必要がなくなる。それにより、上記のような不純物領域の重なりをなくすことができ、ソース耐圧が低下するのを防止することが可能となる。
【０５３６】
以下に、図を用いて、本実施例について、より具体的に説明する。まず、図１０８を参照して、本実施例における特徴部分となるのは、ワード線方向に散在する各ソース領域２２３を電気的に接続する配線層２６２が形成されていることである。それ以外の構造は、上記の各実施例と同様である。この配線層２６２は、この場合であれば、多結晶シリコンなどで形成されている。
【０５３７】
この配線層２６２は、フィールド酸化膜２０６で分離されている各ソース領域２２３を互いに接続している。したがって、図１０９に示されるように、ソース領域２２３上およびソース領域２２３に挟まれたフィールド酸化膜２０６上に、配線層２６２は延在している。このように、配線層２６２を備えることにより、各ソース領域２２３を電気的に接続することができるため、フィールド酸化膜２０６の一部をエッチング除去する必要がなくなる。それにより、上述したように、ソース線耐圧が低下するのを防止することが可能となる。
【０５３８】
次に、図１１０〜図１１９を用いて、上記の構造を有する不揮発性半導体記憶装置の製造方法について説明する。まず図１１０を参照して、上記の第２の実施例と同様の工程を経て、高温酸化膜２１７、導電膜２１６、ＯＮＯ膜２１５、第１の多結晶シリコン膜２１４をエッチングする。それにより、フローティングゲート電極２１９およびコントロールゲート電極２２０が形成される。そして、レジスト２１８ａを除去する。
【０５３９】
次に、図１１１に示されるように、選択ゲートトランジスタのみを露出させるようにレジストパターン２２１ａを形成する。そして、このレジストパターン２２１ａをマスクとして用いて、リン（Ｐ）を６０ＫｅＶ，３．０×１０１３ｃｍ−２の条件でイオン注入する。それにより、選択ゲートトランジスタのソース／ドレイン領域２２３，２２４を形成する。その後、上記のレジスト２２１ａを除去する。
【０５４０】
次に、図１１２を参照して、選択ゲートトランジスタとなるトランジスタを覆い、他のメモリトランジスタを露出させるようにレジストパターン２２１ｂを形成する。そして、このレジストパターン２２１ｂをマスクとして用いて、３５ＫｅＶ，５．５×１０１５ｃｍ−２の条件で、砒素（Ａｓ）をイオン注入する。それにより、メモリトランジスタのソース／ドレイン領域が形成される。その後、レジスト２２１ｂを除去する。
【０５４１】
次に、図１１３を参照して、メモリトランジスタ領域にＣＶＤ法を用いて、２０００Å程度の膜厚を有する高温酸化膜を形成する。そして、この高温酸化膜を異方性エッチングすることによって、選択ゲートトランジスタの側壁あるいはメモリトランジスタの側壁にサイドウォール２２５を形成する。そして、このサイドウォール２２５をマスクとして用いて、３５ＫｅＶ，４．０×１０１５ｃｍ−２の条件で、砒素（Ａｓ）をイオン注入する。それにより、周辺部のトランジスタのソース／ドレイン領域およびソース領域２２３、ドレイン領域２２４を形成する。
【０５４２】
次に、図１１４を参照して、メモリトランジスタ領域に、ＴＥＯＳ（Ｔｅｔｒａｅｔｈｙｌ Ｏｒｔｈｏ Ｓｉｌｉｃａｔｅ）膜などからなるシリコン酸化膜２２６を堆積する。そして、３０分程度の酸化膜のシンタ処理を行なう。その後、ソース領域２２３上に位置するシリコン酸化膜２２６を露出させるようにレジストパターン２６１を形成する。そして、このレジストパターン２６１をマスクとして用いて、ソース領域２２３上に位置するシリコン酸化膜２２６、サイドウォール２２５の一部をエッチングする。それにより、図１１５に示されるように、ソース領域２２３上に位置する領域にコンタクトホール２６８を形成する。そして、レジスト２６１を除去する。
【０５４３】
次に、図１１６を参照して、ＣＶＤ法などを用いて、上記のコンタクトホール２６８内表面およびシリコン酸化膜２２６上に、多結晶シリコン層２６２を形成する。そして、この多結晶シリコン層２６２上に、ＣＶＤ法などを用いて、酸化膜２６３を形成する。そして、ソース領域２２３上に位置する酸化膜２６３上に、レジストパターン２６４を形成する。このとき、レジストパターン２６４の端部は、ソース側に位置するフローティングゲート電極２１９、コントロールゲート電極２２０の端部上に位置するようにする。それにより、多結晶シリコン層２６２と副ビット線２２７との距離を離すことができ、多結晶シリコン層２６２と副ビット線２２７との所望の耐圧を確保することができる。さらに、コントロールゲート電極２２０と多結晶シリコン層２６２間の耐圧も所望の値とすることができる。
【０５４４】
そして、図１１７に示されるように、上記のレジストパターン２６４をマスクとして用いて酸化膜２６３および多結晶シリコン層２６２をエッチングする。それにより、ワード線方向に散在する各ソース領域２２３を電気的に接続する配線層２６２が形成されることになる。
【０５４５】
次に、図１１８を参照して、レジスト２６４を除去した後、酸化膜２２６，２６３上に、ＣＶＤ法などを用いて酸化膜２６５を形成する。そして、ドレイン拡散領域２２４上に位置する酸化膜２６５を露出させるようにレジストパターン２６６を形成する。そして、このレジストパターン２６６をマスクとして用いて、ドレイン領域２２４上に位置する各酸化膜２６５，２２６をエッチング除去する。それにより、ドレイン領域２２４の一部が露出することになる。
【０５４６】
その後、図１１９を参照して、上記のレジスト２６６を除去した後、ＣＶＤ法などを用いて、２０００Å程度の膜厚を有する多結晶シリコン層を形成し、この多結晶シリコン層に不純物を導入することによって導電性をもたせる。そして、この多結晶シリコン層上に所定形状のレジスト２２８を塗布し、このレジスト２２８をマスクとして上記の多結晶シリコン層をパターニングすることによって、副ビット線２２７が形成される。以下、前記の第２の実施例と同様の工程を経て不揮発性半導体記憶装置が形成されることになる。
【０５４７】
（１７） 第１７実施例
次に、図１２０〜図１２５および図１５６〜図１５９を用いて、本発明に基づく第１７実施例について説明する。図１２０は、本発明に従った第１７実施例における不揮発性半導体記憶装置の部分断面図である。図１２１〜図１２５は、図１２０に示される不揮発性半導体記憶装置の製造工程の第１工程〜第５工程を示す図である。図１５６は、上記の第１７実施例における不揮発性半導体記憶装置の従来構造を示す平面図（ａ）および（ａ）におけるＢ−Ｂ線に沿って見た断面図（ｂ）を示す図である。図１５７は、図１５６に示される従来の不揮発性半導体記憶装置の書込動作を説明するための部分断面図である。図１５８は、図１５６に示される不揮発性半導体記憶装置の消去動作を説明するための部分断面図である。図１５９は、図１５６に示される従来の不揮発性半導体記憶装置における問題点を説明するための部分断面図である。
【０５４８】
まず、図１５６〜図１５９を用いて、本発明に基づく第１７実施例における不揮発性半導体記憶装置の従来の構造について説明する。図１５６（ａ）および図１５６（ｂ）を参照して、このタイプの不揮発性半導体記憶装置は、一般的に、バーチャルグランド構成のメモリセルアレイ（Ｖｉｒｔｕａｌ Ｇｒｏｕｎｄ
Ａｒｒａｙ）を有する不揮発性半導体記憶装置と呼ばれている。
【０５４９】
図１５６（ｂ）を参照して、ｐ型半導体基板３０１の主表面には、ビット線として機能するｎ型の高濃度不純物領域３０２ａ，３０２ｂ，３０２ｃ，３０２ｄが互いに略平行に間隔を隔てて形成されている。これらの高濃度不純物領域３０２ａ〜３０２ｄに挟まれた領域上に、絶縁膜３０４を介してフローティングゲート３０５ａ、３０５ｂ、３０５が形成されている。そして、これらのフローティングゲート３０５ａ，３０５ｂ，３０５を覆うように、絶縁膜３０６が形成されている。この絶縁膜３０６表面上に、コントロールゲート３０７が形成されている。コントロールゲート３０７は、図１５６（ａ）を参照して、複数のフローティングゲート３０５上に延在し、高濃度不純物領域３０２ａ〜３０２ｄと略直交する。
【０５５０】
次に、図１５７および図１５８を用いて、上記の構造を有する従来の不揮発性半導体記憶装置の従来の動作について説明する。まず書込動作について説明する。図１５６（ａ）および図１５７を参照して、フローティングゲート３０５ｂに書込みを行なう場合について説明する。フローティングゲート３０５ｂに書込を行なう際には、このフローティングゲート３０５ｂ上を延在するコントロールゲート３０７に１２Ｖ程度の電圧が印加され、ビット線として機能する高濃度不純物領域３０２ｂに５Ｖ程度の電圧が印加される。
【０５５１】
このとき、高濃度不純物領域３０２ａは、フローティング状態に保持される。不純物領域３０２ｃは、接地電位に保持される。それにより、高濃度不純物領域３０２ｂから高濃度不純物領域３０２ｃに電流が流れる。このときに、フローティングゲート３０５ｂに電子が注入されることになる。それにより、フローティングゲート３０５ｂに書込が行なわれる。
【０５５２】
次に、消去動作について説明する。各フローティングゲート３０５，３０５ａ，３０５ｂに書込まれた情報を消去する際には、各コントロールゲート３０７が接地電位に保持され、各高濃度不純物領域３０２ａ〜３０２ｄに１０Ｖ程度の電圧が印加される。それにより、各フローティングゲート３０５，３０５ａ，３０５ｂから同時に電子が引き抜かれ、書込まれた情報が消去されることになる。この様子が、図１５８に示されている。
【０５５３】
以上のような構成を有し、動作を行なう従来のバーチャルグランド構成のメモリセルアレイを有する不揮発性半導体記憶装置に本発明に従った動作を行なわせた場合には、次に説明するような問題点が生じることとなる。その問題点について、図１５９を用いて説明する。
【０５５４】
従来のバーチャルグランド構成のメモリセルアレイを有する不揮発性半導体記憶装置に本発明に従った動作を行なわせた場合には、本発明に従った書込動作を行なった際に問題点が生じることとなる。図１５９を参照して、本発明に従った書込動作を行なわせることによってたとえばフローティングゲート３０５ａに情報を書込むには、選択されたコントロールゲート３０７に、たとえば−８Ｖ程度の電圧が印加される。このとき、選択されたビット線、この場合であれば、ビット線として機能する高濃度不純物領域３０２ｂに５Ｖ程度の電圧が印加される。そして、非選択のビット線、この場合であれば、高濃度不純物領域３０２ａ，３０２ｃ，３０２ｄは、接地電位に保持される。
【０５５５】
それにより、図１５９において矢印で示されるように、フローティングゲート３０５ａから電子が引き抜かれると同時に、フローティングゲート３０５ａと隣接するフローティングゲート３０５ｂからも電子が引き抜かれることになる。それは、高濃度不純物領域３０２ｂの一方の端部がフローティングゲート３０５ａと部分的に重なり、他方の端部がフローティングゲート３０５ｂと部分的に重なるように形成されているからである。
【０５５６】
このように、高濃度不純物領域３０２ｂと、フローティングゲート３０５ａおよびフローティングゲート３０５ｂが部分的に重なるような位置関係に形成されることによって、その重なった部分において、ＦＮ現象によってそれぞれのフローティングゲート３０５ａ，３０５ｂから電子が引き抜かれてしまう。すなわち、両方のフローティングゲート３０５ａ，３０５ｂに情報が書込まれたことになる。その結果、不揮発性半導体記憶装置の誤動作を引き起こすといった問題点が生じることとなる。
【０５５７】
本実施例における不揮発性半導体記憶装置は、上記のような問題点を解決するために考案されたものである。以下、本実施例における不揮発性半導体記憶装置の構造および動作について、図１２０〜図１２５を用いて説明する。
【０５５８】
図１２０を参照して、本実施例におけるバーチャルグランド構成のメモリセルアレイを有する不揮発性半導体記憶装置は、ビット線として機能する高濃度不純物領域３０２ａ，３０２ｂ，３０２ｃ，３０２ｄの一方の端部は、フローティングゲート３０５の下に位置し、他方の端部は、隣接するフローティングゲート３０５の下には位置しないように形成されている。高濃度不純物領域３０２ａ，３０２ｂ，３０２ｃ，３０２ｄの濃度は、好ましくは、１０２０／ｃｍ３ 以上である。
【０５５９】
より具体的には、図１２０を参照して、高濃度不純物領域３０２ｂの一方端はフローティングゲート３０５ａの下に位置するが、このフローティングゲート３０５ａと隣接するフローティングゲート３０５ｂと不純物領域３０２ｂとは重ならないようにオフセットされている。それ以外の構造に関しては、図１５６（ｂ）に示される従来の構造とほぼ同様である。
【０５６０】
このように、高濃度不純物領域３０２ｂの端部を隣接するフローティングゲート３０５ｂと重ならないように形成することによって、たとえばフローティングゲート３０５ａに本発明に従った書込動作を行なう際に、隣接するフローティングゲート３０５ｂから電子が引き抜かれるといった状況を回避することが可能となる。それにより、より確実に情報の書込を行なうことが可能となる。
【０５６１】
次に、図１２１〜図１２５を用いて、図１２０に示される構造を有する本実施例における不揮発性半導体記憶装置の製造方法について説明する。まず図１２１（ａ）および（ｂ）を参照して、ｐ型半導体基板３０１主表面上に、１００Å程度の膜厚を有する絶縁膜３０４を形成する。そして、この絶縁膜３０４上に、ＣＶＤ法などを用いて、１０００Å程度の膜厚を有する第１多結晶シリコン層３０５ｃを堆積する。
【０５６２】
この第１多結晶シリコン３０５ｃ上に、所望の膜厚を有するレジスト３０８を塗布する。このレジスト３０８を所定形状にパターニングする。このパターニングされたレジスト３０８をマスクとして用いて、エッチングすることによって第１多結晶シリコン層３０５ｃをパターニングする。
【０５６３】
次に、図１２２（ａ）を参照して、上記の第１多結晶シリコン層３０５ｃをパターニングした後、レジスト３０８をマスクとして用いて、砒素（Ａｓ）などのｎ型の不純物をｐ型半導体基板３０１の主表面にイオン注入する。このとき、不純物の注入角度を所定角度θだけ傾ける。それにより、レジスト３０８によるシャドーイング効果によって、ｐ型半導体基板３０１の主表面に、隣合うフローティングゲートのうち一方にのみその端部が部分的に重なるように高濃度不純物領域３０２ａ〜３０２ｄを形成することが可能となる。
【０５６４】
上記の傾斜角度θの値は、好ましくは、約７°である。このようにして、θの角度だけ鉛直方向に対して角度を持たせて砒素（Ａｓ）をイオン注入することによって、レジスト３０８に従ってパターニングされた隣り合う第１多結晶シリコン層３０５ｃのうち、一方の第１多結晶シリコン層３０５ｃとは重なるが他方の第１多結晶シリコン層３０５ｃとはオフセットされた高濃度不純物領域３０２ａ〜３０２ｄが形成されることになる。この状態を平面的に見た様子が図１２２（ｂ）に示されている。
【０５６５】
次に、図１２３を参照して、レジスト３０８を除去した後、ＣＶＤ法などを用いて、第１多結晶シリコン層３０５ｃを覆うように酸化膜３０９を形成する。そして、この酸化膜３０９をエッチバックすることによって、酸化膜３０９を第１多結晶シリコン層３０５ｃの間に埋込む。
【０５６６】
次に、図１２４を参照して、ＣＶＤ法などを用いて、上記の酸化膜３０９上および第１多結晶シリコン層３０５ｃ上に、絶縁膜３０６を形成する。この絶縁膜３０６上に、ＣＶＤ法などを用いて、所定膜厚の第２多結晶シリコン層３０７ａを堆積する。その後、図１２５（ａ）を参照して、上記の第２多結晶シリコン層３０７ａ上にレジスト３１０を塗布し、このレジスト３１０を所定形状にパターニングする。この場合であれば、図１２５（ｂ）を参照して、高濃度不純物領域３０２ａ〜３０２ｄと略直交する方向にレジスト３１０をパターニングする。このようにパターニングされたレジスト３１０をマスクとして用いてエッチングすることによって、図１２５（ａ）に示されるように、コントロールゲート３０７，フローティングゲート３０５ａ，３０５ｂ，３０５および絶縁膜３０６を形成する。その後、レジスト３１０を除去する。以上の工程を経て、図１２０に示される不揮発性半導体記憶装置が完成する。
【０５６７】
次に、図１２６を用いて、図１２０に示された上記の第１７実施例の他の態様について説明する。図１２０に示される不揮発性半導体記憶装置においては、高濃度不純物領域３０２ａ〜３０２ｄのみが形成されていた。しかし、本実施例においては、書込動作に関与するｎ型の高濃度不純物領域３０２ａ〜３０２ｄを上記の第１７実施例と同様の方法を用いて形成し、さらに、ｎ型の低濃度不純物領域３０３を形成している。このように低濃度不純物領域３０３を設けることによって、不揮発性半導体記憶装置の動作特性を向上させることが可能となる。この低濃度不純物領域３０３の形成方法としては、砒素（Ａｓ）などのｎ型の不純物を、従来例と同様の注入角度で半導体基板３０１の主表面にイオン注入することによって形成される。
【０５６８】
注入条件の一例としては、低濃度不純物領域３０３の形成には、注入量１０１１／ｃｍ２ 以上の量の砒素（Ａｓ）を注入する。それにより、形成される低濃度不純物領域３０３の濃度は、１０１６／ｃｍ３ 以上の濃度を有するものとなる。また、このとき、高濃度不純物領域３０２ａ〜３０２ｄの形成に際しては、砒素（Ａｓ）の注入量は、好ましくは、１０１５／ｃｍ２ 以上である。それにより、高濃度不純物領域３０２ａ〜３０２ｄの濃度は、１０２０／ｃｍ３ 以上のものとなる。
【０５６９】
次に、図１２７を参照して、本発明を要約する。図１２７は、本発明に従った不揮発性半導体記憶装置の必須の構成を示した模式図である。図１２７を参照して、半導体基板４０１の主表面には、間隔を隔てて不純物領域４０２ａ，４０２ｂが形成されている。この不純物領域４０２ａ，４０２ｂの間のチャネル領域４０９上には絶縁膜４０３が形成されている、この絶縁膜４０３上にはフローティングゲート４０４が形成されている。このフローティングゲート４０４が電子蓄積手段となる。フローティングゲート４０４上には絶縁膜４０５を介してワード線４０６が形成される。ワード線４０６上には層間絶縁膜４０７が形成され、この層間絶縁膜４０７上にはビット線４０８が形成される。ビット線４０８は、層間絶縁膜４０７に設けられたコンタクトホール４１０を介して不純物領域４０２ａと電気的に接続されている。
【０５７０】
以上の構成を有する不揮発性半導体記憶装置において、本発明に従った特徴的な動作が行なわれることになる。まず、本発明に従った不揮発性半導体記憶装置の特徴的な動作においては、初期状態は消去状態となる。すなわち、フローティングゲート４０４に電子が蓄積された状態が消去状態（初期状態）となる。フローティングゲート４０４に電子を蓄積する方法としては、まずビット線４０８をフローティング状態に保持し、半導体基板４０１にたとえば−１０Ｖ程度の電圧を印加する。このとき、ワード線４０６に１０Ｖ程度の電圧を印加する。それにより、チャネル領域４０９全面でのＦＮ現象（チャネルＦＮ）によって、フローティングゲート４０４内に電子を注入することが可能となる。このとき、消去状態のメモリトランジスタのしきい値電圧Ｖｔｈ（Ｅ）は、読出時にワード線４０６に印加される電圧ＶＲｅａｄよりも高い値となっている。
【０５７１】
上記のようにまず消去状態とした後、所定のメモリトランジスタから電子を引き抜くことによって情報の書込が行なわれることになる。書込みの際には、ビット線４０８に５Ｖ程度の電圧を印加する。このとき、半導体基板４０１は接地電位に保たれる。そして、ワード線４０６に−１０Ｖ程度の電圧を印加する。それにより、フローティングゲート４０４から電子が引き抜かれることになる。このとき、電子の引き抜きは、フローティングゲート４０４と不純物領域４０２ａとの重なり部分でのＦＮ現象によって行なわれることになる。その結果、書込後のメモリトランジスタのしきい値電圧Ｖｔｈ（ｐ）は、読出時のワード線４０６に印加される電圧ＶＲｅａｄよりも小さい値となる。
【０５７２】
以上説明したように、本発明に従った不揮発性半導体記憶装置の動作においては、メモリトランジスタに電子を注入した状態が消去状態となっており、すべてのメモリトランジスタのうち所定のメモリトランジスタから電子を引き抜くことによって情報が書込まれることになる。なお、上記の各実施例においては、本発明を不揮発性半導体記憶装置に適用した場合について説明した。しかし、本発明は、不揮発性半導体記憶装置以外の半導体記憶装置にも適用可能である。
【０５７３】
【発明の効果】
この発明によれば、メモリセルがセクタに分割され、ビット線を主副ビット線構成としており、消去単位を小さくすることができ、消去時の電圧発生回路負荷を軽減することができ、また、消去用およびプログラム用に電子移動手段を設けており、ビット毎にメモリセルのしきい値電圧の制御を行うことができる。また、ソース線を介することなく消去およびプログラムを実行することができる。
【図面の簡単な説明】
【図１】第１〜第１１の実施例におけるプログラムおよび消去動作としきい値電圧との関係を従来例と比較して示す図である。
【図２】第１〜第１１の実施例における消去状態およびプログラム状態を従来例と比較して示す図である。
【図３】第１〜第１１の実施例における一括消去時のしきい値電圧を示す図である。
【図４】第１〜第１１の実施例における一括消去動作によるしきい値電圧の変化を示す図である。
【図５】第１の実施例によるフラッシュメモリの全体の構成を示すブロック図である。
【図６】第１の実施例におけるプログラム時および消去時のメモリセルへの電圧印加条件を示す図である。
【図７】第１の実施例における一括消去動作時、プログラム動作時および読出動作時の電圧印加条件を示す図である。
【図８】第１の実施例における書換動作を説明するためのフローチャートである。
【図９】第２の実施例におけるプログラム時および消去時のメモリセルへの電圧印加条件を示す図である。
【図１０】第２の実施例における一括消去動作時、プログラム動作時および読出動作時の電圧印加条件を示す図である。
【図１１】第３の実施例によるフラッシュメモリの全体の構成を示すブロック図である。
【図１２】図１１のフラッシュメモリの含まれるＸデコーダの構成を示すブロック図である。
【図１３】第３の実施例におけるプログラム時および消去時のメモリセルへの電圧印加条件を示す図である。
【図１４】第３の実施例における一括消去動作時、プログラム動作時および読出動作時の電圧印加条件を示す図である。
【図１５】第４の実施例におけるページ一括消去動作時、プログラム動作時および読出動作時の電圧印加条件を示す図である。
【図１６】第４の実施例における書換動作を説明するためのフローチャートである。
【図１７】第５の実施例におけるページ一括消去動作時、プログラム動作時および読出動作時の電圧印加条件を示す図である。
【図１８】第６の実施例によるフラッシュメモリの全体の構成を示すブロック図である。
【図１９】図１８のフラッシュメモリに含まれるメモリアレイおよびそれに関連する部分の詳細な構成を示す回路図である。
【図２０】第６の実施例におけるプログラム時および消去時のメモリセルへの電圧印加条件を示す図である。
【図２１】第６の実施例におけるセクタ一括消去動作時、プログラム動作時および読出動作時の電圧印加条件を示す図である。
【図２２】第６の実施例におけるプログラム動作およびベリファイ動作を説明するためのフローチャートである。
【図２３】第６の実施例によるフラッシュメモリに用いられるメモリセルの構造を示す断面図である。
【図２４】第６の実施例における２つの隣接したメモリセルの構造図である。
【図２５】第６の実施例におけるメモリセルアレイのレイアウト図である。
【図２６】図６の実施例のメモリセルアレイにおいて与えられる電圧を示す回路図である。
【図２７】高電圧発生回路の等価回路を示す回路図である。
【図２８】第６の実施例によるフラッシュメモリに用いられる高電圧発生回路の一部の構造を示す断面図である。
【図２９】図２８に示した構造において寄生トランジスタが存在することを説明するための断面図である。
【図３０】図２９に示した寄生トランジスタにより構成された回路の等価回路図である。
【図３１】第６の実施例によるフラッシュメモリに用いられる高電圧発生回路の別の構造を示す断面図である。
【図３２】負電圧発生回路の等価回路を示す回路図である。
【図３３】第６の実施例によるフラッシュメモリに用いられる負電圧発生回路の一部の構造を示す断面図である。
【図３４】第７の実施例によるフラッシュメモリに含まれるメモリアレイおよびそれに関連する部分の詳細な構成を示す回路図である。
【図３５】第７の実施例におけるプログラム時の主ビット線の電圧の変化を示す図である。
【図３６】第８の実施例によるフラッシュメモリの全体の構成を示すブロック図である。
【図３７】図３６のフラッシュメモリに含まれるメモリアレイおよびそれに関連する部分の詳細な構成を示す回路図である。
【図３８】ゲートバーズビークがない場合の消去時のメモリセルの状態を説明するための図である。
【図３９】ゲートバーズビークがない場合の消去時の選択セクタのメモリセルおよび非選択セクタのメモリセルへの電圧印加条件を示す図である。
【図４０】ゲートバーズビークがない場合のセクタ一括消去動作時の電圧印加条件を示す図である。
【図４１】ゲートバーズビークがない場合に用いられるソースデコーダの構成を示す回路図である。
【図４２】図４１のソースデコーダの各部の電圧を示す図である。
【図４３】ゲートバーズビークがある場合の消去時のメモリセルの状態を説明するための図である。
【図４４】ゲートバーズビークがある場合の消去時の選択セクタのメモリセルおよび非選択セクタのメモリセルへの電圧印加条件を示す図である。
【図４５】ゲートバーズビークがある場合のセクタ一括消去動作時の電圧印加条件を示す図である。
【図４６】ゲートバーズビークがある場合に用いられるソースデコーダの構成を示す回路図である。
【図４７】図４６のソースデコーダの各部の電圧を示す図である。
【図４８】ウェル電位が低い場合の消去時の選択セクタのメモリセルおよび非選択セクタのメモリセルへの電圧印加条件を示す図である。
【図４９】ウェル電位が低い場合のセクタ一括消去動作時の電圧印加条件を示す図である。
【図５０】ウェル電位が低い場合に用いられるソースデコーダの構成を示す回路図である。
【図５１】図５０のソースデコーダの各部の電圧を示す図である。
【図５２】第９の実施例によるフラッシュメモリの全体の構成を示すブロック図である。
【図５３】図５２のフラッシュメモリに含まれるメモリアレイおよびそれに関連する部分の詳細な構成を示す回路図である。
【図５４】第９の実施例におけるセクタ一括消去動作時の電圧印加条件を示す図である。
【図５５】図５２のフラッシュメモリに含まれるセレクトゲートデコーダおよびソーススイッチの構成を示す回路図である。
【図５６】図５５のセレクトゲートデコーダおよびソーススイッチの各部の電圧を示す図である。
【図５７】第１０の実施例によるフラッシュメモリにおけるプログラム動作を説明するためのフローチャートである。
【図５８】第１１の実施例によるフラッシュメモリにおけるプログラム動作を説明するためのフローチャートである。
【図５９】第１２の実施例によるフラッシュメモリの全体の構成を示すブロック図である。
【図６０】図５９に示したメモリセルアレイおよびその周辺回路の回路図である。
【図６１】図６０に示したワード線とローカルデコーダの出力線との間の接続態様を示す半導体基板上のレイアウト図である。
【図６２】図６０に示した２つのメモリセル１４９１および１４９２の間の分離を示す断面構造図である。
【図６３】図６０に示した２つのメモリセル１４９１および１４９２の間の分離をフィールドシールドトランジスタにより行なう場合の断面構造図である。
【図６４】第１２の実施例において用いられるワード線電圧制御回路およびプリデコーダの回路図である。
【図６５】この発明に従った不揮発性半導体記憶装置の第１３実施例のメモリトランジスタ部の一部の断面図である。
【図６６】（ａ）はこの発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の一部の断面図であり、（ｂ）はその等価回路図である。
【図６７】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタの断面構造図である。
【図６８】図６６（ａ）に示す構造のコントロールゲートを形成した状態までにおける平面図である。
【図６９】図６６（ａ）に示す構造の副ビット線を形成した状態までにおける平面図である。
【図７０】図６６（ａ）に示す構造の主ビット線を形成した状態までにおける平面図である。
【図７１】図６６（ａ）に示す構造のアルミ配線を形成した状態までにおける平面図である。
【図７２】この発明に従った不揮発性半導体記憶装置の第１４実施例の全体の構成の第１の例を示すブロック図である。
【図７３】この発明に従った不揮発性半導体記憶装置の第１４実施例の全体の構成の第２の例を示すブロック図である。
【図７４】この発明に従った不揮発性半導体記憶装置の第１４実施例の全体の構成の第３の例を示すブロック図である。
【図７５】この発明に従った不揮発性半導体記憶装置の第１４実施例の全体の構成の第４の例を示すブロック図である。
【図７６】この発明に従った不揮発性半導体記憶装置の第１４実施例の全体の構成の第５の例を示すブロック図である。
【図７７】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第１工程を示す断面図である。
【図７８】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第２工程を示す断面図である。
【図７９】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第３工程を示す断面図である。
【図８０】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第４工程を示す断面図である。
【図８１】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第５工程を示す断面図である。
【図８２】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第６工程を示す断面図である。
【図８３】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第７工程を示す断面図である。
【図８４】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第８工程を示す断面図である。
【図８５】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第９工程を示す断面図である。
【図８６】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第１０工程を示す断面図である。
【図８７】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第１１工程を示す断面図である。
【図８８】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第１２工程を示す断面図である。
【図８９】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第１３工程を示す断面図である。
【図９０】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第１４工程を示す断面図である。
【図９１】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第１５工程を示す断面図である。
【図９２】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第１６工程を示す断面図である。
【図９３】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第１７工程を示す断面図である。
【図９４】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第１８工程を示す断面図である。
【図９５】この発明に従った不揮発性半導体記憶装置の第１４実施例のメモリトランジスタ部の製造方法の第１９工程を示す断面図である。
【図９６】この発明に従った不揮発性半導体記憶装置の第１４実施例のセレクトゲートコンタクト部の製造方法の第１工程を示す断面図である。
【図９７】この発明に従った不揮発性半導体記憶装置の第１４実施例のセレクトゲートコンタクト部の製造方法の第２工程を示す断面図である。
【図９８】この発明に従った不揮発性半導体記憶装置の第１４実施例のセレクトゲートコンタクト部の製造方法の第３工程を示す断面図である。
【図９９】この発明に従った不揮発性半導体記憶装置の第１４実施例のセレクトゲートコンタクト部の製造方法の第４工程を示す断面図である。
【図１００】この発明に従った不揮発性半導体記憶装置の第１４実施例のセレクトゲートコンタクト部の製造方法の第５工程を示す断面図である。
【図１０１】この発明に従った不揮発性半導体記憶装置の第１４実施例のソース線コンタクト部の平面図である。
【図１０２】この発明に従った不揮発性半導体記憶装置の第１４実施例のソース線コンタクト部の製造方法の第１工程を示す断面図である。
【図１０３】この発明に従った不揮発性半導体記憶装置の第１４実施例のソース線コンタクト部の製造方法の第２工程を示す断面図である。
【図１０４】この発明に従った不揮発性半導体記憶装置の第１４実施例のソース線コンタクト部の製造方法の第３工程を示す断面図である。
【図１０５】この発明に従った不揮発性半導体記憶装置の第１４実施例のソース線コンタクト部の製造方法の第４工程を示す断面図である。
【図１０６】この発明に従った不揮発性半導体記憶装置の第１４実施例のソース線コンタクト部の製造方法の第５工程を示す断面図である。
【図１０７】この発明に従った不揮発性半導体記憶装置の第１５実施例のメモリトランジスタ部の断面図である。
【図１０８】この発明に従った不揮発性半導体記憶装置の第１６実施例のメモリトランジスタ部の一部の断面図である。
【図１０９】図６９におけるＦ−Ｆ線に沿って見た断面に対応する断面を示す図である。
【図１１０】この発明に従った不揮発性半導体記憶装置の第１６実施例のメモリトランジスタ部の製造方法の第１０工程を示す断面図である。
【図１１１】この発明に従った不揮発性半導体記憶装置の第１６実施例のメモリトランジスタ部の製造方法の第１１工程を示す断面図である。
【図１１２】この発明に従った不揮発性半導体記憶装置の第１６実施例のメモリトランジスタ部の製造方法の第１２工程を示す断面図である。
【図１１３】この発明に従った不揮発性半導体記憶装置の第１６実施例のメモリトランジスタ部の製造方法の第１３工程を示す断面図である。
【図１１４】この発明に従った不揮発性半導体記憶装置の第１６実施例のメモリトランジスタ部の製造方法の第１４工程を示す断面図である。
【図１１５】この発明に従った不揮発性半導体記憶装置の第１６実施例のメモリトランジスタ部の製造方法の第１５工程を示す断面図である。
【図１１６】この発明に従った不揮発性半導体記憶装置の第１６実施例のメモリトランジスタ部の製造方法の第１６工程を示す断面図である。
【図１１７】この発明に従った不揮発性半導体記憶装置の第１６実施例のメモリトランジスタ部の製造方法の第１７工程を示す断面図である。
【図１１８】この発明に従った不揮発性半導体記憶装置の第１６実施例のメモリトランジスタ部の製造方法の第１８工程を示す断面図である。
【図１１９】この発明に従った不揮発性半導体記憶装置の第１６実施例のメモリトランジスタ部の製造方法の第１９工程を示す断面図である。
【図１２０】この発明に従った不揮発性半導体記憶装置の第１７実施例を示す部分断面図である。
【図１２１】（ａ）はこの発明に従った不揮発性半導体記憶装置の第１７実施例のメモリトランジスタ部の製造方法の第１工程を示す部分断面図である。（ｂ）はこの場合の平面図である。
【図１２２】（ａ）はこの発明に従った不揮発性半導体記憶装置の第１７実施例のメモリトランジスタ部の製造方法の第２工程を示す部分断面図である。（ｂ）はこの場合の平面図である。
【図１２３】この発明に従った不揮発性半導体記憶装置の第１７実施例のメモリトランジスタ部の製造方法の第３工程を示す部分断面図である。
【図１２４】この発明に従った不揮発性半導体記憶装置の第１７実施例のメモリトランジスタ部の製造方法の第４工程を示す部分断面図である。
【図１２５】（ａ）はこの発明に従った不揮発性半導体記憶装置の第１７実施例のメモリトランジスタ部の製造方法の第５工程を示す部分断面図である。（ｂ）はこの場合の平面図である。
【図１２６】この発明に従った不揮発性半導体記憶装置の第１７実施例の他の態様を示す部分断面図である。
【図１２７】この発明に従った不揮発性半導体記憶装置の特徴的な動作を説明するための模式図である。
【図１２８】従来のフラッシュメモリに用いられるスタックゲート型メモリセルの構造を示す断面図である。
【図１２９】従来のフラッシュメモリにおけるプログラムおよび消去動作としきい値電圧との関係を示す図である。
【図１３０】従来のフラッシュメモリにおけるプログラム時および消去時のメモリセルへの電圧印加条件を示す図である。
【図１３１】従来のフラッシュメモリの全体の構成を示すブロック図である。
【図１３２】図１３１のフラッシュメモリに含まれるＸデコーダの構成を示すブロック図である。
【図１３３】従来のフラッシュメモリにおけるプログラム動作時の電圧印加条件を示す図である。
【図１３４】従来のフラッシュメモリにおける消去前書込動作を説明するためのフローチャートである。
【図１３５】従来のフラッシュメモリにおける一括消去動作を説明するためのフローチャートである。
【図１３６】従来のフラッシュメモリにおける一括消去動作時の電圧印加条件を示す図である。
【図１３７】従来のフラッシュメモリにおける読出動作時の電圧印加条件を示す図である。
【図１３８】従来のフラッシュメモリにおけるプログラム動作時、消去動作時および読出動作時における各線の電圧を示す図である。
【図１３９】従来のフラッシュメモリにおいて消去前書込動作を行なうことなく一括消去動作を行なった場合のしきい値電圧を示す図である。
【図１４０】従来のフラッシュメモリにおいて消去前書込動作を行なった後一括消去動作を行なった場合のしきい値電圧を示す図である。
【図１４１】従来のフラッシュメモリにおける書換動作を説明するためのフローチャートである。
【図１４２】従来のフラッシュメモリにおいて一括消去動作を行なった場合のしきい値電圧の変化を示す図である。
【図１４３】選択トランジスタを含むメモリセルの構造を示す断面図である。
【図１４４】セクタ分割時のディスターブを説明するための図である。
【図１４５】主ビット線および副ビット線を有する従来のフラッシュメモリのメモリセルアレイのレイアウト図である。
【図１４６】従来のフラッシュメモリのメモリセルの構造図である。
【図１４７】従来のフラッシュメモリのメモリセルアレイにおいて与えられる電圧を示す回路図である。
【図１４８】フラッシュメモリの一般的な構成を示すブロック図である。
【図１４９】ＮＯＲ型のメモリセルマトリックスの概略構成を示す等価回路図である。
【図１５０】ＮＯＲ型のメモリトランジスタの断面構造図である。
【図１５１】ＮＯＲ型の平面的配置を示す概略平面図である。
【図１５２】図１５１のＡ−Ａ線に沿う部分断面図である。
【図１５３】ＮＡＮＤ型フラッシュメモリのメモリセルマトリックスの一部の等価回路図である。
【図１５４】ＮＡＮＤ型フラッシュメモリのメモリセルマトリックスの一部の断面図である。
【図１５５】ＮＡＮＤ型フラッシュメモリのメモリトランジスタの断面構造図である。
【図１５６】（ａ）は従来のバーチャルグランド構成のメモリセルアレイを有する不揮発性半導体記憶装置の概略構成を示す平面図である。（ｂ）は（ａ）におけるＢ−Ｂ線に沿って見た断面図である。
【図１５７】図１５６に示される不揮発性半導体記憶装置の従来の書込動作を説明するための図である。
【図１５８】図１５６に示される不揮発性半導体記憶装置の従来の消去動作を説明するための図である。
【図１５９】図１５６に示される従来の不揮発性半導体記憶装置に本発明に従った動作を行なわせた場合の問題点を説明するための図である。
【符号の説明】
８０ 半導体基板
８１ ｎウェル領域
８２ ｐウェル領域
８３ａ、ｂ ソース／ドレイン領域
８４ａ、ｂ ソース領域
８５ａ、ｂ ドレイン領域
８６ セレクトゲートトランジスタ
８７ａ、ｂ、ｃ、ｄ メモリトランジスタ
８８ コントロールゲート
８９ フローティングゲート
９０ 副ビット線
９１ａ、ｂ 分岐線
９２ 主ビット線
９３ ＭＯＳトランジスタ
１００１ Ｐ− 型半導体基板
１００２ ドレイン
１００３ ソース
１００４ 絶縁膜
１００５ フローティングゲート
１００６ コントロールゲート
１００８ Ｐ− ウェル
１０１０，１０ａ メモリアレイ
１０２０ アドレスバッファ
１０３０ Ｘデコーダ
１０４０ Ｙデコーダ
１０５０ Ｙゲート
１０６０ センスアンプ
１０７０ データ入出力バッファ
１０８０ 書込回路
１０９０ Ｖｐｐ／Ｖｃｃ切換回路
１００ ベリファイ電圧発生回路
１１１０ ソース制御回路
１１２０ 制御信号バッファ
１１３０ 制御回路
１１４０ 負電圧制御回路
１２１０，１２２０ 高電圧発生回路
１２３０，１２４０ 負電圧発生回路
１２５０ ウェル電位発生回路
１２６０ セレクトゲートデコーダ
１２７０ ソースデコーダ
１２８１，１２８２ ソーススイッチ
ＢＬ１，ＢＬ２，ＢＬ３ ビット線
ＷＬ０，ＷＬ１，ＷＬ２，ＷＬ３ ワード線
Ｍ１１，Ｍ１２，Ｍ１３，Ｍ２１，Ｍ２２，Ｍ２３，Ｍ３１，Ｍ３２，Ｍ３３メモリセル
ＳＬ ソース線
ＳＥ１，ＳＥ２ セクタ
ＭＢ０，ＭＢ１ 主ビット線
ＳＢ０１，ＳＢ０２，ＳＢ１１，ＳＢ１２ 副ビット線
ＳＬ１，ＳＬ２ ソース線
ＳＧＬ１，ＳＧＬ２ セレクトゲート線
なお、各図中同一符号は同一または相当部分を示す。[0001]
[Industrial applications]
The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to an electrically programmable and erasable nonvolatile semiconductor memory device including a stack gate type memory cell (hereinafter, referred to as a flash memory).
[0002]
[Prior art]
First, the general definitions of erase and program will be described. Erasing refers to changing the threshold voltages of a plurality of memory cells to a predetermined state at once. Programming means changing the threshold voltage of a selected memory cell to another predetermined state. The data "1" is made to correspond to the erased memory cell, and the data "0" is made to correspond to the programmed memory cell.
[0003]
(1) Cross-sectional structure of memory cell (FIGS. 128 and 129)
FIG. 128 shows a cross-sectional structure of a general stack gate type memory cell (memory transistor) used in a conventional flash memory. Two N + type impurity regions are formed on the main surface of the P− type semiconductor substrate 1001 at a predetermined interval. One impurity region forms a drain 1002 and the other impurity region forms a source 1003. On a region of the semiconductor substrate 1001 between the drain 1002 and the source 1003, an insulating film 1004 (about 100 °) made of an extremely thin oxide film or the like is formed. A floating gate 1005 is formed over the insulating film 1004, and a control gate 1006 is formed thereover via an insulating film. Thus, the memory cell has a double gate structure. Note that the P − type semiconductor substrate 1001 may be replaced with a P − well.
[0004]
In a flash memory, information (data) is stored in a memory cell depending on whether electrons are injected into the floating gate 1005 or electrons are emitted from the floating gate 1005.
[0005]
In a state where electrons are injected into the floating gate 1005, the threshold voltage of the memory cell viewed from the control gate 1006 is high, and as shown in FIG. 129, unless the control gate voltage becomes Vg0 or more, the drain 1002 and the source No current flows between 1003. This is because the positive voltage is canceled by the negative charges of the electrons accumulated in the floating gate 1005. This state is called a program state. In this case, data “0” is stored in the memory cell. Since the electrons accumulated in the floating gate 1005 do not disappear semi-permanently as they are, the stored data is also held semi-permanently.
[0006]
In the state where electrons are emitted from the floating gate 1005, the threshold voltage of the memory cell as viewed from the control gate 1006 is low. As shown in FIG. 129, when the control gate voltage becomes Vg1 or more, the drain 1002 and the source Current flows between 1003. This state is called an erase state. In this case, data "1" is stored in the memory cell.
[0007]
By detecting such two states, data stored in the memory cell can be read.
[0008]
(2) Memory cell programming and erasing (FIG. 130)
FIG. 130A shows a voltage application condition at the time of programming of the memory cell, and FIG. 130B shows a voltage application condition at the time of erasing the memory cell.
[0009]
At the time of programming, a write voltage Vw (typically about 6 V) is applied to the drain 1002, a high voltage Vpp (typically about 12 V) is applied to the control gate 1006, and the source 1003 is grounded. Thus, hot electrons due to avalanche breakdown are generated near the drain 1002, or channel hot electrons having high energy are generated in a channel formed in a region between the drain 1002 and the source 1003. Hot electrons accelerated by the high voltage of the control gate 1006 jump over the energy barrier by the insulating film 1004 and are injected into the floating gate 1005 from near the drain. As a result, the threshold voltage of the memory cell increases.
[0010]
At the time of erasing, the drain 1002 is set in a floating state, a high voltage Vpp is applied to the source 1003, and the control gate 1006 is grounded. Thus, a high voltage is generated in the thin insulating film 1004, and electrons are emitted from the floating gate 1005 to the source 1003 by a tunnel phenomenon. As a result, the threshold voltage of the memory cell decreases.
[0011]
Thus, at the time of programming, electrons are injected into the floating gate 1005 by hot electrons. Therefore, as shown in FIG. 130, a P + type impurity region 1002a is provided along the drain 1002 so that a higher electric field is generated in the channel direction or the substrate direction.
[0012]
At the time of erasing, electrons are emitted from the floating gate 1005 to the source 1003 by a tunnel phenomenon. Therefore, at the time of erasing, only an electric field between the floating gate 1005 and the source 1003 is required. It is preferable that the electric field in the channel direction or the substrate direction be small so that a leak current does not occur. Therefore, an N − -type impurity region 1003 a is provided along the source 1003 in order to weaken the electric field in the channel direction or the substrate direction.
[0013]
(3) Overall configuration of flash memory (FIGS. 131 and 132)
FIG. 131 is a block diagram showing the overall configuration of a conventional flash memory.
[0014]
Memory array 1010 includes a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines, and a plurality of memory cells provided at intersections thereof.
[0015]
FIG. 131 shows four memory cells M00, M01, M10, and M11 arranged in two rows and two columns for the sake of simplicity. The drains of the memory cells M00 and M01 are connected to the bit line BL0, and the drains of the memory cells M10 and M11 are connected to the bit line BL1. The control gates of the memory cells M00 and M10 are connected to the word line WL0, and the control gates of the memory cells M01 and M11 are connected to the word line WL1. The sources of the memory cells M00, M01, M10, M11 are connected to a source line SL.
[0016]
Address buffer 1020 receives an externally applied address signal AD, supplies an X address signal to X decoder 1030, and supplies a Y address signal to Y decoder 1040. X decoder 1030 selects one of a plurality of word lines WL0 and WL1 in response to the X address signal. Y decoder 1040 generates selection signals Y0 and Y1 for selecting any of a plurality of bit lines in response to a Y address signal.
[0017]
Y gate 1050 includes Y gate transistors YG0 and YG1 corresponding to bit lines BL0 and BL1. Y gate transistors YG0 and YG1 connect bit lines BL0 and BL1 to sense amplifier 1060 and write circuit 1080 in response to selection signals Y0 and Y1, respectively.
[0018]
At the time of reading, sense amplifier 1060 detects data read on bit line BL0 or bit line BL1, and outputs the same to outside via data input / output buffer 1070. During programming, externally applied data DA is applied to write circuit 1080 via data input / output buffer 1070, and write circuit 1080 applies a write voltage to bit lines BL0 and BL1 according to the data.
[0019]
Vpp / Vcc switching circuit 1090 receives an externally applied high voltage (normally 12 V) and an externally applied power supply voltage Vcc (normally 5 V), and applies a high voltage Vpp or Supply power supply voltage Vcc. Verify voltage generating circuit 1100 receives an externally applied power supply voltage Vcc, and applies a predetermined verify voltage to a selected word line at the time of verification described later. The source control circuit 1110 applies a high voltage Vpp to the source line SL at the time of erasing.
[0020]
Control signal buffer 1120 supplies a control signal CT supplied from the outside to control circuit 1130. The control circuit 1130 controls the operation of each circuit.
[0021]
As shown in FIG. 132, X decoder 1030 includes a decoder circuit 1301 and a plurality of high voltage switches 1302 corresponding to a plurality of word lines WL. Decoder circuit 1301 decodes X address signal XA and generates a selection signal for selecting any one of a plurality of word lines WL. Each high voltage switch 1302 applies a high voltage Vpp or a power supply voltage Vcc to the selected word line WL in response to a control signal SW provided from the control circuit 1130.
[0022]
This flash memory is formed on a chip CH.
(4) Operation of flash memory (FIGS. 133 to 140)
(A) Program operation (Fig. 133)
FIG. 133 is a diagram showing voltage application conditions during a program operation. Here, it is assumed that memory cell M00 is programmed, for example. Control signal for designating a program operation is supplied to control circuit 1130 via control signal buffer 1120. Vpp / Vcc switching circuit 1090 is externally supplied with high voltage Vpp. Vpp / Vcc switching circuit 1090 supplies high voltage Vpp to X decoder 1030 and Y decoder 1040.
[0023]
X decoder 1030 selects word line WL0 in response to an X address signal supplied from address buffer 1020, and applies high voltage Vpp to it.
[0024]
Further, Y decoder 1040 supplies a high voltage selection signal Y0 to Y gate transistor YG0 in response to a Y address signal supplied from address buffer 1020. This turns on the Y gate transistor YG0.
[0025]
Source control circuit 1110 applies 0 V to source line SL. Write circuit 1080 is activated. Thereby, write voltage Vw is applied to bit line BL0.
[0026]
As a result, a voltage is applied to the memory cell M00 as shown in FIG. 130A, and the memory cell M00 is programmed.
[0027]
(B) Erasing operation (FIGS. 134 to 136)
The erase operation includes a pre-erase write operation and a batch erase operation.
[0028]
(I) Write operation before erase (FIG. 134)
Before the memory cells are erased collectively, all the memory cells are programmed by the above method. Thus, the threshold voltages of all the memory cells are increased. This is called a pre-erase write operation.
[0029]
The pre-erase write operation will be described with reference to the flowchart in FIG. First, it is determined whether or not the data of all the memory cells is “0” (step S51). If the data of all the memory cells is not "0", the address specified by the address signal is set to the address 0 (step S52). Then, the memory cell specified by the address signal is programmed by the above-described program operation (step S53).
[0030]
Next, it is determined whether or not the address specified by the address signal is the last address (step S54). If the address is not the last address, the address is incremented by one (step S55), and the program operation is performed (step S53). This operation is continued until the address reaches the final address (steps S53, S54, S55). When the address becomes the last address, the pre-erase write operation ends.
[0031]
(Ii) Batch erase operation (FIGS. 135 and 136)
Next, the batch erase operation will be described with reference to the flowchart in FIG. FIG. 136 shows voltage application conditions at the time of batch erasing.
[0032]
First, a control signal designating batch erase is supplied to the control circuit 1130 via the control signal buffer 1120. At the time of batch erasing, Vpp / Vcc switching circuit 1090 applies high voltage Vpp to source control circuit 1110. The source control circuit 1110 applies the high voltage Vpp to the source line SL (Step S61).
[0033]
The X decoder 1030 grounds the word lines WL0 and WL1. The Y decoder 1040 supplies 0V selection signals Y0 and Y1 to the Y gate transistors YG0 and YG1, respectively. Thereby, the bit lines BL0 and BL1 enter a floating state.
[0034]
As a result, a voltage is applied to all the memory cells as shown in FIG. 130B, and the threshold voltages of all the memory cells decrease.
[0035]
It is difficult to lower the threshold voltages of all the memory cells below a predetermined value only by once applying a high voltage (erase voltage) to the source line SL. Therefore, generally, a high voltage pulse is applied to the source line SL a plurality of times, and an erase verify operation is performed after each pulse application.
[0036]
First, after applying a high voltage pulse to the source line SL (step S61), the source line SL is set to 0 V (step S62), and address 0 is selected (step S63). Then, a predetermined verify voltage lower than the power supply voltage Vcc is applied to the selected word line by the verify voltage generating circuit 1100 (step S64). Thereby, the data of the selected memory cell is read out to the corresponding bit line, and detected by sense amplifier 1060. Then, it is determined whether the data detected by the sense amplifier 1060 is "1" (step S65).
[0037]
If the data detected by sense amplifier 1060 is "0", steps S61 to S64 are repeated.
[0038]
If the data detected by the sense amplifier 1060 is "1", it is determined whether or not the address specified by the address signal is the last address (step S66). If the address is not the last address, the address is incremented by 1 (step S67). Thus, data of all memory cells is read while incrementing the address by one. If the read data is "0", a high voltage pulse is applied to the source line SL to erase the memory cell.
[0039]
In this way, all the memory cells are gradually erased while monitoring the threshold voltage of the memory cells.
[0040]
(C) Read operation (FIG. 137)
FIG. 137 shows voltage application conditions during the read operation. Here, it is assumed that data is read from memory cell M00.
[0041]
First, a control signal designating a read operation is supplied to control circuit 1130 via control signal buffer 1120. X decoder 1030 selects word line WL0 in response to an X address signal supplied from address buffer 1020, and applies power supply voltage Vcc to it. At this time, the potential of the unselected word line is kept at 0V.
[0042]
Y decoder 1040 turns on Y gate transistor YG0 in response to a Y address signal provided from address buffer 1020. Thereby, bit line BL0 is connected to sense amplifier 1060. At this time, 0 V is applied to the source line SL by the source control circuit 1110.
[0043]
As a result, when the threshold voltage of the memory cell M00 is low, the memory cell M00 is turned on. Thereby, current I flows through resistor R in sense amplifier 1060, and read voltage Vr on bit line BL0 decreases. The read voltage Vr on bit line BL0 is output as data "1" via inverter INV2.
[0044]
When the threshold voltage of the memory cell M00 is high, the memory cell M00 is turned off. Thereby, read voltage Vr on bit line BL0 increases. The read voltage Vr on bit line BL0 is output as data "0" via inverter INV2.
[0045]
When the voltage of the bit line at the time of reading becomes close to the power supply voltage Vcc, hot electrons may be generated and the memory cell may be programmed. This is called soft light. In order to prevent this soft write, the read voltage Vr on the bit line is set to about 1 V by the N-channel transistor TR and the inverter INV1.
[0046]
(D) Potential of each line in each operation (FIG. 138)
FIG. 138 shows potentials of a word line, a bit line, and a source line in a program operation, an erase operation, and a read operation. At the time of programming and writing before erasure, the high voltage Vpp is applied to the word line, the write voltage Vw is applied to the bit line, and 0 V is applied to the source line. At the time of batch erasing, the high voltage Vpp is applied only to the source line, 0 V is applied to the word line, and the bit line is in a floating state. At the time of reading, the power supply voltage Vcc is applied to the word line, the source line becomes 0 V, and the read voltage Vr appears on the bit line.
[0047]
(E) Reasons why the pre-erase write operation is required (FIGS. 139 and 140)
Next, the reason why the pre-erase write operation is required at the time of erasure will be described with reference to FIGS. FIG. 139 shows a change in the threshold voltage of the memory cell when the program operation and the batch erase operation are performed. FIG. 140 shows a change in the threshold voltage of the memory cell when the program operation, the pre-erase write operation, and the batch erase operation are performed.
[0048]
In the batch erase operation, as shown in FIG. 130B, the control gate 1006 of the memory cell becomes 0 V, the drain 1002 is in a floating state, and the source 1003 is supplied with the high voltage Vpp. Under such a voltage application condition, a high voltage is generated between the source 1003 and the floating gate 1005, and the electrons stored in the floating gate 1005 are extracted to the source 1003 by the high voltage. As a result, the threshold voltage of the memory cell decreases.
[0049]
However, if this erase operation is performed in a state where the threshold voltage is low (data "1"), the threshold voltage of the memory cell becomes negative as shown in FIG. This is called depletion of the memory cell. Due to the depletion of the memory cells, the following problem occurs during reading.
[0050]
Here, it is assumed that in the read operation shown in FIG. 137, memory cell M00 is selected and memory cell M01 is depleted by batch erasure. That is, the threshold voltage of the memory cell M01 is negative.
[0051]
In this case, the power supply voltage Vcc is applied to the word line WL0, but the potential of the word line WL1 remains at 0V. If the memory cell M00 stores data "0", the memory cell M00 does not turn on even if the potential of the word line WL0 becomes the power supply voltage Vcc. Therefore, no current is generated in bit line BL0.
[0052]
However, when the threshold voltage of the memory cell M01 is negative, the memory cell M01 is turned on even if the potential of the word line WL1 is 0V. As a result, a current is generated in the bit line BL0. In this case, sense amplifier 1060 determines that the data stored in memory cell M00 is "1".
[0053]
As described above, if the threshold voltage of at least one of the memory cells connected to the bit line is negative, a current flows through the bit line even when the memory cell is in a non-selected state. Will flow. Therefore, data stored in the selected memory cell cannot be read accurately.
[0054]
In order to solve such a problem, as shown in FIG. 140, a pre-erase write operation is performed before the batch erase operation. As a result, the threshold voltages of all the memory cells are temporarily set to a high state, and then the collective erase operation is performed. As a result, the voltage of the erased memory cell is unified to a positive value and lower than the power supply voltage Vcc. As described above, the reliability is improved by the pre-erase write operation.
[0055]
Hereinafter, the structure of the conventional flash memory will be described in more detail.
A flash memory exists as a memory device in which data can be freely written and which can be electrically erased. An EEPROM composed of one transistor and capable of electrically erasing written information charges at once, a so-called flash memory is disclosed in U.S. Pat. No. 4,868,619, "An In-System Reprogrammable 32K × 8 CMOS". Flash Memory "by Virgil Niles Kynett et al. , IEEE Journal of Solid-State Circuits, vol. 23, no. 5, October 1988.
[0056]
FIG. 148 is a block diagram showing a general configuration of the flash memory. In the figure, the flash memory includes a memory cell matrix 1, an X address decoder 2, a Y gate 3, a Y address decoder 4, an address buffer 5, a write circuit 6, a sense amplifier 7, and a memory cell matrix 1 arranged in a matrix. , An input / output buffer 8 and a control logic 9.
[0057]
The memory cell matrix 1 has a plurality of memory transistors arranged in a matrix therein. X address decoder 2 and Y gate 3 are connected to select a row and a column of memory cell matrix 1. The Y gate 3 is connected to a Y address decoder 4 for giving column selection information. An address buffer 5 for temporarily storing address information is connected to each of the X address decoder 2 and the Y address decoder 4.
[0058]
The Y gate 3 is connected to a write circuit 6 for performing a write operation at the time of data input and a sense amplifier 7 for determining “0” and “1” from a current value flowing at the time of data output. An input / output buffer 8 for temporarily storing input / output data is connected to the write circuit 6 and the sense amplifier 7, respectively. A control logic 9 for controlling the operation of the flash memory is connected to the address buffer 5 and the input / output buffer 8. The control logic 9 performs control based on a chip enable signal, an output enable signal, and a program signal.
[0059]
FIG. 149 is an equivalent circuit diagram showing a schematic configuration of memory cell matrix 1 shown in FIG. 148. A flash memory having this memory cell matrix is called a NOR type. In the figure, a plurality of word lines WL1, WL2,..., WLi extending in the row direction and a plurality of bit lines BL1, BL2,. I do. Memory transistors Q11, Q12,..., Qij each having a floating gate are arranged at intersections of each word line and each bit line. The drain of each memory transistor is connected to each bit line. The control gate of the memory transistor is connected to each word line. The sources of the memory transistors are connected to source lines S1, S2,. The sources of the memory transistors belonging to the same row are connected to each other as shown in the figure.
[0060]
FIG. 150 is a partial cross-sectional view showing a cross-sectional structure of one memory transistor included in the NOR flash memory as described above. FIG. 151 is a schematic plan view showing a planar arrangement of the NOR type flash memory. FIG. 152 is a partial sectional view taken along line AA of FIG. The structure of the NOR flash memory will be described with reference to these drawings.
[0061]
Referring to FIGS. 150 and 152, an n-type impurity region, for example, a drain region 11 and a source region 12 are formed on main surface of p-type impurity region 10 provided on a silicon substrate at an interval. I have. In a region interposed between the drain region 11 and the source region 12, a control gate 13 and a floating gate 14 are formed so as to form a channel. The floating gate 14 is formed on the p-type impurity region 10 with a thin gate oxide film 15 having a thickness of about 100 ° interposed. The control gate 13 is formed on the floating gate 14 with an interlayer insulating film 16 interposed therebetween so as to be electrically separated from the floating gate 14. Floating gate 14 is formed from polycrystalline silicon. The control gate 13 is composed of a polycrystalline silicon layer or a laminated film of a polycrystalline silicon layer and a refractory metal. Oxide film 17 is formed by depositing the surface of a polycrystalline silicon layer constituting floating gate 14 and control gate 13 by a CVD method. Further, a smooth coat film 21 (see FIG. 152) is formed so as to cover the floating gate 14 and the control gate 13.
[0062]
As shown in FIG. 151, control gates 13 are formed as word lines so as to be connected to each other and extend in the horizontal direction (row direction). The bit line 18 is arranged so as to be orthogonal to the word line 13 and is electrically connected to each drain region 11 through a drain contact 20. As shown in FIG. 152, the bit line 18 is formed on the smooth coat film 21. As shown in FIG. 151, the source region 12 extends in the direction in which the word line 13 extends, and is formed in a region surrounded by the word line 13 and the field oxide film 19. The drain region 11 is also formed in a region surrounded by the word line 13 and the field oxide film 19.
[0063]
The operation of the NOR flash memory configured as described above will be described with reference to FIG.
[0064]
First, in a write operation, a voltage of about 5 V is applied to the drain region 11 and a voltage of about 10 V is applied to the control gate 13. Then, the source region 12 and the p-type impurity region 10 are kept at the ground potential (OV). At this time, a current of several hundred μA flows through the channel of the memory transistor. Among the electrons flowing from the source to the drain, the electrons accelerated in the vicinity of the drain become electrons having high energy in the vicinity of the electrons, that is, so-called channel hot electrons. The electrons are injected into the floating gate 14 by an electric field generated by the voltage applied to the control gate 13 as shown by the arrow (1). In this manner, electrons are stored in floating gate 14, and the threshold voltage Vth of the memory transistor becomes, for example, 8V. This state is called a write state, "0".
[0065]
Next, in the erasing operation, a voltage of about 5 V is applied to the source region 12, a voltage of about -10V is applied to the control gate 13, and the p-type impurity region 10 is kept at the ground potential. Then, the drain region 11 is released. Due to the electric field generated by the voltage applied to the source region 12, the electrons in the floating gate 14 pass through the thin gate oxide film 15 by the FN tunnel phenomenon as shown by the arrow (2). In this way, the electrons in floating gate 14 are extracted, whereby the threshold voltage Vth of the memory transistor becomes, for example, 2V. This state is called an erased state, "1". Since the sources of the respective memory transistors are connected as shown in FIG. 149, all the memories can be collectively erased by this erasing operation.
[0066]
Further, in the read operation, a voltage of about 5 V is applied to the control gate 13 and a voltage of about 1 V is applied to the drain region 11. Then, the source region 12 and the p-type impurity region 10 are kept at the ground potential. At this time, “1” or “0” is determined depending on whether a current flows in the channel region of the memory transistor.
[0067]
That is, in the writing state, Vth is 8 V, so that no channel is formed and no current flows. On the other hand, in the erase state, Vth is 2 V, so that a channel is formed and a current flows.
[0068]
In the NOR type, electrons are injected into the floating gate 14 using channel hot electrons to set the write state to “0”. Since the injection of electrons by channel hot electrons is inefficient, the NOR type has a problem that the power consumption increases.
[0069]
Referring to FIG. 152, for example, when the memory transistor 22a is selected and written, by applying a voltage of about 5 V to the drain region 11 and about 10 V to the control gate 13 as described above, Writing is performed on floating gate 14 of transistor 22a.
[0070]
Next, when the memory transistor 22b is selected and written, the same voltage is applied to the drain region 11 and the control gate 13 in the memory transistor 22b. The memory transistor 22a and the memory transistor 22b share the drain region 11. Therefore, the voltage applied to the drain region 11 when writing to the memory transistor 22b may cause electrons injected into the floating gate 14 of the memory transistor 22a to be drawn out to the drain region 11 by a tunnel phenomenon. This phenomenon is called a drain disturb phenomenon. Due to the drain disturb phenomenon, electrons are extracted from the floating gate of the memory transistor into which the electrons have been injected, so that the memory transistor, which should have been in the written state, becomes in the erased state, causing a malfunction of the flash memory.
[0071]
The NAND type solves the problem of the NOR type. The NAND flash memory is, for example, a PP.NIXEI ELECTRONICS 1992.2.17 (No. 547). 180-181. FIG. 153 is an equivalent circuit diagram of a part of the memory cell matrix of the NAND flash memory. In select gate transistors 39a, 39b, and 39c, one impurity region is connected to a bit line, and the other impurity region is connected to memory transistors 38a, 38b, and 38c.
[0072]
Eight memory transistors 38a arranged in the vertical direction are selected by the select gate transistor 39a, eight memory transistors 38b arranged in the vertical direction are selected by the select gate transistor 39b, and eight memory transistors 38b are arranged in the vertical direction by the select gate transistor 39c. The memory transistors 38c arranged in a line are selected. These memory transistors 38a, 38b, 38c are grounded through select gate transistors 23a, 23b, 23c, respectively.
[0073]
FIG. 154 is a cross-sectional view of a part of the memory cell matrix of the NAND flash memory. Impurity regions 27 are formed at intervals in P-type impurity regions 30 formed in silicon substrate 26. Between each impurity region 27, a memory transistor 38a including a floating gate 29 and a control gate 28 is formed.
[0074]
FIG. 155 is a sectional structural view of the memory transistor 38a. In the p-type impurity region 30 formed on the silicon substrate, an impurity region 27 is formed with a space therebetween. On the p-type impurity region 30 between the impurity regions 27, a gate oxide film 35, a floating gate 29, an interlayer insulating film 36, and a control gate 28 are stacked. Control gate 28 and floating gate 29 are covered with oxide film 37.
[0075]
The operation of the NAND flash memory will be described below with reference to FIGS. First, the write operation will be described. For example, when writing data to the memory transistor 38a having the word line W8, the select gate S2 of the select gate transistor, the bit line B1, the source line and the p-type impurity region 30 are kept at the ground potential, and S1, B2 and B3 are set to about 10V. A voltage is applied, a voltage of about 20 V is applied to the word line W8, and the other word lines W1 to W7 are kept at the ground potential. As a result, as shown by (1) in FIG. 155, in the memory transistor 38a having the word line W8 (control gate 28), electrons in the channel region are injected into the floating gate 29 by the channel FN. This is the write state "0", and at this time, Vth is 3V.
[0076]
Next, the erasing operation will be described. When erasing, a voltage of 20 V is applied to the bit lines, S1, S2 and p-type impurity region 30, and the word lines W1 to W8 are kept at the ground potential. At this time, as indicated by {circle around (2)} in FIG. 155, electrons are extracted from the floating gate 29 of the memory transistor 38a in the write state “0” to the channel region by the channel FN to the erase state “1”. Vth in the erase state "1" is -2V.
[0077]
Next, the read operation will be described. For example, when reading the memory transistor 38a having the word line W8, a voltage of about 1 V is applied to the bit line B1, and the source line and the substrate are kept at the ground potential. Then, the word line W8 is kept at the ground potential, and a voltage of about 5 V is applied to the word lines W1 to W7. Further, a predetermined voltage is applied to the selection gates S1 and S2 to turn on the selection gate transistor.
[0078]
Since the word line W8 is kept at the ground potential (0 V), when the memory transistor 38a having the word line W8 is in the erase state "1", the memory transistor 38a is turned on, and when the write state is "0", the memory transistor 38a is turned on. The transistor 38a is turned off. Since the memory transistor 38a having the word lines W1 to W7 has a voltage of 5 V applied to the word lines W1 to W7, the memory transistor 38a is turned on regardless of the write state "0" and the erase state "1".
[0079]
Therefore, when the memory transistor 38a having the word line W8 is in the erased state "1", referring to FIG. 154, the current passes through the channel formed by each of the word lines W1 to W8, passes through the bit line, and passes through the sense amplifier. It is led to. On the other hand, when the memory transistor 38a having the word line W8 is in the write state "0", no channel is formed depending on the word line W8, so that no current flows to the sense amplifier. When the current is sensed by the sense amplifier, the erase state is determined to be “1”, and when the current is not sensed, the write state is determined to be “0”.
[0080]
Injecting electrons into the floating gate using the channel FN is more efficient than injecting electrons using channel hot electrons. Therefore, the power consumption of the NAND type can be lower than that of the NOR type.
[0081]
Further, the NAND type uses the channel FN at the time of writing and does not apply a high voltage to the drain region of the memory transistor, so that the drain disturb phenomenon can be eliminated.
[0082]
[Problems to be solved by the invention]
(1) Rewriting operation (Fig. 141)
When rewriting the data stored in the memory cell in the above-mentioned conventional flash memory, as shown in FIG. 141, a pre-erase write operation is performed (step S71), and a batch erase operation is performed (step S72). Thereafter, a program operation is performed (step S73).
[0083]
As the capacity of the flash memory increases, the time required for the pre-erase write operation becomes very long. For example, in a 1M-bit flash memory, the time required to program memory cells at all addresses is as long as 1-2 seconds.
[0084]
A long time required for the pre-erase write operation means that a long time is required for rewriting data. This is very inconvenient for the user.
[0085]
(2) Depletion due to over-erasure (Figs. 142 and 143)
As described above, at the time of erasing, by performing a pre-erase write operation before the collective erase operation, the threshold voltages of the memory cells are made substantially the same. However, actually, the erasing characteristics of a plurality of memory cells existing in an erasing unit always have variations.
[0086]
If this variation is very large, as shown in FIG. 142, some memory cells are over-erased and the over-erased memory cells are depleted.
[0087]
In such a depleted memory cell, a current flows even if its control gate is grounded. As a result, data read from the memory cell connected to the same bit line as the depleted memory cell is disturbed by the depleted memory cell, and the data is always determined to be “1”.
[0088]
Such a problem does not exist in a memory cell having a structure as shown in FIG.
[0089]
In FIG. 143, N + -type impurity regions 1302, 1303, and 1310 are formed on a main surface of a P − -type semiconductor substrate 1301 at predetermined intervals. A gate electrode 1304 is formed over a region between impurity regions 1302 and 1303 with an insulating film made of an oxide film interposed therebetween. Thus, a selection transistor 1305 is formed.
[0090]
Floating gate 1307 is formed on impurity region 1303 via an extremely thin oxide film 1306 of about 100 °, and control gate 1308 is formed above it via an insulating film. Thus, a memory transistor 1309 having a two-layer gate structure is formed.
[0091]
The selection transistor 1305 and the memory transistor 1309 form a 1-bit memory cell. Impurity region 1302 is connected to bit terminal B, and gate electrode 1304 is connected to word terminal W. Impurity region 1310 is connected to source terminal S. Control gate 1308 is connected to control gate terminal CG.
[0092]
In the memory cell shown in FIG. 143, since selection transistor 1305 is provided, even if memory transistor 1309 is depleted, the above-described problem does not occur.
[0093]
However, the memory cell of FIG. 143 has a more complicated structure and requires a larger area as compared with the stacked gate memory cell shown in FIG.
[0094]
(3) Disturb between sectors (Fig. 144)
In a conventional flash memory, data rewriting units can be subdivided by dividing a memory array into sectors. In this case, there is a problem that the memory cells in the selected sector affect the memory cells in the non-selected sectors. This is called disturb.
[0095]
For example, as shown in FIG. 144, consider a case where a plurality of memory cells connected to word line WL0 are divided into sectors SE1 and SE2. In this case, when programming the memory cells in the sector SE1, a high voltage is also applied to the control gates of the memory cells in the unselected sector SE2.
[0096]
Also, consider a case where a plurality of memory cells connected to bit line BL0 are divided into sectors SE1 and SE3. In this case, when programming the memory cells in the sector SE1, a high voltage is also applied to the drains of the memory cells in the unselected sector SE3.
[0097]
In any case, even if the disturb occurs about several thousand times, the data can be sufficiently guaranteed. However, since a plurality of sectors exist on the same word line and the same bit line, if the number of rewrites of a memory cell in one sector is set to 10,000, the number of disturbances occurring in other sectors is as follows. .
[0098]
Number of disturbances = (10000 times) x (number of sectors-1)
Thus, when there are a plurality of sectors, the number of disturbances occurring in a certain sector becomes enormous. In recent years, the number of required sector rewrite guarantees is increasing more and more, and disturb between different sectors is a serious problem.
[0099]
(4) Power consumption
When programming a conventional flash memory, electrons are injected into the floating gate by channel hot electrons. Therefore, a large channel current is required at the time of programming. Therefore, the power consumption during programming increases.
[0100]
(5) Degree of integration
On the other hand, US Pat. No. 5,126,808 discloses a conventional flash memory having a main bit line and a sub bit line. In such a flash memory, electron injection by channel hot electrons is used for programming, and a large channel current flows. As a result, the following problems are caused.
[0101]
FIG. 145 is a layout diagram on a semiconductor substrate of a conventional flash memory having a main bit line and a sub bit line. Referring to FIG. 145, a main bit line MB and sub-bit lines SB0 and SB1 are formed in parallel on a semiconductor substrate. Word lines VL0, WL1,... And select gate lines SGL0, SGL1 are formed in a direction perpendicular to these bit lines. A memory cell is formed at a position where each word line and a sub-bit line intersect. For example, memory cells M11, M12,... Are formed at positions where each word line WL0, WL1,. Select gate transistor SG 'for sector selection is formed at a position where main bit line MB and select gate line SGL0 intersect. An N + diffusion layer 1405 is formed in a semiconductor substrate.
[0102]
In the memory cells M11, M12,... Shown in FIG. 145, since programming using channel hot electrons is performed as described above, a large channel current flows through the sub-bit line SB1. Therefore, since this large current flows through select gate transistor SG 'for selecting a sector, it is necessary to select the channel width of select gate transistor SG' to a large value. This means that the select gate transistor SG 'occupies a large area on the semiconductor substrate, and as a result, the degree of integration on the semiconductor substrate is reduced.
[0103]
In addition, in the flash memory shown in FIG. 145, in order to reduce the resistance of main bit line MB and sub-bit lines SB0 and SB1, first and second aluminum wiring layers are formed of sub-bit lines SB0 and SB1 and main bit line SB0 and SB1. It is formed as a bit line MB. Therefore, an aluminum wiring layer cannot be used to reduce the resistance of word lines WL0, WL1,... Formed by the polysilicon layer. As a result, a delay occurs in signal propagation on the word line, and a high operation speed cannot be obtained.
[0104]
FIG. 146 is a structural diagram of a memory cell of a conventional flash memory. Referring to FIG. 146, two memory cells M00 and M10 are separated by a separation oxide film 1402 formed on P well 1008. For example, when programming is performed on memory cell M10, a high voltage of 10V is applied to second aluminum wiring layer 1006 forming the control gate, while a voltage of 5V is applied to drain 1002 'of transistor M10. If the width Wb of the isolation oxide film 1402 is too narrow, a MOS transistor 1403 using this isolation oxide film 1402 as a gate oxide film is equivalently present. The presence of equivalent MOS transistor 1403 prevents desired operation in memory cells M00 and M10. Therefore, width Wb of isolation oxide film 1402 cannot be selected to be a small value in order to prevent the generation of equivalent MOS transistor 1403. This means that the degree of integration in the memory cell array is reduced.
[0105]
FIG. 147 is a circuit diagram showing the operation of the flash memory using a negative voltage. FIG. 147 (a) shows the voltage applied for programming, while FIG. 147 (b) shows the voltage applied for erasing.
[0106]
Referring to FIG. 147 (a), to inject electrons into the floating gate of memory cell M00, a voltage of 5V is applied to bit line BL0, while a negative voltage of -10V is applied to word line WL11. On the other hand, a voltage of 5 V is applied to the unselected word line WL12. In other words, an X decoder not shown needs to output voltages of -10V and 5V.
[0107]
Referring to FIG. 147 (b), in order to erase the data stored in the selected sector SE1, a positive voltage of 10 V is applied to word lines WL11 and WL12, while bit lines BL0 and BL1 have a high impedance. Brought to the state. On the other hand, a negative voltage of -8 V is applied to the word lines WL21 and WL22 in the unselected selector SE2. In other words, an X decoder (not shown) needs to output a positive voltage of 10V and a negative voltage of -8V.
[0108]
Therefore, an X decoder (not shown) needs to output an output voltage having a voltage difference of 15 V in a program operation, and output an output voltage having a voltage difference of 18 V in an erase operation. Therefore, since the voltage difference between the output voltages is large, it is difficult to form the X decoder in a smaller occupied area on the semiconductor substrate.
[0109]
(6) External power supply
At the time of programming, it is necessary to apply a voltage of 5V to 6V to the drain of each memory cell. As described above, programming with channel hot electrons requires a large channel current, and it is very difficult to generate this drain voltage by internal boosting using a single external power supply of 3V or 5V. Even if this is possible, a large number of bits cannot be programmed at the same time, and the programming time is enormous.
[0110]
However, the NAND type has a drawback that the read operation is slow because the read operation is performed by passing a current through eight memory transistors arranged in series.
[0111]
In addition, since a relatively high voltage of 20 V is used for writing and erasing, there is a problem that high integration is difficult.
[0112]
An object of the present invention is to reduce the time required for an erasing operation in a flash memory, thereby shortening the time required for a rewriting operation.
[0113]
Another object of the present invention is to prevent depletion of a stacked gate memory cell due to overerasing.
[0114]
Still another object of the present invention is to prevent disturbance when a memory array is divided into sectors.
[0115]
Still another object of the present invention is to reduce power consumption during programming.
[0116]
Still another object of the present invention is to provide a flash memory operable by a single external power supply.
[0117]
Still another object of the present invention is to provide a nonvolatile semiconductor device which can be operated with low power consumption, can reduce a drain disturb phenomenon, can speed up a read operation, and can lower a maximum voltage. It is to provide a storage device.
[0118]
[Means for Solving the Problems]
Nonvolatile semiconductor memory device according to the first inventionPlace,A plurality of memory cells formed in a well and arranged in rows and columns, a plurality of word lines provided corresponding to the plurality of rows, and a plurality of main bit lines provided corresponding to the plurality of columns And a source line provided commonly to the plurality of memory cells. The plurality of memory cells are divided into a plurality of sectors each having a plurality of memory cells arranged in a plurality of rows and a plurality of columns.
The nonvolatile semiconductor memory device according to the first invention further includes a plurality of sub-bit lines provided corresponding to the plurality of sectors, each including a plurality of sub-bit lines corresponding to a plurality of columns in the corresponding sector. And a plurality of sub-bit line groups for selectively connecting the plurality of sub-bit line groups to the plurality of main bit lines. 1 Connection means. Each of the plurality of memory cells includes a control gate connected to a corresponding word line, a drain connected to a corresponding sub-bit line, a source connected to the source line, and a floating gate.
The nonvolatile semiconductor memory device according to the first invention further comprises: an erasing electron moving means for moving electrons between the floating gates of the plurality of memory cells in the selected sector and the well at the time of erasing; A program electron moving means for moving electrons between the floating gate and the drain end of the selected memory cell, a positive voltage generating means for receiving a power supply voltage from outside and generating a predetermined positive voltage, and Negative voltage generating means for receiving a voltage and generating a predetermined negative voltage. The erasing electron moving unit receives a positive voltage from the positive voltage generating unit and a negative voltage from the negative voltage generating unit, and is provided between each floating gate of a plurality of memory cells corresponding to a selected sector and the well. A voltage is applied to the word line and the well, which is sufficient for electrons to move to the insulating film by a tunnel phenomenon. 1 Voltage applying means. The program electron transfer means applies a voltage between the selected word line and the selected sub-bit line to move electrons between each floating gate and the drain end of the selected memory cell. And a second voltage application unit.
Preferably, each of the plurality of memory cells is not depleted during either erasing or programming.
Instead of this, preferably, each of the plurality of memory cells is not depleted during either erasing or programming, and the threshold voltage of the memory cell during erasing and the memory cell during programming When reading memory cell data, the threshold voltage of the memory cell at the time of erasing is compared with an intermediate value between the threshold voltage of the memory cell at the time of programming. Read means for determining the logic level of the memory cell data is further provided.
[0119]
A nonvolatile semiconductor memory device according to a second aspect of the present invention includes a plurality of memory cells formed in a well and arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided corresponding to the plurality of rows, A plurality of main bit lines provided corresponding to the plurality of columns;,A source line commonly provided to the plurality of memory cells. The plurality of memory cells are divided into a plurality of sectors each including a plurality of memory cells arranged in a plurality of rows and a plurality of columns.
A nonvolatile semiconductor memory device according to a second invention further includes a plurality of sub-bit line groups provided corresponding to the plurality of sectors, each including a plurality of sub-bit lines corresponding to a plurality of columns in the corresponding sector.,First connection means for selectively connecting the plurality of sub-bit line groups to the plurality of main bit lines. Each of the plurality of memory cells includes a control gate connected to a corresponding word line, a drain connected to a corresponding sub-bit line, a source connected to the source line, and a floating gate.
The non-volatile semiconductor storage device according to the second invention further comprises an erasing electron moving means for moving electrons between the floating gates of the plurality of memory cells in the selected sector and the wells during erasing, At the time of programming, a program electron moving means for moving electrons between the floating gate and the drain end of the selected memory cell, a plurality of capacitance means provided corresponding to the plurality of main bit lines, And second connection means for connecting the plurality of capacitance means to each of the plurality of main bit lines.
A nonvolatile semiconductor memory device according to a third aspect of the present invention includes a plurality of memory cells formed in a well and arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided corresponding to the plurality of rows, A plurality of main bit lines provided corresponding to the plurality of columns; and a source line provided commonly to the plurality of memory cells. The plurality of memory cells are divided into a plurality of sectors each including a plurality of memory cells arranged in a plurality of rows and a plurality of columns.
The nonvolatile semiconductor memory device according to the third invention further includes a plurality of sub-bit lines provided corresponding to the plurality of sectors, each including a plurality of sub-bit lines corresponding to a plurality of columns in the corresponding sector. And a first connection means for selectively connecting the plurality of sub-bit line groups to the plurality of main bit lines. Each of the plurality of memory cells includes a control gate connected to a corresponding word line, a drain connected to a corresponding sub-bit line, a source connected to the source line, and a floating gate.
The nonvolatile semiconductor memory device according to the third invention further comprises: an erasing electron moving means for moving electrons between the plurality of memory cells in the selected sector, the floating gate and the well at the time of erasing; Program moving means for moving electrons between the floating gate and the drain end of the selected memory cell.
The source line is divided into a plurality of portions corresponding to the plurality of sectors, and the erasing electron transfer means corresponds to a source line portion corresponding to a selected sector and an unselected sector during erasing. And the potential of the source line to be set are different from each other.
A nonvolatile semiconductor memory device according to a fourth aspect of the present invention includes a plurality of memory cells formed in a well and arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided corresponding to the plurality of rows, The memory device includes a plurality of main bit lines provided corresponding to a plurality of columns, and a source line provided commonly to the plurality of memory cells. The plurality of memory cells are divided into a plurality of sectors each including a plurality of memory cells arranged in a plurality of rows and a plurality of columns.
A nonvolatile semiconductor memory device according to a fourth aspect, wherein a plurality of sub-bit line groups are provided corresponding to the plurality of sectors and each include a plurality of sub-bit lines corresponding to a plurality of columns in the corresponding sector. And first connection means for selectively connecting the plurality of sub-bit line groups to the plurality of main bit lines. Each of the plurality of memory cells includes a control gate connected to a corresponding word line, a drain connected to a corresponding sub-bit line, a source connected to the source line, and a floating gate.
The nonvolatile semiconductor memory device according to the fourth invention further comprises: an erasing electron moving means for moving electrons between the floating gates of the plurality of memory cells in the selected sector and the well at the time of erasing; Floating gate and drain of selected memory cell A program electron transfer unit for transferring electrons between the source and the source line, a capacitor unit, and a second connection unit for connecting the capacitor unit to the source line during erasing.
A nonvolatile semiconductor memory device according to a fifth aspect of the present invention includes a plurality of memory cells formed in a well and arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided corresponding to the plurality of rows, A plurality of main bit lines provided corresponding to the plurality of columns; and a source line provided commonly to the plurality of memory cells. The plurality of memory cells are divided into a plurality of sectors each including a plurality of memory cells arranged in a plurality of rows and a plurality of columns.
A nonvolatile semiconductor memory device according to a fifth aspect of the present invention includes a plurality of sub-bit line groups provided corresponding to the plurality of sectors, each including a plurality of sub-bit lines corresponding to a plurality of columns in the corresponding sector. And first connecting means for selectively connecting the plurality of sub-bit line groups to the plurality of main bit lines. Each of the plurality of memory cells includes a control gate connected to a corresponding word line, a drain connected to a corresponding sub-bit line, a source connected to the source line, and a floating gate.
The nonvolatile semiconductor memory device according to the fifth invention further comprises: an erasing electron moving means for moving electrons between floating gates of a plurality of memory cells in a selected sector and the well at the time of erasing; In some cases, a program electron transfer means for transferring electrons between the floating gate and the drain end of the selected memory cell is provided.
The program electron transfer means precharges a selected main bit line to a predetermined potential in accordance with data and applies a predetermined voltage to a selected word line, and then temporarily grounds a source line. And voltage applying means for applying a negative voltage to the selected multi-word line.
[0120]
【Example】
First, the relationship between the program and erase operations and the threshold voltage in the first to eleventh embodiments described below will be described in comparison with a conventional example.
[0121]
In the conventional example, as shown in FIG. 1B, the threshold voltage of the memory cell is increased by the programming operation, and the threshold voltage of the memory cell is decreased by the erasing operation. On the other hand, in the embodiment, as shown in FIG. 1A, the threshold voltage of the memory cell is decreased by the program operation, and the threshold voltage of the memory cell is increased by the erase operation.
[0122]
That is, in the conventional example, as shown in FIG. 2B, electrons are emitted from the floating gate in the memory cell in the erased state, and the threshold voltage is low. In the memory cell in the programmed state, electrons are injected into the floating gate, and the threshold voltage is high.
[0123]
On the other hand, in the embodiment, as shown in FIG. 2A, in the memory cell in the erased state, electrons are injected into the floating gate, and the threshold voltage is high. In the memory cell in the programmed state, electrons are emitted from the floating gate, and its threshold voltage is low.
[0124]
The point that the erase state corresponds to data "1" and the program state corresponds to data "0" is the same in the embodiment and the conventional example.
[0125]
As described above, in the embodiment, the threshold voltage of each memory cell is increased by the erasing operation. Therefore, as shown in FIG. The threshold voltage can be made higher than the power supply voltage Vcc.
[0126]
In addition, as shown in FIG. 4, even if the threshold voltages of a plurality of memory cells vary, some of the memory cells are not depleted by the batch erase operation.
[0127]
(1) First embodiment (FIGS. 5 to 8)
(A) Overall configuration of flash memory (FIG. 5)
FIG. 5 is a block diagram showing the overall configuration of the flash memory according to the first embodiment. The entire configuration of the flash memory of FIG. 5 is the same as the conventional flash memory of FIG. 131 except that the voltage application conditions in each operation are different. The flash memory of FIG. 5 is also formed on the chip CH.
[0128]
(B) Programming and erasing of memory cells (FIG. 6)
FIG. 6A shows conditions for applying a voltage to a memory cell during programming. FIG. 6B shows conditions for applying a voltage to the memory cell at the time of erasing.
[0129]
At the time of programming, as shown in FIG. 6A, a high voltage Vpp (normally about 12 V) is applied to the drain 1002, 0 V is applied to the control gate 1006, and the source 1003 is brought into a floating state. Accordingly, a high electric field is generated between the floating gate 1005 and the drain 1002, and electrons are emitted from the floating gate 1005 to the drain 1002 by a tunnel phenomenon. As a result, the threshold voltage of the memory cell decreases.
[0130]
At the time of erasing, as shown in FIG. 6B, 0V is applied to the drain 1002, a high voltage Vpp (normally about 12V) is applied to the control gate 1006, and a predetermined high voltage VSL (6V) is applied to the source 1003. Apply. As a result, hot electrons or channel hot electrons are generated near the source 1003 due to avalanche breakdown. These hot electrons are accelerated by the high voltage Vpp of the control gate 1006, jump over the energy barrier by the insulating film 1004, and are injected into the floating gate 1005. As a result, the threshold voltage of the memory cell increases.
[0131]
As described above, electrons are emitted from the floating gate 1005 to the drain 1002 by a tunnel phenomenon at the time of programming. Therefore, an N − -type impurity region 1002 b is provided along the drain 1002 to weaken the electric field in the channel direction or the substrate direction.
[0132]
Further, at the time of erasing, electrons are injected into the floating gate 1005 from the vicinity of the source 1003 by hot electrons. Therefore, a P + -type impurity region 1003b is provided along the source 1003 so that a higher electric field is generated in the channel direction or the substrate direction.
[0133]
Note that the P- well 1008 may be a P- type semiconductor substrate.
(C) Operation of flash memory (Fig. 7)
Next, a batch erase operation, a program operation, and a read operation of the flash memory will be described with reference to FIG. FIG. 7 shows some memory cells M11 to M13, M21 to M23, and M31 to M33 included in the memory array 1010.
[0134]
(I) Batch erase operation ((a) of FIG. 7)
First, a control signal designating a batch erasing operation is supplied to control circuit 1130 via control signal buffer 1120. Vpp / Vcc switching circuit 1090 is externally supplied with high voltage Vpp.
[0135]
Vpp / Vcc switching circuit 1090 applies high voltage Vpp to X decoder 1030. The X decoder 1030 selects all the word lines WL to WL3 and applies a high voltage Vpp to them. Y decoder 1040 turns on all Y gate transistors included in Y gate 1050. Write circuit 1080 applies 0 V to all bit lines BL1 to BL3 via Y gate 1050. Source control circuit 1110 applies a predetermined high voltage VSL (VSL <Vpp) to source line SL.
[0136]
In this way, a voltage is applied to all the memory cells M11 to M33 as shown in FIG. As a result, all the memory cells M11 to M33 are erased.
[0137]
(Ii) Program operation ((b) of FIG. 7)
Here, it is assumed that the memory cell M12 is programmed. That is, data “0” is written to the memory cell M12, and data “1” is written to another memory cell.
[0138]
First, a control signal designating a program operation is supplied to control circuit 1130 via control signal buffer 1120. Vpp / Vcc switching circuit 1090 is externally supplied with high voltage Vpp.
[0139]
X decoder 1030 selects word line WL2 in response to an X address signal supplied from address buffer 1020, applies 0 V to selected word line WL2, and supplies power supply voltage Vcc to unselected word lines WL1 and WL3. Is applied.
[0140]
Vpp / Vcc switching circuit 1090 applies high voltage Vpp to writing circuit 1080. Data is sequentially applied from outside to the write circuit 1080 via the data input / output buffer 1070. At this time, Y decoder 1040 sequentially turns on the Y gate transistors in Y gate 1050 in response to the Y address signal provided from address buffer 1020. Write circuit 1080 applies high voltage Vpp to bit line BL1 via Y gate 1050, and applies power supply voltage Vcc to bit lines BL2 and BL3. The source control circuit 1110 sets the source line SL to a floating state.
[0141]
In this way, a voltage is applied to the memory cell M12 as shown in FIG. At this time, the other memory cells are in one of the following states.
[0142]
(A) The high voltage Vpp is applied to the drain, the power supply voltage Vcc is applied to the control gate, and the source is in a floating state.
[0143]
(B) The power supply voltage Vcc is applied to the drain, 0 V is applied to the control gate, and the source is in a floating state.
[0144]
(C) The power supply voltage Vcc is applied to the drain, the power supply voltage Vcc is applied to the control gate, and the source is in a floating state.
[0145]
As a result, a high electric field is generated only between the floating gate and the drain of the memory cell M12, and only the memory cell M12 is programmed.
[0146]
(Iii) Read operation ((c) in FIG. 7)
The reading operation is almost the same as the operation described with reference to FIG. Here, it is assumed that data is read from memory cell MC12. First, a control signal designating a read operation is supplied to control circuit 1130 via control signal buffer 1120.
[0147]
X decoder 1030 selects word line WL2 in response to an X address signal provided from address buffer 1020, and applies power supply voltage Vcc to it. At this time, the other word lines WL1 and WL3 are kept at 0V. Y decoder 1040 turns on one Y gate transistor in Y gate 1050 in response to a Y address signal provided from address buffer 1020. Source control circuit 1110 grounds source line SL.
[0148]
Thereby, the read voltage Vr appears on the bit line BL1. The read voltage Vr is detected and amplified by the sense amplifier 1060, and output to the outside via the data input / output buffer 1070.
[0149]
(D) Rewriting operation (Fig. 8)
The operation of rewriting data in the flash memory will be described with reference to the flowchart of FIG.
[0150]
First, it is determined whether or not data "1" is stored in all memory cells (step S1). If data "1" is not stored in all the memory cells, a batch erase operation is performed (step S2). Thereafter, a program operation is performed (step S3). Thus, data can be rewritten without performing the pre-write erasing operation as in the conventional example.
[0151]
(E) Modified example
During programming, the unselected bit lines BL2 and BL3 may be in a floating state. At this time, the unselected memory cells are in one of the following states.
[0152]
(A) The high voltage Vpp is applied to the drain, the power supply voltage Vcc is applied to the control gate, and the source is in a floating state.
[0153]
(B) The drain is in a floating state, 0 V is applied to the control gate, and the source is in a floating state.
[0154]
(C) The drain is in a floating state, the power supply voltage Vcc is applied to the control gate, and the source is in a floating state.
[0155]
Also in this case, a high electric field is generated only between the floating gate and the drain of the memory cell M12, and only the memory cell M12 is programmed by a tunnel phenomenon.
[0156]
At the time of programming, the power supply voltage Vcc may be applied to the source line SL. At this time, the high voltage Vpp is applied to the drain of the memory cell M12, 0 V is applied to the control gate, and the power supply voltage Vcc is applied to the source. Other memory cells are in one of the following states.
[0157]
(A) The high voltage Vpp is applied to the drain, the power supply voltage Vcc is applied to the control gate, and the power supply voltage Vcc is applied to the source.
[0158]
(B) The power supply voltage Vcc is applied to the drain, 0 V is applied to the control gate, and the power supply voltage Vcc is applied to the source.
[0159]
(C) The power supply voltage Vcc is applied to the drain, the power supply voltage Vcc is applied to the control gate, and the power supply voltage Vcc is applied to the source.
[0160]
Also in this case, a high electric field is generated only between the floating gate and the drain of the memory cell M12, and only the memory cell M12 is programmed by a tunnel phenomenon.
[0161]
At the time of programming, unselected bit lines BL2 and BL3 may be in a floating state, and power supply voltage Vcc may be applied to source line SL. At this time, the high voltage Vpp is applied to the drain of the memory cell M12, 0 V is applied to the control gate, and the power supply voltage Vcc is applied to the source. The other memory cells are in one of the following states.
[0162]
(A) The high voltage Vpp is applied to the drain, the power supply voltage Vcc is applied to the control gate, and the power supply voltage Vcc is applied to the source.
[0163]
(B) The drain is in a floating state, 0 V is applied to the control gate, and the power supply voltage Vcc is applied to the source.
[0164]
(C) The drain is in a floating state, the power supply voltage Vcc is applied to the control gate, and the power supply voltage Vcc is applied to the source.
[0165]
Also in this case, a high electric field is generated only between the floating gate and the drain of the memory cell M12, and only the memory cell M12 is programmed by a tunnel phenomenon.
[0166]
A verify operation may be performed after the batch erase operation. Further, by applying 0V to the control gates of all the memory cells and applying a high voltage Vpp to the P-well (or the P- type semiconductor substrate) before the batch erase operation, the control gates of all the memory cells are The electrons may be extracted, and then the batch erase operation may be performed while performing the verify operation. This makes it possible to further reduce the variation in the threshold voltage of the collectively erased memory cells.
[0167]
(F) Effect of the first embodiment
In a conventional flash memory, electrons are injected into the floating gate from the drain side. Therefore, when the potential of the bit line increases during the read operation, electrons are injected from the drain into the selected memory cell, and soft writing may occur.
[0168]
On the other hand, in the flash memory of the first embodiment, electrons are injected from the source side into the floating gate. Therefore, during a read operation, soft write is unlikely to occur.
[0169]
The program operation may be performed while performing the verify operation. Thereby, variation in the threshold voltage of the programmed memory cell can be reduced.
[0170]
(2) Second embodiment (FIGS. 9 and 10)
The overall configuration of the flash memory according to the second embodiment is the same as the configuration shown in FIG.
[0171]
(A) Memory cell programming and erasing (FIG. 9)
FIG. 9A shows conditions for applying a voltage to a memory cell during programming. FIG. 9B shows conditions for applying a voltage to the memory cell at the time of erasing. The voltage application conditions at the time of programming are the same as the voltage application conditions shown in FIG.
[0172]
At the time of erasing, as shown in FIG. 9B, 0V is applied to the drain 1002, a high voltage Vpp (normally about 12V) is applied to the control gate 1006, and 0V is applied to the source 1003. Accordingly, a channel ch is formed in a region between the source 1003 and the drain 1002, and a high electric field is generated between the channel ch and the floating gate 1005. Electrons are injected into the floating gate 1005 from the channel ch by a tunnel phenomenon. As a result, the threshold voltage of the memory cell increases.
[0173]
In this embodiment, electrons are emitted from the floating gate 1005 to the drain 1002 by a tunnel phenomenon during programming. Therefore, an N − -type impurity region 1002 c is provided along the drain 1002 to weaken the electric field in the channel direction or the substrate direction.
[0174]
Note that an N − -type impurity region 1003 c may be provided along the source 1003. As described above, when the N− type impurity regions 1002c and 1003c are provided on both the drain side and the source side, the number of manufacturing steps is reduced.
[0175]
(B) Operation of flash memory (FIG. 10)
Next, a batch erase operation, a program operation, and a read operation of the flash memory will be described with reference to FIG. The program operation and the read operation are the same as in the first embodiment. Therefore, the batch erase operation will be described below.
[0176]
First, a control signal designating a batch erasing operation is supplied to control circuit 1130 via control signal buffer 1120. Vpp / Vcc switching circuit 1090 is externally supplied with high voltage Vpp.
[0177]
Vpp / Vcc switching circuit 1090 applies high voltage Vpp to X decoder 1030. X decoder 1030 selects all word lines WL1 to WL3 and applies high voltage Vpp to them. Y decoder 1040 turns on all Y gate transistors included in Y gate 1050. Write circuit 1080 applies 0 V to all bit lines BL1 to BL3 via Y gate 1050. Source control circuit 1110 applies 0 V to source line SL.
[0178]
Thus, a voltage is applied to all the memory cells M11 to M33 as shown in FIG. 9B. As a result, all the memory cells M11 to M33 are erased.
[0179]
Note that a negative voltage may be positively applied to the P- well (or the P- type semiconductor substrate) during the batch erasing operation.
[0180]
Data rewriting is performed according to the procedure shown in FIG. Therefore, data can be rewritten without performing the pre-erase write operation as in the conventional example.
[0181]
(3) Third embodiment (FIGS. 11 to 14)
FIG. 11 is a block diagram showing the overall configuration of the flash memory according to the third embodiment. The flash memory of FIG. 11 differs from the flash memory of FIG. 5 in the following points.
[0182]
Further provided is a negative voltage control circuit 1140 that receives a negative voltage −Vee applied from the outside and generates a predetermined negative voltage. 12, the X decoder 1030 includes a plurality of potential control switches 1303 connected to a plurality of word lines WL, instead of the plurality of high voltage switches 1302 (see FIG. 132). Each potential control switch 1303 applies a high voltage Vpp or power supply voltage Vcc provided from Vpp / Vcc switching circuit 1090 or a negative voltage -Vee provided from negative voltage control circuit 1140 to corresponding word line WL.
[0183]
(B) Memory cell programming and erasing (FIG. 13)
FIG. 13A shows conditions for applying a voltage to a memory cell during programming. FIG. 13B shows conditions for applying a voltage to the memory cell at the time of erasing.
[0184]
At the time of programming, as shown in FIG. 13A, a power supply voltage Vcc (normally about 5 V) is applied to the drain 1002, a negative voltage −Vee (−12 V) is applied to the control gate 1006, and the source 1003 is in a floating state. To Accordingly, a high electric field is generated between the floating gate 1005 and the drain 1002, and electrons are emitted from the floating gate 1005 to the drain 1002 by a tunnel phenomenon. As a result, the threshold voltage of the memory cell decreases.
[0185]
The voltage application conditions at the time of erasing are the same as the voltage application conditions shown in FIG.
[0186]
As described above, electrons are emitted from the floating gate 1005 to the drain 1002 by a tunnel phenomenon at the time of programming. Therefore, an N − -type impurity region 1002 d is provided along the drain 1002 to weaken the electric field in the channel direction or the substrate direction.
[0187]
Further, at the time of erasing, electrons are injected into the floating gate 1005 from the vicinity of the source 1003 by hot electrons. Therefore, a P + -type impurity region 1003d is provided along the source 1003 so that a higher electric field is generated in the channel direction or the substrate direction.
[0188]
(C) Operation of flash memory (FIG. 14)
Next, a batch erase operation, a program operation, and a read operation of the flash memory will be described with reference to FIG. The batch erasing operation and the reading operation are the same as in the first embodiment. Therefore, the program operation will be described below.
[0189]
Here, it is assumed that the memory cell M12 is programmed. That is, data “0” is written to the memory cell M12, and data “1” is written to another memory cell.
[0190]
First, a control signal designating a program operation is supplied to control circuit 1130 via control signal buffer 1120. Negative voltage control circuit 1140 is externally supplied with negative voltage -Vee.
[0191]
The X decoder 1030 selects the word line WL2 in response to the X address signal given from the address buffer 1020, applies the negative voltage -Vee from the negative voltage control circuit 1140 to the selected word line WL2, and 0 V is applied to the word lines WL1 and WL3.
[0192]
Vpp / Vcc switching circuit 1090 supplies power supply voltage Vcc to writing circuit 1080. Data is sequentially applied from outside to the write circuit 1080 via the data input / output buffer 1070. At this time, Y decoder 1040 sequentially turns on the Y gate transistors in Y gate 1050 in response to the Y address signal supplied from address buffer 1020. Write circuit 1080 applies power supply voltage Vcc to bit line BL1 via Y gate 1050, and applies 0 V to bit lines BL2 and BL3. The source control circuit 1110 sets the source line SL to a floating state.
[0193]
In this way, a voltage is applied to the memory cell M12 as shown in FIG. At this time, the other memory cells are in one of the following states.
[0194]
(A) The power supply voltage Vcc is applied to the drain, 0 V is applied to the control gate, and the source is in a floating state.
[0195]
(B) 0 V is applied to the drain, negative voltage -Vee is applied to the control gate, and the source is in a floating state.
[0196]
(C) 0 V is applied to the drain, 0 V is applied to the control gate, and the source is in a floating state.
[0197]
(E) Modified example
During programming, the unselected bit lines BL2 and BL3 may be in a floating state. At this time, the unselected memory cells are in one of the following states.
[0198]
(A) The power supply voltage Vcc is applied to the drain, 0 V is applied to the control gate, and the source is in a floating state.
[0199]
(B) The drain is in a floating state, a negative voltage -Vee is applied to the control gate, and the source is in a floating state.
[0200]
(C) The drain is in a floating state, 0 V is applied to the control gate, and the source is in a floating state.
[0201]
Also in this case, a high electric field is generated only between the floating gate and the drain of the memory cell M12, and only the memory cell M12 is programmed by a tunnel phenomenon.
[0202]
During programming, an unselected bit line may be set to a floating state and 0 V may be applied to the source line SL. At this time, the power supply voltage Vcc is applied to the drain of the memory cell M12, the negative voltage -Vee is applied to the control gate, and 0 V is applied to the source. Other memory cells are in one of the following states.
[0203]
(A) The power supply voltage Vcc is applied to the drain, 0 V is applied to the control gate, and 0 V is applied to the source.
[0204]
(B) The drain is in a floating state, a negative voltage -Vee is applied to the control gate, and 0 V is applied to the source.
[0205]
(C) The drain is in a floating state, 0 V is applied to the control gate, and 0 V is applied to the source.
[0206]
Also in this case, a high electric field is generated only between the floating gate and the drain of the memory cell M12, and only the memory cell M12 is programmed by a tunnel phenomenon.
[0207]
In the third embodiment, the batch erasing operation may be performed in the same manner as in the second embodiment shown in FIG. A voltage is applied to each memory cell as shown in FIG.
[0208]
In this case, since the injection of electrons into the floating gate and the emission of electrons from the floating gate are performed using the tunnel phenomenon, power consumption is reduced. Therefore, a high voltage and a negative voltage can be generated internally from the externally applied power supply voltage.
[0209]
(4) Fourth embodiment (FIGS. 15 and 16)
The overall configuration of the flash memory according to the fourth embodiment is the same as the configuration shown in FIG. The voltage application conditions to the memory cells at the time of programming and erasing are the same as the voltage application conditions shown in FIGS. 6A and 6B. The fourth embodiment differs from the first embodiment only in the control method.
[0210]
(A) Operation of flash memory (FIG. 15)
Next, a page erase operation, a program operation, and a read operation of the flash memory will be described with reference to FIG. The program operation and the read operation are the same as in the first embodiment. Therefore, the page batch erasing operation will be described below.
[0211]
All memory cells connected to one word line are called a page. In the page batch erasing operation, batch erasing is performed in page units. Here, the batch erase operation of the page corresponding to word line WL2 will be described.
[0212]
First, a control signal designating a batch page erase operation is applied to control circuit 1130 via control signal buffer 1120. Vpp / Vcc switching circuit 1090 is externally supplied with high voltage Vpp.
[0213]
Vpp / Vcc switching circuit 1090 applies high voltage Vpp to X decoder 1030. X decoder 1030 selects word line WL2 in response to an X address signal applied from address buffer 1020, applies high voltage Vpp to selected word line WL2, and applies 0 V to unselected word lines WL1 and WL3. Is applied. Y decoder 1040 turns on all Y gate transistors included in Y gate 1050. Write circuit 1080 applies 0 V to all bit lines BL1 to BL3 via Y gate 1050. Source control circuit 1110 applies a predetermined high voltage VSL (VSL <Vpp) to source line SL.
[0214]
In this way, a voltage is applied to the memory cells M12, M22, M32 connected to the word line WL2 as shown in FIG. 6B. As a result, the memory cells M12, M22, M32 are erased.
[0215]
In each memory cell connected to the unselected word lines WL1 and WL3, 0 V is applied to the drain 1002, the high voltage VSL is applied to the source 1003, and 0 V is applied to the control gate 1006. Therefore, there is little possibility that hot electrons are injected into the floating gate 1005 over the energy barrier of the insulating film 1004. Therefore, only the memory cells connected to the selected word line WL2 are collectively erased.
[0216]
As described above, in the fourth embodiment, the batch erasing operation is performed not on a memory array basis but on a page basis.
[0217]
(B) Rewriting operation (FIG. 16)
A data rewriting operation in the flash memory according to the fourth embodiment will be described with reference to a flowchart of FIG.
[0218]
First, it is determined whether or not data “1” is stored in all memory cells (step S11). When data "1" is not stored in all the memory cells, a page batch erasing operation is performed for a page to be rewritten (step S12). Thereafter, a program operation is performed (step S13).
[0219]
In this manner, data can be rewritten in page units without performing the pre-write erasing operation as in the conventional example.
[0220]
(5) Fifth embodiment (FIG. 17)
The overall configuration of the flash memory according to the fifth embodiment is the same as the configuration shown in FIG. The voltage application conditions to the memory cell at the time of programming and erasing are the same as the voltage application conditions shown in FIGS. 9A and 9B. The fifth embodiment differs from the second embodiment only in the control method.
[0221]
A page batch erasing operation, a programming operation, and a reading operation of the flash memory according to the fifth embodiment will be described with reference to FIG. The program operation and the read operation are the same as in the second embodiment. Therefore, the page batch erasing operation will be described below. Here, the batch erase operation of the page corresponding to word line WL2 will be described.
[0222]
First, a control signal designating a batch page erase operation is applied to control circuit 1130 via control signal buffer 1120. Vpp / Vcc switching circuit 1090 is externally supplied with high voltage Vpp.
[0223]
Vpp / Vcc switching circuit 1090 applies high voltage Vpp to X decoder 1030. X decoder 1030 selects word line WL2 in response to an X address signal supplied from address buffer 1020, applies high voltage Vpp to the selected word line WL2, and applies a high voltage to unselected word lines WL1 and WL3. 0 V is applied. Y decoder 1040 turns on all Y gate transistors included in Y gate 1050. Write circuit 1080 applies 0 V to all bit lines BL1 to BL3 via Y gate 1050. Source control circuit 1110 applies 0 V to source line SL.
[0224]
In this way, a voltage is applied to the memory cells M12, M22, M32 connected to the word line WL2, as shown in FIG. 9B. As a result, the memory cells M12, M22, M32 are erased.
[0225]
In each memory cell connected to the unselected word lines WL1 and WL3, 0 V is applied to the drain 1002, the source 1003, and the control gate 1006. Therefore, no high electric field is generated between the floating gate 1005 and the source 1003, and electrons are not injected into the floating gate 1005 by a tunnel phenomenon. Therefore, only the memory cells connected to the selected word line are erased collectively.
[0226]
Thus, also in the fifth embodiment, batch erasing can be performed in page units, not in memory array units.
[0227]
Data rewriting is performed according to the procedure shown in FIG. Therefore, data can be rewritten in page units without performing the pre-erase write operation as in the conventional example.
[0228]
(6) Sixth embodiment (FIGS. 18 to 33)
(A) Overall configuration of flash memory (FIGS. 18 and 19)
FIG. 18 is a block diagram showing the overall configuration of the flash memory according to the sixth embodiment. FIG. 19 is a circuit diagram showing a detailed configuration of the memory array and its related parts.
[0229]
The flash memory shown in FIG. 18 differs from the conventional flash memory shown in FIG. 131 in the following points. The memory array 1010a is divided into a plurality of sectors. In the example of FIG. 18, the memory array 1010a is divided into sectors SE1 and SE2. Memory array 1010a includes select gates SG1 and SG2 corresponding to sectors SE1 and SE2, respectively.
[0230]
Memory array 1010a is formed in P-well 1008. Vpp / Vcc switching circuit 1090 shown in FIG. 131 is not provided, and high voltage generating circuits 1210 and 1220, negative voltage generating circuits 1230 and 1240, well potential generating circuit 1250, and select gate decoder 1260 are further provided. High voltage generation circuits 1210 and 1220 receive power supply voltage Vcc (for example, 5 V) from the outside and generate a high voltage (for example, 10 V). Negative voltage generation circuits 1230 and 1240 receive power supply voltage Vcc from the outside and generate a negative voltage (for example, -10 V). Well potential generating circuit 1250 applies a negative voltage (for example, −5 V) to P− well 1008 during erasing. Select gate decoder 1260 selectively activates select gates SG1 and SG2 in response to a part of the address signal from address buffer 1020.
[0231]
Next, reference is made to FIG. A plurality of main bit lines are arranged in memory array 1010a. FIG. 19 shows two main bit lines MB0 and MB1. Main bit lines MB0 and MB1 are connected to sense amplifier 1060 and write circuit 1080 via Y gate transistors YG0 and YG1, respectively.
[0232]
A plurality of sub-bit lines are arranged corresponding to each main bit line. In the example of FIG. 19, two sub-bit lines SB01 and SB02 are provided corresponding to main bit line MB0, and two sub-bit lines SB11 and SB12 are provided corresponding to main bit line MB1.
[0233]
A plurality of word lines are arranged so as to cross the plurality of sub-bit lines. In the example of FIG. 19, word lines WL0 and WL1 are arranged so as to cross sub bit lines SB01 and SB11, and word lines WL2 and WL3 are arranged so as to cross sub bit lines SB02 and SB12.
[0234]
At the intersections of the sub-bit lines SB01, SB02, SB11, SB12 and the word lines WL0 to WL3, memory cells M00 to M03, M10 to M13 are provided, respectively. Memory cells M00, M01, M10, and M11 are included in sector SE1, and memory cells M02, M03, M12, and M13 are included in sector SE2.
[0235]
The drain of each memory cell is connected to a corresponding sub-bit line, the control gate is connected to a corresponding word line, and the source is connected to a source line SL.
[0236]
Select gate SG1 includes select gate transistors SG01 and SG11, and select gate SG2 includes select gate transistors SG02 and SG12. Sub-bit lines SB01 and SB02 are connected to main bit line MB0 via select gate transistors SG01 and SG02, respectively, and sub-bit lines SB11 and SB12 are connected to main bit line MB1 via select gate transistors SG11 and SG12, respectively. . Select gate line SGL1 of select gate decoder 1260 is connected to select gate transistors SG01 and SG11, and select gate line SGL2 is connected to select gate transistors SG02 and SG12.
[0237]
(B) Programming and erasing of memory cells (FIG. 20)
FIG. 20A shows conditions for applying a voltage to a memory cell during programming. FIG. 20B shows conditions for applying a voltage to the memory cell at the time of erasing.
[0238]
At the time of programming, as shown in FIG. 20A, a positive voltage (for example, 5 V) is applied to the drain 1002, a negative voltage (for example, -10 V) is applied to the control gate 1006, and the source 1003 is brought into a floating state. -Apply 0V to the well 1008. Accordingly, a high electric field is generated between the floating gate 1005 and the drain 1002, and electrons are emitted from the floating gate 1005 to the drain 1002 by a tunnel phenomenon. As a result, the threshold voltage of the memory cell decreases.
[0239]
At the time of erasing, as shown in FIG. 20B, the drain 1002 is set to the floating state, a high voltage (for example, 10 V) is applied to the control gate 1006, the source 1003 is set to the floating state, and the negative voltage ( For example, -5V) is applied. Thereby, a high voltage (in this case, 15 V) is applied between control gate 1006 and P-well 1008, and a high electric field is generated between source 1003 and floating gate 1005. As a result, electrons are injected from the source 1003 into the floating gate 1005 by the tunnel phenomenon, and the threshold voltage of the memory cell increases.
[0240]
As described above, electrons are emitted from the floating gate 1005 to the drain 1002 by a tunnel phenomenon at the time of programming. Therefore, an N − -type impurity region 1002 e is provided along the drain 1002 to weaken the electric field in the channel direction or the substrate direction.
[0241]
Note that an N − -type impurity region 1003 e may be provided along the source 1003. As described above, when the N − -type impurity regions 1002e and 1003e are provided on both the drain side and the source side, the number of manufacturing steps is reduced.
[0242]
(C) Operation of flash memory (FIG. 21)
Next, the collective sector erase operation, program operation, and read operation of the flash memory will be described with reference to FIG.
[0243]
(I) Sector batch erase operation
Here, it is assumed that the sector SE1 is collectively erased. First, a control signal designating a collective sector erase operation is applied to control circuit 1130 via control signal buffer 1120. Thereby, high voltage generation circuit 1220 and negative voltage generation circuit 1230 are activated.
[0244]
The high voltage generation circuit 1220 applies a high voltage (10 V) to the X decoder 1030. The X decoder 1030 applies a high voltage (10 V) to the word lines WL0 and WL1 of the sector SE1, and applies 0 V to the word lines WL2 and WL3 of the sector SE2. Negative voltage generating circuit 1230 applies a negative voltage to Y decoder 1040 and well potential generating circuit 1250. Y decoder 1040 applies a negative voltage (−5 V) to Y gate transistors YG 0 and YG 1 in Y gate 1050. Thereby, main bit lines MB0 and MB1 enter a floating state. The source control circuit 10 sets the source line SL to a floating state. Also, well potential generating circuit 1250 applies a negative voltage (−5 V) to P− well 1008. Select gate decoder 1260 applies 0 V to select gate lines SG1 and SG2.
[0245]
In this way, a voltage is applied to the memory cells M00, M01, M10, and M11 in the sector SE1 as shown in FIG. As a result, all the memory cells in the sector SE1 are erased.
[0246]
At this time, in each memory cell in the non-selected sector SE2, the voltage applied between the control gate and the P- well is 5V. Therefore, no tunnel phenomenon occurs. Further, since this potential condition is almost the same as the potential condition at the time of reading, disturbance to data hardly occurs.
[0247]
(Ii) Program operation ((b) of FIG. 21)
Here, it is assumed that the memory cell M00 is programmed. That is, data “0” is written to the memory cell M00, and data “1” is written to the memory cell M10.
[0248]
First, a control signal designating a program operation is supplied to control circuit 1130 via control signal buffer 1120. Thereby, high voltage generation circuit 1210 and negative voltage generation circuit 1240 are activated.
[0249]
Negative voltage generating circuit 1240 applies a negative voltage to X decoder 1030. X decoder 1030 selects word line WL0 in response to an X address signal provided from address buffer 1020, applies a negative voltage (−10 V) to selected word line WL0, and selects unselected word lines WL1 to WL3. To 0 V.
[0250]
High voltage generation circuit 1210 applies a high voltage to Y decoder 1040, write circuit 1080, and select gate decoder 1260. First, data “0” is externally applied to write circuit 1080 via data input / output buffer 1070 and latched. Y decoder 1040 applies a high voltage (for example, 7 V) to Y gate transistor YG0 in Y gate 1050 and applies 0 V to Y gate transistor YG1 in response to a Y address signal provided from address buffer 1020. This turns on the Y gate transistor YG0.
[0251]
Write circuit 1080 applies a program voltage (5 V) corresponding to data "0" to main bit line MB0 via Y gate transistor YG0. Further, select gate decoder 1260 applies a high voltage (for example, (7 V)) to select gate line SGL1 and 0 V to select gate line SGL2, whereby sub-bit lines SB01 and SB11 are connected to main bit lines MB0 and SB11, respectively. The source control circuit 1110 sets the source line SL to a floating state, and the well potential generation circuit 1250 applies 0 V to the P- well 1008.
[0252]
In this way, a voltage is applied to the memory cell M00 as shown in FIG. As a result, the threshold voltage of the memory cell M00 decreases.
[0253]
After a lapse of a predetermined time (for example, 1 ms), data "1" is externally applied to write circuit 1080 via data input / output buffer 1070 and latched. Y decoder 1040 applies a high voltage (7 V) to Y gate transistor YG1 in Y gate 1050 and 0 V to Y gate transistor YG0 in response to a Y address signal provided from address buffer 1020. This turns on the Y gate transistor YG1. Write circuit 1080 applies 0 V corresponding to data "1" to main bit line MB1 via Y gate transistor YG1. Therefore, the threshold voltage of memory cell M10 is kept high.
[0254]
A verify operation may be performed during a program operation. This verify operation will be described with reference to the flowchart of FIG.
[0255]
As described above, a negative voltage (−10 V) is applied to the selected word line WL0, and a high voltage (7V) is applied to the selected select gate line SGL1 (step S21). Further, the source line SL is set in a floating state (step S22), 5 V is applied to the main bit line MB0 for data "0", and 0 V is applied to the main bit line MB1 for data "1" (step S23). Thereby, the threshold voltage of memory cell M00 decreases. At this time, the threshold voltage of the memory cell M10 is kept high.
[0256]
After a lapse of a fixed time (for example, 1 ms), the control circuit 1130 starts a verify operation. Thereby, verify voltage generating circuit 1100 is activated. Verify voltage generating circuit 1100 supplies a verify voltage lower than normal power supply voltage Vcc to X decoder 1030. As a result, a verify voltage is applied to the selected word line WL0 (step S24). The source line SL is grounded by the source control circuit 1110 (step S25). Thereby, a read operation is performed (step S26).
[0257]
When the threshold voltage of memory cell M00 is higher than the verify voltage, no current flows through main bit line MB0. Therefore, sense amplifier 1060 detects data “1”. In this case, control circuit 1130 determines that the program is insufficient, and performs the program operation and the verify operation again (steps S27, S21 to S26).
[0258]
When the threshold voltage of memory cell M00 becomes lower than the verify voltage, a current flows through main bit line MB0. Therefore, sense amplifier 1060 detects data “0”. In this case, control circuit 1130 determines that the program is sufficient, and ends the program operation for memory cell M00.
[0259]
The X address signal applied to X decoder 1030 is sequentially incremented, and a program operation and a verify operation are sequentially performed on word lines WL1, WL2, WL3 (steps S28, S29).
[0260]
(Iii) Read operation ((c) in FIG. 21)
Here, it is assumed that data is read from memory cell M00. First, a control signal designating a read operation is supplied to control circuit 1130 via control signal buffer 1120.
[0261]
X decoder 1030 selects word line WL0 in response to an X address signal supplied from address buffer 1020, and applies power supply voltage Vcc (5 V) thereto. At this time, the word lines WL1, WL2, WL3 are kept at 0V. Select gate decoder 1260 applies 5 V to select gate line SGL1 and 0 V to select gate line SGL2. Y decoder 1040 turns on Y gate transistor YG 0 in Y gate 1050 in response to a Y address signal provided from address buffer 1020. Source control circuit 1110 grounds source line SL.
[0262]
Thereby, read voltage Vr appears on main bit line MBO. This read voltage Vr is detected by the sense amplifier 1060 and output to the outside via the data input / output buffer 1070.
[0263]
(D) Cross-sectional structure of memory cell (FIG. 23)
FIG. 23 is a diagram showing a sectional structure of a memory cell used in the flash memory of this embodiment. The structure shown in FIG. 23 is called a triple well structure.
[0264]
An N- well 1009 is formed in a predetermined region of the P- type semiconductor substrate 1001, and a P- well 1008 is formed in the N- well 1009. Two N + -type impurity regions are formed at predetermined intervals in a predetermined region in P − well 1008. One of the N + -type impurity regions forms a drain 1002 and the other forms a source 1003. A floating gate 1005 is formed on a region between the source 1002 and the drain 1003 via an insulating film 1004 (about 100 °) such as an extremely thin oxide film, and a control gate 1006 is formed thereon via an insulating film. Is done. Thus, a memory cell MC is formed.
[0265]
CMOS circuit region 1300 includes an N-channel transistor formed in a P-well and a P-channel transistor formed in an N-well.
[0266]
(E) High integration
FIG. 24 is a structural diagram of two adjacent memory cells in the sixth embodiment. As shown in FIG. 24, two memory cells M00 and M10 are separated by a separation oxide film 1400 formed on P well 1008.
[0267]
In the programming operation, a voltage of 5 V is applied to the drain 1002 'of the selected memory cell M10, while a voltage of 0 V is applied to the drain 1002 of the unselected memory cell M00. In addition, a negative voltage of −10 V is applied to second aluminum wiring layer 1006 forming the control gate. Therefore, MOS transistor 1401 equivalently exists using isolation oxide film 1400 as a gate oxide film.
[0268]
This equivalent NMOS transistor 1401 receives a negative voltage of -10 V through a gate electrode. Therefore, this equivalent transistor 1401 cannot conduct in the above-described program operation, and therefore, it is possible to select width Wa of isolation oxide film 1400 to a smaller value than width Wb shown in FIG. And therefore a higher degree of integration is obtained.
[0269]
FIG. 25 is a layout diagram of a memory cell array on a semiconductor substrate in the sixth embodiment. As described above, in the sixth embodiment, since the program operation and the erase operation are performed using the tunnel phenomenon, the current flowing through the sub-bit line is extremely small. Therefore, the channel width of select gate transistors SG0 and SG1 for selecting a sector can be selected to a smaller value as compared with the example shown in FIG. Therefore, a layout suitable for higher integration can be obtained.
[0270]
FIG. 26 is a circuit diagram showing voltages applied to the memory cell array of the sixth embodiment. FIG. 26A shows the voltage applied in the program operation, while FIG. 26B shows the voltage applied in the erase operation.
[0271]
As shown in FIG. 26A, in a program operation, an X decoder (not shown) outputs -10V and 0V output voltages. In other words, the X decoder outputs an output voltage having a voltage difference of 10V.
[0272]
On the other hand, as shown in FIG. 26B, the X decoder requires output voltages of 10 V and 0 V in the erasing operation. In other words, the X decoder outputs an output voltage having a voltage difference of 10V.
[0273]
As can be seen by comparing the output voltage difference (ie, 10 V) shown in FIG. 26 with the output voltage difference (ie, 15 V and 18 V) shown in FIG. 147, the output voltage difference of the X decoder in the sixth embodiment is reduced. I have. This contributes to improving the integration of the X decoder. That is, in the sixth embodiment, since the output voltage difference of the X decoder becomes small, it becomes possible to form the X decoder in a smaller occupied area on the semiconductor substrate.
[0274]
(F) High voltage generation circuit (FIGS. 27 and 28)
FIG. 27A shows an equivalent circuit of the high voltage generation circuit. The high voltage generation circuit includes a plurality of diodes D210 and a plurality of capacitances C210. Two-phase clock signals φ and / φ are applied to the capacitance C210. Thereby, a charge pump is configured.
[0275]
Each diode D210 is usually configured by an N-channel transistor as shown in FIG. The back gate of the N-channel transistor is grounded.
[0276]
However, when the power supply voltage Vcc is low (for example, 3 V), it is difficult to obtain a high voltage due to the back gate effect. The back gate effect means that when the back gate voltage decreases relative to the source voltage, the threshold voltage increases.
[0277]
Therefore, in this embodiment, the structure shown in FIG. 28 is used. A plurality of N− wells 1211 are formed in the P− type semiconductor substrate 1001, and a P + type impurity region 1212 and an N + type impurity region 1213 are formed in each N− well 1211. These P + -type impurity regions 1212 and N + -type impurity regions 1213 constitute a diode.
[0278]
According to this configuration, the back gate effect does not occur because each diode does not have a back gate.
[0279]
However, in some cases, a parasitic transistor (bipolar transistor) as shown in FIG. 29 may be present in the high voltage generating circuit having the structure shown in FIG. Referring to FIG. 29, pnp type parasitic transistors 1411 and 1412 can be formed by P + type impurity region 1212, N− well 1211 and P− type semiconductor substrate 1001. Therefore, the circuit shown in FIG. 30 can be equivalently formed by the presence of these parasitic transistors 1411, 1412,.
[0280]
FIG. 30 is an equivalent circuit diagram of a circuit including the parasitic transistors 1411, 1412,... Shown in FIG. As can be seen from FIG. 30, the cascaded parasitic transistors 1411, 1412,... Amplify a small leak current ILEAK, thereby causing an excessive current In. That is, assuming that the current amplification factor of each of the parasitic transistors 1411, 1412,... Is hfe, an excessive current In determined by the following equation flows.
[0281]
I1 = (1 + hfe) · ILEAK
In = (1 + hfe) n ILEAK
Therefore, in order to prevent an excessive current In from flowing in the high voltage generating circuit, a structure shown in FIG. 31 is proposed.
[0282]
FIG. 31 is a sectional view showing another structure of the high voltage generation circuit used in the flash memory according to the sixth embodiment. As shown in FIG. 31, a triple well structure is applied to a high voltage generation circuit. This prevents the presence of the parasitic transistors 1411, 1412,... As shown in FIG. 29, and a stable boosting operation can be performed.
[0283]
(G) Negative voltage generation circuit (FIGS. 32 and 33)
FIG. 32A shows an equivalent circuit of the negative voltage generation circuit. The negative voltage generation circuit includes a plurality of diodes D230 and a plurality of capacitances C230. Two-phase clock signals φ and / φ are applied to the capacitance C230. Thereby, a charge pump is configured.
[0284]
Each diode D230 is usually formed by a P-channel transistor as shown in FIG. The back gate of the P-channel transistor is grounded.
[0285]
However, when the power supply voltage Vcc is low (for example, 3 V), it is difficult to obtain a low negative voltage due to the back gate effect.
[0286]
Therefore, in this embodiment, a triple well structure shown in FIG. 33 is used. An N- well 1231 is formed in the P- type semiconductor substrate 1001, a plurality of P- wells 1232 are formed in the N- well 1231, and an N + type impurity region 1233 and a P + type impurity region 1234 are formed in each P- well 1232. It is formed. N + type impurity region 1233 and P + type impurity region 1234 constitute a diode.
[0287]
According to this configuration, the back gate effect does not occur because each diode does not have a back gate. Further, as shown in FIG. 23, since the memory cells are also formed in the N- well, the number of manufacturing steps does not increase.
[0288]
(7) Seventh embodiment (FIGS. 34 and 35)
FIG. 34 is a circuit diagram showing a detailed configuration of a memory array of the flash memory according to the seventh embodiment and parts related thereto. The overall configuration of the flash memory according to the embodiment of FIG. 7 is the same as the configuration shown in FIG.
[0289]
The seventh embodiment differs from the sixth embodiment in that capacitances C0 and C1 are connected to main bit lines MB0 and MB1 via transfer gate transistors TG0 and TG1, respectively. Well potential VB is applied to capacitances C0 and C1. Control signal CG1 is applied from control circuit 1130 to transfer gate transistors TG0 and TG1. The configuration of the other parts is the same as the configuration shown in FIG.
[0290]
Assuming that the programming time for one memory cell is, for example, 1 ms, a 2-bit configuration as shown in FIG. 34 requires 2 ms for programming. Actually, since the number of memory cells connected to one word line is hundreds to thousands, rewriting data takes an enormous amount of time. By providing a data latch for each main bit line, memory cells connected to a plurality of bit lines may be simultaneously programmed. However, layout becomes difficult.
[0291]
Therefore, as shown in the seventh embodiment, capacitances C0 and C1 are provided.
[0292]
During programming, the transfer gate transistors TG0 and TG1 turn on in response to the control signal CG1. Further, Y decoder 1040 switches Y gate transistors YG0 and YG1 at high speed, for example, at a period of several tens of microseconds in response to the Y address signal. At this time, data is sequentially applied to write circuit 1080 in accordance with the Y address signal. Thereby, capacitances C0 and C1 are charged according to data via main bit lines MB0 and MB1. This operation is repeated for 1 ms.
[0293]
In general, the current required for tunneling of electrons from the floating gate is several nanoamps or less, so that the current accumulated in the capacitances C0 and C1 can supply the current required for tunneling.
[0294]
As shown in FIG. 35, for example, when Y gate transistors YG0 and YG1 are switched every 250 μsec, the program voltage is not applied to main bit line MB0 for a period of 250 μsec to 500 μsec and for a period of 750 μsec to 1 ms. . However, during these periods, the voltage of the main bit line MB0 is held by the electric charge accumulated in the main bit line MB0 and the capacitance C0. Therefore, the time required to program the memory cells connected to main bit lines MB0 and MB1 is 1 ms.
[0295]
Here, the amount of voltage decrease ΔV during the period when the program voltage is not applied to main bit line MB0 is determined by the value of capacitance C0 and the switching frequency of the Y gate transistor. As the value of the capacitance C0 is larger or the switching frequency is larger, the decrease in the program voltage is suppressed, and the programming is performed stably and at a high speed.
[0296]
When the capacitances C0 and C1 are formed by MOS capacitors, it is preferable to connect the main bit lines MB0 and MB1 to the gates. If the main bit lines MB0 and MB1 are connected to the diffusion layer of the MOS capacitor, the charged program voltage may be discharged in a short time due to, for example, junction leakage at a high temperature.
[0297]
Voltage application conditions during programming and erasing are the same as in the sixth embodiment. Also, the sector batch erasing operation and the programming operation are the same as in the sixth embodiment.
[0298]
(8) Eighth embodiment (FIGS. 36 to 51)
(A) Overall configuration of flash memory (FIGS. 36 and 37)
FIG. 36 is a block diagram showing the overall configuration of the flash memory according to the eighth embodiment. FIG. 37 is a circuit diagram showing a detailed configuration of the memory array and its related parts.
[0299]
The flash memory of FIG. 36 differs from the flash memory of the sixth embodiment shown in FIG. 18 in the following points. A source decoder 1270 is provided instead of the source control circuit 1110. Negative voltage generation circuit 1230 applies a negative voltage to select gate decoder 1260 and source decoder 1270 instead of Y decoder 1040.
[0300]
As shown in FIG. 37, the sources of the memory cells M00, M01, M10, and M11 in the sector SE1 are connected to the source line SL1, and the sources of the memory cells M02, M03, M12, and M13 in the sector SE2 are connected to the source line SL2. Connected. The output terminal of source decoder 1270 is connected to source lines SL1 and SL2.
[0301]
At the time of erasing, the source of each memory cell in the selected sector is in a floating state. If a leak path exists in the source, the source potential increases and the electric field between the source and the floating gate decreases.
[0302]
Therefore, in order to stabilize the source potential at the time of erasing, capacitances C11 and C12 may be connected to the source lines SL1 and SL2 via transfer gate transistors TG11 and TG12, respectively.
[0303]
Well potential VB is applied to capacitances C11 and C12. A control signal CG2 is supplied from the control circuit 1130 to the transfer gate transistors TG11 and TG12.
[0304]
At the time of erasing, the transfer gate transistors TG11 and TG12 turn on in response to the control signal CG2. Thereby, the change in the source potential is reduced.
[0305]
Since the program operation and the read operation in the eighth embodiment are the same as those in the sixth embodiment, the sector batch erase operation will be described below.
[0306]
In the sixth embodiment, at the time of erasing, a voltage is applied as shown in FIG. However, if erasing is performed in a very short time (for example, several milliseconds), the formation of the inversion layer below the memory cell cannot follow the voltage application, and a depletion layer is formed below the memory cell. .
[0307]
In such a case, it is preferable that the conditions for applying a voltage to the memory cells in the selected sector and the conditions for applying a voltage to the memory cells in the unselected sector be different.
[0308]
The voltage application conditions are different depending on whether there is no gate bird's beak in the insulating film 1004 (tunnel insulating film) below the floating gate 1005 or when there is a gate bird's beak. Here, the gate bird's beak refers to a state in which the periphery of the lower surface of the floating gate 1005 is eroded by the tunnel insulating film below the floating gate 1005 during manufacturing, as indicated by gb in FIG. As a result, the thickness of the tunnel insulating film is increased below the periphery of the floating gate 1005.
[0309]
First, the voltage application conditions when there is no or small gate bird's beak will be described, and then the voltage application conditions when the gate bird's beak is large will be described.
[0310]
(B) When there is no gate bird's beak (FIGS. 38 to 42)
(I) Erasing the memory cell (FIGS. 38 and 39)
38, Cg is the capacitance between the control gate 1006 and the floating gate 1005, Cf is the capacitance between the floating gate 1005 and the P- well 1008, Cb is the capacitance due to the depletion layer, and Cd is the capacitance between the drain 1002 and the floating gate 1005. Cs indicates the capacitance between the source 1003 and the floating gate 1005. Ct indicates a combined capacitance of the capacitance Cf and the capacitance Cb.
[0311]
Now, a positive voltage VCG is applied to the control gate 1006, and a negative voltage VB is applied to the P- well 1008. In this case, since the drain 1002 and the source 1003 are in a floating state, the drain voltage Vd and the source voltage Vs become substantially the negative voltage VB. Assuming that the potential of the floating gate 1005 at this time is VFG and the initial accumulated charge is 0, the following equation is established from the charge conservation law.
[0312]
(VCG−VFG) · Cg = (VFG−VB) · (Cs + Ct + Cd) (1)
The following equation is obtained by expanding equation (1).
[0313]
VFG = {VCG · Cg + (Cs + Ct + Cd) · VB} / (Cs + Ct + Cd + Cg) (2)
Expanding equation (2) further gives the following equation.
[0314]
VFG = {VCG + (Cs + Ct + Cd) .VB / Cg} / {(Cs + Ct + Cd) / Cg + 1} (3)
Here, Cs and Cd can be ignored because they are smaller than Cg. Therefore, equation (3) becomes as follows.
[0315]
VFG = (VCG + Ct · VB / Cg) / (Ct / Cg + 1) (4)
When the depletion layer expands, the capacitance Cb decreases and the capacitance Ct also decreases. Therefore, potential VFG of floating gate 1005 approaches potential VCG of control gate 1006. However, the potentials of the drain 1002 and the source 1003 in the floating state are substantially the same as the potential of the P- well 1008.
[0316]
In this case, the electric field E between the floating gate 1005 and the drain 1002 or the source 1003 is expressed by the following equation.
[0317]
E = (VFG−VB) / TOX (5)
Here, VFG represents the potential of the floating gate 1005, VB represents the potential of the P- well 1008, and TOX represents the thickness of the tunnel insulating film.
[0318]
Since the potential VFG of the floating gate 1005 increases, the electric field between the floating gate 1005 and the drain 1002 and the electric field between the floating gate 1005 and the source 1003 increase. Therefore, the tunnel effect at the end of the drain 1002 or the source 1003 is improved. Therefore, the erasing efficiency is improved.
[0319]
Such an effect is preferable in a selected sector, but not preferable in a non-selected sector.
[0320]
Therefore, the source 1003 of the memory cell in the selected sector is set to a floating state as shown in FIG. 39A, and the source 1003 of the memory cell in the non-selected sector is set to FIG. As shown in the figure, the same potential as the potential of the P-well 1008 or a potential higher than the potential of the P-well 1008 is supplied.
[0321]
Thus, in a memory cell in a non-selected sector, a channel ch is formed between the source 1003 and the drain 1002, and the potential of the channel ch is supplied from the source 1003. Therefore, the potential of the floating gate 1005 decreases due to capacitive coupling between the floating gate 1005 and the channel ch, and the electric field applied to the tunnel insulating film is reduced. As a result, the data of the memory cells in the non-selected sectors is stably protected.
[0322]
(Ii) Sector batch erase operation of flash memory (FIG. 40)
With reference to FIG. 40, a description will be given of the collective sector erase operation of the flash memory when there is no gate bird's beak. Here, it is assumed that the sector SE1 is collectively erased.
[0323]
10 V is applied to the word lines WL0 and WL1 in the sector SE1, and 0 V is applied to the word lines WL2 and WL3 in the sector SE2. Further, 0 V is applied to the select gate lines SGL1 and SGL2. -5 V is applied to the P-well 1008. The source line SL1 is set in a floating state, and −5 V is applied to the source line SL2.
[0324]
Thus, the memory cells in the sector SE1 can be erased collectively while the data in the memory cells in the sector SE2 are protected stably.
[0325]
(Iii) Source decoder (FIGS. 41 and 42)
FIG. 41 is a diagram showing a configuration of a source decoder 1270 used when there is no gate bird's beak. FIG. 42 is a diagram showing voltages of respective parts of the source decoder 1270 of FIG. FIG. 41 shows only a portion related to source line SL1. The configuration of the portion related to source line SL2 is the same as the configuration shown in FIG. 41 except that input signals applied to input terminals AD0, AD1, and AD2 are different.
[0326]
The back gates of P-channel transistors P1, P2, P3 are connected to terminal VDD, and the back gates of N-channel transistors N1, N2, N3, N4 are connected to terminal VBB.
[0327]
At the time of erasing, 0 V is applied to the terminal VDD, and the same negative voltage (-5 V) as the well potential is applied to the terminal VBB. Further, the same negative voltage (-5 V) as the well potential or a negative voltage higher than the well potential is applied to the terminal VBB2.
[0328]
When the sector SE1 is selected, an input signal of 0 V is applied to all of the input terminals AD0 to AD2. Therefore, the transistor N4 turns off and the source line SL1 enters a floating state. When the sector SE1 is not selected, an input signal of −5 V is applied to one of the input terminals AD0 to AD2. Therefore, the transistor N4 turns on, and −5 V is applied to the source line SL1.
[0329]
At the time of programming and reading, the power supply voltage Vcc (5 V) is applied to the terminal VDD, 0 V is applied to the terminal VBB, and 0 V is applied to the terminal VBB2.
[0330]
At the time of programming, an input signal of 5 V is applied to all of the input terminals AD0 to AD2. Therefore, the transistor N4 turns off and the source line SL1 enters a floating state.
[0331]
At the time of reading, an input signal of 0 V is applied to all of the input terminals AD0 to AD2. Therefore, the transistor N4 is turned on, and 0 V is applied to the source line SL1.
[0332]
(C) When there is a gate bird's beak (FIGS. 43 to 47)
(I) Erasing the memory cell (FIGS. 43 and 44)
As shown in FIG. 43, if the gate bird's beak gb is large, the diffusion layers forming the drain 1002 and the source 1003 may not extend below the thin tunnel insulating film. In this case, no tunnel effect occurs between the drain 1002 and the floating gate 1005 and between the source 1003 and the floating gate 1005. Therefore, erasing is performed by the tunnel effect between P- well 1008 and floating gate 1005.
[0333]
The electric field E between the floating gate 1005 and the P- well 1008 is expressed by the following equation.
[0334]
E = (VFG−VB) / (TOX + Id) (6)
Here, VFG represents the potential of the floating gate 1005, VB represents the potential of the P− well 1008, TOX represents the thickness of the tunnel insulating film, and Id represents the thickness of the depletion layer. When the drain 1002 and the source 1003 are in a floating state as described above, the electric field is weakened by the depletion layer, and the erasing efficiency is reduced.
[0335]
In such a case, as shown in FIG. 44A, the same negative voltage (−5 V) as the potential of the P− well 1008 is applied to the source 1003 of the memory cell in the selected sector, and The source 1003 of the memory cell in the sector is floated as shown in FIG.
[0336]
Thus, in the memory cell in the selected sector, a channel ch is formed between the source 1003 and the drain 1002, and the potential of the channel ch is supplied from the source 1003. Therefore, a sufficient electric field is applied to the tunnel insulating film between the channel ch and the floating gate 1005, and a tunnel phenomenon occurs between the channel ch and the floating gate 1005. As a result, the erasing efficiency of the memory cells in the selected sector is improved.
[0337]
On the other hand, since the source 1003 of the memory cell in the unselected sector is in a floating state, no channel is formed between the source 1003 and the drain 1002, and a depletion layer is formed below the memory cell. Therefore, the electric field between floating gate 1005 and P− well 1008 is reduced.
[0338]
(Ii) Batch flash sector erase operation (FIG. 45)
The collective sector erase operation of the flash memory when there is a gate bird's beak will be described with reference to FIG. Here, it is assumed that the sector SE1 is collectively erased.
[0339]
10 V is applied to the word lines WL0 and WL1 in the sector SE1, and 0 V is applied to the word lines WL2 and WL3 in the sector SE2. Further, 0 V is applied to the select gate lines SGL1 and SGL2. -5 V is applied to the P-well 1008. -5 V is applied to the source line SL1, and the source line SL2 is set in a floating state.
[0340]
Thus, the memory cells in the sector SE1 can be erased collectively while the data in the memory cells in the sector SE2 are protected stably.
[0341]
(Iii) Source decoder (FIGS. 46 and 47)
FIG. 46 is a diagram showing a configuration of a source decoder 1270 used when there is a gate bird's beak. FIG. 47 is a diagram showing voltages of respective parts of the source decoder 1270 of FIG. FIG. 48 shows only a portion related to source line SL1. The configuration of the portion related to source line SL2 is the same as the configuration shown in FIG. 46 except that input signals applied to input terminals AD0, AD1, and AD2 are different.
[0342]
The back gates of P-channel transistors P1, P2, P3, and P4 are connected to terminal VDD, and the back gates of N-channel transistors N1, N2, N3, N5, and N6 are connected to terminal VBB.
[0343]
At the time of erasing, 0 V is applied to the terminal VDD, and the same negative voltage (-5 V) as the well potential is applied to the terminal VBB.
[0344]
When the sector SE1 is selected, an input signal of 0 V is applied to all of the input terminals AD0 to AD2. Therefore, the transistor N6 turns on, and −5 V is applied to the source line SL1. When the sector SE1 is not selected, an input signal of −5 V is applied to one of the input terminals AD0 to AD2. Therefore, the transistor N6 is turned off, and the source line SL1 enters a floating state.
[0345]
At the time of programming and reading, the power supply voltage Vcc (5 V) is applied to the terminal VDD, and 0 V is applied to the terminal VBB.
[0346]
At the time of programming, an input signal of 0 V is applied to all of the input terminals AD0 to AD2. Therefore, the transistor N6 turns off and the source line SL1 enters a floating state.
[0347]
At the time of reading, an input signal of 5 V is applied to all of the input terminals AD0 to AD2. Therefore, the transistor N6 is turned on, and 0 V is applied to the source line SL1.
[0348]
(D) When the well potential is low (FIGS. 48 to 51)
(I) Erasing the memory cell (FIG. 48)
In the above description, it is assumed that the voltage applied to the P- well at the time of erasing is -5V. If the well potential is further lowered to further improve the erase efficiency, disturb in unselected sectors becomes a problem.
[0349]
For example, when the gate bird's beak is large, as shown in FIG. 46, a negative voltage (−5 V) of the terminal VBB equal to the well potential is applied to the source line of the selected sector, and the non-selected sector is The source line is in a floating state.
[0350]
However, when the well potential lowers, the electric field between the floating gate and the P- well increases in the memory cells in the unselected sectors. As a result, the data of the memory cells in the non-selected sectors cannot be reliably protected.
[0351]
Therefore, a voltage higher than the well potential is applied to the source lines of the non-selected sectors. For example, as shown in FIG. 48, the potential of P-well 1008 is set to -10V. In this case, as shown in FIG. 48A, -10 V which is the same as the well potential is applied to the source 1003 of the memory cell in the selected sector, and the source 1003 of the memory cell in the non-selected sector is applied. Applies -5V.
[0352]
Thereby, the potential difference between the channel and control gate 1006 can be set to 5 V in the memory cells in the non-selected sectors.
[0353]
(Ii) Sector batch erase operation of flash memory (FIG. 49)
The sector batch erasing operation of the flash memory when the well potential is low will be described with reference to FIG. Here, it is assumed that the sector SE1 is collectively erased.
[0354]
10 V is applied to the word lines WL0 and WL1 in the sector SE1, and 0 V is applied to the word lines WL2 and WL3 in the sector SE2. Further, 0 V is applied to the select gate lines SGL1 and SGL2. -10 V is applied to the P-well 1008. -10 V is applied to the source line SL1, and -5 V is applied to the source line SL2.
[0355]
Thus, the memory cells in the sector SE1 can be erased collectively while the data in the memory cells in the sector SE2 are protected stably.
[0356]
(Iii) Source decoder (FIGS. 50 and 51)
FIG. 50 shows a configuration of source decoder 1270 used when the well potential is low. FIG. 51 is a diagram showing voltages of respective parts of the source decoder 1270 of FIG. FIG. 50 shows only a portion related to source line SL1. The configuration of a portion related to source line SL2 is the same as the configuration shown in FIG. 50 except that input signals applied to input terminals AD0, AD1, and AD2 are different.
[0357]
The back gates of P-channel transistors P1, P2, P3, and P5 are connected to terminal VDD, and the back gates of N-channel transistors N1, N2, and N3 are connected to terminal VBB.
[0358]
At the time of erasing, -5 V is applied to the terminal VDD, and the same negative voltage (-10 V) as the well potential is applied to the terminal VBB. Further, 0 V is applied to the control line CSL, and −10 V is applied to the control line DSL.
[0359]
When the sector SE1 is selected, an input signal of 0 V is applied to all of the input terminals AD0 to AD2. Therefore, -10 V is applied to source line SL1. When the sector SE1 is not selected, an input signal of −10 V is applied to any of the input terminals AD0 to AD2. Therefore, -5 V is applied to source line SL1. Note that the potential of the source line at the time of non-selection can be freely selected by changing the potential applied to the terminal VDD at the time of erasing.
[0360]
At the time of programming and reading, the power supply voltage Vcc (5 V) is applied to the terminal VDD, and 0 V is applied to the terminal VBB.
[0361]
During programming, 0 V is applied to the control line CSL, and 5 V is applied to the control line DSL. Therefore, source line SL1 is in a floating state.
[0362]
At the time of reading, 5 V is applied to the control line CSL, and 0 V is applied to the control line DSL. Further, an input signal of 5 V is applied to all of the input terminals AD0 to AD2. Therefore, 0 V is applied to source line SL1.
[0363]
(9) Ninth embodiment (FIGS. 52 to 56)
(A) Overall configuration of flash memory (FIGS. 52 and 53)
FIG. 52 is a block diagram showing the entire configuration of the flash memory according to the ninth embodiment. FIG. 53 is a circuit diagram showing a detailed configuration of the memory array and its related parts.
[0364]
The flash memory of FIG. 52 differs from the flash memory of the eighth embodiment shown in FIG. 36 in the following points. Source switches 1281 and 1282 are provided instead of the source decoder 1270. Negative voltage generating circuit 1230 applies a negative voltage to select gate decoder 1260.
[0365]
As shown in FIG. 53, the source switch 1281 receives the potential on the select gate line SGL1, and controls the potential of the source line SL1. Source switch 1282 receives the potential on select gate line SGL2 and controls the potential of source line SL2. The source switches 1281 and 1282 are controlled by a control signal CG3 from the control circuit 1130.
[0366]
Since the program operation and the read operation in the ninth embodiment are the same as those in the sixth embodiment, the erase operation will be described below.
[0367]
(B) Batch flash sector erase operation (FIG. 54)
A collective sector erase operation of the flash memory according to the ninth embodiment will be described with reference to FIG. Here, it is assumed that the batch erasing of the sector SE1 is performed.
[0368]
As described in the eighth embodiment, -10 V is applied to the P- well 1008 in order to further improve the erase efficiency. 10 V is applied to the word lines WL0 and WL1 in the sector SE1, and 0 V is applied to the word lines WL2 and WL3 in the sector SE2. Further, -10 V is applied to the select gate line SGL1, and -5 V is applied to the select gate line SGL2. -10 V is applied to the source line SL1 by the source switch 1281, and -5 V is applied to the source line SL2 by the source switch 1282.
[0369]
As a result, the sector SE1 can be efficiently erased collectively without causing disturbance in the sector SE2.
[0370]
(C) Select gate decoder and source switch (FIGS. 55 and 56)
FIG. 55 is a circuit diagram showing a configuration of a select gate decoder and a source switch used in the flash memory of the ninth embodiment. FIG. 56 is a diagram showing voltages of respective parts of the select gate decoder and the source switch of FIG. FIG. 55 shows only a portion related to select gate line SGL1 of select gate decoder 1260 and source switch 1281 connected to source line SL1. The structure of select gate decoder 1260 related to select gate line SGL2 and source switch 1282 are the same as the structure shown in FIG. 55 except that input signals applied to input terminals AD0, AD1 and AD2 are different. .
[0371]
The back gates of P-channel transistors P21 to P25 are connected to terminal VDD, and the back gates of N-channel transistors N21 to N28 are connected to terminal VBB. The control signal CG3 shown in FIG. 53 is provided by control lines ASL and BSL.
[0372]
At the time of erasing, 0 V is applied to the terminal VDD, and -10 V is applied to the terminal VBB. -5 V is applied to the terminal VBB2, and -10 V is applied to the terminal VSG. 0 V is applied to the control line ASL, and -10 V is applied to the control line BSL.
[0373]
When the sector SE1 is selected, an input signal of 0 V is applied to all of the input terminals AD0 to AD2. Therefore, the transistors N25 and P25 are turned on, and the potential (−10 V) of the terminal VSG is applied to the select gate line SGL1. Further, since the potential of the control line ASL is 0 V, the transistor N27 is turned on, and the potential of the terminal VSG (−10 V) is also applied to the source line SL1.
[0374]
When the sector SE1 is not selected, an input signal of −10 V is applied to any of the input terminals AD0 to AD2. Therefore, the transistor N26 is turned on, and the potential (−5 V) of the terminal VBB2 is applied to the select gate line SGL1. Further, the potential (−5 V) of the terminal VBB2 is also applied to the source line SL1 via the transistor N27. Note that by changing the voltage applied to the terminal VBB2, the potential of the source line of a non-selected sector can be changed freely.
[0375]
At the time of programming, the power supply voltage Vcc (7 V) is applied to the terminal VDD, and 0 V is applied to the terminals VBB and VBB2. 7 V is applied to the terminal VSG, and 0 V is applied to the control lines ASL and BSL.
[0376]
When the sector SE1 is selected, the transistors N25 and P25 are turned on, and the potential (7 V) of the terminal VSG is applied to the select gate line SGL1. At this time, since the transistors N27 and N28 are off, the source line SL1 is in a floating state. When the sector SE1 is not selected, the transistor N26 is turned on, and the potential (0 V) of the terminal VBB2 is applied to the select gate line SGL1. Also at this time, since the transistors N27 and N28 are off, the source line SL1 is in a floating state.
[0377]
At the time of reading, the power supply voltage Vcc (5 V) is applied to the terminal VDD, and 0 V is applied to the terminals VBB and VBB2. 5 V is applied to the terminal VSG. 0 V is applied to the control line ASL, and 5 V is applied to the control line BSL.
[0378]
When the sector SE1 is selected, the transistors N25 and P25 are turned on, and the potential (5 V) of the terminal VSG is applied to the select gate line SGL1. At this time, since the transistor N28 is on, the source line SL1 is grounded. When the sector SE1 is not selected, the transistor N26 is turned on, and the potential (0 V) of the terminal VBB2 is applied to the select gate line SGL1. Also at this time, since the transistor N28 is on, the source line SL1 is grounded.
[0379]
As described above, the well potential is applied to the source line of the selected sector and the potential higher than the well potential is applied to the source line of the unselected sector at the time of erasing without the need for the source decoder 1270 shown in FIG. Can be applied.
[0380]
(10) Tenth embodiment (FIG. 57)
A feature of the flash memory according to the tenth embodiment is that a verify operation is not required at the time of programming. The configuration of the flash memory of the tenth embodiment is the same as the configuration of the flash memory of any of the sixth to ninth embodiments. The batch erasing operation and the reading operation are the same as those in the sixth to ninth embodiments.
[0381]
The programming operation of the flash memory according to the tenth embodiment will be described with reference to the flowchart of FIG.
[0382]
First, the potential of the selected word line is set to the verify level, and a high voltage is applied to the selected select gate line (step S31). This turns on the selected select gate transistor. Then, the source line is set in a floating state (step S32). The main bit line corresponding to data "0" is precharged to 5V, and the main bit line corresponding to data "1" is maintained at 0V (step S33).
[0383]
Thereafter, the source line is grounded for a certain period (step S34). If the threshold voltage of the memory cell in the selected sector is higher than the verify level, the potential of the main bit line corresponding to data "0" is maintained at the precharge level. If the threshold voltage of the memory cell in the selected sector is lower than the verify level, the main bit line corresponding to data "0" is discharged through the memory cell.
[0384]
Thereafter, the source line is set in a floating state (step S35), and a negative voltage is applied to the selected word line (step S36). Thereby, only the memory cells connected to the main bit line precharged to 5 V are programmed.
[0385]
After repeating the above program cycle a specified number of times (step S37), the X address is incremented, and the above program cycle is repeated for the next word line (steps S38 and S39). When the above program cycle is repeated for all the word lines in the selected sector, the program operation ends (step S38).
[0386]
According to the above method, after the program voltage is applied to the main bit line, the program operation can be performed at a high speed without performing the verify operation one by one.
[0387]
In order to stably maintain the precharge level, as shown in the second embodiment, a capacitance may be connected to the main bit line via a transfer gate transistor, and these transfer gate transistors may be turned on during programming. .
[0388]
The above method can be similarly applied to the flash memories of other embodiments.
[0389]
(11) Eleventh embodiment (FIG. 58)
A feature of the flash memory according to the eleventh embodiment is that a verify operation is not required at the time of programming. The configuration of the flash memory of the eleventh embodiment is the same as the configuration of the flash memory of any of the sixth to ninth embodiments. The batch erasing operation and the reading operation are the same as those in the sixth to ninth embodiments.
[0390]
The program operation of the flash memory according to the eleventh embodiment will be described with reference to FIG.
[0391]
First, the potential of the selected word line is set to the verify level, and a high voltage is applied to the selected select gate line (step S41). This turns on the selected select gate transistor. Then, the source line is set in a floating state (step S42). The main bit line corresponding to data "0" is precharged to 5V, and the main bit line corresponding to data "1" is maintained at 0V (step S43).
[0392]
Thereafter, the source line is grounded for a certain period (step S44). If the threshold voltage of the memory cell in the selected sector is higher than the verify level, the potential of the main bit line corresponding to data "0" is maintained at the precharge level. If the threshold voltage of the memory cell in the selected sector is lower than the verify level, the main bit line corresponding to data "0" is discharged through the memory cell.
[0393]
Thereafter, if the potentials of all the main bit lines are not at 0 V (step S45), the source line is set to a floating state (step S46), and a negative voltage is applied to the selected word line (step S47). Thereby, only the memory cells connected to the main bit line precharged to 5 V are programmed.
[0394]
After the above program cycle is repeated until the potentials of all bit lines become 0 V (step S45), the X address is incremented, and the above program cycle is repeated for the next word line (steps S48 and S49). When the above program cycle is performed for all the word lines in the selected sector, the program operation ends (step S48).
[0395]
According to the above method, after the program voltage is applied to the main bit line, the program operation can be performed at a high speed without performing the verify operation one by one, and the program operation can be automatically terminated.
[0396]
The above method can be similarly applied to the flash memories of other embodiments.
[0397]
(12) Twelfth embodiment (FIGS. 59 to 64)
FIG. 59 is a block diagram showing the overall configuration of the flash memory according to the twelfth embodiment. In the flash memory shown in FIG. 59, the program operation and the erase operation are performed in a manner similar to that of the flash memory shown in FIG.
[0398]
Referring to FIG. 59, this flash memory is divided into predecoders 1451 to 1454, a global decoder 1455, a select gate decoder 1456, well potential control circuits 1457 and 1458, source line drivers 1459 and 1460, and sectors. Memory cell arrays 1461 and 1462, and local decoders 1463 and 1464.
[0399]
FIG. 60 is a circuit diagram of the memory cell array and its peripheral circuits shown in FIG. FIG. 60 shows detailed circuits of global decoder 1455, local decoder 1464, memory cell array, source line driver 1460, and select gate decoder 1456. In FIG. 60, “2AL” indicates a wiring formed by the second aluminum wiring layer, and “2POL” indicates a wiring formed by the second polysilicon layer.
[0400]
Table 1 below shows voltages applied to the circuits shown in FIGS. 59 and 60 in the erase operation, the program operation, and the read operation.
[0401]
[Table 1]

[0402]
In the twelfth embodiment, in addition to the various advantages already described, the following additional advantages can be obtained.
[0403]
FIG. 61 is a layout diagram on a semiconductor substrate showing a connection mode between word lines WL00 to WL07 and WL10 to WL17 shown in FIG. 60 and output lines WL0 to WL7 of local decoder 1464. Referring to FIG. 61, each of word lines WL00 to WL07 and WL10 to WL17 is formed of a second polysilicon layer. On the other hand, each output line of local decoder 1464 is formed by a first aluminum wiring layer. The connection between each word line and the corresponding output signal line is made via a through hole. It is pointed out that the connection mode shown in FIG. 61 is also shown in the circuit diagram shown in FIG.
[0404]
By using the connection modes shown in FIGS. 60 and 61, the connection between the word line and the output line of the local decoder is simplified, and therefore, the wiring density is reduced, and as a result, a high degree of integration is obtained.
[0405]
FIG. 62 is a cross-sectional view showing the separation between the two memory cells 1491 and 1492 shown in FIG. Memory cells 1491 and 1492 shown in FIG. 60 are located at positions closest to the other sector in each sector. In order to separate these transistors 1491 and 1492, an isolation oxide film 1490 is formed in the semiconductor substrate as shown in FIG. The width Wc of isolation oxide film 1490 required to separate two adjacent transistors 1491 and 1492 is smaller than that in the case where transistors 1495 and 1496 for a field shield as shown in FIG. 63 are used. . That is, in the example shown in FIG. 63, a large width Wd is required only for forming transistors 1495 and 1496 for isolation, but by using isolation oxide film 1490, two transistors 1491 adjacent to each other with a smaller width Wc are required. And 1492 can be separated. Thereby, a higher degree of integration can be obtained.
[0406]
FIG. 64 is a circuit diagram of a word line voltage control circuit and a predecoder used in the twelfth embodiment. The word line voltage control circuit 1470 shown in FIG. 64 is omitted in FIG. 59 for simplification.
[0407]
Referring to FIG. 64, word line voltage control circuit 1470 includes a VPP generator 1471, a VBB generator 1472, a voltage detector 1473, an inverter 1474, a VPP switching circuit 1475, a VPP switching circuit 1476, and a CMOS. Transmission gates 1477 and 1478.
[0408]
Predecoder 1452 includes a PMOS transistor 1481 and an NMOS transistor 1482 forming a CMOS transmission gate.
[0409]
In word line voltage control circuit 1470 and predecoder 1452 shown in FIG. 64, the voltages shown in Table 1 described above are applied to execute an erase operation, a program operation, and a read operation.
[0410]
Generally, an external voltage VEW for testing is applied to check the distribution of threshold voltages of memory cells of a flash memory. As shown in FIG. 64, in test mode operation, external voltage VEW is supplied via CMOS transmission gate 1478 in word line voltage control circuit 1470 and CMOS transmission gate in predecoder 1452 (constituted by transistors 1481 and 1482). This is applied to word lines WL00 to WL17 shown in FIG. Since the voltage path of the external voltage VEW is formed only by the CMOS circuit, no voltage loss occurs due to the threshold voltage of the MOS transistor. In other words, the external voltage VEW that changes in a wider range can be applied to the word line without changing the voltage level, and a desired test can be performed.
[0411]
(13) 13th embodiment
FIG. 65 is a schematic diagram of a thirteenth embodiment of the nonvolatile semiconductor memory device according to the present invention. The semiconductor substrate 80 is divided into a memory transistor region and a peripheral region. In the memory transistor region, memory transistors 87a, 87b, 87c, 87d are formed with a space therebetween. In the main surface of the semiconductor substrate 80, in the memory transistor region, n-type source regions 84a and 84b and n-type drain regions 85a and 85b are formed at intervals. The source region 84a becomes a source region of the memory transistors 87a and 87b, and the source region 84b becomes a source region of the memory transistors 87c and 87d.
[0412]
The drain region 85a becomes a drain region of the memory transistors 87b and 87c, and the drain region 85b becomes a drain region of the memory transistor 87d. Reference numeral 88 indicates a control gate, and 89 indicates a floating gate.
[0413]
A select gate transistor 86 having n-type source / drain regions 83a and 83b is formed in the memory transistor region on the main surface of the semiconductor substrate 80. The source / drain region 83b also functions as a drain region of the memory transistor 87a.
[0414]
A sub-bit line 90 made of polycrystalline silicon is formed on the memory transistors 87a, 87b, 87c, 87d. Sub bit line 90 is connected to source / drain region 83b. Branch line 91a branched from sub-bit line 90 is connected to drain region 85a, and branch line 91b is connected to drain region 85b. A main bit line 92 made of aluminum is formed on sub bit line 90. The main bit line 92 is connected to the source / drain region 83a.
[0415]
In the semiconductor substrate 80, a p-well region 82 is formed so as to surround the memory transistor region, and an n-well region 81 is formed so as to surround the p-well region 82. A MOS transistor 93 is formed in the peripheral region. A more detailed description of the nonvolatile semiconductor memory device according to the present invention will be given using a fourteenth embodiment.
[0416]
(14) Fourteenth embodiment
FIG. 66A is a cross-sectional view of a part of a memory transistor portion of a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention. A p-well region 210 is formed on a p-type silicon substrate 201 with a space therebetween. On p well region 210, memory transistors 250 to 257, 261, 262 and select gate transistors 259, 260 are formed. In the p-well region 210, an n-type source region 223 and an n-type drain region 224 of each memory transistor are formed. Reference numeral 249 denotes an n-type impurity region.
[0417]
Each memory transistor and select gate transistor are covered with a silicon oxide film 247. The source region 223 is covered with a silicon oxide film 247. On the other hand, the drain region 224 and the impurity region 249 are not covered with the silicon oxide film. Each memory transistor has a floating gate 219 and a control gate 220.
[0418]
Each drain region 224 of the memory transistors 250 to 257 is electrically connected by one sub-bit line 227a. The drain regions 224 of the memory transistors 261 and 262 are electrically connected by one sub-bit line 227b. The impurity region 249 is electrically connected to the connection conductive layer 248. On the field oxide film 206, a dummy gate transistor 258 having a dummy gate 242 is formed. Details of the dummy gate transistor will be described later.
[0419]
An interlayer insulating film 245 is formed on sub bit lines 227a and 227b, and a main bit line 233 is formed on interlayer insulating film 245. The main bit line 233 is electrically connected to the connection conductive layer 248. An interlayer insulating film 246 is formed on main bit line 233, and an aluminum wiring 238 is formed on interlayer insulating film 246 with a space therebetween.
[0420]
On the other hand, n-well region 207 is formed in silicon substrate 201 so as to cover p-well region 210.
[0421]
FIG. 66B is an equivalent circuit diagram of the memory transistor shown in FIG. Each drain region of the eight memory transistors is connected to a sub-bit line, and a source region is connected to a source line. The selection gate 1 conducts / cuts off the main bit line and the sub-bit line. Word lines 1 to 8 are control gates.
[0422]
FIG. 67 is a sectional structural view of a memory transistor of a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention. A gate oxide film 213 is formed between the p-well region 210 and the floating gate 219, and an ONO film 215 is formed between the floating gate 219 and the control gate 220.
[0423]
Next, the operation of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIGS. First, the erasing operation will be described. In the NOR type and the NAND type described in the conventional example, the erased state is obtained by extracting electrons. In the fourteenth embodiment, the erased state is obtained by injecting electrons. That is, when the memory transistors 250 to 257 are erased collectively, the main bit line 233 is kept in a floating state and the select gate transistor 259 is turned off. As a result, the sub bit line 227a is also in a floating state. Then, a voltage of about −10 V is applied to the source line and the p-well region 210a. Then, a voltage of about 10 V is applied to the word lines 1 to 8. As a result, as shown by (2) in FIG. 67, electrons in the channel region are injected into the floating gate 219 by the channel FN phenomenon, which is one of the tunnel effects. This is the erased state "1", and the value of Vth is about 6V.
[0424]
Next, the write operation will be described. For example, when the memory transistor 257 is set to the write state “0”, the select gate transistor 259 is turned on, and a voltage of about 5 V is applied to the main bit line 233. As a result, the voltage of the sub bit line 227a also becomes about 5V. Then, the p-well region 210a is kept at the ground potential, and the source line is set to OPEN. Further, a voltage of about -10 V is applied to the word line 8, and the word lines 1 to 7 are kept at the ground potential. As a result, as shown in (1) of FIG. 67, the electrons accumulated in the floating gate 219 of the memory transistor 257 are extracted to the drain region 224 by the drain FN phenomenon, which is one of the tunnel effects. As a result, the memory transistor 257 enters the write state “0”, and at this time, the value of Vth becomes about 1V.
[0425]
Next, the read operation will be described. For example, when reading memory transistor 257, select gate transistor 259 is turned on, and a voltage of about 1 V is applied to main bit line 233. Then, the source line and the p-well region 210a are kept at the ground potential. Then, a voltage of about 3 to 5 V is applied to the word line 8, and the word lines 1 to 7 are set to the ground potential. At this time, when the memory transistor 257 is in the erased state “1”, no channel is formed and no current flows through the bit line. On the other hand, when the write state is "0", a channel is formed and a current flows through the bit line. Thus, a write state / erase state is determined.
[0426]
In the fourteenth embodiment, a negative voltage is applied to the p-well region 210. Since there is an n-well region 207 around the p-well region 210, even if a negative voltage is applied, the p-well region 210 and the n-well region 207 are in a reverse bias state, and a voltage is applied to the p-well region 210. Also, no voltage is applied to the peripheral circuit formation region.
[0427]
At the time of erasing operation, a negative voltage is applied to the p-well region and a positive voltage is applied to the word line, so that the maximum voltage value is reduced while the voltage between the p-well region 210 and the control gate 220 is reduced. By making the potential difference relatively large, it is possible to cause the channel FN effect.
[0428]
As shown in FIG. 66A, a sub-bit line 227a is connected to each drain region 224 of the memory transistors 250 to 257. For this reason, in the read operation, a large read current can be obtained, so that the read operation can be performed at a higher speed than in the NAND type.
[0429]
Further, as shown in FIG. 67, since the drain operation is used for the write operation, the write operation can be performed with higher efficiency as compared with the case where the channel hot electrons are used, whereby the power consumption can be reduced.
[0430]
Next, a planar arrangement state of the structure shown in FIG. FIG. 68 is a plan view up to the state where the control gate 220 is formed. The state of FIG. 68 cut along the line AA shows the state up to the control gate 220 in FIG. The control gate 220, the selection gate 234, the dummy gate 242, and the source line 223a extend in the vertical direction. The source lines 223a connect the source regions 223 shown in FIG. Field oxide films 206 and drain regions 224 are formed alternately. The wiring layer on the select gate 234 (corresponding to the control gate of the memory transistor) is not shown.
[0431]
FIG. 69 shows a state where sub-bit lines 227a and 227b are formed on FIG. The source line 223a is electrically connected to the wiring layer 241. The wiring layer 241 is formed simultaneously with the sub-bit lines 227a and 227b.
[0432]
The selection gate 234 is electrically connected to the poly pad 236. The poly pad 236 is also formed simultaneously with the sub-bit lines 227a and 227b. The contacts between the sub-bit lines 227a and 227b and the drain region 224 are not shown. Further, the contact between the connection conductive layer 248 and the impurity region 249 is not shown.
[0433]
FIG. 70 shows a state where a main bit line 233 is formed on FIG. The main bit line 233 is electrically connected to the connection conductive layer 248. The aluminum electrodes 237a, 237b, 237c, and 237d are formed simultaneously with the main bit line 233. Aluminum electrode 237a is electrically connected to one poly pad 236, and aluminum electrode 237b is electrically connected to the other poly pad 236. The aluminum electrode 237c is electrically connected to the wiring layer 241. The aluminum electrode 237d is electrically connected to the dummy gate 242.
[0434]
FIG. 71 shows a state in which aluminum wirings 238a to 238g are formed on FIG. Aluminum wiring 238a is electrically connected to aluminum electrode 237a, aluminum wiring 238b is electrically connected to aluminum electrode 237b, aluminum wiring 238e is electrically connected to aluminum electrode 237c, and aluminum wiring 238f and 238g are aluminum electrodes. 237b.
[0435]
Next, first to seventh examples of the entire configuration and operation of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to Table 2.
[0436]
The memory cell matrix included in this nonvolatile semiconductor memory device is divided into a plurality of sectors as described below. Table 2 shows conditions for applying voltages to the memory cells (memory transistors) in the selected sector and the memory cells (memory transistors) in the non-selected sectors. In Table 2, Vd indicates a drain voltage, Vg indicates a control gate voltage, Vs indicates a source voltage, and Vbb indicates a well voltage.
[0437]
[Table 2]

[0438]
<1> First example
(A) Overall configuration of a nonvolatile semiconductor memory device
FIG. 72 is a block diagram showing the entire configuration of the nonvolatile semiconductor memory device according to the first example.
[0439]
The memory cell matrix 70 is divided into sectors SE1 and SE2. Memory cell matrix 70 includes select gates SG1 and SG2 corresponding to sectors SE1 and SE2, respectively. Memory cell matrix 70 is formed in P well region 71.
[0440]
In memory cell matrix 70, two main bit lines MB0 and MB1 are arranged. Main bit lines MB0 and MB1 are connected to sense amplifier 52 and write circuit 53 via Y gate transistors YG0 and YG1 in Y gate 72, respectively.
[0441]
Two sub-bit lines SB01 and SB02 are provided corresponding to main bit line MB0, and two sub-bit lines SB11 and SB12 are provided corresponding to main bit line MB1.
[0442]
Word lines WL0 and WL1 are arranged so as to cross sub bit lines SB01 and SB11, and word lines WL2 and WL3 are arranged so as to cross sub bit lines SB02 and SB12.
[0443]
At the intersections of the sub-bit lines SB01, SB02, SB11, SB12 and the word lines WL0 to WL3, memory cells (memory transistors) M00 to M03, M10 to M13 are provided, respectively. Memory cells M00, M01, M10, and M11 are included in sector S1, and memory cells M02, M03, M12, and M13 are included in sector SE2.
[0444]
The drain of each memory cell is connected to a corresponding sub-bit line, the control gate is connected to a corresponding word line, and the source is connected to a source line SL.
[0445]
Select gate SG1 includes select gate transistors SG01 and SG11, and select gate SG2 includes select gate transistors SG02 and SG12. Sub-bit lines SB01 and SB02 are connected to main bit line MB0 via select gate transistors SG01 and SG02, respectively, and sub-bit lines SB11 and SB12 are connected to main bit line MB1 via select gate transistors SG11 and SG12, respectively. .
[0446]
Address buffer 58 receives an externally applied address signal, supplies an X address signal to X decoder 59, and supplies a Y address signal to Y decoder 57. X decoder 59 selects one of a plurality of word lines WL0 to WL3 in response to the X address signal. Y decoder 57 generates a selection signal for selecting one of a plurality of main bit lines MB0 and MB1 in response to the Y address signal.
[0447]
Y gate transistors in Y gate 72 connect main bit lines MB0 and MB1 to sense amplifier 52 and write circuit 53 in response to the selection signals, respectively.
[0448]
At the time of reading, sense amplifier 52 detects data read on main bit line MB0 or main bit line MB1, and outputs the same to outside via data input / output buffer 51.
[0449]
At the time of writing, externally applied data is applied to write circuit 53 via data input / output buffer 51, and write circuit 53 applies a program voltage to main bit lines MB0 and MB1 according to the data.
[0450]
High voltage generating circuits 54 and 55 receive power supply voltage Vcc (for example, 5 V) from the outside and generate a high voltage. Negative voltage generating circuit 56 receives power supply voltage Vcc from the outside and generates a negative voltage. Verify voltage generating circuit 60 receives an externally applied power supply voltage Vcc, and applies a predetermined verify voltage to a selected word line at the time of verification. Well potential generation circuit 61 applies a negative voltage to p well region 71 at the time of erasing. The source control circuit 62 applies a high voltage to the source line SL at the time of erasing. Select gate decoder 63 selectively activates select gates SG1 and SG2 in response to a part of the address signal from address buffer 58.
[0451]
Write / erase control circuit 50 controls the operation of each circuit in response to an externally applied control signal.
[0452]
(B) Operation of nonvolatile semiconductor memory device
Next, sector erase operation, write operation and read operation of the nonvolatile semiconductor memory device will be described with reference to Table 1.
[0453]
(I) Sector erase operation
Here, it is assumed that the sector SE1 is collectively erased. First, the write / erase control circuit 50 is supplied with a control signal designating a sector batch erasing operation. Thereby, high voltage generation circuit 55 and negative voltage generation circuit 56 are activated.
[0454]
The high voltage generation circuit 55 applies a high voltage (10 V) to the X decoder 59. The X decoder 59 applies a high voltage (10 V) to the word lines WL0 and WL1 of the sector SE1, and applies 0 V to the word lines WL2 and WL3 of the sector SE2. Negative voltage generating circuit 56 applies a negative voltage to Y decoder 57 and well potential generating circuit 61. Y decoder 57 applies a negative voltage to Y gate transistors YG0 and YG1 in Y gate 72. Thereby, main bit lines MB0 and MB1 enter a floating state. The source control circuit 62 sets the source line SL to a floating state. Further, well potential generating circuit 61 applies a negative voltage (−8 V) to p well region 71. The select gate decoder 63 turns off the select gates SG1 and SG2.
[0455]
Thus, a voltage is applied to the memory cells in the selected sector SE1 and the memory cells in the non-selected sector SE2 as shown in (E1) of Table 2. As a result, all the memory cells in the sector SE1 are erased.
[0456]
(Ii) Write operation
Here, it is assumed that the memory cell M00 is programmed. That is, data “0” is written to memory cell M00, and memory cell M10 holds data “1”.
[0457]
First, a control signal designating a program operation is applied to write / erase control circuit 50. Thereby, high voltage generation circuit 54 and negative voltage generation circuit 56 are activated.
[0458]
Negative voltage generating circuit 56 applies a negative voltage to X decoder 59. X decoder 59 selects word line WL0 in response to an X address signal provided from address buffer 58, applies a negative voltage (−8 V) to selected word line WL0, and selects unselected word lines WL1 to WL3. To 0 V.
[0459]
The high voltage generation circuit 54 applies a high voltage to the Y decoder 57, the write circuit 53, and the select gate decoder 63. First, data “0” is externally applied to the write circuit 53 via the data input / output buffer 51 and latched. Y decoder 57 applies a high voltage to Y gate transistor YG0 in Y gate 72 and applies 0 V to Y gate transistor YG1 in response to a Y address signal provided from address buffer 58. This turns on the Y gate transistor YG0.
[0460]
Write circuit 53 applies a program voltage (5 V) corresponding to data "0" to main bit line MB0 via Y gate transistor YG0. The select gate decoder 63 turns on the select gate SG1 and turns off the select gate SG2. Thereby, sub-bit lines SB01 and SB11 are connected to main bit lines MB0 and MB1, respectively. The source control circuit 62 sets the source line SL to a floating state. Well potential generating circuit 61 applies 0 V to p well region 71.
[0461]
Thus, a voltage is applied to the memory cell M00 as shown in the left column of (P1) in Table 2. As a result, the threshold voltage of the memory cell M00 decreases.
[0462]
After a lapse of a predetermined time (for example, 1 ms), data “1” is externally applied to write circuit 53 via data input / output buffer 51 and latched. Y decoder 57 applies a high voltage to Y gate transistor YG1 in Y gate 72 and applies 0 V to Y gate transistor YG0 in response to a Y address signal provided from address buffer 58. This turns on the Y gate transistor YG1. Write circuit 53 applies 0 V corresponding to data "1" to main bit line MB1 via Y gate transistor YG1.
[0463]
Thus, a voltage is applied to the memory cell M10 as shown in the right column of (P1) in Table 2. As a result, the threshold voltage of the memory cell M10 is kept high.
[0464]
(Iii) Read operation
Here, it is assumed that data is read from memory cell M00. First, a control signal designating a read operation is applied to write / erase control circuit 50.
[0465]
X decoder 59 selects word line WL0 in response to an X address signal provided from address buffer 58, and applies 3V to it. At this time, the word lines WL1 to WL3 are kept at 0V. Select gate decoder 63 turns on select gate SG1 and turns off select gate SG2. Y decoder 57 turns on Y gate transistor YG 0 in Y gate 72 in response to a Y address signal provided from address buffer 58. Source control circuit 62 grounds source line SL.
[0466]
In this way, a voltage is applied to the selected memory cell M00 as shown in the left column of (R1) in Table 2. Thereby, if the content of M00 is "1", a read current flows to main bit line MB0. This read current is detected by the sense amplifier 52 and output to the outside via the data input / output buffer 51. At this time, a voltage is applied to the unselected memory cells as shown in the right column of (R1) in Table 2.
[0467]
<2> Second example
(A) Overall configuration of a nonvolatile semiconductor memory device
FIG. 73 is a block diagram showing the entire configuration of the nonvolatile semiconductor memory device according to the second example.
[0468]
The nonvolatile semiconductor memory device of FIG. 73 differs from the nonvolatile semiconductor memory device of FIG. 72 in that negative voltage generating circuit 56 applies a negative voltage to source control circuit 62 at the time of erasing.
[0469]
The configuration of the other parts is the same as the configuration shown in FIG.
(B) Operation of nonvolatile semiconductor memory device
The write operation and read operation of the nonvolatile semiconductor memory device of the second example are similar to those of the first example. In the sector erase operation, the source control circuit 62 applies a negative voltage (−8 V) to the source line SL, which is different from the first example.
[0470]
At the time of batch erasing, a voltage is applied to the memory cells in the selected sector as shown in the left column of (E2) in Table 2, and to the memory cells in the non-selected sectors, the right column of (E2) in Table 2 is applied. A voltage is applied as shown in FIG.
[0471]
<3> Third example
(A) Overall configuration of a nonvolatile semiconductor memory device
FIG. 74 is a block diagram showing the entire configuration of the nonvolatile semiconductor memory device according to the third example.
[0472]
The nonvolatile semiconductor memory device of the third example is different from the nonvolatile semiconductor memory device of the first example in the following points. A source decoder 102 is provided instead of the source control circuit 62. Negative voltage generating circuit 56 applies a negative voltage to select gate decoder 63 and source decoder 102 instead of Y decoder 57.
[0473]
The sources of the memory cells M00, M01, M10, and M11 in the sector SE1 are connected to the source line SL1, and the sources of the memory cells M02, M03, M12, and M13 in the sector SE2 are connected to the source line SL2. The output terminal of source decoder 102 is connected to source lines SL1 and SL2.
[0474]
(B) Operation of nonvolatile semiconductor memory device
The write operation and read operation of the nonvolatile semiconductor memory device of the third example are similar to those of the first example. In the sector batch erasing operation, the source decoder 102 sets the source line corresponding to the selected sector to a floating state, and applies a negative voltage (−8 V) to the source line corresponding to the non-selected sector. For example, at the time of batch erasing of the sector SE1, the source line SL1 is set to a floating state, and −8 V is applied to the source line SL2.
[0475]
In this way, the voltage is applied to the memory cells in the selected sector as shown in the left column of (E3) in Table 2, and the memory cells in the non-selected sectors are applied to the right of (E3) in Table 2 Voltage is applied as shown in the column.
[0476]
As a result, the memory cells in the selected sector can be erased collectively while the data of the memory cells in the non-selected sector are protected stably.
[0477]
<4> Fourth example
(A) Overall configuration of a nonvolatile semiconductor memory device
FIG. 75 is a block diagram showing the overall configuration of the nonvolatile semiconductor memory device according to the fourth example.
[0478]
The nonvolatile semiconductor memory device of the fourth example is different from the nonvolatile semiconductor memory device of the third example shown in FIG. 74 in the following point. Negative voltage generating circuit 56 applies a negative voltage only to well potential generating circuit 61 at the time of erasing, and does not apply a negative voltage to select gate decoder 63 and source decoder 102.
[0479]
(B) Operation of nonvolatile semiconductor memory device
The write operation and the read operation of the nonvolatile semiconductor memory device of the fourth example are similar to those of the first example.
[0480]
At the time of the batch erasing operation, the source decoder 102 sets the source line corresponding to the selected sector to a floating state, and applies 0 V to the source line corresponding to the non-selected sector. For example, at the time of batch erasing of the sector SE1, the source line SL1 is in a floating state, and 0 V is applied to the source line SL2.
[0481]
In this way, the voltage is applied to the memory cells in the selected sector as shown in the left column of (E4) in Table 2, and the memory cells in the non-selected sectors are applied to the memory cells in the unselected sector. Voltage is applied as shown in the right column.
[0482]
As a result, it is possible to collectively erase the memory cells in the selected sector while stably protecting the data in the memory cells in the non-selected sector.
[0483]
<5> Fifth example
(A) Overall configuration of a nonvolatile semiconductor memory device
FIG. 76 is a block diagram showing the entire configuration of the nonvolatile semiconductor memory device according to the fifth example.
[0484]
The nonvolatile semiconductor memory device of the fifth example is different from the nonvolatile semiconductor memory device of the fourth example shown in FIG. 75 in the following point. Two negative voltage generating circuits 56a and 56b are provided. Negative voltage generating circuit 56a applies a negative voltage to well potential generating circuit 61, select gate decoder 63 and source decoder 102. Negative voltage generating circuit 56b applies a negative voltage to X decoder 59. The configuration of the other parts is the same as the configuration shown in FIG.
[0485]
(B) Operation of nonvolatile semiconductor memory device
The write operation and the read operation of the nonvolatile semiconductor memory device of the fifth example are the same as those of the first example.
[0486]
At the time of the sector erase operation, the source decoder 102 sets the source line corresponding to the selected sector to a floating state, and applies -4 V to the source line corresponding to the non-selected sector. For example, at the time of batch erasing of the sector SE1, the source line SL1 is in a floating state, and -4 V is applied to the source line SL2.
[0487]
In this way, a voltage is applied to the memory cells in the selected sector as shown in the left column of (E5) in Table 2, and the memory cells in the non-selected sectors are applied to (E5) in Table 2 Voltage is applied as shown.
[0488]
As a result, the memory cells in the selected sector can be erased collectively while the data of the memory cells in the non-selected sector are protected stably.
[0489]
<6> Sixth example
The entire configuration of the nonvolatile semiconductor memory device according to the sixth example is the same as the configuration shown in FIG. The write operation and the read operation of the nonvolatile semiconductor memory device of the sixth example are the same as those of the first example.
[0490]
At the time of the batch erase operation, the source decoder 102 applies -8 V to the source line corresponding to the selected sector and 0 V to the source line corresponding to the non-selected sector. For example, at the time of batch erasing of sector SE1, -8 V is applied to source line SL1 and 0 V is applied to source line SL2.
[0490]
In this way, the voltage is applied to the memory cells in the selected sector as shown in the left column of (E6) in Table 2, and the memory cells in the non-selected sectors are applied to the memory cells in the non-selected sectors. Voltage is applied as shown in the right column.
[0492]
As a result, the memory cells in the selected sector can be erased collectively while the data of the memory cells in the non-selected sector are protected stably.
[0493]
<7> Seventh example
The overall configuration of the nonvolatile semiconductor memory device according to the seventh example is the same as the configuration shown in FIG. The writing operation and the reading operation of the nonvolatile semiconductor memory device of the seventh example are the same as those of the first example.
[0494]
During the sector erase operation, the source decoder 102 applies −8 V to the source line corresponding to the selected sector and −4 V to the source line corresponding to the non-selected sector. For example, when the sector SE1 is selected, −8 V is applied to the source line SL1 and −4 V is applied to the source line SL2.
[0495]
In this way, a voltage is applied to the memory cells in the selected sector as shown in the left column of (E7) in Table 2, and the memory cells in the non-selected sector are applied to the right column of (E7) in Table 2 A voltage is applied as shown in FIG.
[0496]
As a result, the memory cells in the selected sector can be erased collectively while the data of the memory cells in the non-selected sector are protected stably.
[0497]
<8> Advantages of each example
In the first and second examples, the unselected sectors receive some disturbance from the substrate, but the source decoder is not required, and only one negative voltage generation circuit is required.
[0498]
In the third example, the unselected sector receives a small disturbance from the substrate. Also, only one negative voltage generation circuit is required. Furthermore, the junction withstand voltage of the source at the time of erasing may be low. However, a source decoder is required.
[0499]
In the fourth and sixth examples, the unselected sector receives the least disturbance from the substrate. Also, only one negative voltage generation circuit is required. However, a source decoder is required, and only a junction withstand voltage of 8 V is required.
[0500]
In the fifth and seventh examples, the disturb received by the non-selected sector from the substrate may be rather small, and the junction withstand voltage of the source may be as small as 4V. However, a source decoder is required, and two negative voltage generation circuits are required.
[0501]
Next, a method of manufacturing the nonvolatile semiconductor memory device according to the fourteenth embodiment of the present invention shown in FIG. 66A will be described with reference to FIGS. 77 to 95 are cross-sectional views showing first to nineteenth steps in the method for manufacturing a nonvolatile semiconductor memory device having the above-described structure.
[0502]
First, referring to FIG. 77, an underlying oxide film 202 having a thickness of about 300 ° is formed on the main surface of p-type silicon substrate 201. Then, a polycrystalline silicon film 203 having a thickness of about 500 ° is formed on the underlying oxide film 202 by using a CVD (Chemical Vapor Deposition) method. On this polycrystalline silicon film 203, a silicon nitride film 204 of about 1000 ° is formed by using a CVD method or the like. Then, a resist 205 is formed on the silicon nitride film 204 so as to expose the element isolation region. The silicon nitride film 204 and the polycrystalline silicon film 203 on the element isolation region are etched by performing anisotropic etching using the resist 205 as a mask.
[0503]
Thereafter, resist 205 is removed, and selective oxidation is performed using silicon nitride film 204 as a mask, thereby forming field oxide film 206 as shown in FIG. Then, the polycrystalline silicon film 203 and the silicon nitride film 204 are removed.
[0504]
Next, as shown in FIG. 79, phosphorus (P) is ion-implanted into a part of the memory transistor region and a part of the peripheral circuit region under the condition of 3.0 MeV and 2.0 × 10 13 cm −3. Then, impurity driving is performed at a temperature of 1000 ° C. for one hour. Thereby, n-well 207 is formed. Thereafter, as shown in FIG. 80, a resist 209 is formed so as to cover the memory cell formation region, and using this resist 209 as a mask, phosphorus (P) is added at 1.2 MeV and 1.0 × 10 13 cm −3. Ion implantation is performed under the conditions, and phosphorus (P) is further implanted under the conditions of 180 KeV and 3.5 × 10 12 cm −3. Thereby, an n-well (not shown) is formed in a part of the peripheral circuit region.
[0505]
Next, referring to FIG. 81, boron (B) is ion-implanted into the memory transistor region under the condition of 700 KeV and 1.0 × 10 13 cm −3, and further boron is implanted under the condition of 180 KeV and 3.5 × 10 12 cm −3. (B) is ion-implanted. Thereby, p well 210 is formed.
[0506]
After impurity implantation for controlling the threshold voltage of each memory transistor is performed, referring to FIG. 82, the entire surface of the main surface of p-type silicon substrate 201 is subjected to a thermal oxidation treatment to form a film of about 150 °. A thick gate insulating film 211 is formed. Then, a resist 212 is formed so as to cover a selection gate transistor (described later) formation region on the gate insulating film 211. Using the resist 212 as a mask, etching is performed to remove portions of the gate insulating film 211 other than the select gate transistor formation region.
[0507]
By removing the resist 212 and performing thermal oxidation again, a gate insulating film 213 having a thickness of about 100 ° is formed on the entire surface of the p-type silicon substrate 201. Thus, gate insulating films 211 and 213 having a thickness of about 250 ° are formed in the select gate transistor formation region. Then, a first polycrystalline silicon film 214 is formed on gate insulating films 211 and 213 to a thickness of about 1200 ° by a CVD method or the like. Then, a resist 212a having a predetermined shape (in this case, a plurality of resist patterns is formed intermittently in a direction perpendicular to the paper surface) is deposited on the first polycrystalline silicon film thickness 214, and the resist 212a is formed. Is etched using first as a mask.
[0508]
Thereafter, as shown in FIG. 84, a high-temperature oxide film having a thickness of about 100 ° is formed on first polycrystalline silicon film 214 by using a CVD method or the like, and a CVD method is formed on the high-temperature oxide film. A silicon nitride film is formed to a thickness of about 100 ° using, for example, and a high-temperature oxide film having a thickness of about 150 ° is formed on the silicon nitride film by a CVD method. Thereby, an ONO film 215 is formed.
[0509]
Next, referring to FIG. 85, an impurity-introduced polycrystalline silicon layer is formed on the ONO film 215 to a thickness of about 1200 ° by the CVD method. Then, a tungsten silicide (WSi) layer is formed on the polycrystalline silicon layer to a thickness of about 1200 ° by a sputtering method. Thus, a conductive layer 216 serving as a control gate electrode is formed. A high-temperature oxide film 217 having a thickness of about 2000 ° is formed on conductive layer 216 by using a CVD method. Then, a resist 218 is formed on the high-temperature oxide film 217 located on the memory transistor region and the peripheral transistor formation region, and etching is performed using the resist 218 as a mask to form a transistor electrode used in a peripheral circuit. I do.
[0510]
Next, referring to FIG. 86, a resist 218a is formed on the high-temperature oxide film 217 intermittently in the horizontal direction in FIG. Then, using the resist 218a as a mask, the high-temperature oxide film 217, the conductive film 216, the ONO film 215, and the first polycrystalline silicon film 214 are etched. Thereby, a floating gate electrode 219 and a control gate electrode 220 are formed.
[0511]
Next, referring to FIG. 87 (a), a resist 221 is further applied on the flash memory in the state shown in FIG. 86, and this resist 221 is patterned so as to expose a portion serving as a source region of the memory transistor. I do. FIG. 87 (b) is a plan view showing a partial plane of the flash memory in the state shown in FIG. 87 (a). Then, a cross section viewed along the line BB in FIG. 87 (b) is shown in FIG. 87 (a). The field oxide film 206 formed on the source region is removed by performing dry etching using the resist 221 thus patterned as a mask.
[0512]
Then, after removing the resists 218a and 211, as shown in FIG. 88, a resist pattern 221a is formed so as to expose only the select gate transistor. Then, using this resist pattern 221a as a mask, phosphorus (P) is ion-implanted under the conditions of 60 KeV and 3.0 × 10 13 cm −3. Thereby, source / drain regions 223 and 224 of the select gate transistor are formed. Then, the resist 221a is removed.
[0513]
Thereafter, referring to FIG. 89, a resist pattern 221b is formed so as to cover a transistor serving as a select gate transistor and expose other memory cells. Then, using this resist 221b as a mask, arsenic (As) is ion-implanted under the conditions of 35 KeV and 5.5 × 10 15 cm −3. Thus, source / drain regions and source lines of the memory transistor are formed. Then, the resist 221b is removed.
[0514]
Next, referring to FIG. 90, a high-temperature oxide film having a thickness of about 2000 ° is formed in the memory transistor region by using the CVD method. Then, a sidewall 225 is formed on the side wall of the select gate transistor or the side wall of the memory transistor by anisotropically etching the high-temperature oxide film. Then, arsenic (As) is ion-implanted under the conditions of 35 KeV and 4.0 × 10 15 cm −3 using the side wall 225 as a mask. Thus, source / drain regions of the peripheral transistor are formed.
[0515]
Thereafter, referring to FIG. 91, a silicon oxide film 226 made of a TEOS (Tetra ethyl ortho Silicate) film or the like is deposited in the memory transistor region. Then, sintering of the oxide film is performed for about 30 minutes. Then, as shown in FIG. 92, the side wall 225a is formed by anisotropically etching the silicon oxide film 226. With the formation of the sidewall 225a, the source region in the memory cell is covered with the silicon oxide film.
[0516]
Next, referring to FIG. 93, a polycrystalline silicon layer having a thickness of about 2000 ° is formed by a CVD method or the like, and conductivity is imparted by introducing impurities into the polycrystalline silicon layer. A sub-bit line 227 is formed by applying a resist 228 having a predetermined shape on the polycrystalline silicon layer and patterning using the resist 228 as a mask.
[0517]
Next, referring to FIG. 94, after removing the resist 228, a silicon oxide film 229 made of a TEOS film or the like is formed on the sub-bit line 227 by using the CVD method. The thickness of this silicon oxide film 229 is about 1500 °. On this silicon oxide film 229, a silicon nitride film 230 having a thickness of about 500 ° is formed by a CVD method or the like. Then, on this silicon nitride film 230, a silicon oxide film 231 made of a BPTEOS film or the like having a thickness of about 10000 ° is formed by using a CVD method or the like. Thereafter, reflow is performed by a heat treatment at about 850 ° C., and the BPTEOS film is etched back by about 5,000 ° using HF or the like. Then, a resist 232 having a predetermined shape is deposited on the silicon oxide film 231, and the silicon oxide films 229 and 231 and the silicon nitride film 230 are etched using the resist 232 as a mask. Thus, a contact hole 233a for connecting the sub bit line 227 to the main bit line 233 formed in a later step is formed.
[0518]
Next, referring to FIG. 95, a tungsten plug 233b is formed in the contact hole 233a by using the CVD method and the etch-back method. Then, an aluminum alloy layer having a thickness of about 5000 ° is formed on the tungsten plug 233b and the silicon oxide film 231 by using a sputtering method or the like. Then, a resist 232a having a predetermined shape is deposited on the aluminum alloy layer, and the aluminum alloy layer is patterned using the resist 232a as a mask, whereby the main bit line 233 is formed. After that, the resist 232a is removed, and an interlayer insulating layer is formed on the main bit line. Then, an aluminum wiring layer is further formed on the interlayer insulating layer through a through-hole forming step. Thus, the nonvolatile semiconductor device shown in FIG. 66A is formed.
[0519]
Next, a method for manufacturing the select gate contact portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIGS. FIG. 96 to FIG. 100 are cross-sectional views taken along line CC in FIG. 68.
[0520]
First, referring to FIG. 96, the steps up to the high-temperature oxide film 217 are formed through the same steps as in the above embodiment. The select gate transistor is connected to an aluminum wiring layer 238 formed thereover via a contact hole. Therefore, a contact hole is formed at the connection portion. This contact is shown in FIG. Referring to FIG. 97, after depositing high-temperature oxide film 217 as described above, etching is performed to remove high-temperature oxide film 217 and conductive film 216 at the contact portion. Thereby, a contact hole 251 is formed.
[0521]
Referring to FIG. 98, after an oxide film made of a TEOS film or the like is formed on the entire surface by using a CVD method or the like, silicon oxide film 235 is left on the side wall of contact hole 251 by performing anisotropic etching. Let it. At this time, the ONO film 215 on the first polycrystalline silicon film 214 is also etched when the silicon oxide film 235 serving as the sidewall is formed, so that the first polycrystalline silicon film 214 is exposed.
[0522]
Next, referring to FIG. 99, a poly pad 236 made of polycrystalline silicon is formed in the contact hole 251 and at the same time, a sub-bit line 227 is formed. Thereafter, as shown in FIG. 100, an interlayer insulating film 245 is formed on the poly pad 236 and the sub-bit line 227. Then, a contact hole 251a is formed in a portion of the interlayer insulating film 245 located above the poly pad 236, and an aluminum electrode 237 is formed in the contact hole 251a. At this time, the main bit line 233 is formed simultaneously with the formation of the aluminum electrode 237. As described above, by forming the poly pad 236 at the contact portion of the select gate transistor, the aspect ratio at this contact portion can be reduced, and the margin for overlapping the patterns can be increased.
[0523]
After the main bit line 233 and the aluminum electrode 237 are formed as described above, the nonvolatile semiconductor memory device is formed through the same steps as those in the above embodiment.
[0524]
Next, a method of manufacturing the source line contact portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIGS. FIG. 101 is a plan view showing a part of the nonvolatile semiconductor memory device shown in FIG. First, referring to FIG. 101, source line 223a is formed in source line contact portion 239 so as to have a width W1 larger than width W2 of source line 223a other than the contact portion. On the other hand, reflecting the shape, the width of the drain region is as small as W4 at a portion sandwiched between the source line contact portions 239, and the width of W3 is larger at other portions. In this embodiment, the formation of the contact hole in the source line contact portion 239 and the formation of the contact hole in the drain contact portion 240 are to be performed at the same time by utilizing such a difference in width.
[0525]
The details will be described below with reference to FIGS. FIG. 102 (I) is a diagram showing a cross section viewed along line DD in FIG. 101. FIG. 102 (II) is a view showing a cross section viewed along line EE in FIG. 101. Hereinafter, the same applies to FIGS. 103 to 106.
[0526]
First, referring to FIG. 102, a floating gate electrode 219, an ONO film 215, a control gate electrode 220, and a high-temperature oxide film 217 in a memory transistor are formed through the same steps as in the above embodiment. At this time, in FIG. (I), the interval between the source portions is wider than the interval between the drain portions, and in FIG. (II), the interval between the drain portions is wider than the interval between the source portions.
[0527]
On the memory transistor in such a state, as shown in FIG. 103, a side wall 225 is formed in the same manner as in the above embodiment. Then, an oxide film 226 is further deposited on the sidewalls 225 as shown in FIG.
[0528]
Thereafter, referring to FIG. 105 (I), anisotropic etching is performed on oxide film 226 to form contact hole 239a in source line contact portion 239. At this time, since the width of the source portion is larger than the width of the drain portion, the source portion is more easily etched, and a contact hole 239a is formed in the source portion, but no contact hole is formed in the drain portion.
[0529]
On the other hand, referring to FIG. 105 (II), in this case, since the width of the drain portion is wider than that of the source portion, contact holes are formed only in the drain portion in the same manner as described above. 240a will be formed. After the contact holes 239a and 240a are simultaneously formed in this manner, as shown in FIG. 106, a sub-bit line 227 and a wiring layer 241 made of polycrystalline silicon or the like are formed on the memory transistor. .
[0530]
As described above, according to this embodiment, the formation of the source line contact portion 239 and the formation of the drain contact portion 240 are performed simultaneously by utilizing the difference in the width of the source line 223a and the difference in the width of the drain portion. Becomes possible. Further, since a mask for forming each contact hole is not required, the process can be simplified and the manufacturing cost can be reduced.
[0531]
(15) 15th embodiment
Next, a fifteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIG. FIG. 107A is a cross-sectional view of the nonvolatile semiconductor memory device after the formation of the sub-bit line 227 in the case where the dummy memory transistor is not formed. FIG. FIG. 21 is a sectional view of a fifteenth embodiment of the nonvolatile semiconductor memory device. First, referring to FIG. 107 (a), one end of sub bit line 227 is cut off on select gate transistor 234, and the other end is cut off on field oxide film 206. In such a case, there is a problem that the field oxide film 206 is reduced in film thickness at the time of contact etching and the like, and the separation characteristics are deteriorated.
[0532]
Therefore, in the fifteenth embodiment, the dummy memory transistor 242b is formed on the field oxide film 206. As a result, it is possible to reduce the step in the sub-bit line 227 without deteriorating the isolation breakdown voltage between elements. As described above, in the fifteenth embodiment, the dummy memory transistor 242b is formed on the field oxide film 206. However, as shown in FIG. 107B, the dummy memory transistor 242a is formed on the p-type silicon substrate 201. It may be formed directly. This makes it possible to inject electrons between the dummy gate 242 and the p-type silicon substrate 201 using FN tunneling. This makes it possible to have a field shield effect. Also, it is possible to inject electrons into the dummy gate 242 by channel hot electrons using the sub-bit line 227 sandwiching the dummy memory transistor 242a. With this, the same field shield effect as in the above case can be expected.
[0533]
(16) Sixteenth embodiment
Next, a sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIGS. FIG. 108 is a partial cross-sectional view of the memory transistor portion of the nonvolatile semiconductor memory device according to the sixteenth embodiment according to the present invention. FIG. 109 is a cross-sectional view corresponding to a cross-section taken along line FF in FIG. 69. 110 to 119 are cross-sectional views showing the tenth to nineteenth steps of the manufacturing process of the nonvolatile semiconductor memory device according to this embodiment.
[0534]
In each of the above embodiments, the field oxide film 206 located on the source region is removed by etching, and in this state, the source line is formed by implanting arsenic (As) or the like into the source region. However, in this case, the following problems can be considered. Immediately below the field oxide film 206, boron (B) or the like is previously injected through the field oxide film 206 in order to improve the isolation characteristics between elements. Therefore, as described above, when arsenic (As) for forming a source line is implanted after etching field oxide film 206, boron (B) implanted through field oxide film 206 and source A portion that overlaps with arsenic (As) implanted for line formation will occur. As a result, there is a problem that the carrier concentration is offset in the overlapping portion, and the source withstand voltage is lowered.
[0535]
Therefore, in this embodiment, in order to form a source line, a wiring layer made of polycrystalline silicon or the like into which impurities are introduced so as to electrically connect the source regions is formed. Thus, the wiring layer can be formed on the field oxide film 206, so that it is not necessary to remove the field oxide film 206 located on the source line formation region. Thereby, the overlap of the impurity regions as described above can be eliminated, and a decrease in the source withstand voltage can be prevented.
[0536]
Hereinafter, the present embodiment will be described more specifically with reference to the drawings. First, referring to FIG. 108, a feature of this embodiment is that a wiring layer 262 for electrically connecting source regions 223 scattered in the word line direction is formed. Other structures are the same as those in the above embodiments. In this case, the wiring layer 262 is formed of polycrystalline silicon or the like.
[0537]
The wiring layer 262 connects the source regions 223 separated by the field oxide film 206 to each other. Therefore, as shown in FIG. 109, wiring layer 262 extends over source region 223 and field oxide film 206 sandwiched between source regions 223. By providing the wiring layer 262 in this manner, each source region 223 can be electrically connected, so that it is not necessary to remove a part of the field oxide film 206 by etching. This makes it possible to prevent the source line breakdown voltage from being reduced as described above.
[0538]
Next, a method for manufacturing the nonvolatile semiconductor memory device having the above structure will be described with reference to FIGS. First, referring to FIG. 110, the high-temperature oxide film 217, the conductive film 216, the ONO film 215, and the first polycrystalline silicon film 214 are etched through the same steps as in the second embodiment. Thereby, a floating gate electrode 219 and a control gate electrode 220 are formed. Then, the resist 218a is removed.
[0539]
Next, as shown in FIG. 111, a resist pattern 221a is formed so as to expose only the select gate transistor. Then, using the resist pattern 221a as a mask, phosphorus (P) is ion-implanted under the conditions of 60 KeV and 3.0 × 10 13 cm −2. Thereby, source / drain regions 223 and 224 of the select gate transistor are formed. After that, the resist 221a is removed.
[0540]
Next, referring to FIG. 112, a resist pattern 221b is formed so as to cover a transistor serving as a select gate transistor and expose another memory transistor. Then, using this resist pattern 221b as a mask, arsenic (As) is ion-implanted under the conditions of 35 KeV and 5.5 × 10 15 cm −2. Thereby, source / drain regions of the memory transistor are formed. After that, the resist 221b is removed.
[0541]
Next, referring to FIG. 113, a high-temperature oxide film having a thickness of about 2000 ° is formed in the memory transistor region by using the CVD method. Then, a sidewall 225 is formed on the side wall of the select gate transistor or the side wall of the memory transistor by anisotropically etching the high-temperature oxide film. Then, arsenic (As) is ion-implanted under the conditions of 35 KeV and 4.0 × 10 15 cm −2 using the side wall 225 as a mask. Thus, the source / drain regions of the peripheral transistor, the source region 223, and the drain region 224 are formed.
[0542]
Next, referring to FIG. 114, a silicon oxide film 226 made of a TEOS (Tetraethyl Ortho Silicate) film or the like is deposited in the memory transistor region. Then, sintering of the oxide film is performed for about 30 minutes. Thereafter, a resist pattern 261 is formed to expose the silicon oxide film 226 located on the source region 223. Then, using the resist pattern 261 as a mask, the silicon oxide film 226 and a part of the side wall 225 located on the source region 223 are etched. Thereby, as shown in FIG. 115, a contact hole 268 is formed in a region located above source region 223. Then, the resist 261 is removed.
[0543]
Next, referring to FIG. 116, a polycrystalline silicon layer 262 is formed on the inner surface of contact hole 268 and silicon oxide film 226 by using a CVD method or the like. Then, an oxide film 263 is formed on polycrystalline silicon layer 262 by using a CVD method or the like. Then, a resist pattern 264 is formed on the oxide film 263 located on the source region 223. At this time, the end of the resist pattern 264 is located above the ends of the floating gate electrode 219 and the control gate electrode 220 located on the source side. Thereby, the distance between polycrystalline silicon layer 262 and sub-bit line 227 can be increased, and a desired breakdown voltage between polycrystalline silicon layer 262 and sub-bit line 227 can be ensured. Further, the withstand voltage between control gate electrode 220 and polycrystalline silicon layer 262 can be set to a desired value.
[0544]
Then, as shown in FIG. 117, oxide film 263 and polycrystalline silicon layer 262 are etched using resist pattern 264 as a mask. Thus, a wiring layer 262 for electrically connecting the source regions 223 scattered in the word line direction is formed.
[0545]
Next, referring to FIG. 118, after removing resist 264, oxide film 265 is formed on oxide films 226 and 263 by using a CVD method or the like. Then, a resist pattern 266 is formed to expose the oxide film 265 located on the drain diffusion region 224. Then, using the resist pattern 266 as a mask, the oxide films 265 and 226 located on the drain region 224 are removed by etching. Thereby, a part of the drain region 224 is exposed.
[0546]
Thereafter, referring to FIG. 119, after removing the above-mentioned resist 266, a polycrystalline silicon layer having a film thickness of about 2000 ° is formed by a CVD method or the like, and impurities are introduced into this polycrystalline silicon layer. This imparts conductivity. A sub-bit line 227 is formed by applying a resist 228 having a predetermined shape on the polycrystalline silicon layer and patterning the polycrystalline silicon layer using the resist 228 as a mask. Thereafter, the nonvolatile semiconductor memory device is formed through the same steps as in the second embodiment.
[0547]
(17) Seventeenth embodiment
Next, a seventeenth embodiment based on the present invention will be described with reference to FIGS. 120 to 125 and FIGS. 156 to 159. FIG. 120 is a partial cross-sectional view of the nonvolatile semiconductor memory device according to the seventeenth embodiment according to the present invention. FIG. 121 to FIG. 125 are views showing first to fifth steps of the manufacturing process of the nonvolatile semiconductor memory device shown in FIG. FIG. 156 is a plan view showing the conventional structure of the nonvolatile semiconductor memory device according to the seventeenth embodiment, and FIG. 156 is a view showing a cross section taken along line BB in FIG. . FIG. 157 is a partial cross-sectional view for describing a write operation of the conventional nonvolatile semiconductor memory device shown in FIG. 156. FIG. 158 is a partial cross-sectional view for describing an erasing operation of the nonvolatile semiconductor memory device shown in FIG. 156. FIG. 159 is a partial cross-sectional view for describing a problem in the conventional nonvolatile semiconductor memory device shown in FIG. 156.
[0548]
First, a conventional structure of a nonvolatile semiconductor memory device according to a seventeenth embodiment of the present invention will be described with reference to FIGS. Referring to FIGS. 156 (a) and 156 (b), this type of nonvolatile semiconductor memory device generally has a virtual ground configuration memory cell array (Virtual Ground).
Array).
[0549]
Referring to FIG. 156 (b), on the main surface of p-type semiconductor substrate 301, n-type high-concentration impurity regions 302a, 302b, 302c, 302d functioning as bit lines are formed substantially parallel to each other with an interval therebetween. Have been. Floating gates 305a, 305b, and 305 are formed on a region sandwiched between these high-concentration impurity regions 302a to 302d with an insulating film 304 interposed therebetween. An insulating film 306 is formed to cover these floating gates 305a, 305b, 305. A control gate 307 is formed on the surface of the insulating film 306. Referring to FIG. 156 (a), control gate 307 extends over a plurality of floating gates 305 and is substantially orthogonal to high concentration impurity regions 302a to 302d.
[0550]
Next, a conventional operation of the conventional nonvolatile semiconductor memory device having the above structure will be described with reference to FIGS. First, the write operation will be described. Referring to FIG. 156 (a) and FIG. 157, a case where writing is performed on floating gate 305b will be described. When writing to floating gate 305b, a voltage of about 12 V is applied to control gate 307 extending on floating gate 305b, and a voltage of about 5 V is applied to high concentration impurity region 302b functioning as a bit line. Is done.
[0551]
At this time, the high concentration impurity region 302a is kept in a floating state. Impurity region 302c is kept at the ground potential. Thus, a current flows from the high-concentration impurity region 302b to the high-concentration impurity region 302c. At this time, electrons are injected into the floating gate 305b. Thereby, writing is performed on floating gate 305b.
[0552]
Next, the erasing operation will be described. When erasing information written in each of the floating gates 305, 305a, 305b, each control gate 307 is kept at the ground potential, and a voltage of about 10 V is applied to each of the high-concentration impurity regions 302a to 302d. As a result, electrons are simultaneously extracted from the floating gates 305, 305a, 305b, and the written information is erased. This is shown in FIG.
[0553]
When a nonvolatile semiconductor memory device having a memory cell array of a conventional virtual ground configuration having the above configuration and operating is operated in accordance with the present invention, the following problems will occur. Will occur. The problem will be described with reference to FIG.
[0554]
When a conventional nonvolatile semiconductor memory device having a memory cell array having a virtual ground configuration is operated according to the present invention, a problem occurs when the write operation according to the present invention is performed. . Referring to FIG. 159, to write information into, for example, floating gate 305a by performing a write operation according to the present invention, a voltage of, for example, about -8 V is applied to selected control gate 307. . At this time, a voltage of about 5 V is applied to the selected bit line, in this case, the high concentration impurity region 302b functioning as a bit line. Then, unselected bit lines, in this case, the high-concentration impurity regions 302a, 302c, and 302d are held at the ground potential.
[0555]
As a result, as indicated by arrows in FIG. 159, electrons are extracted from floating gate 305a, and at the same time, electrons are extracted from floating gate 305b adjacent to floating gate 305a. This is because one end of the high-concentration impurity region 302b is formed so as to partially overlap with the floating gate 305a, and the other end is formed so as to partially overlap with the floating gate 305b.
[0556]
Since the high-concentration impurity region 302b and the floating gate 305a and the floating gate 305b are formed in such a positional relationship that they partially overlap each other, the floating gates 305a and 305b are formed in the overlapping portion by the FN phenomenon. Electrons are extracted from the That is, information has been written to both floating gates 305a and 305b. As a result, there arises a problem that a malfunction of the nonvolatile semiconductor memory device is caused.
[0557]
The nonvolatile semiconductor memory device according to the present embodiment has been devised to solve the above problems. Hereinafter, the structure and operation of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS.
[0558]
Referring to FIG. 120, in the nonvolatile semiconductor memory device having the memory cell array of the virtual ground configuration according to the present embodiment, one end of high-concentration impurity regions 302a, 302b, 302c, and 302d functioning as bit lines is floating. The other end is located below the gate 305 so as not to be located below the adjacent floating gate 305. The concentration of the high concentration impurity regions 302a, 302b, 302c, 302d is preferably 1020 / cm3 or more.
[0559]
More specifically, referring to FIG. 120, one end of high-concentration impurity region 302b is located below floating gate 305a, but floating gate 305b adjacent to floating gate 305a does not overlap impurity region 302b. So that they are offset. Other structures are almost the same as the conventional structure shown in FIG. 156 (b).
[0560]
As described above, by forming the end portion of the high-concentration impurity region 302b so as not to overlap with the adjacent floating gate 305b, for example, when performing the writing operation according to the present invention on the floating gate 305a, It is possible to avoid a situation in which electrons are extracted from 305b. This makes it possible to write information more reliably.
[0561]
Next, a method for manufacturing the nonvolatile semiconductor memory device having the structure shown in FIG. 120 in this embodiment will be described with reference to FIGS. First, referring to FIGS. 121A and 121B, an insulating film 304 having a thickness of about 100 ° is formed on the main surface of p-type semiconductor substrate 301. Then, a first polycrystalline silicon layer 305c having a thickness of about 1000 ° is deposited on insulating film 304 by using a CVD method or the like.
[0562]
On this first polycrystalline silicon 305c, a resist 308 having a desired film thickness is applied. This resist 308 is patterned into a predetermined shape. The first polycrystalline silicon layer 305c is patterned by etching using the patterned resist 308 as a mask.
[0563]
Next, referring to FIG. 122 (a), after patterning the first polycrystalline silicon layer 305c, an n-type impurity such as arsenic (As) is p-type semiconductor substrate using resist 308 as a mask. Ion implantation is performed on the main surface of the substrate 301. At this time, the implantation angle of the impurity is inclined by a predetermined angle θ. Thus, high-concentration impurity regions 302a to 302d are formed on the main surface of p-type semiconductor substrate 301 by the shadowing effect of resist 308 such that the ends thereof partially overlap only one of the adjacent floating gates. It becomes possible.
[0564]
The value of the tilt angle θ is preferably about 7 °. In this manner, arsenic (As) is ion-implanted at an angle with respect to the vertical direction by an angle of θ, so that one of the adjacent first polycrystalline silicon layers 305 c patterned according to the resist 308 is formed. High-concentration impurity regions 302a to 302d that overlap with the first polycrystalline silicon layer 305c but are offset from the other first polycrystalline silicon layer 305c are formed. FIG. 122 (b) shows this state as viewed in plan.
[0565]
Next, referring to FIG. 123, after removing resist 308, oxide film 309 is formed using CVD or the like so as to cover first polycrystalline silicon layer 305c. Then, oxide film 309 is buried between first polysilicon layers 305c by etching back oxide film 309.
[0566]
Next, referring to FIG. 124, an insulating film 306 is formed on oxide film 309 and first polycrystalline silicon layer 305c using a CVD method or the like. On this insulating film 306, a second polycrystalline silicon layer 307a having a predetermined thickness is deposited by using a CVD method or the like. Thereafter, referring to FIG. 125 (a), a resist 310 is applied on second polycrystalline silicon layer 307a, and this resist 310 is patterned into a predetermined shape. In this case, referring to FIG. 125B, the resist 310 is patterned in a direction substantially orthogonal to the high-concentration impurity regions 302a to 302d. By etching using the resist 310 patterned as described above as a mask, a control gate 307, floating gates 305a, 305b, 305 and an insulating film 306 are formed as shown in FIG. After that, the resist 310 is removed. Through the above steps, the nonvolatile semiconductor memory device shown in FIG. 120 is completed.
[0567]
Next, another mode of the seventeenth embodiment shown in FIG. 120 will be described with reference to FIG. In the nonvolatile semiconductor memory device shown in FIG. 120, only high-concentration impurity regions 302a to 302d are formed. However, in the present embodiment, the n-type high-concentration impurity regions 302a to 302d involved in the writing operation are formed by using the same method as in the above-described seventeenth embodiment. 303 are formed. By providing the low-concentration impurity regions 303 in this manner, it is possible to improve the operation characteristics of the nonvolatile semiconductor memory device. The low-concentration impurity region 303 is formed by ion-implanting an n-type impurity such as arsenic (As) into the main surface of the semiconductor substrate 301 at the same implantation angle as in the conventional example.
[0568]
As an example of the implantation condition, arsenic (As) is implanted in an amount of 1011 / cm 2 or more to form the low concentration impurity region 303. Thus, the concentration of the low-concentration impurity region 303 to be formed has a concentration of 1016 / cm3 or more. At this time, in forming the high-concentration impurity regions 302a to 302d, the implantation amount of arsenic (As) is preferably 1015 / cm2 or more. Thereby, the concentration of the high-concentration impurity regions 302a to 302d becomes 1020 / cm3 or more.
[0569]
The invention will now be summarized with reference to FIG. FIG. 127 is a schematic diagram showing an essential configuration of the nonvolatile semiconductor memory device according to the present invention. Referring to FIG. 127, impurity regions 402a and 402b are formed on the main surface of semiconductor substrate 401 at intervals. An insulating film 403 is formed on the channel region 409 between the impurity regions 402a and 402b. A floating gate 404 is formed on the insulating film 403. The floating gate 404 serves as an electron storage unit. A word line 406 is formed over the floating gate 404 via an insulating film 405. An interlayer insulating film 407 is formed on the word line 406, and a bit line 408 is formed on the interlayer insulating film 407. Bit line 408 is electrically connected to impurity region 402a via contact hole 410 provided in interlayer insulating film 407.
[0570]
In the nonvolatile semiconductor memory device having the above configuration, a characteristic operation according to the present invention is performed. First, in the characteristic operation of the nonvolatile semiconductor memory device according to the present invention, the initial state is an erased state. That is, the state where electrons are accumulated in the floating gate 404 is the erased state (initial state). As a method of accumulating electrons in the floating gate 404, first, the bit line 408 is held in a floating state, and a voltage of, for example, about −10 V is applied to the semiconductor substrate 401. At this time, a voltage of about 10 V is applied to the word line 406. Thus, electrons can be injected into the floating gate 404 by the FN phenomenon (channel FN) over the entire surface of the channel region 409. At this time, the threshold voltage Vth (E) of the memory transistor in the erased state is higher than the voltage VRead applied to the word line 406 at the time of reading.
[0571]
As described above, first, after erasing, information is written by extracting electrons from a predetermined memory transistor. At the time of writing, a voltage of about 5 V is applied to the bit line 408. At this time, the semiconductor substrate 401 is kept at the ground potential. Then, a voltage of about −10 V is applied to the word line 406. As a result, electrons are extracted from the floating gate 404. At this time, the extraction of electrons is performed by the FN phenomenon at the overlapping portion between the floating gate 404 and the impurity region 402a. As a result, the threshold voltage Vth (p) of the memory transistor after writing has a value smaller than the voltage VRead applied to the word line 406 during reading.
[0572]
As described above, in the operation of the nonvolatile semiconductor memory device according to the present invention, the state in which electrons are injected into the memory transistor is the erased state, and electrons are emitted from a predetermined memory transistor among all the memory transistors. Information will be written by pulling out. In each of the above embodiments, a case has been described in which the present invention is applied to a nonvolatile semiconductor memory device. However, the present invention is also applicable to semiconductor storage devices other than nonvolatile semiconductor storage devices.
[0573]
【The invention's effect】
thisAccording to the invention,The memory cells are divided into sectors, and the bit lines are composed of main and sub-bit lines, the erasing unit can be reduced, the load on the voltage generating circuit at the time of erasing can be reduced, and An electron transfer unit is provided, and the threshold voltage of the memory cell can be controlled for each bit. In addition, erasing and programming can be performed without using a source line.
[Brief description of the drawings]
FIG. 1 is a diagram showing a relationship between program and erase operations and threshold voltages in first to eleventh embodiments in comparison with a conventional example.
FIG. 2 is a diagram showing an erased state and a programmed state in the first to eleventh embodiments in comparison with a conventional example.
FIG. 3 is a diagram showing threshold voltages at the time of batch erasing in the first to eleventh embodiments.
FIG. 4 is a diagram showing a change in threshold voltage due to a batch erase operation in the first to eleventh embodiments.
FIG. 5 is a block diagram showing the overall configuration of the flash memory according to the first embodiment.
FIG. 6 is a diagram showing conditions for applying a voltage to a memory cell during programming and erasing in the first embodiment.
FIG. 7 is a diagram illustrating voltage application conditions during a batch erase operation, a program operation, and a read operation in the first embodiment.
FIG. 8 is a flowchart for explaining a rewriting operation in the first embodiment.
FIG. 9 is a diagram showing conditions for applying a voltage to a memory cell during programming and erasing in the second embodiment.
FIG. 10 is a diagram illustrating voltage application conditions during a batch erase operation, a program operation, and a read operation in the second embodiment.
FIG. 11 is a block diagram showing an overall configuration of a flash memory according to a third embodiment.
FIG. 12 is a block diagram showing a configuration of an X decoder included in the flash memory of FIG. 11;
FIG. 13 is a diagram showing conditions for applying a voltage to a memory cell during programming and erasing in the third embodiment.
FIG. 14 is a diagram showing voltage application conditions during a batch erase operation, a program operation, and a read operation in the third embodiment.
FIG. 15 is a diagram illustrating voltage application conditions during a page erase operation, a program operation, and a read operation in the fourth embodiment.
FIG. 16 is a flowchart for explaining a rewriting operation in the fourth embodiment.
FIG. 17 is a diagram illustrating voltage application conditions during a page erase operation, a program operation, and a read operation in the fifth embodiment.
FIG. 18 is a block diagram showing an overall configuration of a flash memory according to a sixth embodiment.
19 is a circuit diagram showing a detailed configuration of a memory array included in the flash memory of FIG. 18 and a portion related thereto.
FIG. 20 is a diagram showing conditions for applying a voltage to a memory cell during programming and erasing in the sixth embodiment.
FIG. 21 is a diagram showing voltage application conditions during a collective sector erase operation, a program operation, and a read operation in the sixth embodiment.
FIG. 22 is a flowchart for explaining a program operation and a verify operation in the sixth embodiment.
FIG. 23 is a sectional view showing a structure of a memory cell used in a flash memory according to a sixth embodiment.
FIG. 24 is a structural diagram of two adjacent memory cells in the sixth embodiment.
FIG. 25 is a layout diagram of a memory cell array in the sixth embodiment.
FIG. 26 is a circuit diagram showing voltages applied in the memory cell array of the embodiment in FIG. 6;
FIG. 27 is a circuit diagram showing an equivalent circuit of a high voltage generation circuit.
FIG. 28 is a sectional view showing a partial structure of a high-voltage generating circuit used in a flash memory according to a sixth embodiment;
FIG. 29 is a cross-sectional view for explaining that a parasitic transistor exists in the structure shown in FIG. 28;
30 is an equivalent circuit diagram of a circuit constituted by the parasitic transistors shown in FIG.
FIG. 31 is a sectional view showing another structure of the high voltage generation circuit used in the flash memory according to the sixth embodiment.
FIG. 32 is a circuit diagram showing an equivalent circuit of a negative voltage generation circuit.
FIG. 33 is a sectional view showing a partial structure of a negative voltage generating circuit used in a flash memory according to a sixth embodiment;
FIG. 34 is a circuit diagram showing a detailed configuration of a memory array included in a flash memory according to a seventh embodiment and portions related thereto.
FIG. 35 is a diagram showing a change in voltage of a main bit line during programming in the seventh embodiment.
FIG. 36 is a block diagram showing an overall configuration of a flash memory according to an eighth embodiment.
FIG. 37 is a circuit diagram showing a detailed configuration of a memory array included in the flash memory of FIG. 36 and portions related thereto.
FIG. 38 is a diagram for explaining a state of a memory cell at the time of erasing when there is no gate bird's beak.
FIG. 39 is a diagram showing conditions for applying voltage to the memory cells of the selected sector and the memory cells of the non-selected sector at the time of erasing when there is no gate bird's beak.
FIG. 40 is a diagram showing voltage application conditions during a collective sector erase operation when there is no gate bird's beak.
FIG. 41 is a circuit diagram showing a configuration of a source decoder used when there is no gate bird's beak.
FIG. 42 is a diagram showing voltages of respective parts of the source decoder of FIG. 41;
FIG. 43 is a diagram illustrating a state of a memory cell at the time of erasing when there is a gate bird's beak.
FIG. 44 is a diagram showing conditions for applying a voltage to a memory cell of a selected sector and a memory cell of a non-selected sector at the time of erasing when there is a gate bird's beak.
FIG. 45 is a diagram showing voltage application conditions during a collective sector erase operation when there is a gate bird's beak.
FIG. 46 is a circuit diagram showing a configuration of a source decoder used when there is a gate bird's beak.
FIG. 47 is a diagram showing voltages of respective parts of the source decoder of FIG. 46;
FIG. 48 is a diagram showing conditions for applying a voltage to a memory cell of a selected sector and a memory cell of an unselected sector at the time of erasing when the well potential is low.
FIG. 49 is a diagram showing voltage application conditions during a collective sector erase operation when a well potential is low.
FIG. 50 is a circuit diagram showing a configuration of a source decoder used when a well potential is low.
FIG. 51 is a diagram showing voltages of respective parts of the source decoder of FIG. 50;
FIG. 52 is a block diagram showing an overall configuration of a flash memory according to a ninth embodiment.
FIG. 53 is a circuit diagram showing a detailed configuration of a memory array included in the flash memory of FIG. 52 and a portion related thereto.
FIG. 54 is a diagram showing voltage application conditions during a collective sector erase operation in the ninth embodiment.
FIG. 55 is a circuit diagram showing a configuration of a select gate decoder and a source switch included in the flash memory of FIG. 52.
FIG. 56 is a diagram showing voltages of respective parts of the select gate decoder and the source switch of FIG. 55.
FIG. 57 is a flowchart illustrating a program operation in the flash memory according to the tenth embodiment.
FIG. 58 is a flowchart for explaining a program operation in the flash memory according to the eleventh embodiment;
FIG. 59 is a block diagram showing an overall configuration of a flash memory according to a twelfth embodiment.
FIG. 60 is a circuit diagram of the memory cell array and its peripheral circuits shown in FIG. 59.
FIG. 61 is a layout diagram on a semiconductor substrate showing a connection mode between the word lines shown in FIG. 60 and the output lines of the local decoder.
FIG. 62 is a cross-sectional structural diagram showing separation between two memory cells 1491 and 1492 shown in FIG. 60;
FIG. 63 is a cross-sectional structure diagram in a case where separation between two memory cells 1491 and 1492 shown in FIG. 60 is performed by a field shield transistor.
FIG. 64 is a circuit diagram of a word line voltage control circuit and a predecoder used in the twelfth embodiment.
FIG. 65 is a cross-sectional view of a part of a memory transistor portion of a thirteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 66 (a) is a sectional view of a part of a memory transistor section of a nonvolatile semiconductor memory device according to a fourteenth embodiment of the present invention, and FIG. 66 (b) is an equivalent circuit diagram thereof.
FIG. 67 is a sectional view showing a memory transistor according to a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 68 is a plan view up to a state where a control gate having the structure shown in FIG. 66A is formed.
FIG. 69 is a plan view up to a state where a sub-bit line having the structure shown in FIG. 66A is formed.
FIG. 70 is a plan view up to a state where a main bit line having the structure shown in FIG. 66A is formed.
FIG. 71 is a plan view up to a state where aluminum wiring having the structure shown in FIG. 66A is formed.
FIG. 72 is a block diagram showing a first example of the entire configuration of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 73 is a block diagram showing a second example of the entire configuration of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 74 is a block diagram showing a third example of the entire configuration of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 75 is a block diagram showing a fourth example of the entire configuration of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 76 is a block diagram showing a fifth example of the entire configuration of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 77 is a cross-sectional view showing a first step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 78 is a sectional view showing a second step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 79 is a cross sectional view showing a third step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 80 is a cross-sectional view showing a fourth step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 81 is a cross sectional view showing a fifth step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 82 is a sectional view showing a sixth step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 83 is a cross sectional view showing a seventh step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 84 is a cross-sectional view showing an eighth step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 85 is a cross-sectional view showing a ninth step of the method for manufacturing the memory transistor section of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 86 is a sectional view showing a tenth step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 87 is a cross sectional view showing an eleventh step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 88 is a sectional view showing a twelfth step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 89 is a sectional view showing a thirteenth step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 90 is a sectional view showing a fourteenth step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 91 is a sectional view showing a fifteenth step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 92 is a sectional view showing a sixteenth step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 93 is a sectional view showing a seventeenth step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 94 is a cross-sectional view showing an eighteenth step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 95 is a sectional view showing a nineteenth step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 96 is a cross-sectional view showing a first step of the method for manufacturing the select gate contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 97 is a cross sectional view showing a second step of the method for manufacturing the select gate contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 98 is a cross sectional view showing a third step of the method for manufacturing the select gate contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 99 is a cross sectional view showing a fourth step of the method for manufacturing the select gate contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 100 is a sectional view showing a fifth step of the method for manufacturing the select gate contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 101 is a plan view of a source line contact portion in a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 102 is a sectional view showing a first step of the method of manufacturing the source line contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 103 is a cross sectional view showing a second step of the method for manufacturing the source line contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 104 is a sectional view showing a third step of the method of manufacturing the source line contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 105 is a sectional view showing a fourth step of the method of manufacturing the source line contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 106 is a sectional view showing a fifth step of the method of manufacturing the source line contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 107 is a cross-sectional view of a memory transistor part of a fifteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 108 is a partial cross-sectional view of a memory transistor portion of a sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 109 is a view showing a cross section corresponding to a cross section viewed along line FF in FIG. 69;
FIG. 110 is a sectional view showing a tenth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 111 is a cross-sectional view showing an eleventh step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 112 is a sectional view showing a twelfth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 113 is a cross-sectional view showing a thirteenth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 114 is a sectional view showing a fourteenth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 115 is a cross-sectional view showing a fifteenth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 116 is a cross-sectional view showing a sixteenth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 117 is a sectional view showing a seventeenth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 118 is a cross-sectional view showing an eighteenth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 119 is a sectional view showing a nineteenth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
FIG. 120 is a partial cross sectional view showing a seventeenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 121 (a) is a partial cross-sectional view showing a first step of the method for manufacturing the memory transistor portion of the seventeenth embodiment of the nonvolatile semiconductor memory device according to the present invention. (B) is a plan view in this case.
FIG. 122 (a) is a partial cross-sectional view showing a second step of the method for manufacturing the memory transistor portion in the seventeenth embodiment of the nonvolatile semiconductor memory device according to the present invention; (B) is a plan view in this case.
FIG. 123 is a partial cross sectional view showing a third step of the method for manufacturing the memory transistor portion of the seventeenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 124 is a partial cross sectional view showing a fourth step of the method for manufacturing the memory transistor portion of the seventeenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 125 (a) is a partial cross-sectional view showing a fifth step of the method for manufacturing the memory transistor portion in the seventeenth embodiment of the nonvolatile semiconductor memory device according to the present invention. (B) is a plan view in this case.
FIG. 126 is a partial sectional view showing another mode of the seventeenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
FIG. 127 is a schematic diagram for explaining a characteristic operation of the nonvolatile semiconductor memory device according to the present invention.
FIG. 128 is a cross-sectional view showing a structure of a stack gate type memory cell used in a conventional flash memory.
FIG. 129 is a diagram showing a relationship between program and erase operations and a threshold voltage in a conventional flash memory.
FIG. 130 is a diagram showing conditions for applying a voltage to a memory cell during programming and erasing in a conventional flash memory.
FIG. 131 is a block diagram showing the overall configuration of a conventional flash memory.
132 is a block diagram illustrating a configuration of an X decoder included in the flash memory of FIG. 131.
FIG. 133 is a diagram showing voltage application conditions during a program operation in a conventional flash memory.
FIG. 134 is a flowchart for describing a pre-erase write operation in a conventional flash memory.
FIG. 135 is a flow chart for explaining a batch erasing operation in a conventional flash memory.
FIG. 136 is a diagram showing voltage application conditions during a batch erase operation in a conventional flash memory.
FIG. 137 is a diagram showing voltage application conditions during a read operation in a conventional flash memory.
FIG. 138 is a diagram showing voltages of respective lines in a conventional flash memory during a program operation, an erase operation, and a read operation.
FIG. 139 is a diagram showing a threshold voltage when a collective erase operation is performed without performing a pre-erase write operation in a conventional flash memory.
FIG. 140 is a diagram showing a threshold voltage when a collective erase operation is performed after performing a pre-erase write operation in a conventional flash memory.
FIG. 141 is a flowchart illustrating a rewrite operation in a conventional flash memory.
FIG. 142 is a diagram showing a change in threshold voltage when a batch erase operation is performed in a conventional flash memory.
FIG. 143 is a cross-sectional view showing a structure of a memory cell including a selection transistor.
FIG. 144 is a diagram for explaining disturbance at the time of sector division.
FIG. 145 is a layout diagram of a memory cell array of a conventional flash memory having main bit lines and sub-bit lines.
FIG. 146 is a structural diagram of a memory cell of a conventional flash memory.
FIG. 147 is a circuit diagram showing a voltage applied in a memory cell array of a conventional flash memory.
FIG. 148 is a block diagram showing a general configuration of a flash memory.
FIG. 149 is an equivalent circuit diagram showing a schematic configuration of a NOR type memory cell matrix.
FIG. 150 is a cross-sectional structure diagram of a NOR-type memory transistor;
FIG. 151 is a schematic plan view showing a planar arrangement of a NOR type.
FIG. 152 is a partial sectional view taken along line AA of FIG. 151.
FIG. 153 is an equivalent circuit diagram of a part of a memory cell matrix of the NAND flash memory.
FIG. 154 is a cross-sectional view of a part of the memory cell matrix of the NAND flash memory.
FIG. 155 is a cross-sectional structure diagram of a memory transistor of a NAND flash memory.
FIG. 156 (a) is a plan view showing a schematic configuration of a conventional nonvolatile semiconductor memory device having a memory cell array having a virtual ground configuration. (B) is sectional drawing seen along the BB line in (a).
FIG. 157 is a view illustrating a conventional write operation of the nonvolatile semiconductor memory device shown in FIG. 156.
FIG. 158 is a view illustrating a conventional erase operation of the nonvolatile semiconductor memory device shown in FIG. 156.
FIG. 159 is a diagram for describing a problem when the conventional nonvolatile semiconductor memory device shown in FIG. 156 is operated according to the present invention.
[Explanation of symbols]
80 Semiconductor substrate
81 n-well region
82 p-well region
83a, b source / drain regions
84a, b source region
85a, b drain region
86 Select gate transistor
87a, b, c, d memory transistors
88 Control Gate
89 floating gate
90 Sub bit line
91a, b branch line
92 Main bit line
93 MOS transistor
1001 P-type semiconductor substrate
1002 drain
1003 sauce
1004 insulating film
1005 floating gate
1006 Control gate
1008 P-well
1010, 10a memory array
1020 Address buffer
1030 X decoder
1040 Y decoder
1050 Y gate
1060 Sense amplifier
1070 Data input / output buffer
1080 writing circuit
1090 Vpp / Vcc switching circuit
100 Verify voltage generation circuit
1110 Source control circuit
1120 Control signal buffer
1130 Control circuit
1140 Negative voltage control circuit
1210,1220 High voltage generation circuit
1230, 1240 Negative voltage generation circuit
1250 Well potential generation circuit
1260 Select gate decoder
1270 source decoder
1281,1282 source switch
BL1, BL2, BL3 bit line
WL0, WL1, WL2, WL3 Word line
M11, M12, M13, M21, M22, M23, M31, M32, M33 memory cells
SL source line
SE1, SE2 sector
MB0, MB1 main bit line
SB01, SB02, SB11, SB12 Sub-bit line
SL1, SL2 source line
SGL1, SGL2 select gate line
The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (7)

A plurality of memory cells formed in the well and arranged in rows and columns;
A plurality of word lines provided corresponding to the plurality of rows;
A plurality of main bit lines provided corresponding to the plurality of columns;
A source line commonly provided to the plurality of memory cells,
The plurality of memory cells are divided into a plurality of sectors each having a plurality of memory cells arranged in a plurality of rows and a plurality of columns,
A plurality of sub-bit line groups provided corresponding to the plurality of sectors, each including a plurality of sub-bit lines corresponding to a plurality of columns in the corresponding sector;
First connection means for selectively connecting the plurality of sub-bit line groups to the plurality of main bit lines ,
Each of the plurality of memory cells includes a control gate connected to a corresponding word line, a drain connected to a corresponding sub-bit line, a source connected to the source line, and a floating gate,
At the time of erasing, erasing electron moving means for moving electrons between the floating gates of the plurality of memory cells in the selected sector and the well,
At the time of programming, a program electron moving means for moving electrons between the floating gate and the drain end of the selected memory cell,
Positive voltage generating means for receiving a power supply voltage from outside and generating a predetermined positive voltage;
Negative voltage generating means for receiving the power supply voltage from the outside and generating a predetermined negative voltage,
The erasing electron moving unit receives a positive voltage from the positive voltage generating unit and a negative voltage from the negative voltage generating unit, and receives a voltage between each floating gate of a plurality of memory cells corresponding to a selected sector and the well. Including first voltage applying means for applying a voltage enough for electrons to move to the insulating film by the tunnel phenomenon to the word line and the well ,
The program electron transfer means applies a voltage between the selected word line and the selected sub-bit line to move electrons between each floating gate and the drain end of the selected memory cell. A nonvolatile semiconductor memory device including a second voltage applying unit . 2. The non-volatile semiconductor memory device according to claim 1, wherein each of the plurality of memory cells is not depleted during either erasing or programming. Each of the plurality of memory cells is not depleted at any of erasing and programming, and has a threshold voltage of the memory cell at the time of erasing and a threshold voltage of the memory cell at the time of programming, Means for determining the logic level of the memory cell data by comparing the threshold voltage of the memory cell at the time of erasing with the intermediate value of the threshold voltage of the memory cell at the time of programming when reading the memory cell data The nonvolatile semiconductor memory device according to claim 1, further comprising: A plurality of memory cells formed in the well and arranged in a plurality of rows and a plurality of columns;
A plurality of word lines provided corresponding to the plurality of rows;
A plurality of main bit lines provided corresponding to the plurality of columns;
A source line commonly provided to the plurality of memory cells,
The plurality of memory cells are divided into a plurality of sectors each including a plurality of memory cells arranged in a plurality of rows and a plurality of columns,
A plurality of sub-bit line groups provided corresponding to the plurality of sectors, each including a sub-bit line corresponding to a plurality of columns in the corresponding sector;
First connection means for selectively connecting the plurality of sub-bit line groups to the plurality of main bit lines,
Each of the plurality of memory cells has a control gate connected to a corresponding word line, a drain connected to a corresponding sub-bit line, a source connected to the source line, and a floating gate. Including a loading gate,
At the time of erasing, erasing electron moving means for moving electrons between the floating gates of the plurality of memory cells in the selected sector and the wells,
At the time of programming, a program electron moving means for moving electrons between the floating gate and the drain end of the selected memory cell,
A plurality of capacitance means provided corresponding to the plurality of main bit lines;
A non-volatile semiconductor memory device, further comprising: a second connection means for connecting the plurality of capacitance means to each of the plurality of main bit lines during programming. A plurality of memory cells formed in the well and arranged in a plurality of rows and a plurality of columns;
A plurality of word lines provided corresponding to the plurality of rows;
A plurality of main bit lines provided corresponding to the plurality of columns;
A source line commonly provided to the plurality of memory cells,
  The plurality of memory cells are divided into a plurality of sectors each including a plurality of memory cells arranged in a plurality of rows and a plurality of columns,
A plurality of sub-bit line groups provided corresponding to the plurality of sectors, each including a plurality of sub-bit lines corresponding to a plurality of columns in the corresponding sector;
First connection means for selectively connecting the plurality of sub-bit line groups to the plurality of main bit lines,
Each of the plurality of memory cells includes a control gate connected to a corresponding word line, a drain connected to a corresponding sub-bit line, a source connected to the source line, and a floating gate,
At the time of erasing, erasing electron moving means for moving electrons between the plurality of memory cells and the floating gate and the well in the selected sector,
At the time of programming, further comprises a program electron transfer means for transferring electrons between the floating gate and the drain end of the selected memory cell,
  The source line is divided into a plurality of portions corresponding to the plurality of sectors,
The nonvolatile semiconductor memory device, wherein the erasing electron transfer means sets a source line portion corresponding to a selected sector and a source line portion corresponding to an unselected sector to different potentials at the time of erasing. A plurality of memory cells formed in the well and arranged in a plurality of rows and a plurality of columns;
A plurality of word lines provided corresponding to the plurality of rows;
A plurality of main bit lines provided corresponding to the plurality of columns;
A source line commonly provided to the plurality of memory cells,
The plurality of memory cells are divided into a plurality of sectors each including a plurality of memory cells arranged in a plurality of rows and a plurality of columns,
A plurality of sub-bit line groups provided corresponding to the plurality of sectors, each including a plurality of sub-bit lines corresponding to a plurality of columns in the corresponding sector;
First connection means for selectively connecting the plurality of sub-bit line groups to the plurality of main bit lines,
Each of the plurality of memory cells includes a control gate connected to a corresponding word line, a drain connected to a corresponding sub-bit line, a source connected to the source line, and a floating gate,
At the time of erasing, erasing electron moving means for moving electrons between the floating gates of the plurality of memory cells in the selected sector and the well,
At the time of programming, a program electron moving means for moving electrons between the floating gate and the drain end of the selected memory cell,
Capacity means;
The non-volatile semiconductor memory device further includes a second connection unit that connects the capacitance unit to the source line at the time of erasing . A plurality of memory cells formed in the well and arranged in a plurality of rows and a plurality of columns;
A plurality of word lines provided corresponding to the plurality of rows;
A plurality of main bit lines provided corresponding to the plurality of columns;
A source line commonly provided to the plurality of memory cells,
The plurality of memory cells are divided into a plurality of sectors each including a plurality of memory cells arranged in a plurality of rows and a plurality of columns,
A plurality of sub-bit line groups provided corresponding to the plurality of sectors, each including a plurality of sub-bit lines corresponding to a plurality of columns in the corresponding sector;
First connection means for selectively connecting the plurality of sub-bit line groups to the plurality of main bit lines,
Each of the plurality of memory cells includes a control gate connected to a corresponding word line, a drain connected to a corresponding sub-bit line, a source connected to the source line, and a floating gate,
  At the time of erasing, erasing electron moving means for moving electrons between the floating gate of the plurality of memory cells in the selected sector and the well,
At the time of programming, further comprises a program electron moving means for moving electrons between the floating gate and the drain end of the selected memory cell,
The electronic transfer means for a program,
After precharging the selected main bit line to a predetermined potential in accordance with the data and applying a predetermined voltage to the selected word line, the source line is temporarily grounded, and then a negative voltage is applied to the selected multi-word line. A non-volatile semiconductor storage device including a voltage application unit for applying a voltage.

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