JP2001358238A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need of the write operation before erasing to reduce the time taken for one-shot erase operation and the time taken for the rewrite operation of data in a flash memory comprising a plurality of stack gate type memory cells. SOLUTION: For erasing, a plurality of memory cells inject electrons from their sources 1003 at once into their floating gates 1005, this raising the threshold voltage of the plurality of memory cells. For programming, selected memory cells discharge electrons from their floating gates 1005 at once into their drains 1002, this dropping the threshold voltage of the selected memory cells.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to an electrically programmable and erasable nonvolatile semiconductor memory device including a stack gate type memory cell (hereinafter referred to as a flash memory).

[0002]

2. Description of the Related Art First, general definitions of erase and program will be described. Erasing refers to changing the threshold voltages of a plurality of memory cells to a predetermined state at once. Programming means changing the threshold voltage of a selected memory cell to another predetermined state. The data "1" is made to correspond to the erased memory cell, and the data "0" is made to correspond to the programmed memory cell.

(1) Cross-sectional structure of memory cell (FIG. 12)
FIG. 128 shows a cross-sectional structure of a general stack gate type memory cell (memory transistor) used in a conventional flash memory. Two N + -type impurity regions are formed on the main surface of P − -type semiconductor substrate 1001 at a predetermined interval. One impurity region forms a drain 1002 and the other impurity region forms a source 1003. Semiconductor substrate 1 between drain 1002 and source 1003
On the region 001, an insulating film 1004 (about 100 °) made of an extremely thin oxide film or the like is formed. Insulating film 10
04, a floating gate 1005 is formed,
Further, a control gate 10 is further formed thereon via an insulating film.
06 is formed. Thus, the memory cell has a double gate structure. Incidentally, the P- type semiconductor substrate 1001
May be replaced by a P-well.

In a flash memory, information (data) is stored in a memory cell depending on whether electrons are injected into the floating gate 1005 or electrons are emitted from the floating gate 1005.

In a state where electrons are injected into the floating gate 1005, the threshold voltage of the memory cell viewed from the control gate 1006 is high, and as shown in FIG. No current flows between 1002 and source 1003. This is the floating gate 1005
This is because the positive voltage is canceled by the negative charges of the electrons stored in the memory cell. This state is called a program state. In this case, data “0” is stored in the memory cell. Since the electrons stored in the floating gate 1005 do not disappear semi-permanently as they are, the stored data is also held semi-permanently.

When electrons are emitted from the floating gate 1005, the control gate 1
006, the threshold voltage of the memory cell is low.
As shown at 29, when the control gate voltage becomes Vg1 or more, a current flows between the drain 1002 and the source 1003. This state is called an erase state. in this case,
Data “1” is stored in the memory cell.

By detecting such two states, data stored in a memory cell can be read.

(2) Programming and Erasing of Memory Cell (FIG. 130) FIG. 130 (a) shows a voltage application condition when programming the memory cell, and FIG. 130 (b) shows a voltage application when erasing the memory cell. Indicates conditions.

At the time of programming, a write voltage Vw (typically about 6 V) is applied to the drain 1002, a high voltage Vpp (typically about 12V) is applied to the control gate 1006, and the source 1003 is grounded. Accordingly, hot electrons due to avalanche breakdown are generated near the drain 1002, or channel hot electrons having high energy are generated in a channel formed in a region between the drain 1002 and the source 1003. Hot electrons accelerated by the high voltage of the control gate 1006 jump over the energy barrier of the insulating film 1004 and are injected into the floating gate 1005 from near the drain. As a result, the threshold voltage of the memory cell increases.

At the time of erasing, the drain 1002 is set in a floating state, the high voltage Vpp is applied to the source 1003, and the control gate 1006 is grounded. As a result, a high voltage is generated in the thin insulating film 1004, and the floating gate 1005
03 emits electrons. As a result, the threshold voltage of the memory cell decreases.

As described above, at the time of programming, electrons are injected into the floating gate 1005 by hot electrons. Therefore, as shown in FIG. 130, the P + -type impurity region 10 is formed along the drain 1002 so that a higher electric field is generated in the channel direction or the substrate direction.
02a is provided.

At the time of erasing, electrons are emitted from the floating gate 1005 to the source 1003 by a tunnel phenomenon. Therefore, at the time of erasing, only an electric field between the floating gate 1005 and the source 1003 is required. It is preferable that the electric field in the channel direction or the substrate direction be small so that a leak current does not occur. Therefore, in order to weaken the electric field in the channel direction or the substrate direction, the N − -type impurity region
a is provided.

(3) Overall Configuration of Flash Memory (FIGS. 131 and 132) FIG. 131 is a block diagram showing the overall configuration of a conventional flash memory.

Memory array 1010 includes a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines, and a plurality of memory cells provided at intersections thereof.

FIG. 131 shows four memory cells M arranged in two rows and two columns for the sake of simplicity.
00, M01, M10, and M11 are shown. The drains of memory cells M00 and M01 are connected to bit line BL0, and the drains of memory cells M10 and M11 are bit line B
L1. The control gates of memory cells M00 and M10 are connected to word line WL0, and the control gates of memory cells M01 and M11 are word line WL1.
Connected to. Memory cells M00, M01, M10, M
Eleven sources are connected to a source line SL.

Address buffer 1020 receives an externally applied address signal AD and converts the X address signal to X.
The Y address signal is applied to a Y decoder 1030. X decoder 1030 selects one of a plurality of word lines WL0 and WL1 in response to an X address signal. Y decoder 1040 generates selection signals Y0 and Y1 for selecting any of a plurality of bit lines in response to a Y address signal.

The Y gate 1050 is connected to the bit lines BL0, BL
1 includes Y gate transistors YG0 and YG1. The Y gate transistors YG0, YG1 respond to the selection signals Y0, Y1, respectively.
1 is connected to the sense amplifier 1060 and the write circuit 1080.

At the time of reading, sense amplifier 1060 detects data read on bit line BL0 or bit line BL1, and outputs the same to outside via data input / output buffer 1070. During programming, externally applied data DA is applied to write circuit 1080 via data input / output buffer 1070, and write circuit 1080 applies a write voltage to bit lines BL0 and BL1 according to the data.

Vpp / Vcc switching circuit 1090 receives an externally applied high voltage (normally 12 V) and an externally applied power supply voltage Vcc (normally 5 V), and receives X decoder 1030, Y decoder 1040 and write circuit 108.
0 is supplied with the high voltage Vpp or the power supply voltage Vcc. Verify voltage generating circuit 1100 receives an externally applied power supply voltage Vcc, and applies a predetermined verify voltage to a selected word line at the time of verification described later. The source control circuit 1110 applies a high voltage Vpp to the source line SL at the time of erasing.

The control signal buffer 1120 supplies a control signal CT supplied from the outside to the control circuit 1130. The control circuit 1130 controls the operation of each circuit.

X decoder 1030 includes a decoder circuit 1301 and a plurality of word lines W, as shown in FIG.
L includes a plurality of high voltage switches 1302 corresponding to L. Decoder circuit 1301 decodes X address signal XA and generates a selection signal for selecting one of a plurality of word lines WL. Each high voltage switch 1302
Supplies high voltage Vpp or power supply voltage Vcc to selected word line WL in response to control signal SW provided from control circuit 1130.

This flash memory has a chip CH
Formed on top. (4) Operation of Flash Memory (FIGS. 133 to 14)
0) (a) Program Operation (FIG. 133) FIG. 133 is a diagram showing voltage application conditions during the program operation. Here, it is assumed that memory cell M00 is programmed, for example. Control circuit 1130 is supplied with a control signal designating a program operation via control signal buffer 1120. Vpp / Vcc switching circuit 10
90 is supplied with a high voltage Vpp from outside. Vpp /
Vcc switching circuit 1090 applies high voltage Vpp to X decoder 1030 and Y decoder 1040.

X decoder 1030 responds to an X address signal supplied from address buffer 1020 to select word line WL0 and apply a high voltage Vpp thereto.

In response to the Y address signal supplied from address buffer 1020, Y decoder 1040 supplies a high voltage selection signal Y to Y gate transistor YG0.
Give 0. Thereby, the Y gate transistor YG0
Turns on.

The source control circuit 1110 includes a source line SL
To 0V. Write circuit 1080 is activated. Thereby, write voltage Vw is applied to bit line BL0.

As a result, FIG.
A voltage is applied as shown in FIG.
0 is programmed.

(B) Erasing Operation (FIGS. 134 to 136) The erasing operation includes a pre-erase writing operation and a batch erasing operation.

(I) Write operation before erasure (FIG. 134) Before the memory cells are erased collectively, all the memory cells are programmed by the above method. Thus, the threshold voltages of all the memory cells are increased. This is called a pre-erase write operation.

The pre-erase write operation will be described with reference to the flowchart of FIG. First, it is determined whether or not the data of all the memory cells is "0" (step S51). If the data of all the memory cells is not "0", the address specified by the address signal is set to the address 0 (step S52). Then, the memory cell specified by the address signal is programmed by the above-described program operation (step S5).
3).

Next, it is determined whether or not the address specified by the address signal is the last address (step S5).
4). If the address is not the last address, the address is incremented by one (step S55), and the program operation is performed (step S53). This operation is continued until the address reaches the final address (steps S53 and S53).
54, S55). When the address becomes the last address, the pre-erase write operation ends.

(Ii) Batch erase operation (FIG. 135, FIG. 1)
36) Next, the batch erase operation will be described with reference to the flowchart in FIG. FIG. 136 shows voltage application conditions during batch erase.

First, a control signal designating batch erasure is applied to control circuit 1130 via control signal buffer 1120. At the time of batch erase, Vpp / Vcc switching circuit 10
90 supplies a high voltage Vpp to the source control circuit 1110. The source control circuit 1110 applies the high voltage Vpp to the source line SL (Step S61).

The X decoder 1030 is connected to the word line W
L0 and WL1 are grounded. The Y decoder 1040 supplies 0V selection signals Y0 and Y1 to the Y gate transistors YG0 and YG1, respectively. Thereby, the bit line BL
0 and BL1 are in a floating state.

As a result, all the memory cells have the configuration shown in FIG.
As shown in FIG. 30B, a voltage is applied, and the threshold voltages of all the memory cells decrease.

It is difficult to lower the threshold voltages of all memory cells below a predetermined value only by once applying a high voltage (erase voltage) to source line SL. Therefore, generally, a high voltage pulse is applied to the source line SL a plurality of times, and an erase verify operation is performed after each pulse application.

First, after applying a high-voltage pulse to the source line SL (step S61), the source line SL is set to 0 V (step S62), and address 0 is selected (step S61).
63). Then, a predetermined verify voltage lower than the power supply voltage Vcc is applied to the selected word line by the verify voltage generating circuit 1100 (step S64).
Thereby, the data of the selected memory cell is read out to the corresponding bit line, and detected by sense amplifier 1060. Then, it is determined whether or not the data detected by the sense amplifier 1060 is "1" (step S65).

If the data detected by sense amplifier 1060 is "0", steps S61 to S64 are repeated.

If the data detected by the sense amplifier 1060 is "1", it is determined whether or not the address specified by the address signal is the last address (step S66). If the address is not the last address, the address is incremented by 1 (step S67). In this way, data of all memory cells are read while incrementing the address by one. If the read data is "0", a high voltage pulse is applied to the source line SL to erase the memory cell.

In this way, all the memory cells are gradually erased while monitoring the threshold voltage of the memory cells.

(C) Read Operation (FIG. 137) FIG. 137 shows voltage application conditions during the read operation. Here, it is assumed that data is read from memory cell M00.

First, a control signal designating a read operation is applied to control circuit 1130 via control signal buffer 1120. X-decoder 1030 is provided in address buffer 1
The word line WL0 is selected in response to the X address signal given from 020, and the power supply voltage Vcc is applied thereto.
At this time, the potential of the unselected word line is kept at 0V.

Y decoder 1040 turns on Y gate transistor YG 0 in response to a Y address signal supplied from address buffer 1020. Thereby, bit line BL0 is connected to sense amplifier 1060. At this time, 0 V is applied to the source line SL by the source control circuit 1110.

As a result, when the threshold voltage of memory cell M00 is low, memory cell M00 is turned on. Thus, current I flows through resistor R in sense amplifier 1060, and read voltage Vr on bit line BL0 decreases. The read voltage Vr on bit line BL0 is output as data "1" via inverter INV2.

When the threshold voltage of the memory cell M00 is high, the memory cell M00 is turned off. Thereby, the read voltage Vr on the bit line BL0 increases. The read voltage Vr on bit line BL0 is output as data "0" via inverter INV2.

When the voltage of the bit line at the time of reading becomes close to the power supply voltage Vcc, hot electrons are generated and the memory cell may be programmed. This is called soft light. To prevent this soft light,
N-channel transistor TR and inverter INV1
Thereby, the read voltage Vr on the bit line is set to about 1V.

(D) The potential of each line in each operation (FIG. 1
38) FIG. 138 shows potentials of a word line, a bit line, and a source line in a program operation, an erase operation, and a read operation. At the time of programming and writing before erasure, the high voltage Vpp is applied to the word line, the write voltage Vw is applied to the bit line, and 0 V is applied to the source line. At the time of batch erasing, the high voltage Vpp is applied only to the source line, 0 V is applied to the word line, and the bit line is in a floating state. At the time of reading, the power supply voltage Vcc is applied to the word line, the source line becomes 0 V, and the read voltage V
r appears.

(E) Reason for the need for write operation before erasure (FIGS. 139 and 140) Next, the reason for the need for write operation before erasure at the time of erasure is shown in FIG.
This will be described with reference to FIG. 39 and FIG. FIG. 139 shows a change in the threshold voltage of the memory cell when the program operation and the batch erase operation are performed. FIG.
Numeral 40 indicates a change in the threshold voltage of the memory cell when the program operation, the pre-erase write operation and the batch erase operation are performed.

In the batch erase operation, as shown in FIG. 130B, the control gate 1006 of the memory cell becomes 0 V, the drain 1002 is in a floating state, and the source 1003 is supplied with a high voltage Vpp. Under such a voltage application condition, a high voltage is generated between the source 1003 and the floating gate 1005, and the electrons stored in the floating gate 1005 are extracted to the source 1003 by the high voltage. As a result, the threshold voltage of the memory cell decreases.

However, if this erasing operation is performed in a state where the threshold voltage is low (data "1"), the threshold voltage of the memory cell becomes negative as shown in FIG. This is called depletion of the memory cell. Due to the depletion of the memory cell, the following problem occurs at the time of reading.

Here, in the read operation shown in FIG. 137, memory cell M00 is selected and memory cell M00 is selected.
Assume that 01 is depleted by batch erasure. That is, the threshold voltage of the memory cell M01 is negative.

In this case, the power supply voltage V is applied to the word line WL0.
Although cc is applied, the potential of the word line WL1 remains at 0V. If the memory cell M00 stores data "0", the memory cell M00 does not turn on even if the potential of the word line WL0 becomes the power supply voltage Vcc. Therefore,
No current is generated in the bit line BL0.

However, when the threshold voltage of the memory cell M01 is negative, the potential of the word line WL1 becomes zero.
Even at V, the memory cell M01 is turned on. As a result, a current is generated in the bit line BL0. In this case, the sense amplifier 1060 causes the memory cell M00
Is determined to be "1".

As described above, if the threshold voltage of at least one of the memory cells connected to the bit line is negative, even if that memory cell is in a non-selected state, Current flows through the Therefore, data stored in the selected memory cell cannot be read accurately.

To solve such a problem, FIG.
As shown by 0, a pre-erase write operation is performed before the batch erase operation. As a result, the threshold voltages of all the memory cells are temporarily set to a high state, and then a collective erase operation is performed. As a result, the voltage of the erased memory cell is unified to a positive value and lower than the power supply voltage Vcc. Thus, the reliability is improved by the pre-erase write operation.

Hereinafter, the structure of a conventional flash memory will be described in more detail. A flash memory exists as a memory device in which data can be freely written and which can be electrically erased. An EEPROM comprising one transistor and capable of electrically erasing written information charges at once, a so-called flash memory is disclosed in U.S. Pat. No. 4,868,619, "An In-
SystemReprogrammable 32K ×
8 CMOS Flash Memory "by V
irgil Niles Kynett et a
l. , IEEE Journal of Solid-
State Circuits, vol. 23, no.
5, October 1988.

FIG. 148 is a block diagram showing a general configuration of a flash memory. In the figure, a flash memory is a memory cell matrix 1 arranged in a matrix.
, X address decoder 2, Y gate 3, Y address decoder 4, address buffer 5, write circuit 6
, A sense amplifier 7, an input / output buffer 8, and a control logic 9.

The memory cell matrix 1 has a plurality of memory transistors arranged in a matrix therein. X address decoder 2 and Y gate 3 are connected to select a row and a column of memory cell matrix 1. The Y gate 3 is connected to a Y address decoder 4 for giving column selection information. X address decoder 2
And the Y address decoder 4 are connected to an address buffer 5 for temporarily storing address information.

The Y gate 3 is connected to a write circuit 6 for performing a write operation at the time of data input and a sense amplifier 7 for determining "0" and "1" from a current value flowing at the time of data output. An input / output buffer 8 for temporarily storing input / output data is connected to the write circuit 6 and the sense amplifier 7, respectively. Address buffer 5 and input / output buffer 8
Is connected to a control logic 9 for controlling the operation of the flash memory. The control logic 9 performs control based on a chip enable signal, an output enable signal, and a program signal.

FIG. 149 is an equivalent circuit diagram showing a schematic configuration of memory cell matrix 1 shown in FIG. 148.
A flash memory having this memory cell matrix is called a NOR type. In the figure, a plurality of word lines WL1, WL2,..., WLi extending in the row direction and a plurality of bit lines BL1, BL2,.
Lj are arranged so as to be orthogonal to each other to form a matrix. Memory transistors Q11, Q12,..., Qij each having a floating gate are arranged at the intersection of each word line and each bit line. The drain of each memory transistor is connected to each bit line. The control gate of the memory transistor is connected to each word line. The sources of the memory transistors are connected to the respective source lines S1, S2,. The sources of the memory transistors belonging to the same row are connected to each other as shown in the figure.

FIG. 150 is a partial cross sectional view showing a cross sectional structure of one memory transistor constituting the above NOR type flash memory. FIG. 151 is a schematic plan view showing a planar arrangement of the NOR type flash memory. FIG. 152 is a partial sectional view taken along line AA of FIG.
The structure of the NOR flash memory will be described with reference to these drawings.

Referring to FIGS. 150 and 152, an n-type impurity region, for example, a drain region 11 and a source region 12 are spaced apart from each other on the main surface of p-type impurity region 10 provided on a silicon substrate. Is formed. In a region sandwiched between the drain region 11 and the source region 12, a control gate 13 and a floating gate 14 are formed so as to form a channel.
The floating gate 14 is formed on the p-type impurity region 10 with a thin gate oxide film 15 having a thickness of about 100 ° interposed. The control gate 13 is formed on the floating gate 14 with an interlayer insulating film 16 interposed therebetween so as to be electrically separated from the floating gate 14. Floating gate 14 is formed from polycrystalline silicon. The control gate 13 is composed of a polycrystalline silicon layer or a laminated film of a polycrystalline silicon layer and a refractory metal. Oxide film 17 is formed by depositing the surface of a polycrystalline silicon layer constituting floating gate 14 and control gate 13 by a CVD method. Further, a smooth coat film 21 (see FIG. 152) is formed so as to cover the floating gate 14 and the control gate 13.

As shown in FIG. 151, the control gates 13 are formed as word lines so as to be connected to each other and extend in the horizontal direction (row direction). The bit line 18 is arranged so as to be orthogonal to the word line 13 and is electrically connected to each drain region 11 through a drain contact 20. As shown in FIG. 152, the bit line 18 is formed on the smooth coat film 21. As shown in FIG. 151, source region 12 extends along the direction in which word line 13 extends, and word line 13 and field oxide film 1 are formed.
9 and is formed in the area surrounded by. Drain region 1
1 is also formed in a region surrounded by the word line 13 and the field oxide film 19.

The operation of the NOR flash memory configured as described above will be described with reference to FIG.

First, in the write operation, the drain region 1
A voltage of about 5 V for 1 and 10 V for control gate 13
Voltage is applied. Then, source region 12 and p-type impurity region 10 are kept at the ground potential (OV). At this time, a current of several 100 μA flows through the channel of the memory transistor. Of the electrons flowing from the source to the drain, the electrons accelerated in the vicinity of the drain become electrons having high energy in the vicinity of the electrons, that is, channel hot electrons. These electrons are injected into the floating gate 14 as shown by the arrow due to the electric field generated by the voltage applied to the control gate 13. In this manner, electrons are stored in floating gate 14, and the threshold voltage Vth of the memory transistor becomes, for example, 8V. This state is called a write state, "0".

Next, in the erasing operation, the source region 1
A voltage of about 5 V is applied to the control gate 1 and the control gate 1
3, a voltage of about −10 V is applied to the p-type impurity region 1.
0 is held at the ground potential. And the drain region 11
Is released. Due to the electric field generated by the voltage applied to the source region 12, the electrons in the floating gate 14 pass through the thin gate oxide film 15 by the FN tunnel phenomenon, as indicated by arrows. Thus, the electrons in the floating gate 14 are extracted, so that the threshold voltage Vth of the memory transistor becomes, for example, 2V. This state is called an erased state, "1".
Since the sources of the respective memory transistors are connected as shown in FIG. 149, all the memories can be collectively erased by this erasing operation.

Further, in the read operation, a voltage of about 5 V is applied to the control gate 13 and 1 V is applied to the drain region 11.
Voltage is applied. Then, the source region 12 and the p-type impurity region 10 are kept at the ground potential. At this time, “1” or “0” is determined depending on whether a current flows in the channel region of the memory transistor.

That is, since Vth is 8 V in the writing state, no channel is formed and no current flows. On the other hand, in the erase state, Vth is 2 V, so that a channel is formed and a current flows.

In the NOR type, electrons are injected into the floating gate 14 using channel hot electrons, and the write state is set to “0”. Since injection of electrons by channel hot electrons is inefficient, the NOR type has a problem that power consumption increases.

Referring to FIG. 152, for example, when selecting and writing to memory transistor 22a, a voltage of about 5 V is applied to drain region 11 and a voltage of about 10 V to control gate 13 as described above. Thereby, writing is performed on floating gate 14 of memory transistor 22a.

Next, the same voltage is applied to the drain region 11 and the control gate 13 of the memory transistor 22b when the memory transistor 22b is selected and written. The memory transistor 22a and the memory transistor 22b share the drain region 11. Therefore, the voltage applied to the drain region 11 when writing to the memory transistor 22b may cause electrons injected into the floating gate 14 of the memory transistor 22a to be extracted to the drain region 11 by a tunnel phenomenon. This phenomenon is called a drain disturb phenomenon. Due to the drain disturb phenomenon, electrons are extracted from the floating gate of the memory transistor into which the electrons have been injected, so that the memory transistor, which should have been in the written state, is in the erased state, causing a malfunction of the flash memory.

A solution to the problem of the NOR type is NAN.
There is a D type. NAND type flash memory is, for example, N
IKKEI ELECTRONICS 1992.2.
17 (no. 547). 180-181. FIG. 153 is an equivalent circuit diagram of a part of the memory cell matrix of the NAND flash memory. Each of select gate transistors 39a, 39b, and 39c has one impurity region connected to a bit line and the other impurity region connected to memory transistors 38a, 38b, and 3c, respectively.
8c.

Eight memory transistors 38a arranged in the vertical direction are selected by the select gate transistor 39a, eight memory transistors 38b arranged in the vertical direction are selected by the select gate transistor 39b, and the vertical direction is selected by the select gate transistor 39c. Are selected from the eight memory transistors 38c. These memory transistors 38a, 38b, 38
c is the select gate transistor 23a, 2
Grounded through 3b and 23c.

FIG. 154 is a sectional view of a part of the memory cell matrix of the NAND flash memory. In P-type impurity region 30 formed in silicon substrate 26, impurity regions 27 are formed at intervals. A memory transistor 38 having a floating gate 29 and a control gate 28 between each impurity region 27
a is formed.

FIG. 155 is a sectional structural view of the memory transistor 38a. In the p-type impurity region 30 formed on the silicon substrate, an impurity region 27 is formed with a space therebetween. On the p-type impurity region 30 between the impurity regions 27, a gate oxide film 35, a floating gate 29, an interlayer insulating film 36, and a control gate 28 are stacked. Control gate 28 and floating gate 29 are covered with oxide film 37.

FIG. 1 shows the operation of the NAND flash memory.
This will be described below with reference to FIGS. First, the write operation will be described. For example, when writing to the memory transistor 38a having the word line W8, the select gate S2 of the select gate transistor, the bit line B1, the source line, and the p-type impurity region 30 are kept at the ground potential, and S1, B
2, a voltage of about 10 V is applied to B3, a voltage of about 20 V is applied to the word line W8, and the other word lines W1 to W7 are kept at the ground potential. As a result, as shown in FIG. 155, in the memory transistor 38a having the word line W8 (control gate 28), electrons in the channel region are injected into the floating gate 29 by the channel FN. This is the write state “0”, and at this time Vth
Is 3V.

Next, the erasing operation will be described. When erasing, the bit lines, S1, S2, p-type impurity region 3
A voltage of 20 V is applied to 0, and the word lines W1 to W8 are kept at the ground potential. At this time, as shown by in FIG. 155, electrons are extracted from the floating gate 29 of the memory transistor 38a in the write state "0" to the channel region by the channel FN to the erase state "1". Vth in the erase state "1" is -2V.

Next, the read operation will be described. For example, when reading the memory transistor 38a having the word line W8, a voltage of about 1 V is applied to the bit line B1.
Keep source lines and substrate at ground potential. And the word line W8
Is maintained at the ground potential, and a voltage of about 5 V is applied to the word lines W1 to W7. Further, a predetermined voltage is applied to the selection gates S1 and S2 to turn on the selection gate transistor.

Since the word line W8 is kept at the ground potential (0 V), when the memory transistor 38a having the word line W8 is in the erase state "1", the memory transistor 3
When the memory transistor 8a is turned on and the writing state is "0", the memory transistor 38a is turned off. Word lines W1 to W7
Memory transistors 38a having word lines W1 to W
Since a voltage of 5 V is applied to 7, the write state “0”,
Memory transistor 3 regardless of the erase state "1"
8a turns ON.

Therefore, when the memory transistor 38a having the word line W8 is in the erased state "1", FIG.
Referring to FIG. 4, a current passes through a channel formed by each of the word lines W1 to W8, passes through a bit line, and is guided to a sense amplifier. On the other hand, when the memory transistor 38a having the word line W8 is in the write state "0", the word line W8
In some cases, no channel is formed, so that no current flows to the sense amplifier. When the current is sensed by the sense amplifier, the erase state is determined to be “1”, and when the current is not sensed, the write state is determined to be “0”.

Injecting electrons into the floating gate using the channel FN is more efficient than injecting electrons using channel hot electrons. Therefore, the power consumption of the NAND type can be lower than that of the NOR type.

In the NAND type, the channel FN is used at the time of writing.
And no high voltage is applied to the drain region of the memory transistor, so that the drain disturb phenomenon can be eliminated.

[0082]

(1) Rewrite operation (FIG. 141) When rewriting data stored in a memory cell in the above-mentioned conventional flash memory, as shown in FIG. An operation is performed (step S71), a batch erasing operation is performed (step S72), and then a program operation is performed (step S73).

As the capacity of the flash memory increases,
The time required for the pre-erase write operation becomes very long. For example, in a 1M-bit flash memory, the time required to program memory cells at all addresses is as long as 1-2 seconds.

The long time required for the pre-erase write operation means that the data rewrite takes a long time. This is very inconvenient for the user.

(2) Depletion by Over-Erasing (FIGS. 142 and 143) As described above, at the time of erasing, the pre-erase write operation is performed before the collective erase operation to reduce the threshold voltage of the memory cell. The values are almost the same. However, in practice, the erasing characteristics of a plurality of memory cells existing in an erasing unit always have variations.

As shown in FIG. 142, when this variation is extremely large, some memory cells are overerased, and the overerased memory cells are depleted.

In such a depleted memory cell, a current flows even if its control gate is grounded. As a result, data read from a memory cell connected to the same bit line as the depleted memory cell is disturbed by the depleted memory cell, and data is always "1".
Will be determined.

Such a problem does not exist in a memory cell having a structure as shown in FIG.

In FIG. 143, the P − type semiconductor substrate 13
01 at a predetermined interval on the main surface of the N + -type impurity region 130.
2, 1303 and 1310 are formed. A gate electrode 1304 is formed over a region between impurity regions 1302 and 1303 with an insulating film made of an oxide film interposed therebetween. Thus, a selection transistor 1305 is formed.

A floating gate 1307 is formed on impurity region 1303 via an extremely thin oxide film 1306 of about 100 °, and a control gate 1308 is formed above the floating gate 1307 via an insulating film.
Thus, a memory transistor 1309 having a two-layer gate structure is formed.

A 1-bit memory cell is constituted by select transistor 1305 and memory transistor 1309. Impurity region 1302 is connected to bit terminal B, and gate electrode 1304 is connected to word terminal W. Impurity region 1310 is connected to source terminal S. Control gate 1308 is connected to control gate terminal CG.

In the memory cell shown in FIG. 143, since select transistor 1305 is provided,
Even if the memory transistor 1309 is depleted, the above problem does not occur.

However, the memory cell of FIG.
As compared with the stack gate type memory cell shown in FIG. 128, the structure becomes complicated and a large area is required.

(3) Disturb between sectors (FIG. 14)
4) In a conventional flash memory, a data rewriting unit can be subdivided by dividing a memory array into sectors. In this case, there is a problem that the memory cells in the selected sector affect the memory cells in the non-selected sector. This is called disturb.

For example, as shown in FIG. 144, a plurality of memory cells connected to word line WL0 are stored in sector SE1.
And division into sectors SE2. In this case, when programming the memory cells in the sector SE1, a high voltage is also applied to the control gates of the memory cells in the unselected sector SE2.

A case is considered where a plurality of memory cells connected to bit line BL0 are divided into sectors SE1 and SE3. In this case, while programming the memory cells in sector SE1, unselected sector SE3
The high voltage is also applied to the drains of the memory cells inside the memory cells.

In any case, even if the disturbance occurs about several thousand times, the data can be sufficiently guaranteed. However, since a plurality of sectors exist on the same word line and the same bit line, if the number of rewrites of a memory cell in one sector is set to 10,000, the number of disturbances occurring in other sectors is as follows. .

The number of disturbances = (10000 times) ×
(Number of sectors-1) As described above, when a plurality of sectors exist, the number of disturbances occurring in a certain sector becomes enormous. In recent years, the number of required sector rewrite guarantees is increasing more and more, and disturb between different sectors is a serious problem.

(4) Power Consumption When programming a conventional flash memory, electrons are injected into the floating gate by channel hot electrons. Therefore, a large channel current is required at the time of programming. Therefore, the power consumption during programming increases.

(5) Degree of Integration On the other hand, US Pat. No. 5,126,808 discloses a conventional flash memory having a main bit line and a sub bit line. In such a flash memory, electron injection by channel hot electrons is used for programming, and a large channel current flows. As a result, the following problems are caused.

FIG. 145 is a layout diagram of a conventional flash memory having a main bit line and a sub bit line on a semiconductor substrate. Referring to FIG. 145, main bit line MB and sub-bit lines SB0 and SB1 are formed in parallel on a semiconductor substrate. Word lines VL0, WL1,... And select gate lines SGL0, SGL1 are formed in a direction perpendicular to these bit lines. A memory cell is formed at a position where each word line and a sub-bit line intersect.
For example, at the position where each word line WL0, WL1,... And sub-bit line SB1 intersect, memory cells M11, M12,.
Are formed. Select gate transistor SG 'for sector selection is formed at a position where main bit line MB and select gate line SGL0 intersect. An N + diffusion layer 1405 is formed in a semiconductor substrate.

The memory cells M11 and M1 shown in FIG.
In 2, 2,..., As described above, programming using channel hot electrons is performed, so that a large channel current flows through sub-bit line SB1. Therefore, since this large current flows through select gate transistor SG 'for selecting a sector, it is necessary to select the channel width of select gate transistor SG' to a large value. This means that the select gate transistor SG 'occupies a large area on the semiconductor substrate, and as a result, the degree of integration on the semiconductor substrate is reduced.

In addition, in the flash memory shown in FIG. 145, main bit line MB and sub-bit line SB
In order to reduce the resistance of 0 and SB1, first and second aluminum wiring layers are formed as sub-bit lines SB0 and SB1 and main bit line MB. Therefore, an aluminum wiring layer cannot be used to reduce the resistance of word lines WL0, WL1,... Formed by the polysilicon layer. As a result, a delay occurs in signal propagation on the word line, and a high operation speed cannot be obtained.

FIG. 146 is a structural diagram of a memory cell of a conventional flash memory. Referring to FIG. 146, two memory cells M00 and M10 are separated by a separation oxide film 1402 formed on P well 1008. For example, when programming is performed on memory cell M10, a high voltage of 10 V is applied to second aluminum wiring layer 1006 forming the control gate,
On the other hand, 5V is applied to the drain 1002 'of the transistor M10.
Is applied. If the width W of the isolation oxide film 1402
If b is too narrow, a MOS transistor 1403 using this isolation oxide film 1402 as a gate oxide film is equivalently present. Equivalent MOS transistor 14
The presence of 03 prevents desired operation in memory cells M00 and M10. Therefore, this equivalent MOS
In order to prevent the occurrence of the transistor 1403, the width Wb of the isolation oxide film 1402 cannot be selected to a small value. This means that the degree of integration in the memory cell array is reduced.

FIG. 147 is a circuit diagram showing the operation of the flash memory using a negative voltage. FIG. 147 (a) shows the voltage applied for programming, while FIG.
7 (b) indicates a voltage applied for erasing.

Referring to FIG. 147 (a), memory cell M
To inject electrons into the floating gate 00, a voltage of 5 V is applied to the bit line BL0, and a negative voltage of -10 V is applied to the word line WL11. On the other hand, a voltage of 5 V is applied to the unselected word line WL12. In other words, the X decoder not shown is-
It is necessary to output 10V and 5V voltages.

Referring to FIG. 147 (b), to erase data stored in the selected sector SE1, a positive voltage of 10 V is applied to word lines WL11 and WL12, while bit lines BL0 and BL1 are applied. Are brought into a high impedance state. On the other hand, the word lines WL21 and WL22 in the unselected selector SE2 are provided with-
A negative voltage of 8V is provided. In other words, an X decoder (not shown) needs to output a positive voltage of 10V and a negative voltage of -8V.

Therefore, an X decoder (not shown) needs to output an output voltage having a voltage difference of 15 V in a program operation and output an output voltage having a voltage difference of 18 V in an erase operation. Therefore, since the voltage difference between the output voltages is large, it is difficult to form the X decoder in a smaller occupied area on the semiconductor substrate.

(6) External power supply At the time of programming, 5 V to 6 V is applied to the drain of each memory cell.
It is necessary to apply a voltage of V. As described above, since programming with channel hot electrons requires a large channel current, it is very difficult to create this drain voltage by internal boosting using a single external power supply of 3V or 5V. Even if this is possible, a large number of bits cannot be programmed at the same time, and the programming time is enormous.

However, the NAND type has a drawback that the read operation is slow because the read operation is performed by passing a current through eight memory transistors arranged in series.

Further, since a relatively high voltage of 20 V is used at the time of writing and erasing, there is a problem that high integration is difficult.

An object of the present invention is to reduce the time required for an erasing operation in a flash memory, thereby shortening the time required for a rewriting operation.

Another object of the present invention is to prevent depletion due to over-erasure of a stacked gate type memory cell.

Still another object of the present invention is to prevent disturbance when a memory array is divided into sectors.

Still another object of the present invention is to reduce power consumption during programming.

Still another object of the present invention is to provide a flash memory operable by a single external power supply.

Still another object of the present invention is to operate with low power consumption, reduce the drain disturb phenomenon, speed up the read operation, and lower the maximum voltage. An object of the present invention is to provide a nonvolatile semiconductor memory device.

[0118]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a source which is one impurity region of a first conductivity type formed at a predetermined interval on a main surface of a semiconductor substrate; Formed on a semiconductor substrate between a source and a drain, the first conductivity type impurity region having a high concentration impurity region and a drain having a low concentration impurity region formed to cover the high concentration impurity region. A memory cell including a floating gate formed through an insulating film, a control gate formed through the insulating film on the floating gate, a word line connected to the control gate, and a bit line connected to the drain It is provided with. According to a second aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a first conductive type impurity region formed on a main surface of a semiconductor substrate at a predetermined interval; and a drain having the other first conductive type impurity region. A floating source formed via a certain source, an impurity region of a second conductive type different from the first conductive type formed to cover the source, and an insulating film formed on the semiconductor substrate between the source and the drain The memory cell includes a gate, a memory cell including a floating gate formed through an insulating film on the floating gate, a word line connected to the control gate, and a bit line connected to the drain.

The non-volatile semiconductor memory device according to the third invention is different from the non-volatile semiconductor memory device according to the first invention in that the non-volatile semiconductor memory device has a second conductivity type different from the first conductivity type formed so as to cover the source. It has an impurity region.

[0120]

First, the relationship between the program and erase operations and the threshold voltage in the first to eleventh embodiments described below will be described in comparison with a conventional example.

In the conventional example, as shown in FIG.
The threshold voltage of the memory cell increases by the program operation, and the threshold voltage of the memory cell decreases by the erase operation. On the other hand, in the embodiment, as shown in FIG. 1A, the threshold voltage of the memory cell decreases by the program operation, and the threshold voltage of the memory cell increases by the erase operation.

That is, in the conventional example, as shown in FIG. 2B, in the memory cell in the erased state, electrons are emitted from the floating gate, and the threshold voltage is low. In the memory cell in the programmed state, electrons are injected into the floating gate, and the threshold voltage is high.

On the other hand, in the embodiment, in FIG.
As shown in the figure, in the memory cell in the erased state, electrons are injected into the floating gate, and the threshold voltage is high. In the memory cell in the programmed state, electrons are emitted from the floating gate, and the threshold voltage is low.

The fact that the erase state corresponds to data "1" and the program state corresponds to data "0" is the same in the embodiment and the conventional example.

As described above, in the embodiment, the threshold voltage of each memory cell is increased by the erasing operation. Therefore, as shown in FIG. The threshold voltage of the memory cell can be made higher than power supply voltage Vcc.

As shown in FIG. 4, even if the threshold voltages of a plurality of memory cells vary, some memory cells are not depleted by the collective erase operation.

(1) First Embodiment (FIGS. 5 to 8) (a) Overall Configuration of Flash Memory (FIG. 5) FIG. 5 is a block diagram showing the overall configuration of a flash memory according to the first embodiment. FIG. The overall configuration of the flash memory of FIG. 5 is the same as the conventional flash memory of FIG. 131 except that the voltage application conditions in each operation are different. The flash memory of FIG. 5 is also formed on the chip CH.

(B) Programming and Erasing of Memory Cell (FIG. 6) FIG. 6A shows conditions for applying a voltage to the memory cell during programming. FIG. 6B shows conditions for applying a voltage to the memory cell at the time of erasing.

At the time of programming, as shown in FIG. 6A, a high voltage Vpp (normally about 12 V) is applied to the drain 1002, 0 V is applied to the control gate 1006, and the source 1003 is brought into a floating state. As a result, the floating gate 1005 and the drain 1
002, a high electric field is generated, and electrons are emitted from the floating gate 1005 to the drain 1002 by a tunnel phenomenon. As a result, the threshold voltage of the memory cell decreases.

At the time of erasing, as shown in FIG.
0 V is applied to the drain 1002, a high voltage Vpp (normally about 12 V) is applied to the control gate 1006,
A predetermined high voltage VSL (6 V) is applied to the source 1003. As a result, hot electrons or channel hot electrons are generated near the source 1003 due to avalanche breakdown. These hot electrons are accelerated by the high voltage Vpp of the control gate 1006, jump over the energy barrier by the insulating film 1004, and are injected into the floating gate 1005. As a result, the threshold voltage of the memory cell increases.

As described above, at the time of programming, a floating phenomenon occurs from the floating gate 1005 to the drain 1 due to the tunnel phenomenon.
At 002, electrons are emitted. Therefore, in order to weaken the electric field in the channel direction or the substrate direction, the drain 1002
Are provided along the N- type impurity region 1002b.

At the time of erasing, the floating gate 10 is brought close to the source 1003 by hot electrons.
At 05, electrons are injected. Therefore, the source 1 is set so that a higher electric field is generated in the channel direction or the substrate direction.
A P + type impurity region 1003b is provided along 003.

The P- well 1008 may be a P- type semiconductor substrate. (C) Operation of Flash Memory (FIG. 7) Next, a batch erase operation, a program operation, and a read operation of the flash memory will be described with reference to FIG. FIG.
Shows some memory cells M11 to M13, M21 to M23, and M31 to M33 included in the memory array 1010.

(I) Batch Erase Operation ((a) of FIG. 7) First, the control circuit 11
30 is supplied with a control signal designating a batch erase operation. Vpp / Vcc switching circuit 1090 is externally supplied with high voltage Vpp.

Vpp / Vcc switching circuit 1090 supplies X decoder 1030 with high voltage Vpp. X decoder 1
030 selects all the word lines WL to WL3 and applies a high voltage Vpp to them. Y decoder 1040
Turns on all the Y-gate transistors included in the Y-gate 1050. Write circuit 1080 applies 0 V to all bit lines BL1 to BL via Y gate 1050.
3 The source control circuit 1110 controls the source line S
A predetermined high voltage VSL (VSL <Vpp) is applied to L.

Thus, all memory cells M1
A voltage is applied to 1 to M33 as shown in FIG. As a result, all the memory cells M11 to M3
3 is erased.

(Ii) Program Operation (FIG. 7 (b)) Here, it is assumed that the memory cell M12 is programmed. That is, data “0” is written to the memory cell M12, and data “1” is written to another memory cell.

First, a control signal designating a program operation is applied to control circuit 1130 via control signal buffer 1120. Vpp / Vcc switching circuit 109
0 is supplied with a high voltage Vpp from the outside.

X decoder 1030 selects word line WL2 in response to the X address signal supplied from address buffer 1020, and applies 0 V to selected word line WL2.
And a power supply voltage Vcc is applied to the unselected word lines WL1 and WL3.

Vpp / Vcc switching circuit 1090 applies high voltage Vpp to write circuit 1080. Data is sequentially supplied from outside to the write circuit 1080 via the data input / output buffer 1070. At this time, the Y decoder 1040
Turns on the Y gate transistors in the Y gate 1050 in response to the Y address signal supplied from the address buffer 1020. Write circuit 1080 applies high voltage Vpp to bit line BL1 via Y gate 1050, and applies power supply voltage Vcc to bit lines BL2 and BL3. The source control circuit 1110 sets the source line SL to a floating state.

Thus, a voltage is applied to the memory cell M12 as shown in FIG. At this time, the other memory cells are in one of the following states.

(A) The high voltage Vpp is applied to the drain, the power supply voltage Vcc is applied to the control gate,
The source is in a floating state.

(B) The power supply voltage Vcc is applied to the drain, 0 V is applied to the control gate, and the source is in a floating state.

(C) The power supply voltage Vcc is applied to the drain, the power supply voltage Vcc is applied to the control gate, and the source is in a floating state.

As a result, a high electric field is generated only between the floating gate and the drain of the memory cell M12, and only the memory cell M12 is programmed.

(Iii) Read operation ((c) in FIG. 7) The read operation is almost the same as the operation described with reference to FIG. Here, it is assumed that data is read from memory cell MC12. First, the control signal buffer 1120
, A control signal designating a read operation is applied to control circuit 1130.

X decoder 1030 selects word line WL2 in response to an X address signal supplied from address buffer 1020, and applies power supply voltage Vcc to it. At this time, the other word lines WL1 and WL3 are kept at 0V. The Y decoder 1040 is provided in the address buffer 10
In response to the Y address signal given from the control signal 20, one Y gate transistor in the Y gate 1050 is turned on. Source control circuit 1110 grounds source line SL.

As a result, the read voltage V is applied to the bit line BL1.
r appears. This read voltage Vr is applied to sense amplifier 1060
Is detected and amplified by the data input / output buffer 10
The signal is output to the outside through the line 70.

(D) Rewriting operation (FIG. 8) The rewriting operation of data in this flash memory is shown in FIG.
This will be described with reference to the flowchart of FIG.

First, data "1" is stored in all memory cells.
Is determined (step S1).
If data "1" is not stored in all the memory cells, a batch erase operation is performed (step S2). Thereafter, a program operation is performed (step S3). Thus, data can be rewritten without performing the pre-write erasing operation as in the conventional example.

(E) Modifications At the time of programming, unselected bit lines BL2 and BL3 may be in a floating state. At this time, the unselected memory cells are in one of the following states.

(A) The high voltage Vpp is applied to the drain, the power supply voltage Vcc is applied to the control gate,
The source is in a floating state.

(B) The drain is in a floating state, 0 V is applied to the control gate, and the source is in a floating state.

(C) The drain is in a floating state, the power supply voltage Vcc is applied to the control gate, and the source is in a floating state.

Also in this case, a high electric field is generated only between the floating gate and the drain of the memory cell M12, and only the memory cell M12 is programmed by a tunnel phenomenon.

During programming, power supply voltage Vcc may be applied to source line SL. At this time, the memory cell M12
High voltage Vpp is applied to the drain, 0 V is applied to the control gate, and the power supply voltage Vcc is applied to the source.
Is applied. Other memory cells are in one of the following states.

(A) The high voltage Vpp is applied to the drain, the power supply voltage Vcc is applied to the control gate,
The power supply voltage Vcc is applied to the source.

(B) The power supply voltage Vcc is applied to the drain, 0 V is applied to the control gate, and the power supply voltage Vcc is applied to the source.

(C) The power supply voltage Vcc is applied to the drain, the power supply voltage Vcc is applied to the control gate, and the power supply voltage Vcc is applied to the source.

Also in this case, a high electric field is generated only between the floating gate and the drain of the memory cell M12, and only the memory cell M12 is programmed by a tunnel phenomenon.

At the time of programming, unselected bit lines BL
2 and BL3 in a floating state and the source line SL
May be applied with the power supply voltage Vcc. At this time, the high voltage Vpp is applied to the drain of the memory cell M12, 0 V is applied to the control gate, and the power supply voltage Vcc is applied to the source. The other memory cells are in one of the following states.

(A) The high voltage Vpp is applied to the drain, the power supply voltage Vcc is applied to the control gate,
The power supply voltage Vcc is applied to the source.

(B) The drain is in a floating state, 0 V is applied to the control gate, and the power supply voltage Vcc is applied to the source.

(C) The drain is in a floating state, the power supply voltage Vcc is applied to the control gate, and the power supply voltage Vcc is applied to the source.

Also in this case, a high electric field is generated only between the floating gate and the drain of the memory cell M12, and only the memory cell M12 is programmed by a tunnel phenomenon.

A verify operation may be performed after the batch erase operation. Further, before the batch erase operation, 0V is applied to the control gates of all the memory cells and P
-By applying a high voltage Vpp to a well (or a P- type semiconductor substrate), electrons may be extracted from the control gates of all memory cells, and then a batch erase operation may be performed while performing a verify operation. This makes it possible to further reduce the variation in the threshold voltage of the collectively erased memory cells.

(F) Effect of the First Embodiment In the conventional flash memory, electrons are injected from the drain side to the floating gate. Therefore, when the potential of the bit line increases during the read operation, electrons are injected from the drain into the selected memory cell, and soft writing may occur.

On the other hand, in the flash memory of the first embodiment, electrons are injected into the floating gate from the source side. Therefore, a soft write is less likely to occur during a read operation.

The program operation may be performed while performing the verify operation. Thus, variation in the threshold voltage of the programmed memory cell can be reduced.

(2) Second Embodiment (FIGS. 9 and 10) The overall configuration of the flash memory according to the second embodiment is as follows.
This is the same as the configuration shown in FIG.

(A) Programming and Erasing of Memory Cell (FIG. 9) FIG. 9A shows conditions for applying a voltage to the memory cell during programming. FIG. 9B shows conditions for applying a voltage to the memory cell at the time of erasing. The voltage application conditions at the time of programming are the same as the voltage application conditions shown in FIG.

At the time of erasing, as shown in FIG.
0 V is applied to the drain 1002, a high voltage Vpp (normally about 12 V) is applied to the control gate 1006,
0 V is applied to the source 1003. Accordingly, a channel c is formed in a region between the source 1003 and the drain 1002.
h is formed, and a high electric field is generated between the channel ch and the floating gate 1005. Electrons are injected into the floating gate 1005 from the channel ch by a tunnel phenomenon. As a result, the threshold voltage of the memory cell increases.

In this embodiment, during programming, electrons are emitted from floating gate 1005 to drain 1002 by a tunnel phenomenon. Therefore, in order to weaken the electric field in the channel direction or the substrate direction, the drain 10
N- type impurity region 1002c is provided along line 02.

Note that an N − -type impurity region 1003 c may be provided along the source 1003. As described above, the N − -type impurity regions 1002 are
When c and 1003c are provided, the number of manufacturing steps is reduced.

(B) Operation of Flash Memory (FIG. 1)
0) Next, a batch erase operation, a program operation, and a read operation of the flash memory will be described with reference to FIG. The program operation and the read operation are the same as in the first embodiment. Therefore, the batch erase operation will be described below.

First, a control signal designating a batch erase operation is applied to control circuit 1130 via control signal buffer 1120. Vpp / Vcc switching circuit 1090
Is supplied with a high voltage Vpp from outside.

Vpp / Vcc switching circuit 1090 applies a high voltage Vpp to X decoder 1030. X decoder 1
030 selects all word lines WL1 to WL3,
A high voltage Vpp is applied to them. Y decoder 1040
Turns on all the Y-gate transistors included in the Y-gate 1050. Write circuit 1080 has Y gate 1
050 through all bit lines BL1 to BL3
Is applied. Source control circuit 1110 applies 0 V to source line SL.

Thus, all memory cells M1
A voltage is applied to 1 to M33 as shown in FIG. As a result, all the memory cells M11 to M3
3 is erased.

In the batch erasing operation, a negative voltage may be positively applied to the P- well (or P- type semiconductor substrate).

Data rewriting is performed according to the procedure shown in FIG. Therefore, data can be rewritten without performing the pre-erase write operation as in the conventional example.

(3) Third Embodiment (FIGS. 11 to 14) FIG. 11 is a block diagram showing the overall configuration of a flash memory according to the third embodiment. The flash memory of FIG. 11 differs from the flash memory of FIG. 5 in the following points.

A negative voltage control circuit 1140 which receives externally applied negative voltage -Vee and generates a predetermined negative voltage is further provided. Also, the X decoder 1030
As shown in FIG.
Instead of (see FIG. 132), a plurality of potential control switches 1303 connected to a plurality of word lines WL are included. Each potential control switch 1303 applies a high voltage Vpp or power supply voltage Vcc provided from Vpp / Vcc switching circuit 1090 or a negative voltage -Vee provided from negative voltage control circuit 1140 to corresponding word line WL.

(B) Programming and Erasing of Memory Cell (FIG. 13) FIG. 13A shows conditions for applying a voltage to the memory cell during programming. FIG. 13B shows conditions for applying a voltage to the memory cell at the time of erasing.

At the time of programming, as shown in FIG. 13A, the power supply voltage Vcc (normally 5 V
), A negative voltage −Vee (−12 V) is applied to the control gate 1006, and the source 1003 is brought into a floating state. As a result, a high electric field is generated between the floating gate 1005 and the drain 1002, and the floating gate 1005
, Electrons are emitted to the drain 1002. as a result,
The threshold voltage of the memory cell decreases.

The voltage application conditions at the time of erasing are the same as the voltage application conditions shown in FIG.

As described above, the tunneling phenomenon causes the floating gate 1005 to change the drain 1
At 002, electrons are emitted. Therefore, in order to weaken the electric field in the channel direction or the substrate direction, the drain 1002
Are provided along the N- type impurity region 1002d.

At the time of erasing, the floating gate 10 is brought close to the source 1003 by hot electrons.
At 05, electrons are injected. Therefore, the source 1 is set so that a higher electric field is generated in the channel direction or the substrate direction.
A P + type impurity region 1003d is provided along 003.

(C) Operation of Flash Memory (FIG. 1)
4) Next, a batch erase operation, a program operation, and a read operation of the flash memory will be described with reference to FIG. The batch erasing operation and the reading operation are the same as in the first embodiment. Therefore, the program operation will be described below.

Here, it is assumed that memory cell M12 is programmed. That is, data “0” is written to the memory cell M12, and data “1” is written to another memory cell.

First, a control signal designating a program operation is applied to control circuit 1130 via control signal buffer 1120. Negative voltage control circuit 1140 is externally supplied with negative voltage -Vee.

X decoder 1030 selects word line WL2 in response to the X address signal applied from address buffer 1020, and applies the negative voltage -Vee from negative voltage control circuit 1140 to the selected word line WL2. 0 V is applied to unselected word lines WL1 and WL3.

Vpp / Vcc switching circuit 1090 supplies power supply voltage Vcc to writing circuit 1080. Data is sequentially supplied from outside to the write circuit 1080 via the data input / output buffer 1070. At this time, the Y decoder 104
0 sequentially turns on the Y gate transistors in the Y gate 1050 in response to the Y address signal supplied from the address buffer 1020. The write circuit 1080
The power supply voltage Vc is applied to the bit line BL1 via the gate 1050.
c, and 0 V is applied to the bit lines BL2 and BL3. The source control circuit 1110 sets the source line SL to a floating state.

Thus, a voltage is applied to the memory cell M12 as shown in FIG. At this time, the other memory cells are in one of the following states.

(A) The power supply voltage Vcc is applied to the drain, 0 V is applied to the control gate, and the source is in a floating state.

(B) 0 V is applied to the drain, negative voltage -Vee is applied to the control gate, and the source is in a floating state.

(C) 0 V is applied to the drain, 0 V is applied to the control gate, and the source is in a floating state.

(E) Modifications At the time of programming, unselected bit lines BL2 and BL3 may be in a floating state. At this time, the unselected memory cells are in one of the following states.

(A) The power supply voltage Vcc is applied to the drain, 0 V is applied to the control gate, and the source is in a floating state.

(B) The drain is in a floating state, a negative voltage -Vee is applied to the control gate, and the source is in a floating state.

(C) The drain is in a floating state, 0 V is applied to the control gate, and the source is in a floating state.

Also in this case, a high electric field is generated only between the floating gate and the drain of memory cell M12,
Only the memory cell M12 is programmed by the tunnel phenomenon.

At the time of programming, an unselected bit line may be set to a floating state and 0 V may be applied to source line SL. At this time, the power supply voltage Vcc is applied to the drain of the memory cell M12, the negative voltage -Vee is applied to the control gate, and 0 V is applied to the source.
Other memory cells are in one of the following states.

(A) The power supply voltage Vcc is applied to the drain, 0 V is applied to the control gate, and 0 V is applied to the source.

(B) The drain is in a floating state, a negative voltage -Vee is applied to the control gate, and 0 V is applied to the source.

(C) The drain is in a floating state, and 0 V is applied to the control gate and 0 V is applied to the source.

Also in this case, a high electric field is generated only between the floating gate and the drain of memory cell M12,
Only the memory cell M12 is programmed by the tunnel phenomenon.

In the third embodiment, the batch erasing operation may be performed in the same manner as in the second embodiment shown in FIG.
A voltage is applied to each memory cell as shown in FIG.

In this case, since the injection of electrons into the floating gate and the emission of electrons from the floating gate are performed using the tunnel phenomenon, power consumption is reduced. Therefore, a high voltage and a negative voltage can be internally generated from a power supply voltage supplied from the outside.

(4) Fourth Embodiment (FIGS. 15 and 16) The overall configuration of the flash memory according to the fourth embodiment is the same as the configuration shown in FIG. The voltage application conditions to the memory cells at the time of programming and erasing are the same as the voltage application conditions shown in FIGS. 6A and 6B. The fourth embodiment differs from the first embodiment only in the control method.

(A) Operation of Flash Memory (FIG. 1)
5) Next, a page erase operation, a program operation, and a read operation of the flash memory will be described with reference to FIG. The program operation and the read operation are the same as in the first embodiment. Therefore, the page batch erasing operation will be described below.

All the memory cells connected to one word line are called a page. In the page batch erasing operation, batch erasing is performed in page units. Here, the word line WL
The batch erase operation of the page corresponding to No. 2 will be described.

First, a control signal designating a batch page erase operation is applied to control circuit 1130 via control signal buffer 1120. Vpp / Vcc switching circuit 1
090 is externally supplied with a high voltage Vpp.

Vpp / Vcc switching circuit 1090 supplies X decoder 1030 with high voltage Vpp. X decoder 1
030 is X provided from the address buffer 1020.
In response to the address signal, the word line WL2 is selected, a high voltage Vpp is applied to the selected word line WL2, and 0 V is applied to unselected word lines WL1 and WL3. Y decoder 1040 turns on all Y gate transistors included in Y gate 1050. Write circuit 1080
Applies 0V to all the bit lines BL1 to BL3 via the Y gate 1050. Source control circuit 1110
Is a predetermined high voltage VSL (VSL <Vpp) applied to the source line SL.
Is applied.

In this way, a voltage is applied to the memory cells M12, M22, M32 connected to the word line WL2 as shown in FIG. 6B. as a result,
The memory cells M12, M22, M32 are erased.

In each memory cell connected to unselected word lines WL1 and WL3, 0V is applied to drain 1002.
Is applied, a high voltage VSL is applied to the source 1003,
0 V is applied to the control gate 1006. Therefore, there is little possibility that hot electrons are injected into the floating gate 1005 by jumping over the energy barrier of the insulating film 1004. Therefore, only the memory cells connected to the selected word line WL2 are collectively erased.

As described above, in the fourth embodiment, the collective erasing operation is performed in page units, not in memory array units.

(B) Rewriting Operation (FIG. 16) The rewriting operation of data in the flash memory according to the fourth embodiment will be described with reference to the flowchart of FIG.

First, data "1" is stored in all memory cells.
Is determined (step S1).
1). When data "1" is not stored in all the memory cells, a page batch erasing operation is performed for a page to be rewritten (step S12). Thereafter, a program operation is performed (step S13).

As described above, data can be rewritten page by page without performing the erase operation before writing as in the conventional example.

(5) Fifth Embodiment (FIG. 17) The overall configuration of the flash memory according to the fifth embodiment is as follows.
This is the same as the configuration shown in FIG. The voltage application conditions to the memory cell at the time of programming and erasing are the same as the voltage application conditions shown in FIGS. 9A and 9B. The fifth embodiment differs from the second embodiment only in the control method.

A page erase operation, a program operation, and a read operation of the flash memory according to the fifth embodiment will be described with reference to FIG. The program operation and the read operation are the same as in the second embodiment. Therefore, the page batch erasing operation will be described below. Here, the batch erase operation of the page corresponding to word line WL2 will be described.

First, a control signal designating a page batch erase operation is applied to control circuit 1130 via control signal buffer 1120. Vpp / Vcc switching circuit 1
090 is externally supplied with a high voltage Vpp.

Vpp / Vcc switching circuit 1090 applies a high voltage Vpp to X decoder 1030. X decoder 1
030 is X provided from the address buffer 1020.
In response to the address signal, select word line WL2, apply high voltage Vpp to the selected word line WL2,
0V is applied to unselected word lines WL1 and WL3. Y
Decoder 1040 turns on all Y gate transistors included in Y gate 1050. Write circuit 10
80 applies 0V to all the bit lines BL1 to BL3 via the Y gate 1050. Source control circuit 111
0 applies 0 V to the source line SL.

Thus, a voltage is applied to the memory cells M12, M22, M32 connected to the word line WL2 as shown in FIG. 9B. as a result,
The memory cells M12, M22, M32 are erased.

In each memory cell connected to unselected word lines WL 1 and WL 3, 0 V is applied to drain 1002, source 1003 and control gate 1006. Therefore, the floating gate 1005
No high electric field is generated between the floating gate 1005 and the source 1003, and electrons are not injected into the floating gate 1005 due to a tunnel phenomenon. Therefore, only the memory cells connected to the selected word line are erased collectively.

As described above, also in the fifth embodiment, batch erasing can be performed not on a memory array basis but on a page basis.

Data rewriting is performed according to the procedure shown in FIG. Therefore, data can be rewritten in page units without performing the pre-erase write operation as in the conventional example.

(6) Sixth Embodiment (FIGS. 18 to 33) (a) Overall Configuration of Flash Memory (FIGS. 18 and 1)
9) FIG. 18 is a block diagram showing the overall configuration of the flash memory according to the sixth embodiment. FIG. 19 is a circuit diagram showing a detailed configuration of the memory array and its related parts.

The flash memory of FIG. 18 differs from the conventional flash memory of FIG. 131 in the following points.
The memory array 1010a is divided into a plurality of sectors. In the example of FIG. 18, the memory array 1010a is divided into sectors SE1 and SE2. Memory array 101
0a includes select gates SG1 and SG2 corresponding to sectors SE1 and SE2, respectively.

The memory array 1010a is a P-well 1
008. Vpp / Vcc shown in FIG.
The switching circuit 1090 is not provided and the high voltage generation circuit 121
0, 1220, negative voltage generation circuits 1230, 1240, well potential generation circuit 1250, and select gate decoder 1260 are further provided. High voltage generation circuit 121
0 and 1220 are externally supplied with a power supply voltage Vcc (for example, 5
V) and generates a high voltage (for example, 10 V). Negative voltage generating circuits 1230 and 1240 receive power supply voltage Vcc from the outside and generate a negative voltage (for example, -10 V). Well potential generating circuit 1250 applies a negative voltage (for example, -5 V) to P- well 1008 at the time of erasing. Select gate decoder 1260 includes address buffer 10
Select gates SG1 and SG2 are selectively activated in response to a part of the address signal from 20.

Next, reference is made to FIG. Memory array 10
A plurality of main bit lines are arranged in 10a. FIG. 19 shows two main bit lines MB0 and MB1. The main bit lines MB0 and MB1 are respectively connected to Y gate transistors YG
0, YG1 are connected to the sense amplifier 1060 and the write circuit 1080.

A plurality of sub-bit lines are arranged corresponding to each main bit line. In the example of FIG. 19, two sub-bit lines SB01 and SB02 are provided corresponding to main bit line MB0, and two sub-bit lines SB01 corresponding to main bit line MB1.
11, SB12 are provided.

A plurality of word lines are arranged to cross a plurality of sub-bit lines. In the example of FIG.
Word lines WL0, W
L1 is arranged, and word lines WL2, WL3 are arranged so as to cross the sub-bit lines SB02, SB12.

Sub bit lines SB01, SB02, SB1
1, memory cells M00 to M03 and M10 to M13 are provided at intersections between SB12 and word lines WL0 to WL3, respectively. Memory cells M00, M01, M10, M11
Are included in the sector SE1, and the memory cells M02, M03,
M12 and M13 are included in the sector SE2.

A drain of each memory cell is connected to a corresponding sub-bit line, a control gate is connected to a corresponding word line, and a source is connected to a source line SL.

Select gate SG1 includes select gate transistors SG01 and SG11, and select gate SG2 is select gate transistors SG02 and SG1.
2 inclusive. The sub-bit lines SB01 and SB02 are connected to the main bit line MB0 via select gate transistors SG01 and SG02, respectively.
B12 is a select gate transistor SG1
1 and SG12 to the main bit line MB1.
Select gate line S of select gate decoder 1260
GL1 is the select gate transistors SG01, SG1
1 and the select gate line SGL2 is connected to select gate transistors SG02 and SG12.

(B) Programming and Erasing of Memory Cell (FIG. 20) FIG. 20A shows conditions for applying a voltage to the memory cell during programming. FIG. 20B shows conditions for applying a voltage to the memory cell at the time of erasing.

At the time of programming, as shown in FIG. 20A, a positive voltage (for example, 5 V) is applied to drain 1002, a negative voltage (for example, -10 V) is applied to control gate 1006, and source 1003 is set in a floating state. Then, 0 V is applied to the P − well 1008. As a result, the floating gate 1005 and the drain 1
A high electric field is generated between the floating gate 1002 and the floating gate 1002, and electrons are emitted from the floating gate 1005 to the drain 1002 by a tunnel phenomenon. As a result, the threshold voltage of the memory cell decreases.

At the time of erasing, as shown in FIG. 20B, the drain 1002 is set to the floating state, a high voltage (for example, 10 V) is applied to the control gate 1006, the source 1003 is set to the floating state,
Applying a negative voltage (eg, -5V) to the well 1008; As a result, a high voltage (in this case, 15 V) is applied between the control gate 1006 and the P − well 1008, and the source 1003 and the floating gate 1005 are applied.
And a high electric field is generated between them. As a result, the floating gate 1005
Are injected into the memory cell, and the threshold voltage of the memory cell increases.

As described above, the tunneling phenomenon causes the floating gate 1005 to change the drain 1
At 002, electrons are emitted. Therefore, in order to weaken the electric field in the channel direction or the substrate direction, the drain 1002
Along the region, an N- type impurity region 1002e is provided.

Note that an N − -type impurity region 1003 e may be provided along the source 1003. As described above, the N − -type impurity regions 1002 are
When e and 1003e are provided, the number of manufacturing steps is reduced.

(C) Operation of flash memory (FIG. 2)
1) Next, the sector erase operation, program operation, and read operation of the flash memory will be described with reference to FIG.

(I) Batch Sector Erase Operation Here, it is assumed that the sector SE1 is collectively erased. First, a control signal designating a sector batch erasing operation is applied to control circuit 1130 via control signal buffer 1120. Thereby, high voltage generation circuit 1220 and negative voltage generation circuit 1230 are activated.

The high voltage generation circuit 1220
Apply a high voltage (10V) to 30. X decoder 1030
Applies a high voltage (10 V) to the word lines WL0 and WL1 of the sector SE1, and applies the word lines WL2 and WL2 of the sector SE2.
0 V is applied to WL3. Negative voltage generation circuit 1230 is Y
Negative voltage is applied to decoder 1040 and well potential generating circuit 1250. Y decoder 1040 is a Y gate 105
A negative voltage (−5 V) is applied to the Y gate transistors YG0 and YG1 in 0. Thereby, the main bit line MB
0 and MB1 enter a floating state. The source control circuit 10 sets the source line SL to a floating state. Also, well potential generating circuit 1250 has P- well 1008
A negative voltage (−5 V). Select gate decoder 1260 applies 0 V to select gate lines SG1 and SG2.

In this way, a voltage is applied to the memory cells M00, M01, M10, M11 in the sector SE1, as shown in FIG. as a result,
All memory cells in sector SE1 are erased.

At this time, in each memory cell in the non-selected sector SE2, the voltage applied between the control gate and the P- well is 5V. Therefore, no tunnel phenomenon occurs. Since this potential condition is almost the same as the potential condition at the time of reading, disturbance to data hardly occurs.

(Ii) Program Operation (FIG. 21 (b)) Here, it is assumed that the memory cell M00 is programmed. That is, data “0” is written to the memory cell M00, and data “1” is written to the memory cell M10.

First, a control signal designating a program operation is applied to control circuit 1130 via control signal buffer 1120. Thereby, the high voltage generation circuit 1210
And negative voltage generation circuit 1240 is activated.

Negative voltage generating circuit 1240 is connected to X decoder 10
30 is given a negative voltage. X decoder 1030 selects word line WL0 in response to an X address signal provided from address buffer 1020, and selects selected word line W0.
A negative voltage (−10 V) is applied to L0, and 0 V is applied to unselected word lines WL1 to WL3.

The high voltage generation circuit 1210
40, a high voltage is applied to the write circuit 1080 and the select gate decoder 1260. First, data “0” is externally written to the write circuit 1 via the data input / output buffer 1070.
080 and latched. Y decoder 1040
Applies a high voltage (for example, 7V) to Y gate transistor YG0 in Y gate 1050 and applies 0V to Y gate transistor YG1 in response to a Y address signal supplied from address buffer 1020. As a result, the Y gate transistor YG0 turns on.

Write circuit 1080 applies a program voltage (5 V) corresponding to data "0" to main bit line MB0 via Y gate transistor YG0. The select gate decoder 1260 is connected to the select gate line SGL.
A high voltage (for example, (7 V)) is applied to 1 and 0 V is applied to the select gate line SGL2, whereby the sub-bit lines SB01 and SB11 are connected to the main bit lines MB0 and M, respectively.
B1. The source control circuit 1110 sets the source line SL to a floating state. Well potential generating circuit 1250 applies 0 V to P- well 1008.

Thus, a voltage is applied to the memory cell M00 as shown in FIG. As a result, the threshold voltage of the memory cell M00 decreases.

After a lapse of a predetermined time (for example, 1 ms), data “1” is externally applied to write circuit 1080 via data input / output buffer 1070 and latched.
Y decoder 1040 responds to a Y address signal provided from address buffer 1020 by Y gate 1050.
, A high voltage (7 V) is applied to the Y gate transistor YG1 and 0 V is applied to the Y gate transistor YG0.
This turns on the Y gate transistor YG1.
Write circuit 1080 applies 0 V corresponding to data "1" to main bit line MB1 via Y gate transistor YG1. Therefore, the threshold voltage of memory cell M10 is kept high.

A verify operation may be performed during a program operation. This verify operation will be described with reference to the flowchart of FIG.

As described above, the selected word line WL0
, And a high voltage (7 V) is applied to the selected select gate line SGL1 (step S21). Further, the source line SL is set to the floating state (step S22), and the main bit line MB for data "0" is
5V is applied to 0, and 0V is applied to the main bit line MB1 of data "1" (step S23). Thereby, the threshold voltage of memory cell M00 decreases. At this time, the threshold voltage of the memory cell M10 is kept high.

After a lapse of a fixed time (for example, 1 ms), control circuit 1130 starts a verify operation. Thereby, verify voltage generation circuit 1100 is activated. Verify voltage generation circuit 1100 is connected to X decoder 10
30 is supplied with a verify voltage lower than the normal power supply voltage Vcc. As a result, a verify voltage is applied to the selected word line WL0 (step S24). The source line SL is grounded by the source control circuit 1110 (step S25). Thereby, a read operation is performed (step S26).

When the threshold voltage of memory cell M00 is higher than the verify voltage, no current flows through main bit line MB0. Therefore, sense amplifier 1060 detects data “1”. In this case, control circuit 1130 determines that the program is insufficient, and performs the program operation and the verify operation again (steps S27 and S21).
To S26).

If the threshold voltage of memory cell M00 is lower than the verify voltage, a current flows through main bit line MB0. Therefore, sense amplifier 1060 detects data “0”. In this case, control circuit 1130 determines that the program is sufficient, and ends the program operation for memory cell M00.

The X address signal applied to X decoder 1030 is sequentially incremented, and word lines WL1 and W
A program operation and a verify operation are sequentially performed on L2 and WL3 (steps S28 and S29).

(Iii) Read operation ((c) in FIG. 21) Here, it is assumed that data is read from memory cell M00. First, a control signal designating a read operation is supplied to control circuit 1130 via control signal buffer 1120.

X decoder 1030 selects word line WL0 in response to an X address signal supplied from address buffer 1020, and applies power supply voltage Vcc (5 V) to it. At this time, the word lines WL1, WL2, WL3
Is kept at 0V. Select gate decoder 1260
Applies 5 V to the select gate line SGL1 and 0 V to the select gate line SGL2. Y decoder 10
Reference numeral 40 turns on the Y gate transistor YG0 in the Y gate 1050 in response to the Y address signal supplied from the address buffer 1020. Source control circuit 111
0 grounds the source line SL.

Thus, read voltage Vr appears on main bit line MBO. This read voltage Vr is applied to sense amplifier 106
0 and is output to the outside via the data input / output buffer 1070.

(D) Cross-sectional structure of memory cell (FIG. 23) FIG. 23 is a diagram showing a cross-sectional structure of a memory cell used in the flash memory of this embodiment. The structure shown in FIG. 23 is called a triple well structure.

N-type semiconductor substrate 1001
A well 1009 is formed, and a P-well 1008 is formed in the N-well 1009; P-well 1008
Two N @ + -type impurity regions are formed at predetermined intervals in a predetermined region. One of the N + type impurity regions is a drain 1
002 and the other constitutes the source 1003. On a region between the source 1002 and the drain 1003, a floating gate 1005 is formed via an insulating film 1004 (about 100 °) such as an extremely thin oxide film, and a control gate 1006 is formed thereon via an insulating film. Is done. Thus, a memory cell MC is formed.

CMOS circuit region 1300 includes an N-channel transistor formed in a P- well and a P-channel transistor formed in an N- well.

(E) High integration FIG. 24 is a structural diagram of two adjacent memory cells in the sixth embodiment. As shown in FIG. 24, two memory cells M00 and M10 are separated by a separation oxide film 1400 formed on P well 1008.

In the programming operation, a voltage of 5 V is applied to drain 1002 'of selected memory cell M10, while a voltage of 0 V is applied to drain 1002 of unselected memory cell M00. In addition to this, a second aluminum wiring layer 1006 forming a control gate
Is supplied with a negative voltage of -10V. Therefore, MOS transistor 1401 equivalently exists using isolation oxide film 1400 as a gate oxide film.

This equivalent NMOS transistor 1401
Receives a negative voltage of -10 V through the gate electrode. Therefore, this equivalent transistor 1401 cannot conduct in the above-described program operation, and therefore, it is possible to select width Wa of isolation oxide film 1400 to a smaller value than width Wb shown in FIG. Can,
Therefore, a higher degree of integration can be obtained.

FIG. 25 is a layout diagram of a memory cell array on a semiconductor substrate in the sixth embodiment. As described above, in the sixth embodiment, the program operation and the erase operation are performed by utilizing the tunnel phenomenon.
The current flowing through the sub-bit line becomes extremely small. Therefore, the channel width of select gate transistors SG0 and SG1 for selecting a sector can be selected to a smaller value as compared with the example shown in FIG. Therefore, a layout suitable for higher integration can be obtained.

FIG. 26 is a circuit diagram showing voltages applied to the memory cell array of the sixth embodiment. FIG.
FIG. 26A shows the voltage applied in the program operation, while FIG. 26B shows the voltage applied in the erase operation.

As shown in FIG. 26 (a), in the program operation, an X decoder (not shown)
The output voltages V and 0V are output. In other words, X
The decoder outputs an output voltage having a voltage difference of 10V.

On the other hand, as shown in FIG. 26B, the X decoder requires output voltages of 10 V and 0 V in the erasing operation. In other words, the X decoder is 10V
Is output.

The output voltage difference shown in FIG.
V) and the output voltage difference shown in FIG. 147 (that is, 15 V and 18 V), the output voltage difference of the X decoder in the sixth embodiment is reduced. This contributes to improving the integration of the X decoder. That is, in the sixth embodiment, since the output voltage difference of the X decoder becomes small, it becomes possible to form the X decoder in a less occupied area on the semiconductor substrate.

(F) High voltage generation circuit (FIG. 27, FIG. 2)
8) FIG. 27A shows an equivalent circuit of the high voltage generation circuit. The high voltage generation circuit includes a plurality of diodes D210 and a plurality of capacitances C210. Capacitance C2
10 are supplied with two-phase clock signals φ and / φ. Thereby, a charge pump is configured.

Each diode D210 is usually constituted by an N-channel transistor as shown in FIG. The back gate of the N-channel transistor is grounded.

However, when the power supply voltage Vcc is low (for example, 3 V), it is difficult to obtain a high voltage due to the back gate effect. The back gate effect means that when the back gate voltage decreases relative to the source voltage, the threshold voltage increases.

In this embodiment, the structure shown in FIG. 28 is used. P- type semiconductor substrate 1001 has a plurality of N
-A well 1211 is formed, and a P + -type impurity region 1212 and an N + -type impurity region 1
213 are formed. These P + type impurity regions 121
The 2 and N + type impurity regions 1213 constitute a diode.

According to this configuration, since each diode has no back gate, the back gate effect does not occur.

However, in some cases, a parasitic transistor (bipolar transistor) as shown in FIG. 29 may exist in the high voltage generating circuit having the structure shown in FIG. Referring to FIG. 29, pnp type parasitic transistors 1411 and 1412 are connected to P + type impurity region 1.
212, N- well 1211 and P- type semiconductor substrate 1
001. Therefore, the circuit shown in FIG. 30 can be equivalently formed by the presence of these parasitic transistors 1411, 1412,.

FIG. 30 is an equivalent circuit diagram of a circuit constituted by parasitic transistors 1411, 1412,... Shown in FIG. As can be seen from FIG. 30, the cascaded parasitic transistors 1411, 1412,.
A small leak current ILEAK is amplified, and an excessive current In is caused. That is, assuming that the current amplification factor of each of the parasitic transistors 1411, 1412,... Is hfe, an excessive current In determined by the following equation flows.

I1 = (1 + hfe) .ILEAK In = (1 + hfe) n.ILEAK Therefore, in order to prevent an excessive current In from flowing in the high voltage generating circuit, a structure shown in FIG. 31 is proposed.

FIG. 31 is a sectional view showing another structure of the high voltage generating circuit used in the flash memory according to the sixth embodiment. As shown in FIG. 31, a triple well structure is applied to a high voltage generation circuit. As a result, FIG.
Parasitic transistors 1411, 141 as shown in FIG.
Are prevented from being present, and a stable boosting operation can be performed.

(G) Negative voltage generation circuit (FIGS. 32 and 3)
3) FIG. 32A shows an equivalent circuit of the negative voltage generating circuit. The negative voltage generation circuit includes a plurality of diodes D230 and a plurality of capacitances C230. Capacitance C2
30 is supplied with two-phase clock signals φ and / φ. Thereby, a charge pump is configured.

Each diode D230 is usually constituted by a P-channel transistor as shown in FIG. The back gate of the P-channel transistor is grounded.

However, when power supply voltage Vcc is low (for example, 3 V), it becomes difficult to obtain a low negative voltage due to the back gate effect.

In this embodiment, a triple well structure shown in FIG. 33 is used. P- type semiconductor substrate 10
01, an N-well 1231 is formed.
A plurality of P- wells 1232 are formed in
N + type impurity region 1233 and P
+ Type impurity region 1234 is formed. These N + -type impurity regions 1233 and P + -type impurity regions 1234 constitute a diode.

According to this configuration, since each diode has no back gate, the back gate effect does not occur. Further, as shown in FIG. 23, since the memory cells are also formed in the N- well, the number of manufacturing steps does not increase.

(7) Seventh Embodiment (FIGS. 34 and 35) FIG. 34 is a circuit diagram showing a detailed configuration of a memory array of a flash memory and a portion related thereto according to a seventh embodiment. The overall configuration of the flash memory according to the embodiment of FIG. 7 is the same as the configuration shown in FIG.

The seventh embodiment is different from the sixth embodiment in that capacitances C0 and C1 are connected to main bit lines MB0 and MB1 via transfer gate transistors TG0 and TG1, respectively. Well potential VB is applied to capacitances C0 and C1. A control signal CG1 is supplied from the control circuit 1130 to the transfer gate transistors TG0 and TG1. The configuration of other parts is the same as the configuration shown in FIG.

Assuming that the programming time for one memory cell is, for example, 1 ms, a 2-bit configuration as shown in FIG. 34 requires 2 ms for programming. Actually, since the number of memory cells connected to one word line is several hundred to several thousand, rewriting data takes an enormous amount of time. By providing a data latch for each main bit line, memory cells connected to a plurality of bit lines may be simultaneously programmed. However, layout becomes difficult.

Therefore, as shown in the seventh embodiment, capacitances C0 and C1 are provided.

At the time of programming, transfer gate transistors TG0 and TG1 turn on in response to control signal CG1. In addition, Y decoder 1040 switches Y gate transistors YG0 and YG1 at high speed, for example, at a period of several tens of microseconds in response to the Y address signal. At this time, data is sequentially applied to write circuit 1080 in accordance with the Y address signal. Thereby, main bit lines MB0, MB0,
The capacitances C0 and C1 are charged according to the data via MB1. This operation is repeated for 1 ms.

Generally, the current required for tunneling electrons from the floating gate is several nanoamps or less, so that the current stored in the capacitances C0 and C1 can supply the current required for tunneling.

As shown in FIG. 35, for example, when the Y gate transistors YG0 and YG1 are switched every 250 μsec, the main bit line MB0 is set at 250 μsec to 5
No program voltage is applied for a period of 00 μs and for a period of 750 μs to 1 ms. However, during these periods,
The voltage of the main bit line MB0 is held by the electric charge stored in the main bit line MB0 and the capacitance C0. Therefore, the time required to program the memory cells connected to main bit lines MB0 and MB1 is 1 ms.

Here, the amount of voltage decrease ΔV during a period in which no program voltage is applied to main bit line MB0 is determined by the value of capacitance C0 and the switching frequency of the Y gate transistor. As the value of the capacitance C0 is larger or the switching frequency is larger, the decrease in the program voltage is suppressed, and the programming is performed stably and at a high speed.

When the capacitances C0 and C1 are formed by MOS capacitors, it is preferable to connect the main bit lines MB0 and MB1 to the gates. If the main bit lines MB0, MB
If 1 is connected to the diffusion layer of the MOS capacitor, the charged program voltage may be discharged in a short time due to junction leakage or the like at a high temperature, for example.

The voltage application conditions at the time of programming and erasing are the same as in the sixth embodiment. The sector batch erasing operation and the programming operation are the same as in the sixth embodiment.

(8) Eighth Embodiment (FIGS. 36 to 51) (a) Overall Configuration of Flash Memory (FIGS. 36 and 3)
7) FIG. 36 is a block diagram showing the overall configuration of the flash memory according to the eighth embodiment. FIG. 37 is a circuit diagram showing a detailed configuration of the memory array and its related parts.

The flash memory of FIG. 36 differs from the flash memory of the sixth embodiment shown in FIG. 18 in the following points. A source decoder 1270 is provided instead of the source control circuit 1110. Further, the negative voltage generation circuit 123
0 applies a negative voltage to the select gate decoder 1260 and the source decoder 1270 instead of the Y decoder 1040.

As shown in FIG. 37, the sources of memory cells M00, M01, M10, M11 in sector SE1 are connected to source line SL1, and the sources of memory cells M02, M03, M12, M13 in sector SE2 are source. Line S
L2. The output terminal of source decoder 1270 is connected to source lines SL1 and SL2.

At the time of erasing, the source of each memory cell in the selected sector is in a floating state. If there is a leak path in the source, the source potential rises,
The electric field between the source and the floating gate is reduced.

To stabilize the source potential at the time of erasing, capacitances C11 and C12 may be connected to source lines SL1 and SL2 via transfer gate transistors TG11 and TG12, respectively.

The well potential VB is applied to the capacitances C11 and C12. The control signal CG2 is supplied from the control circuit 1130 to the transfer gate transistors TG11 and TG12.

At the time of erasing, transfer gate transistors TG11 and TG12 turn on in response to control signal CG2. Thus, the change in the source potential is reduced.

Since the program operation and the read operation in the eighth embodiment are the same as those in the sixth embodiment, the collective sector erase operation will be described below.

In the sixth embodiment, at the time of erasing, a voltage is applied as shown in FIG. However, if erasing is performed in a very short time (for example, several milliseconds), the formation of the inversion layer below the memory cell cannot follow the voltage application, and a depletion layer is formed below the memory cell. .

In such a case, it is preferable that the conditions for applying a voltage to the memory cells in the selected sector and the conditions for applying a voltage to the memory cells in the non-selected sector be different.

The voltage application condition is as follows: floating gate 1
The case where there is no gate bird's beak in the insulating film 1004 (tunnel insulating film) under 005 differs from the case where there is a gate bird's beak. Here, the gate bird's beak refers to a state in which the periphery of the lower surface of the floating gate 1005 is eroded by the tunnel insulating film below the floating gate 1005 during manufacturing, as indicated by gb in FIG. As a result, the thickness of the tunnel insulating film is increased below the periphery of the floating gate 1005.

First, the voltage application conditions when there is no or small gate bird's beak will be described, and then the voltage application conditions when the gate bird's beak is large will be described.

(B) When there is no gate bird's beak (FIGS. 38 to 42) (i) Erasure of memory cell (FIGS. 38 and 39) In FIG. 38, Cg is a value between control gate 1006 and floating gate 1005. The capacitance, Cf is the capacitance between the floating gate 1005 and the P− well 1008, Cb is the capacitance due to the depletion layer, and Cd is the drain 10
02 and the floating gate 1005, C
s indicates the capacitance between the source 1003 and the floating gate 1005. Ct indicates a combined capacitance of the capacitance Cf and the capacitance Cb.

Now, a positive voltage VCG is applied to the control gate 1006, and a negative voltage VB is applied to the P− well 1008. In this case, the drain 1002 and the source 10
Since 03 is in a floating state, the drain voltage Vd and the source voltage Vs become substantially the negative voltage VB. Assuming that the potential of the floating gate 1005 at this time is VFG and the initial accumulated charge is 0, the following equation is established from the charge conservation law.

(VCG−VFG) · Cg = (VFG−VB) · (Cs + Ct + Cd) (1) The following expression is obtained by expanding expression (1).

VFG = {VCG · Cg + (Cs + Ct + Cd) · VB} / (Cs + Ct + Cd + Cg) (2) Further, when Expression (2) is expanded, the following expression is obtained.

VFG = {VCG + (Cs + Ct + Cd) · VB / Cg} / {(Cs + Ct + Cd) / Cg + 1} (3) Here, Cs and Cd can be ignored since they are small compared to Cg. Therefore, equation (3) becomes as follows.

VFG = (VCG + Ct · VB / Cg) / (Ct / Cg + 1) (4) When the depletion layer spreads, the capacitance Cb decreases and the capacitance Ct also decreases. Therefore, the floating gate 100
5 is equal to the potential V of the control gate 1006.
Approach CG. However, the potentials of the drain 1002 and the source 1003 in the floating state are almost the same as the potential of the P − well 1008.

In this case, floating gate 1005
And the electric field E between the drain 1002 and the source 1003 is expressed by the following equation.

E = (VFG−VB) / TOX (5) where VFG is the potential of the floating gate 1005, VB is the potential of the P − well 1008, and TOX is the thickness of the tunnel insulating film.

The potential VF of the floating gate 1005
Since G increases, the electric field between the floating gate 1005 and the drain 1002 and the electric field between the floating gate 1005 and the source 1003 increase. Therefore, the drain 1002 or the source 100
The tunnel effect at the end of No. 3 is improved. Therefore, the erasing efficiency is improved.

[0319] Such an effect is preferable in a selected sector, but not preferable in a non-selected sector.

Therefore, the source 1003 of the memory cell in the selected sector is set to the floating state as shown in FIG. 39A, and the source 1003 of the memory cell in the non-selected sector is set to the state shown in FIG. As shown in (b),
The same potential as the potential of the P-well 1008 or a potential higher than the potential of the P-well 1008 is supplied.

Thus, in a memory cell in a non-selected sector, a channel ch is formed between the source 1003 and the drain 1002, and the potential of the channel ch is supplied from the source 1003. Therefore, the potential of the floating gate 1005 becomes
This is reduced by capacitive coupling between the channel 5 and the channel ch, and the electric field applied to the tunnel insulating film is reduced. As a result, the data of the memory cells in the non-selected sectors is stably protected.

(Ii) Sector Batch Erase Operation of Flash Memory (FIG. 40) Referring to FIG. 40, the collective sector erase operation of the flash memory when there is no gate bird's beak will be described. Here, it is assumed that the sector SE1 is collectively erased.

The word lines WL0 and WL1 in the sector SE1
Is applied to the word line WL in the sector SE2.
2, 0V is applied to WL3. Further, 0 V is applied to the select gate lines SGL1 and SGL2. -5 V is applied to the P- well 1008. The source line SL1 is set in a floating state, and -5V is applied to the source line SL2.
Is applied.

[0324] Thereby, the memory cells in sector SE1 can be erased collectively while the data in the memory cells in sector SE2 are stably protected.

(Iii) Source Decoder (FIGS. 41 and 42) FIG. 41 shows a structure of a source decoder 1270 used when there is no gate bird's beak. Also,
FIG. 42 is a diagram showing voltages of respective parts of the source decoder 1270 of FIG. FIG. 41 shows only a portion related to source line SL1. The configuration of the portion related to source line SL2 is the same as the configuration shown in FIG. 41 except that input signals applied to input terminals AD0, AD1, and AD2 are different.

P-channel transistors P1, P2, P3
Are connected to the terminal VDD, and the back gates of the N-channel transistors N1, N2, N3, N4 are connected to the terminal VBB.

At the time of erasing, 0 V is applied to the terminal VDD, and the same negative voltage (-5 V) as the well potential is applied to the terminal VBB. Further, a negative voltage (-5 V) equal to the well potential or a negative voltage higher than the well potential is applied to the terminal VBB2.

When sector SE1 is selected, input terminal AD
An input signal of 0 V is applied to all of 0 to AD2. Therefore, the transistor N4 turns off and the source line SL1
Is in a floating state. When the sector SE1 is not selected, an input signal of −5 V is applied to any of the input terminals AD0 to AD2. Therefore, the transistor N4 is turned on, and −5 V is applied to the source line SL1.

At the time of programming and reading, the terminal VD
The power supply voltage Vcc (5 V) is applied to D, 0 V is applied to the terminal VBB, and 0 V is applied to the terminal VBB2.

At the time of programming, the input terminals AD0 to AD
2 are all provided with a 5V input signal. Therefore, the transistor N4 is turned off, and the source line SL1 enters a floating state.

At the time of reading, an input signal of 0 V is applied to all of the input terminals AD0 to AD2. Therefore, the transistor N4 is turned on, and 0 V is applied to the source line SL1.

(C) When there is a gate bird's beak (FIGS. 43 to 47) (i) Erasure of memory cell (FIGS. 43 and 44) As shown in FIG. In some cases, the diffusion layer forming the source 1003 does not extend below the thin tunnel insulating film. In this case, no tunnel effect occurs between the drain 1002 and the floating gate 1005 and between the source 1003 and the floating gate 1005.
Therefore, erasing is performed by the tunnel effect between P- well 1008 and floating gate 1005.

The electric field E between the floating gate 1005 and the P- well 1008 is expressed by the following equation.

E = (VFG−VB) / (TOX + Id) (6) where VFG is the potential of the floating gate 1005, VB is the potential of the P − well 1008, TOX is the thickness of the tunnel insulating film, and Id is depletion. Indicates the thickness of the layer. When the drain 1002 and the source 1003 are in a floating state as described above, the electric field is weakened by the depletion layer, and the erasing efficiency is reduced.

In such a case, the source 1003 of the memory cell in the selected sector has the same negative voltage (−5) as the potential of the P − well 1008 as shown in FIG.
V), and the source 1003 of the memory cell in the non-selected sector is brought into a floating state as shown in FIG.

As a result, in the memory cell in the selected sector, a channel ch is formed between the source 1003 and the drain 1002, and the potential of the channel ch is supplied from the source 1003. Therefore, channel ch
When a sufficient electric field is applied to the tunnel insulating film between the floating gate 1005 and the floating gate 1005, a tunnel phenomenon occurs between the channel ch and the floating gate 1005. As a result, the erasing efficiency of the memory cells in the selected sector is improved.

On the other hand, since the source 1003 of the memory cell in the unselected sector is in a floating state,
No channel is formed between the source 1003 and the drain 1002, and a depletion layer is formed below the memory cell.
Therefore, the electric field between floating gate 1005 and P − well 1008 is reduced.

(Ii) Batch Sector Erase Operation of Flash Memory (FIG. 45) The collective sector erase operation of the flash memory when there is a gate bird's beak will be described with reference to FIG. Here, it is assumed that the sector SE1 is collectively erased.

The word lines WL0, WL1 in the sector SE1
Is applied to the word line WL in the sector SE2.
2, 0V is applied to WL3. Further, 0 V is applied to the select gate lines SGL1 and SGL2. -5 V is applied to the P- well 1008. -5 V is applied to the source line SL1, and the source line SL2 is set in a floating state.

As a result, it is possible to collectively erase the memory cells in sector SE1 while stably protecting the data in the memory cells in sector SE2.

(Iii) Source Decoder (FIGS. 46 and 47) FIG. 46 is a diagram showing a configuration of a source decoder 1270 used when there is a gate bird's beak. FIG.
FIG. 47 is a diagram showing voltages of respective parts of the source decoder 1270 of FIG. FIG. 48 shows only a portion related to source line SL1. The configuration of a portion related to source line SL2 is the same as the configuration shown in FIG. 46 except that input signals applied to input terminals AD0, AD1, and AD2 are different.

P-channel transistors P1, P2, P
3, the back gates of P4 are connected to terminal VDD, and the back gates of N-channel transistors N1, N2, N3, N5, N6 are connected to terminal VBB.

At the time of erasing, 0 V is applied to the terminal VDD, and the same negative voltage (−5 V) as the well potential is applied to the terminal VBB.
Is applied.

When sector SE1 is selected, input terminal AD
An input signal of 0 V is applied to all of 0 to AD2. Therefore, the transistor N6 turns on and the source line SL1
Is applied with -5V. When the sector SE1 is not selected, an input signal of −5 V is applied to any of the input terminals AD0 to AD2. Therefore, the transistor N6 turns off, and the source line SL1 enters a floating state.

At the time of programming and reading, the terminal VD
The power supply voltage Vcc (5 V) is applied to D, and 0 V is applied to the terminal VBB.

In programming, input terminals AD0-AD
2 are all provided with an input signal of 0V. Therefore, the transistor N6 turns off and the source line SL1 enters a floating state.

At the time of reading, a 5 V input signal is applied to all input terminals AD0 to AD2. Therefore, the transistor N6 is turned on, and 0 V is applied to the source line SL1.

(D) When the well potential is low (FIG.
(FIG. 51) (i) Erasure of Memory Cell (FIG. 48) In the above description, it was assumed that the voltage applied to the P- well at the time of erasure was -5V. If the well potential is further lowered to further improve the erase efficiency, disturb in unselected sectors becomes a problem.

For example, when the gate bird's beak is large, as shown in FIG. 46, the negative voltage (−5) of terminal VBB equal to the well potential is applied to the source line of the selected sector.
V) is applied, and the source lines of the non-selected sectors enter a floating state.

However, when the well potential lowers, the electric field between the floating gate and the P- well increases in the memory cells in the non-selected sectors. As a result, the data of the memory cells in the non-selected sectors cannot be reliably protected.

Accordingly, a voltage higher than the well potential is applied to the source lines of the non-selected sectors. For example, FIG.
As shown in the figure, the potential of the P- well 1008 is set to -10V. In this case, as shown in FIG. 48A, the same -10 V as the well potential is applied to the source 1003 of the memory cell in the selected sector, and the source 1003 of the memory cell in the non-selected sector is applied. Applies -5V.

Thus, the potential difference between the channel and control gate 1006 can be set to 5 V in the memory cells in the non-selected sectors.

(Ii) Batch Sector Erase Operation of Flash Memory (FIG. 49) The sector collective erase operation of the flash memory when the well potential is low will be described with reference to FIG. Here, it is assumed that the sector SE1 is collectively erased.

The word lines WL0 and WL1 in the sector SE1
Is applied to the word line WL in the sector SE2.
2, 0V is applied to WL3. Further, 0 V is applied to the select gate lines SGL1 and SGL2. -10 V is applied to P-well 1008. Source line SL1
−10 V is applied to the source line SL2, and −5 V is applied to the source line SL2.

As a result, the memory cells in sector SE1 can be collectively erased while the data in the memory cells in sector SE2 are protected stably.

(Iii) Source Decoder (FIGS. 50 and 51) FIG. 50 shows a structure of a source decoder 1270 used when the well potential is low. FIG.
FIG. 9 is a diagram illustrating voltages of respective units of a source decoder 1270 of 0. FIG. 50 shows only a portion related to source line SL1. The configuration of a portion related to source line SL2 is the same as the configuration shown in FIG. 50 except that input signals applied to input terminals AD0, AD1, and AD2 are different.

P-channel transistors P1, P2, P
3 and P5 are connected to the terminal VDD, and the back gates of the N-channel transistors N1, N2 and N3 are connected to the terminal VBB.

At the time of erasing, −5 V is applied to the terminal VDD, and the same negative voltage (−10 V) as the well potential is applied to the terminal VBB.
Is applied. Also, 0 V is applied to the control line CSL,
-10 V is applied to the control line DSL.

When sector SE1 is selected, input terminal AD
An input signal of 0 V is applied to all of 0 to AD2. Therefore, -10 V is applied to source line SL1. When the sector SE1 is not selected, an input signal of −10 V is applied to any of the input terminals AD0 to AD2. Therefore, -5 V is applied to source line SL1. Note that the potential of the source line at the time of non-selection can be freely selected by changing the potential applied to the terminal VDD at the time of erasing.

In programming and reading, terminal VD
The power supply voltage Vcc (5 V) is applied to D, and 0 V is applied to the terminal VBB.

At the time of programming, 0 V is applied to control line CSL, and 5 V is applied to control line DSL. Therefore, source line SL1 is in a floating state.

In reading, 5 V is applied to control line CSL, and 0 V is applied to control line DSL. Further, an input signal of 5 V is applied to all of the input terminals AD0 to AD2. Therefore, 0 V is applied to source line SL1.

(9) Ninth Embodiment (FIGS. 52 to 56) (a) Overall Configuration of Flash Memory (FIGS. 52 and 5)
3) FIG. 52 is a block diagram showing the overall configuration of the flash memory according to the ninth embodiment. FIG. 53 is a circuit diagram showing a detailed configuration of a memory array and a portion related thereto.

The flash memory of FIG. 52 differs from the flash memory of the eighth embodiment shown in FIG. 36 in the following point. Source switches 1281 and 1282 are provided instead of the source decoder 1270. Negative voltage generating circuit 1230 applies a negative voltage to select gate decoder 1260.

As shown in FIG. 53, the source switch 12
81 receives the potential on the select gate line SGL1 and controls the potential of the source line SL1. Source switch 1282
Receives the potential on the select gate line SGL2 and controls the potential of the source line SL2. Source switch 1281,1
282 is controlled by a control signal CG3 from the control circuit 1130.

Since the program operation and read operation in the ninth embodiment are similar to those in the sixth embodiment, the erase operation will be described below.

(B) Sector Batch Erase Operation of Flash Memory (FIG. 54) The sector batch erase operation of the flash memory according to the ninth embodiment will be described with reference to FIG. Here, it is assumed that the batch erasing of the sector SE1 is performed.

As described in the eighth embodiment, in order to further improve the erasing efficiency, the P− well 1008 has −10
V is applied. Word lines WL0, W in sector SE1
10V is applied to L1, and 0V is applied to word lines WL2 and WL3 in sector SE2. Further, -10 V is applied to the select gate line SGL1, and -5 V is applied to the select gate line SGL2. -10 V is applied to the source line SL1 by the source switch 1281,
The source line SL2 is -5 V by the source switch 1282.
Is applied.

As a result, the sector SE1 can be efficiently erased in a batch without disturbing the sector SE2.

(C) Select Gate Decoder and Source Switch (FIGS. 55 and 56) FIG. 55 is a circuit diagram showing the configuration of the select gate decoder and source switch used in the flash memory of the ninth embodiment. FIG. 56 is a diagram showing voltages of respective portions of the select gate decoder and the source switch of FIG. FIG. 55 shows a select gate decoder 1260.
Only the portion related to select gate line SGL1 and source switch 1281 connected to source line SL1 are shown. The configuration of select gate decoder 1260 related to select gate line SGL2 and the configuration of source switch 1282 are similar to the configuration shown in FIG. 55 except that input signals applied to input terminals AD0, AD1, and AD2 are different. .

The back gates of P-channel transistors P21 to P25 are connected to terminal VDD, and the back gates of N-channel transistors N21 to N28 are connected to terminal VBB. The control signal CG3 shown in FIG.
Provided by SL, BSL.

At the time of erasing, 0 V is applied to the terminal VDD, and -10 V is applied to the terminal VBB. Terminal VBB2
To the terminal VSG, and -10 V to the terminal VSG. 0 V is applied to the control line ASL and the control line BS
-10 V is applied to L.

When sector SE1 is selected, input terminal AD
An input signal of 0 V is applied to all of 0 to AD2. Therefore, the transistors N25 and P25 are turned on, and the potential of the terminal VSG (−10 V) is applied to the select gate line SGL1.
Is given. Further, since the potential of the control line ASL is 0 V, the transistor N27 is turned on, and the potential (−10 V) of the terminal VSG is also applied to the source line SL1.

When sector SE1 is not selected, input terminal A
An input signal of -10 V is applied to any of D0 to AD2. Therefore, the transistor N26 is turned on, and the potential of the terminal VBB2 (−5 V) is applied to the select gate line SGL1.
Is given. Further, the potential (−5 V) of the terminal VBB2 is also applied to the source line SL1 via the transistor N27. Note that by changing the voltage applied to the terminal VBB2, the potential of the source line of a non-selected sector can be freely changed.

At the time of programming, power supply voltage Vcc (7 V) is applied to terminal VDD, and 0 V is applied to terminals VBB and VBB2.
V is applied. 7 V is applied to the terminal VSG, and 0 V is applied to the control lines ASL and BSL.

When sector SE1 is selected, transistors N25 and P25 are turned on, and the potential (7V) of terminal VSG is applied to select gate line SGL1. At this time, since the transistors N27 and N28 are off, the source line SL1 is in a floating state. When the sector SE1 is not selected, the transistor N26 is turned on, and the potential (0 V) of the terminal VBB2 is applied to the select gate line SGL1. Also at this time, since the transistors N27 and N28 are off, the source line SL1 is in a floating state.

At the time of reading, power supply voltage Vcc is applied to terminal VDD.
(5 V) is applied, and 0 V is applied to the terminals VBB and VBB2. 5 V is applied to the terminal VSG. Control line A
0 V is applied to SL, and 5 V is applied to the control line BSL.

When sector SE1 is selected, transistors N25 and P25 are turned on, and the potential (5V) of terminal VSG is applied to select gate line SGL1. At this time, since the transistor N28 is on, the source line SL1
Is grounded. When the sector SE1 is not selected, the transistor N26 is turned on, and the potential (0 V) of the terminal VBB2 is applied to the select gate line SGL1. Also at this time, since the transistor N28 is on, the source line SL1
Is grounded.

As described above, at the time of erasing, the well potential is applied to the source line of the selected sector and the source line of the non-selected sector is lower than the well potential at the time of erasing without using the source decoder 1270 shown in FIG. A high potential can be applied.

(10) Tenth Embodiment (FIG. 57) A feature of the flash memory according to the tenth embodiment is that a verify operation is not required at the time of programming.
The configuration of the flash memory of the tenth embodiment is the same as the configuration of the flash memory of any of the sixth to ninth embodiments. The batch erase operation and the read operation are also performed in the sixth to
This is the same as the ninth embodiment.

The program operation of the flash memory according to the tenth embodiment will be described with reference to the flowchart of FIG.

First, the potential of the selected word line is set to the verify level, and a high voltage is applied to the selected select gate line (step S31). This turns on the selected select gate transistor. Then, the source line is set in a floating state (step S
32). The main bit line corresponding to data "0" is precharged to 5V, and the main bit line corresponding to data "1" is set to 0.
V (step S33).

After that, the source line is grounded for a certain period (step S34). If the threshold voltage of the memory cell in the selected sector is higher than the verify level,
The potential of the main bit line corresponding to data "0" is maintained at the above precharge level. If the threshold voltage of the memory cell in the selected sector is lower than the verify level, the main bit line corresponding to data "0" is discharged through the memory cell.

After that, the source line is set in a floating state (step S35), and a negative voltage is applied to the selected word line (step S36). Thereby, only the memory cells connected to the main bit line precharged to 5 V are programmed.

After the above program cycle is repeated a specified number of times (step S37), the X address is incremented, and the above program cycle is repeated for the next word line (steps S38 and S39). When the above program cycle is repeated for all the word lines in the selected sector, the program operation ends (step S38).

According to the above-described method, after the program voltage is applied to the main bit line, the program operation can be performed at high speed without performing the verify operation one by one.

In order to stably maintain the precharge level, as shown in the second embodiment, a capacitance is connected to a main bit line via a transfer gate transistor, and these transfer gate transistors are turned on during programming. You may.

The above method can be similarly applied to flash memories of other embodiments.

(11) Eleventh Embodiment (FIG. 58) A feature of the flash memory according to the eleventh embodiment is that a verify operation is not required at the time of programming.
The configuration of the flash memory of the eleventh embodiment is the same as the configuration of the flash memory of any of the sixth to ninth embodiments. The batch erase operation and the read operation are also performed in the sixth to
This is the same as the ninth embodiment.

A program operation of the flash memory according to the eleventh embodiment will be described with reference to FIG.

First, the potential of the selected word line is set to the verify level, and a high voltage is applied to the selected select gate line (step S41). This turns on the selected select gate transistor. Then, the source line is set in a floating state (step S
42). The main bit line corresponding to data "0" is precharged to 5V, and the main bit line corresponding to data "1" is set to 0.
V (step S43).

After that, the source line is grounded for a certain period (step S44). If the threshold voltage of the memory cell in the selected sector is higher than the verify level,
The potential of the main bit line corresponding to data "0" is maintained at the above precharge level. If the threshold voltage of the memory cell in the selected sector is lower than the verify level, the main bit line corresponding to data "0" is discharged through the memory cell.

Thereafter, the potentials of all main bit lines are set to 0V.
If not (step S45), the source line is set in a floating state (step S46), and a negative voltage is applied to the selected word line (step S47). Thereby, only the memory cells connected to the main bit line precharged to 5 V are programmed.

After the above program cycle is repeated until the potentials of all bit lines become 0 V (step S4).
5) The X address is incremented, and the above program cycle is repeated for the next word line (step S).
48, S49). When the program cycle described above is performed for all the word lines in the selected sector, the program operation ends (step S48).

According to the above method, after application of the program voltage to the main bit line, the program operation can be performed at high speed without performing the verify operation one by one, and the program operation can be automatically terminated.

Note that the above method can be similarly applied to flash memories of other embodiments.

(12) Twelfth embodiment (FIGS. 59 to 6)
4) FIG. 59 is a block diagram showing the overall configuration of the flash memory according to the twelfth embodiment. In the flash memory shown in FIG. 59, the program operation and the erase operation are performed in a manner similar to that of the flash memory shown in FIG.

Referring to FIG. 59, this flash memory includes predecoders 1451 to 1454, a global decoder 1455, and a select gate decoder 145.
6, well potential control circuits 1457 and 1458,
Source line drivers 1459 and 1460, and memory cell arrays 1461 and 1462 divided into sectors
And local decoders 1463 and 1464.

FIG. 60 is a circuit diagram of the memory cell array shown in FIG. 59 and its peripheral circuits. In FIG. 60, global decoder 1455 and local decoder 1
464, memory cell array, source line driver 1460
And a detailed circuit for the select gate decoder 1456 is shown. In FIG. 60, “2AL” indicates a wiring formed by the second aluminum wiring layer, and “2P”
"OL" indicates a wiring formed by the second polysilicon layer.

Table 1 below shows voltages applied to the circuits shown in FIGS. 59 and 60 in the erase operation, the program operation, and the read operation.

[0401]

[Table 1]

In the twelfth embodiment, in addition to the various advantages already described, the following additional advantages can be obtained.

FIG. 61 shows the word line WL0 shown in FIG.
FIG. 13 is a layout view on a semiconductor substrate showing a connection mode between 0 to WL07 and WL10 to WL17 and output lines WL0 to WL7 of a local decoder 1464. Referring to FIG. 61, each word line WL00 to WL00
07 and WL10 to WL17 are formed by the second polysilicon layer. On the other hand, the local decoder 146
Each output line 4 is formed by a first aluminum wiring layer.
The connection between each word line and the corresponding output signal line is made via a through hole. It is pointed out that the connection mode shown in FIG. 61 is also shown in the circuit diagram shown in FIG.

By using the connection modes shown in FIGS. 60 and 61, the connection between the word line and the output line of the local decoder is simplified, so that the wiring density is reduced, and as a result, a high degree of integration is obtained. Can be

FIG. 62 is a sectional structural view showing the separation between the two memory cells 1491 and 1492 shown in FIG. Memory cells 1491 and 14 shown in FIG.
Reference numeral 92 is located at a position closest to the other sector in each sector. These transistors 149
In order to separate 1 and 1492, as shown in FIG. 62, an isolation oxide film 1490 is formed in the semiconductor substrate.
Width Wc of isolation oxide film 1490 required to isolate two adjacent transistors 1491 and 1492
Is smaller than the case where transistors 1495 and 1496 for the field shield as shown in FIG. 63 are used. That is, in the example shown in FIG. 63, transistors 1495 and 1496 for isolation are used.
However, the use of the isolation oxide film 1490 makes it possible to separate the two adjacent transistors 1491 and 1492 with a smaller width Wc. Thereby, a higher degree of integration can be obtained.

FIG. 64 is a circuit diagram of a word line voltage control circuit and a predecoder used in the twelfth embodiment. Word line voltage control circuit 1470 shown in FIG.
Are omitted in FIG. 59 for simplicity.

Referring to FIG. 64, word line voltage control circuit 1470 includes VPP generator 1471 and VBB generator 1
472, a voltage detector 1473, and an inverter 1474.
, VPP switching circuit 1475, VPP switching circuit 1476, and CMOS transmission gates 1477 and 1478.

The predecoder 1452 is a PMOS transistor 1 constituting a CMOS transmission gate.
481 and an NMOS transistor 1482.

The word line voltage control circuit 14 shown in FIG.
70 and the predecoder 1452,
The voltages shown in Table 1 above are applied to execute the program operation and the read operation.

Generally, an external voltage VEW for testing is applied to check the distribution of threshold voltages of memory cells of a flash memory. As shown in FIG. 64, in the test mode operation, external voltage VEW is applied to CMOS transmission gate 1478 in word line voltage control circuit 1470 and CMOS transmission gate 1478 in predecoder 1452.
MOS transmission gate (transistor 148
1 and 1482) to the word lines WL00 to WL17 shown in FIG.
Since the voltage path of the external voltage VEW is constituted only by the CMOS circuit, no voltage loss occurs due to the threshold voltage of the MOS transistor. In other words, the external voltage VEW that changes in a wider range can be applied to the word line without changing the voltage level, and a desired test can be performed.

(13) Thirteenth Embodiment FIG. 65 is a schematic diagram of a thirteenth embodiment of the nonvolatile semiconductor memory device according to the present invention. The semiconductor substrate 80 is divided into a memory transistor region and a peripheral region. In the memory transistor area, the memory transistors 87a, 87
7b, 87c and 87d are formed at intervals. In the main surface of the semiconductor substrate 80, in the memory transistor region, n-type source regions 84a and 84b and n-type drain regions 85a and 85b are formed with a space therebetween. The source region 84a becomes a source region of the memory transistors 87a and 87b, and the source region 84b becomes a source region of the memory transistors 87c and 87d.

The drain region 85a becomes the drain region of the memory transistors 87b and 87c, and the drain region 85b becomes the drain region of the memory transistor 87d. Reference numeral 88 indicates a control gate, and 89 indicates a floating gate.

In the main surface of semiconductor substrate 80, n-type source / drain regions 83 are provided in the memory transistor region.
A select gate transistor 86 having a and 83b is formed. The source / drain region 83b also functions as a drain region of the memory transistor 87a.

The memory transistors 87a, 87b, 87
Sub bit lines 9 made of polycrystalline silicon are provided on c and 87d.
0 is formed. Sub bit line 90 is connected to source / drain region 83b. Branch line 91a branched from sub-bit line 90 is connected to drain region 85a,
Branch line 91b is connected to drain region 85b.
A main bit line 92 made of aluminum is formed on sub bit line 90. Main bit line 92 is connected to source / drain region 83a.

[0415] A p-well region 82 is formed in the semiconductor substrate 80 so as to surround the memory transistor region.
N well region 81 is formed to surround p well region 82. A MOS transistor 93 is formed in the peripheral region. A more detailed description of the nonvolatile semiconductor memory device according to the present invention will be given using a fourteenth embodiment.

(14) Fourteenth Embodiment FIG. 66A is a sectional view of a part of a memory transistor portion of a nonvolatile semiconductor memory device according to a fourteenth embodiment of the present invention. A p-well region 2 is formed in the p-type silicon substrate 201.
10 are formed at intervals. p-well region 210
On the top, memory transistors 250 to 257, 261,
262, select gate transistors 259 and 260 are formed. In the p-well region 210, an n-type source region 223 and an n-type drain region 224 of each memory transistor are formed. Reference numeral 249 denotes an n-type impurity region.

Each memory transistor and select gate transistor are covered with a silicon oxide film 247. The source region 223 is covered with a silicon oxide film 247. On the other hand, the drain region 224 and the impurity region 249 are not covered with the silicon oxide film. Each memory transistor has a floating gate 219 and a control gate 220.

The drain regions 224 of the memory transistors 250 to 257 are electrically connected by one sub-bit line 227a. Memory transistor 261,
The drain region 224 of one of the sub bit lines 227
b are electrically connected. Impurity region 249
Are electrically connected to the connection conductive layer 248. Also,
On the field oxide film 206, a dummy gate transistor 258 having a dummy gate 242 is formed. Details of the dummy gate transistor will be described later.

An interlayer insulating film 245 is formed on sub-bit lines 227a and 227b, and a main bit line 233 is formed on interlayer insulating film 245. Main bit line 233
Are electrically connected to the connection conductive layer 248. An interlayer insulating film 246 is formed on main bit line 233, and an aluminum wiring 238 is formed on interlayer insulating film 246 with a space therebetween.

On the other hand, n-well region 207 is formed in silicon substrate 201 so as to cover p-well region 210.

FIG. 66 (b) is an equivalent circuit diagram of the memory transistor shown in FIG. 66 (a). Each drain region of the eight memory transistors is connected to a sub-bit line, and a source region is connected to a source line. The selection gate 1 conducts / cuts off the main bit line and the sub bit line. Word lines 1 to 8 are control gates.

FIG. 67 is a sectional structural view of a memory transistor according to a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention. A gate oxide film 213 is formed between p well region 210 and floating gate 219,
Floating gate 219 and control gate 22
Between zero, an ONO film 215 is formed.

Next, the operation of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIGS. 66 (b) and 67. First, the erasing operation will be described. In the NOR type and NAND type described in the conventional example, the erased state is obtained by extracting electrons. In the fourteenth embodiment, the erased state is obtained by injecting electrons. That is, when the memory transistors 250 to 257 are to be erased collectively, the main bit line 233 is kept in a floating state and the select gate transistor 259 is turned off.
As a result, the sub bit line 227a is also in a floating state. Then, the source line and the p-well region 210a are
A voltage of about 10 V is applied. Then, a voltage of about 10 V is applied to the word lines 1 to 8. As a result, as shown in FIG. 67, electrons in the channel region are injected into the floating gate 219 by the channel FN phenomenon, which is one of the tunnel effects. This is the erased state "1", and the value of Vth is about 6V.

Next, the write operation will be described. For example, when the write state of the memory transistor 257 is “0”, the select gate transistor 259 is turned on, and a voltage of about 5 V is applied to the main bit line 233. As a result, the voltage of the sub bit line 227a also becomes about 5V. And p
The well region 210a is kept at the ground potential, and the source line is
Set to EN. Further, a voltage of about -10 V is applied to the word line 8, and the word lines 1 to 7 are kept at the ground potential.
As a result, as shown in FIG. 67, electrons accumulated in the floating gate 219 of the memory transistor 257 are extracted to the drain region 224 by the drain FN phenomenon, which is one of the tunnel effects. As a result, the memory transistor 257 is in the write state “0”, and the value of Vth is about 1 V at this time.

Next, the read operation will be described. For example, when reading the memory transistor 257, the select gate transistor 259 is turned on and a voltage of about 1 V is applied to the main bit line 233. Then, the source line and the p-well region 210a are kept at the ground potential. And 3-5 on the word line 8
A voltage of about V is applied to set the word lines 1 to 7 to the ground potential. At this time, when the memory transistor 257 is in the erased state “1”, no channel is formed and no current flows through the bit line. On the other hand, when the write state is "0", a channel is formed and a current flows through the bit line. Thus, a write state / erase state is determined.

In the fourteenth embodiment, the p well region 210
Is applied with a negative voltage. Since there is an n-well region 207 around the p-well region 210, even if a negative voltage is applied, the p-well region 210 and the n-well region 207 are in a reverse bias state, and a voltage is applied to the p-well region 210. Also, no voltage is applied to the peripheral circuit formation region.

In the erase operation, a negative voltage is applied to the p-well region and a positive voltage is applied to the word line, so that the value of the maximum voltage is reduced and the p-well region 210 and the control gate are reduced. The potential difference between 220 is relatively large, and it is possible to cause the channel FN effect.

As shown in FIG. 66A, a sub-bit line 227a is connected to each of the drain regions 224 of the memory transistors 250 to 257. For this reason, in the read operation, a large read current can be taken.
The reading operation can be performed at a higher speed as compared with the D-type.

Further, as shown in FIG. 67, since the writing operation uses drain FN, the writing operation can be performed with higher efficiency as compared with the case where channel hot electrons are used, thereby reducing power consumption. I can do it.

Next, the planar arrangement of the structure shown in FIG. 66A will be described. FIG. 68 is a plan view up to the state where the control gate 220 is formed. FIG.
The state cut along the line A shows the state up to the control gate 220 in FIG. Control gate 220, select gate 234, dummy gate 24
2. The source line 223a extends in the vertical direction. The source line 223a connects the source regions 223 shown in FIG. Field oxide films 206 and drain regions 224 are formed alternately. Note that select gate 2
The wiring layer on 34 (corresponding to the control gate of the memory transistor) is not shown.

FIG. 69 is different from FIG.
a and 227b are formed. Source line 2
23a is electrically connected to the wiring layer 241. The wiring layer 241 is formed simultaneously with the sub-bit lines 227a and 227b.

The selection gate 234 is connected to the poly pad 23
6 are electrically connected. The poly pad 236 is also formed simultaneously with the sub-bit lines 227a and 227b. The contacts between the sub-bit lines 227a and 227b and the drain region 224 are not shown. Further, the contact between the connection conductive layer 248 and the impurity region 249 is not shown.

FIG. 70 shows a state where main bit line 233 is formed on FIG. The main bit line 233 is electrically connected to the connection conductive layer 248. Aluminum electrode 23
7a, 237b, 237c and 237d are the main bit lines 23
3 and formed at the same time. Aluminum electrode 237a
Is electrically connected to one poly pad 236, and the aluminum electrode 237b is electrically connected to the other poly pad 236. Aluminum electrode 237c is electrically connected to wiring layer 241. The aluminum electrode 237d is electrically connected to the dummy gate 242.

FIG. 71 shows an aluminum wiring 238a over FIG.
238 g is formed. Aluminum wiring 2
38a is electrically connected to the aluminum electrode 237a, aluminum wiring 238b is electrically connected to the aluminum electrode 237b, aluminum wiring 238e is electrically connected to the aluminum electrode 237c, and aluminum wiring 238f and 238g are connected to the aluminum electrode 237b. It is electrically connected.

Next, the entire structure and operation of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described.
A seventh example will be described with reference to Table 2.

A memory cell matrix included in this nonvolatile semiconductor memory device is divided into a plurality of sectors as described below. Table 2 shows conditions for applying voltages to the memory cells (memory transistors) in the selected sector and the memory cells (memory transistors) in the non-selected sectors. In Table 2, Vd indicates a drain voltage, Vg indicates a control gate voltage, Vs indicates a source voltage, and Vbb indicates a well voltage.

[0437]

[Table 2]

<1> First Example (a) Overall Configuration of Nonvolatile Semiconductor Memory Device FIG. 72 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory device according to a first example.

A memory cell matrix 70 has a sector SE.
1, SE2. Memory cell matrix 70 includes select gates SG1 and SG2 corresponding to sectors SE1 and SE2, respectively. Memory cell matrix 70 is formed in P well region 71.

In the memory cell matrix 70, two main bit lines MB0 and MB1 are arranged. Main bit line MB
0 and MB1 are connected to the sense amplifier 52 and the write circuit 53 via Y gate transistors YG0 and YG1 in the Y gate 72, respectively.

[0441] Two sub-bit lines SB01 and SB02 are provided corresponding to main bit line MB0, and main bit line MB1 is provided.
, Two sub-bit lines SB11 and SB12 are provided.

Word lines WL0 and WL1 are arranged to cross sub-bit lines SB01 and SB11, and word lines WL2 and WL2 are arranged to cross sub-bit lines SB02 and SB12.
WL3 is arranged.

Sub bit lines SB01, SB02, SB1
1, SB12 and the memory cells (memory transistors) M00 to M0 at the intersections of the word lines WL0 to WL3, respectively.
3, M10 to M13 are provided. The memory cells M00,
M01, M10, and M11 are included in sector S1, and memory cells M02, M03, M12, and M13 are included in sector SE2.

Each memory cell has its drain connected to a corresponding sub-bit line, its control gate connected to a corresponding word line, and its source connected to a source line SL.

The select gate SG1 includes select gate transistors SG01 and SG11, and the select gate SG2 includes select gate transistors SG02 and SG1.
2 inclusive. The sub-bit lines SB01 and SB02 are connected to the main bit line MB0 via select gate transistors SG01 and SG02, respectively.
B12 is a select gate transistor SG1
1 and SG12 to the main bit line MB1.

Address buffer 58 receives an externally applied address signal, supplies an X address signal to X decoder 59, and supplies a Y address signal to Y decoder 57. X decoder 59 selects one of a plurality of word lines WL0 to WL3 in response to the X address signal.
Y decoder 57 generates a selection signal for selecting one of a plurality of main bit lines MB0 and MB1 in response to the Y address signal.

The Y gate transistors in Y gate 72 respond to the selection signal, and respond to the selection signals.
B1 is connected to sense amplifier 52 and write circuit 53.

At the time of reading, sense amplifier 52 detects data read on main bit line MB0 or main bit line MB1, and outputs the same to outside via data input / output buffer 51.

At the time of writing, externally applied data is applied to write circuit 53 via data input / output buffer 51, and write circuit 53 causes main bit line M to be applied in accordance with the data.
A program voltage is applied to B0 and MB1.

High voltage generation circuits 54 and 55 receive power supply voltage Vcc (for example, 5 V) from the outside and generate a high voltage. Negative voltage generating circuit 56 receives power supply voltage Vcc from the outside and generates a negative voltage. Verify voltage generating circuit 60
Receives a power supply voltage Vcc externally applied, and applies a predetermined verify voltage to a selected word line at the time of verification. Well potential generation circuit 61 applies a negative voltage to p well region 71 at the time of erasing. Source control circuit 62
Supplies a high voltage to the source line SL at the time of erasing. Select gate decoder 63 responds to a part of the address signal from address buffer 58 to select gate SG.
1. SG2 is selectively activated.

Write / erase control circuit 50 controls the operation of each circuit in response to an externally applied control signal.

(B) Operation of Non-Volatile Semiconductor Storage Device Next, the sector erase operation, write operation and read operation of the non-volatile semiconductor storage device will be described with reference to Table 1.

(I) Sector erase operation Here, it is assumed that the sector SE1 is erased collectively. First, the write / erase control circuit 50 is supplied with a control signal designating a collective sector erase operation. Thereby, high voltage generation circuit 55 and negative voltage generation circuit 56 are activated.

The high voltage generation circuit 55 applies a high voltage (10 V) to the X decoder 59. The X decoder 59 has the sector S
A high voltage (10 V) is applied to the word lines WL0 and WL1 of E1, and 0 V is applied to the word lines WL2 and WL3 of the sector SE2. Negative voltage generating circuit 56 applies a negative voltage to Y decoder 57 and well potential generating circuit 61. Y decoder 57 is connected to Y gate transistors YG 0, YG 0 in Y gate 72.
A negative voltage is applied to YG1. Thereby, the main bit line M
B0 and MB1 enter a floating state. The source control circuit 62 brings the source line SL into a floating state.
Further, well potential generating circuit 61 applies a negative voltage (−8 V) to p well region 71. Select gate decoder 6
Reference numeral 3 turns off the select gates SG1 and SG2.

[0455] In this manner, the memory cells in the selected sector SE1 and the memory cells in the non-selected sector SE2 are
A voltage is applied as shown in (E1) of Table 2. As a result, all the memory cells in the sector SE1 are erased.

(Ii) Write Operation Here, it is assumed that memory cell M00 is programmed. That is, data “0” is written to memory cell M00, and memory cell M10 holds data “1”.

First, a write / erase control circuit 50 is supplied with a control signal designating a program operation. Thereby, high voltage generation circuit 54 and negative voltage generation circuit 56 are activated.

The negative voltage generator 56 applies a negative voltage to the X decoder 59. The X decoder 59 is used for the address buffer 5
8 in response to the X address signal applied from
L0 is selected, and a negative voltage (−) is applied to the selected word line WL0.
8V), and 0 is applied to unselected word lines WL1 to WL3.
V is applied.

The high voltage generating circuit 54 applies a high voltage to the Y decoder 57, the write circuit 53 and the select gate decoder 63. First, data “0” is externally applied to write circuit 53 via data input / output buffer 51 and latched. Y decoder 57 applies a high voltage to Y gate transistor YG0 in Y gate 72 and applies 0 V to Y gate transistor YG1 in response to a Y address signal provided from address buffer 58. Thereby,
Y gate transistor YG0 turns on.

Write circuit 53 has Y gate transistor YG
A program voltage (5 V) corresponding to data “0” is applied to main bit line MB0 via “0”. The select gate decoder 63 turns on the select gate SG1 and turns off the select gate SG2. Thereby, sub-bit lines SB01 and SB11 are connected to main bit lines MB0 and MB1, respectively. Source control circuit 62
Causes the source line SL to be in a floating state. Well potential generating circuit 61 applies 0 V to p well region 71.

Thus, a voltage is applied to the memory cell M00 as shown in the left column of (P1) in Table 2. As a result, the threshold voltage of the memory cell M00 decreases.

After a lapse of a predetermined time (for example, 1 ms), data “1” is externally applied to write circuit 53 via data input / output buffer 51 and latched. Y decoder 5
7 applies a high voltage to the Y gate transistor YG1 in the Y gate 72 in response to the Y address signal given from the address buffer 58, and
To 0 V. This turns on the Y gate transistor YG1. Write circuit 53 applies 0 V corresponding to data "1" to main bit line MB1 via Y gate transistor YG1.

Thus, a voltage is applied to the memory cell M10 as shown in the right column of (P1) in Table 2. As a result, the threshold voltage of the memory cell M10 is kept high.

(Iii) Read operation Here, it is assumed that data is read from memory cell M00. First, a control signal designating a read operation is applied to write / erase control circuit 50.

The X decoder 59 includes an address buffer 58
Word line WL in response to an X address signal applied from
Select 0 and apply 3V to it. At this time, the word lines WL1 to WL3 are kept at 0V. The select gate decoder 63 turns on the select gate SG1, and
The select gate SG2 is turned off. Y decoder 5
7 turns on the Y gate transistor YG0 in the Y gate 72 in response to the Y address signal supplied from the address buffer 58. The source control circuit 62 has a source line S
L is grounded.

As described above, the selected memory cell M
00, a voltage is applied as shown in the left column of (R1) in Table 2. Thereby, if the content of M00 is "1", a read current flows through main bit line MB0. This read current is detected by the sense amplifier 52 and output to the outside via the data input / output buffer 51. At this time, a voltage is applied to the unselected memory cells as shown in the right column of (R1) in Table 2.

<2> Second Example (a) Overall Configuration of Nonvolatile Semiconductor Memory Device FIG. 73 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory device according to a second example.

The nonvolatile semiconductor memory device of FIG.
The difference from the nonvolatile semiconductor memory device is that the negative voltage generating circuit 56 applies a negative voltage to the source control circuit 62 at the time of erasing.

The structure of the other portions is the same as the structure shown in FIG. (B) Operation of Non-Volatile Semiconductor Storage Device The writing operation and the reading operation of the non-volatile semiconductor storage device of the second example are the same as those of the first example. Also, in the sector batch erasing operation, a point different from the first example in that a negative voltage (−8 V) is applied to the source line SL by the source control circuit 62.

At the time of collective erasing, a voltage is applied to the memory cells in the selected sector as shown in the left column of (E2) in Table 2, and the memory cells in the non-selected sectors are shown in (E2) in Table 2.
A voltage is applied as shown in the right column of 2).

<3> Third Example (a) Overall Configuration of Nonvolatile Semiconductor Memory Device FIG. 74 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory device according to a third example.

The nonvolatile semiconductor memory device of the third example is the first embodiment.
The difference from the nonvolatile semiconductor memory device of the example is as follows. Instead of the source control circuit 62, the source decoder 10
2 are provided. Negative voltage generating circuit 56 applies a negative voltage to select gate decoder 63 and source decoder 102 instead of Y decoder 57.

[0473] Memory cells M00 and M0 in sector SE1
The sources of M1, M10 and M11 are connected to a source line SL1, and the memory cells M02, M03 and M1 in the sector SE2.
2, the sources of M13 are connected to the source line SL2. The output terminals of the source decoder 102 are source lines SL1, SL
2 is connected.

(B) Operation of Nonvolatile Semiconductor Memory Device The write operation and read operation of the nonvolatile semiconductor memory device of the third example are the same as those of the first example. In the sector batch erasing operation, the source decoder 102 sets a source line corresponding to a selected sector to a floating state, and applies a negative voltage (−8 V) to a source line corresponding to a non-selected sector. For example, at the time of batch erasing of the sector SE1, the source line SL1 is set in a floating state, and −8 V is applied to the source line SL2.

As described above, a voltage is applied to the memory cells in the selected sector as shown in the left column of (E3) in Table 2, and a memory cell in the non-selected sector is applied to (E3) in Table 2.
A voltage is applied as shown in the right column of 3).

As a result, it is possible to collectively erase the memory cells in the selected sector while stably protecting the data in the memory cells in the non-selected sector.

<4> Fourth Example (a) Overall Configuration of Nonvolatile Semiconductor Memory Device FIG. 75 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory device according to a fourth example.

The nonvolatile semiconductor memory device of the fourth example is shown in FIG.
4 are different from the nonvolatile semiconductor memory device of the third example shown in FIG. Negative voltage generating circuit 56 applies a negative voltage only to well potential generating circuit 61 during erasing, and does not apply a negative voltage to select gate decoder 63 and source decoder 102.

(B) Operation of Nonvolatile Semiconductor Memory Device The write operation and read operation of the nonvolatile semiconductor memory device of the fourth example are similar to those of the first example.

In the batch erase operation, the source decoder 10
2 makes the source line corresponding to the selected sector float, and applies 0 V to the source line corresponding to the non-selected sector. For example, at the time of batch erasing of sector SE1, source line SL1 is set to a floating state and source line S1 is set to a floating state.
0 V is applied to L2.

As described above, the voltage is applied to the memory cells in the selected sector as shown in the left column of (E4) in Table 2, and the memory cells in the non-selected sectors are A voltage is applied as shown in the right column of E4).

As a result, it is possible to collectively erase the memory cells in the selected sector while stably protecting the data in the memory cells in the non-selected sector.

<5> Fifth Example (a) Overall Configuration of Nonvolatile Semiconductor Memory Device FIG. 76 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory device according to a fifth example.

The fifth example of the nonvolatile semiconductor memory device shown in FIG.
5 is different from the nonvolatile semiconductor memory device of the fourth example shown in FIG. Two negative voltage generating circuits 56a and 56b
Is provided. Negative voltage generating circuit 56a applies a negative voltage to well potential generating circuit 61, select gate decoder 63 and source decoder 102. Negative voltage generation circuit 5
6b applies a negative voltage to the X decoder 59. The configuration of the other parts is the same as the configuration shown in FIG.

(B) Operation of Nonvolatile Semiconductor Memory Device The write operation and read operation of the nonvolatile semiconductor memory device of the fifth example are similar to those of the first example.

At the time of the sector erase operation, the source decoder 102 sets the source line corresponding to the selected sector to a floating state, and sets the source line corresponding to the non-selected sector to-.
Apply 4V. For example, at the time of batch erasing of the sector SE1, the source line SL1 is set in a floating state, and -4 V is applied to the source line SL2.

In this way, a voltage is applied to the memory cells in the selected sector as shown in the left column of (E5) in Table 2, and a memory cell in the non-selected sector is applied to ( A voltage is applied as shown in E5).

As a result, it is possible to collectively erase the memory cells in the selected sector while stably protecting the data in the memory cells in the non-selected sector.

<6> Sixth Example The entire configuration of the nonvolatile semiconductor memory device according to the sixth example is the same as the configuration shown in FIG. The write operation and read operation of the nonvolatile semiconductor memory device of the sixth example are the same as those of the first example.

At the time of the batch erase operation, the source decoder 10
2 applies -8 V to the source line corresponding to the selected sector and 0 V to the source line corresponding to the non-selected sector. For example, at the time of batch erasing of the sector SE1, -8 V is applied to the source line SL1 and 0 V is applied to the source line SL2.

In this manner, a voltage is applied to the memory cells in the selected sector as shown in the left column of (E6) in Table 2, and a memory cell in the non-selected sector is applied to ( A voltage is applied as shown in the right column of E6).

As a result, it is possible to collectively erase the memory cells in the selected sector while stably protecting the data in the memory cells in the non-selected sector.

<7> Seventh Example The entire structure of the nonvolatile semiconductor memory device according to the seventh example is similar to the structure shown in FIG. The writing operation and the reading operation of the nonvolatile semiconductor memory device of the seventh example are the same as those of the first example.

In the sector erase operation, the source decoder 102 applies -8 V to the source line corresponding to the selected sector and -4 V to the source line corresponding to the non-selected sector. For example, when sector SE1 is selected, -8V is applied to source line SL1 and -4V is applied to source line SL2.
Is applied.

As described above, a voltage is applied to the memory cells in the selected sector as shown in the left column of (E7) in Table 2, and the memory cells in the non-selected sectors are applied to (E7) in Table 2.
A voltage is applied as shown in the right column of 7).

As a result, it is possible to collectively erase the memory cells in the selected sector while protecting the data in the memory cells in the non-selected sector stably.

<8> Advantages of Each Example In the first and second examples, the non-selected sectors receive some disturbance from the substrate, but the source decoder is unnecessary and only one negative voltage generation circuit is required.

In the third example, the disturbance received by the non-selected sector from the substrate is small. In addition, the negative voltage generation circuit is 1
You only need one. Furthermore, the junction withstand voltage of the source at the time of erasing may be low. However, a source decoder is required.

In the fourth and sixth examples, the unselected sector receives the least disturbance from the substrate. Also, only one negative voltage generating circuit is required. However, a source decoder is required, and only a junction withstand voltage of 8 V is required.

In the fifth and seventh examples, the disturbance received by the non-selected sector from the substrate may be rather small, and the source withstand voltage may be as small as ~ 4V. However, a source decoder is required, and two negative voltage generation circuits are required.

Next, a method of manufacturing the nonvolatile semiconductor memory device according to the fourteenth embodiment of the present invention shown in FIG. 66A will be described with reference to FIGS. 77 to 95 are cross-sectional views showing first to nineteenth steps in the method for manufacturing a nonvolatile semiconductor memory device having the above-described structure.

First, referring to FIG. 77, an underlying oxide film 202 having a thickness of about 300 ° is formed on the main surface of p-type silicon substrate 201. Then, the underlying oxide film 20
2 on top of CVD (Chemical Vapor D)
A polycrystalline silicon film 203 having a thickness of about 500 ° is formed by using an evaporation method. On this polycrystalline silicon film 203, 1000 .ANG.
A silicon nitride film 204 of a degree is formed. Then, a resist 205 is formed on the silicon nitride film 204 so as to expose the element isolation region. By performing anisotropic etching using this resist 205 as a mask,
The silicon nitride film 204 and the polycrystalline silicon film 203 on the element isolation region are etched.

Thereafter, by removing the resist 205 and performing selective oxidation using the silicon nitride film 204 as a mask, a field oxide film 206 is formed as shown in FIG. Then, the polycrystalline silicon film 203 and the silicon nitride film 204 are removed.

Next, as shown in FIG. 79, a part of the memory transistor region and part of the peripheral circuit region
Under the conditions of eV and 2.0 × 10 13 cm −3, phosphorus (P) is ion-implanted. Then, impurity driving is performed at a temperature of 1000 ° C. for one hour. Thereby, n-well 207 is formed. Thereafter, as shown in FIG. 80, a resist 209 is formed so as to cover the memory cell formation region, and using this resist 209 as a mask, phosphorus (P) is added at 1.2 MeV and 1.0 × 10 13 cm -3. Ion implantation is performed under the conditions, and phosphorus (P) is further added at 180 KeV, 3.5 × 1.
Ions are implanted under the condition of 012 cm-3. Thereby, an n-well (not shown) is formed in a part of the peripheral circuit region.

Next, referring to FIG. 81, boron (B) ions are implanted into the memory transistor region under the conditions of 700 KeV and 1.0 × 10 13 cm −3,
V, boron (B) ions are implanted under the conditions of 3.5.times.10@12 cm @ -3. Thereby, p-well 210 is formed.

After impurity implantation for controlling the threshold voltage of each memory transistor is performed, referring to FIG. 82, the entire surface of the main surface of p-type silicon substrate 201 is subjected to a thermal oxidation treatment to achieve 150 ° C. A gate insulating film 211 having a film thickness of about the same is formed. Then, this gate insulating film 2
A resist 212 is formed so as to cover a selection gate transistor (to be described later) formation region on 11. Using the resist 212 as a mask, etching is performed to remove portions of the gate insulating film 211 other than the select gate transistor formation region.

The above-mentioned resist 212 is removed and thermal oxidation is performed again to form a gate insulating film 213 having a thickness of about 100 ° on the entire surface of the p-type silicon substrate 201. Thus, the gate insulating film 21 having a thickness of about 250 ° is formed in the select gate transistor formation region.
1, 213 will be formed. Then, a first polycrystalline silicon film 214 is formed on gate insulating films 211 and 213 to a thickness of about 1200 ° by using a CVD method or the like. Then, the first polycrystalline silicon film thickness 21
4, a resist 212a having a predetermined shape (in this case, a plurality of resist patterns are formed intermittently in a direction perpendicular to the paper surface) is deposited, and the first polycrystalline silicon is formed using the resist 212a as a mask. The film 214 is etched.

Thereafter, as shown in FIG. 84, a high-temperature oxide film having a thickness of about 100 ° is formed on the first polycrystalline silicon film 214 by using a CVD method or the like. A silicon nitride film by CVD method
Then, a high-temperature oxide film having a thickness of about 150 ° is formed on the silicon nitride film by using the CVD method. Thereby, an ONO film 215 is formed.

Next, referring to FIG. 85, a polycrystalline silicon layer doped with impurities is formed on the ONO film 215 to a thickness of about 1200 ° by the CVD method. Then, a tungsten silicide (WSi) layer is formed on this polycrystalline silicon layer by a sputtering method at 1200 °.
It is formed to a thickness of about. Thus, a conductive layer 216 serving as a control gate electrode is formed. A high-temperature oxide film 217 having a thickness of about 2000 ° is formed on conductive layer 216 by using a CVD method. Then, a resist 218 is formed on the high-temperature oxide film 217 located on the memory transistor region and the peripheral transistor formation region, and etching is performed using the resist 218 as a mask to form a transistor electrode used in a peripheral circuit. I do.

Next, referring to FIG. 86, a resist 218a is formed on the high-temperature oxide film 217 intermittently in the horizontal direction in FIG. Then, this resist 218a
High-temperature oxide film 217 and conductive film 21 using
6, the ONO film 215 and the first polycrystalline silicon film 214 are etched. Thereby, a floating gate electrode 219 and a control gate electrode 220 are formed.

Next, referring to FIG. 87 (a), a resist 221 is further applied on the flash memory in the state shown in FIG. 86, and the resist 221 is exposed so as to expose a portion serving as a source region of the memory transistor. 221 is patterned. FIG. 87 (b) is a plan view showing a partial plane of the flash memory in the state shown in FIG. 87 (a). Then, a cross section viewed along line BB in FIG. 87 (b) is shown in FIG. 87 (a). The field oxide film 206 formed on the source region is removed by performing dry etching using the resist 221 thus patterned as a mask.

Then, after removing the resists 218a and 211, as shown in FIG. 88, the resist pattern 221a is exposed so that only the select gate transistor is exposed.
To form Then, using this resist pattern 221a as a mask, phosphorus (P) is applied at 60 KeV, 3.0.
Ion implantation is performed under the condition of × 10 13 cm -3. Thereby,
Source / drain region 22 of select gate transistor
3,224 are formed. Then, the above-mentioned resist 221
a is removed.

Thereafter, referring to FIG. 89, a resist pattern 221b is formed so as to cover a transistor serving as a select gate transistor and expose other memory cells.
Then, using this resist 221b as a mask,
Arsenic (A) under the condition of 35 KeV and 5.5 × 10 15 cm -3
s) is ion-implanted. Thereby, source / drain regions and source lines of the memory transistor are formed. Then, the resist 221b is removed.

Next, referring to FIG. 90, a high-temperature oxide film having a thickness of about 2000 ° is formed in the memory transistor region by using the CVD method. Then, a sidewall 225 is formed on the side wall of the select gate transistor or the side wall of the memory transistor by anisotropically etching the high-temperature oxide film. Then, using this side wall 225 as a mask, 35 KeV,
Under the condition of 4.0 × 10 15 cm −3, arsenic (As) is ion-implanted. Thus, source / drain regions of the peripheral transistor are formed.

Thereafter, referring to FIG. 91, a TEOS (Tetra ethyl o) is formed in the memory transistor region.
A silicon oxide film 226 made of, for example, an rtho silicate film is deposited. Then, sintering of the oxide film is performed for about 30 minutes. Then, as shown in FIG.
By performing anisotropic etching of the silicon oxide film 226, a sidewall 225a is formed. With the formation of the sidewall 225a, the source region in the memory cell is covered with the silicon oxide film.

Next, referring to FIG. 93, a polycrystalline silicon layer having a thickness of about 2000 ° is formed by a CVD method or the like, and conductivity is increased by introducing impurities into the polycrystalline silicon layer. Give it. A sub-bit line 227 is formed by applying a resist 228 having a predetermined shape on the polycrystalline silicon layer and patterning using the resist 228 as a mask.

Next, referring to FIG. 94, after removing the resist 228, a silicon oxide film 229 made of a TEOS film or the like is formed on the sub-bit line 227 by using the CVD method.
To form The thickness of the silicon oxide film 229 is 15
It is about 00 °. On this silicon oxide film 229, C
Using a VD method or the like, a silicon nitride film 230 having a thickness of about 500 ° is formed. Then, the silicon nitride film 23
A silicon oxide film 2 made of a BPTEOS film or the like having a thickness of about 10000.degree.
31 are formed. After that, reflow is performed by a heat treatment at about 850 ° C., and the BPTEOS film is
Etch back about 00Å. Then, a resist 232 having a predetermined shape is deposited on the silicon oxide film 231, and the silicon oxide films 229 and 231 and the silicon nitride film 230 are etched using the resist 232 as a mask. Thus, a contact hole 233a for connecting the sub bit line 227 to the main bit line 233 formed in a later step is formed.

Next, referring to FIG. 95, a tungsten plug 233b is formed in the contact hole 233a by using the CVD method and the etch-back method. Then, on the tungsten plug 233b and the silicon oxide film 231 by using a sputtering method or the like.
An aluminum alloy layer having a thickness of about 5000 ° is formed. Then, a resist 232a having a predetermined shape is deposited on the aluminum alloy layer, and the aluminum alloy layer is patterned using the resist 232a as a mask, whereby the main bit line 233 is formed. After that, the resist 232a is removed, and an interlayer insulating layer is formed on the main bit line. Then, an aluminum wiring layer is further formed on the interlayer insulating layer through a through-hole forming step. Thus, the nonvolatile semiconductor device shown in FIG. 66A is formed.

Next, a method of manufacturing the select gate contact portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIGS. FIGS. 96 to 100 are cross-sectional views taken along line CC in FIG.

First, referring to FIG. 96, steps up to the high-temperature oxide film 217 are formed through the same steps as in the above embodiment.
The selection gate transistor is connected to an aluminum wiring layer 238 formed thereover via a contact hole. Therefore, a contact hole is formed at the connection portion. This contact is shown in FIG. Referring to FIG. 97, after the high-temperature oxide film 217 is deposited as described above, the high-temperature oxide film 217 in the contact portion is etched by performing etching.
And the conductive film 216 is removed. Thereby, a contact hole 251 is formed.

Referring to FIG. 98, after an oxide film made of a TEOS film or the like is formed on the entire surface by using a CVD method or the like, a silicon oxide film is formed on the side wall of contact hole 251 by performing anisotropic etching. 235 are left. At this time, when the silicon oxide film 235 serving as the sidewall is formed, the first polycrystalline silicon film 21 is formed.
Since the ONO film 215 on the substrate 4 is also etched, the first polycrystalline silicon film 214 is exposed.

Next, referring to FIG. 99, a poly pad 236 made of polycrystalline silicon is formed in the contact hole 251 and a sub-bit line 227 is formed at the same time. afterwards,
As shown in FIG. 100, an interlayer insulating film 245 is formed on the poly pad 236 and the sub-bit line 227. Then, the poly pad 236 in the interlayer insulating film 245 is formed.
A contact hole 251a is formed in the upper portion, and an aluminum electrode 237 is formed in the contact hole 251a.
To form At this time, the main bit line 233 is formed simultaneously with the formation of the aluminum electrode 237. in this way,
Poly pad 2 at contact part of select gate transistor
By forming 36, the aspect ratio in the contact portion can be reduced, and the margin for pattern overlapping can be increased.

After the main bit line 233 and the aluminum electrode 237 are formed as described above, a nonvolatile semiconductor memory device is formed through the same steps as in the above embodiment.

Next, a method of manufacturing the source line contact portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIGS. FIG. 101 is a plan view showing a part of the nonvolatile semiconductor memory device shown in FIG. First, referring to FIG. 101, source line 223a is formed in source line contact portion 239 so as to have a width W1 larger than width W2 of source line 223a other than the contact portion. on the other hand,
Reflecting this shape, the width of the drain region is as small as W4 at the portion sandwiched between the source line contact portions 239, and the width of W3 is larger at other portions. By utilizing such a difference in width, in the present embodiment, formation of a contact hole in the source line contact portion 239 and formation of a contact hole in the drain contact portion 240 are to be performed simultaneously.

Hereinafter, a detailed description will be given with reference to FIGS. FIG. 102 (I) is a diagram showing D in FIG.
It is a figure which shows the cross section seen along the -D line. FIG. 102 (I
FIG. I) is a diagram showing a cross section viewed along the line EE in FIG. 101. Hereinafter, the same applies to FIGS. 103 to 106.

First, referring to FIG. 102, the floating gate electrode 219 in the memory transistor is turned on.
An O film 215, a control gate electrode 220 and a high-temperature oxide film 217 are formed through the same steps as in the above embodiment. At this time, in FIG. (I), the interval between the source portions is wider than the interval between the drain portions, and in FIG. (II), the interval between the drain portions is wider than the interval between the source portions.

[0527] In the memory transistor in such a state,
As shown in FIG. 103, a side wall 225 is formed in the same manner as in the above embodiment. Then, an oxide film 226 is further deposited on the side wall 225 as shown in FIG.

Thereafter, referring to FIG. 105 (I), a contact hole 239a is formed in source line contact portion 239 by performing anisotropic etching on oxide film 226 described above. At this time, since the width of the source portion is wider than the width of the drain portion, the source portion is more easily etched, and the source portion has a contact hole 2.
39a is formed, but no contact hole is formed in the drain portion.

On the other hand, referring to FIG. 105 (II), in this case, since the drain portion is wider than the source portion, only the drain portion is used in the same manner as described above. Contact hole 240a is formed in the contact hole. Thus, the contact hole 239a
106 and 240a are formed at the same time, as shown in FIG. 106, a sub-bit line 227 and a wiring layer 241 made of polycrystalline silicon or the like are formed on the memory transistor.

As described above, according to this embodiment, the formation of the source line contact portion 239 and the formation of the drain contact portion 240 are performed by utilizing the difference in the width of the source line 223a and the difference in the width of the drain portion. This can be done simultaneously. In addition, since a mask for forming each contact hole is not required, the process can be simplified and the manufacturing cost can be reduced.

(15) Fifteenth Embodiment Next, a fifteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIG. FIG.
FIG. 7A is a cross-sectional view of the nonvolatile semiconductor memory device after the formation of the sub-bit line 227 in the case where the dummy memory transistor is not formed. FIG. FIG. 35 is a sectional view of a fifteenth embodiment of the semiconductor memory device. First, FIG. 107 (a)
, One end of sub bit line 227 is cut off on select gate transistor 234, and the other end is cut off on field oxide film 206. In such a case,
Field oxide film 206 during contact etching, etc.
However, there is a problem that the film is reduced and the separation characteristics are deteriorated.

Therefore, in the fifteenth embodiment, the dummy memory transistor 2 is formed on the field oxide film 206.
42b. This makes it possible to reduce the step in the sub-bit line 227 without deteriorating the isolation breakdown voltage between elements. As described above, in the fifteenth embodiment, the dummy memory transistor 242b is formed on the field oxide film 206.
As shown in (b), the dummy memory transistor 2
42a may be formed directly on the p-type silicon substrate 201. Thus, electrons can be injected between the dummy gate 242 and the p-type silicon substrate 201 using FN tunneling. This makes it possible to have a field shield effect. The sub bit line 2 sandwiching the dummy memory transistor 242a
27, electrons can be injected into the dummy gate 242 by channel hot electrons.
With this, the same field shield effect as in the above case can be expected.

(16) Sixteenth Embodiment Next, with reference to FIGS. 108 to 119, a sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described. FIG. 108 is a partial cross-sectional view of the memory transistor portion of the nonvolatile semiconductor memory device according to the sixteenth embodiment according to the present invention. FIG. 109 is a cross-sectional view corresponding to a cross-section taken along line FF in FIG. 69. FIG.
FIG. 119 is a cross-sectional view showing a tenth step to a nineteenth step of the manufacturing process of the nonvolatile semiconductor memory device in this embodiment.

In each of the above-described embodiments, the source line is formed by removing the field oxide film 206 located on the source region by etching and implanting arsenic (As) into the source region in this state. However, in this case, the following problems can be considered. Immediately below the field oxide film 206, boron (B) or the like is previously injected through the field oxide film 206 in order to improve the isolation characteristics between elements. Therefore, as described above, when arsenic (As) for forming a source line is implanted after etching field oxide film 206, boron (B) implanted through field oxide film 206 and source A portion that overlaps with arsenic (As) implanted for line formation will occur. This may cause a problem that the carrier concentration is offset in the overlapping portion, and the source withstand voltage is lowered.

Therefore, in this embodiment, in order to form a source line, a wiring layer made of polycrystalline silicon or the like into which impurities are introduced so as to electrically connect the source regions is formed. Thereby, the wiring layer can be formed on the field oxide film 206,
Field oxide film 206 located on source line formation region
There is no need to remove it. Thereby, the overlap of the impurity regions as described above can be eliminated, and a decrease in the source withstand voltage can be prevented.

In the following, this embodiment will be described with reference to the drawings.
This will be described more specifically. First, referring to FIG. 108, the feature of this embodiment is that the wiring layer 2 electrically connects the source regions 223 scattered in the word line direction.
62 is formed. Other structures are
This is the same as the above embodiments. In this case, the wiring layer 262 is formed of polycrystalline silicon or the like.

The wiring layer 262 is formed of the field oxide film 2
The source regions 223 separated by 06 are connected to each other. Therefore, as shown in FIG. 109, wiring layer 262 extends over source region 223 and field oxide film 206 sandwiched between source regions 223. By providing the wiring layer 262 in this manner, each source region 223 can be electrically connected, so that it is not necessary to remove a part of the field oxide film 206 by etching. This makes it possible to prevent the source line breakdown voltage from being reduced as described above.

Next, a method for manufacturing a nonvolatile semiconductor memory device having the above structure will be described with reference to FIGS. Referring to FIG. 110, high-temperature oxide film 217, conductive film 216, ONO film 215, and first polycrystalline silicon film 21 are formed through the same steps as in the second embodiment.
4 is etched. Thereby, a floating gate electrode 219 and a control gate electrode 220 are formed. Then, the resist 218a is removed.

Next, as shown in FIG. 111, a resist pattern 221a is formed so as to expose only the select gate transistor. Using this resist pattern 221a as a mask, phosphorus (P) is
Ion implantation is performed under the conditions of eV and 3.0.times.10@13 cm @ -2.
Thereby, source / drain regions 223 and 224 of the select gate transistor are formed. After that, the resist 221a is removed.

Next, referring to FIG. 112, a resist pattern 221b is formed so as to cover a transistor serving as a select gate transistor and expose another memory transistor.
To form Then, using this resist pattern 221b as a mask, 35 KeV, 5.5 × 10 15 cm
Under the condition of -2, arsenic (As) is ion-implanted. Thereby, source / drain regions of the memory transistor are formed. After that, the resist 221b is removed.

Next, referring to FIG. 113, a high-temperature oxide film having a thickness of about 2000 ° is formed in the memory transistor region by using the CVD method. Then, a sidewall 225 is formed on the side wall of the select gate transistor or the side wall of the memory transistor by anisotropically etching the high-temperature oxide film. Then, using this side wall 225 as a mask, 35 KeV,
Arsenic (As) is ion-implanted under the condition of 4.0 × 10 15 cm −2. Thus, the source / drain regions of the peripheral transistor, the source region 223, and the drain region 224 are formed.

Next, referring to FIG. 114, a TEOS (Tetraethyl Or
A silicon oxide film 226 made of, for example, a silicate film is deposited. Then, sintering of the oxide film is performed for about 30 minutes. Thereafter, a resist pattern 261 is formed to expose the silicon oxide film 226 located on the source region 223. Then, using this resist pattern 261 as a mask, the source region 223 is formed.
Silicon oxide film 226 located on top, sidewall 2
25 is partially etched. Thereby, as shown in FIG. 115, a contact hole 268 is formed in a region located above source region 223. Then, the resist 261 is removed.

Next, referring to FIG. 116, a polycrystalline silicon layer 262 is formed on the inner surface of contact hole 268 and on silicon oxide film 226 by using a CVD method or the like. Then, on this polycrystalline silicon layer 262,
An oxide film 263 is formed using a CVD method or the like. Then, on the oxide film 263 located on the source region 223,
A resist pattern 264 is formed. At this time, the ends of the resist pattern 264 are connected to the floating gate electrode 219 and the control gate electrode 2 located on the source side.
20 on the end. Thus, the distance between polycrystalline silicon layer 262 and sub-bit line 227 can be increased, and polycrystalline silicon layer 262 and sub-bit line 22 can be separated.
7 with a desired withstand voltage. Further, the control gate electrode 220 and the polysilicon layer 262
The withstand voltage between them can also be a desired value.

Then, as shown in FIG. 117, oxide film 263 and polycrystalline silicon layer 262 are etched using resist pattern 264 as a mask. Thus, a wiring layer 262 for electrically connecting the source regions 223 scattered in the word line direction is formed.

Next, referring to FIG. 118, resist 26
After removing 4, oxide film 265 is formed on oxide films 226 and 263 by using a CVD method or the like. Then, a resist pattern 266 is formed to expose the oxide film 265 located on the drain diffusion region 224. And
Using resist pattern 266 as a mask, oxide films 265 and 226 located on drain region 224 are formed.
Is removed by etching. Thereby, the drain region 22
4 will be partially exposed.

Then, referring to FIG. 119, after removing the above-mentioned resist 266, the resist 266 is removed by CVD or the like.
Forming a polycrystalline silicon layer having a thickness of about 00 °,
The polycrystalline silicon layer is made conductive by introducing impurities. Then, a resist 228 having a predetermined shape is applied on the polycrystalline silicon layer.
The sub-bit line 227 is formed by patterning the polycrystalline silicon layer using 8 as a mask.
Hereinafter, a nonvolatile semiconductor memory device is formed through the same steps as in the second embodiment.

(17) Seventeenth Embodiment Next, a seventeenth embodiment according to the present invention will be described with reference to FIGS. 120 to 125 and FIGS. 156 to 159. FIG. 120 is a partial sectional view of the nonvolatile semiconductor memory device according to the seventeenth embodiment of the present invention. Fig. 121
To FIG. 125 are views showing first to fifth steps of the manufacturing process of the nonvolatile semiconductor memory device shown in FIG.
FIGS. 156A and 156A are plan views showing a conventional structure of the nonvolatile semiconductor memory device according to the seventeenth embodiment.
FIG. 4B is a diagram showing a cross-sectional view (b) taken along line BB in FIG. FIG. 157 is a partial cross-sectional view for describing a write operation of the conventional nonvolatile semiconductor memory device shown in FIG. 156. FIG. 158 is a partial cross-sectional view for describing an erasing operation of the nonvolatile semiconductor memory device shown in FIG. 156. FIG. 159 is a partial cross-sectional view for describing a problem in the conventional nonvolatile semiconductor memory device shown in FIG. 156.

First, a conventional structure of a nonvolatile semiconductor memory device according to a seventeenth embodiment of the present invention will be described with reference to FIGS. Referring to FIGS. 156 (a) and 156 (b), this type of non-volatile semiconductor memory device generally includes a memory cell array (Virtual GroundAr) having a virtual ground configuration.
ray) is referred to as a non-volatile semiconductor memory device having a (ray).

Referring to FIG. 156 (b), on the main surface of p-type semiconductor substrate 301, n-type high-concentration impurity regions 302a, 302b, 302c and 30 functioning as bit lines are provided.
2d are formed substantially parallel to each other and at intervals. Floating gates 305a, 305b, and 305 are formed on a region sandwiched between these high-concentration impurity regions 302a to 302d with an insulating film 304 interposed therebetween. These floating gates 305a, 305
An insulating film 306 is formed so as to cover b and 305. On the surface of this insulating film 306, the control gate 3
07 is formed. The control gate 307 is
Referring to FIG. 156 (a), high-concentration impurity regions 302a-30 extend over a plurality of floating gates 305.
It is substantially orthogonal to 2d.

Next, referring to FIGS. 157 and 158,
A conventional operation of the conventional nonvolatile semiconductor memory device having the above structure will be described. First, the write operation will be described. Referring to FIG. 156 (a) and FIG. 157, a case where writing is performed on floating gate 305b will be described. When writing to floating gate 305b, a voltage of about 12 V is applied to control gate 307 extending over floating gate 305b, and high concentration impurity region 3 functioning as a bit line is applied.
A voltage of about 5 V is applied to 02b.

At this time, the high concentration impurity region 302a
It is kept in a floating state. Impurity region 302c
Are kept at the ground potential. Thus, a current flows from the high-concentration impurity region 302b to the high-concentration impurity region 302c. At this time, electrons are injected into the floating gate 305b. Thereby, writing is performed on floating gate 305b.

Next, the erasing operation will be described. When erasing information written in each floating gate 305, 305a, 305b, each control gate 30
7 is maintained at the ground potential, and each high-concentration impurity region 302a
A voltage of about 10 V is applied to .about.302d. Thereby, each floating gate 305, 305a, 305
Electrons are simultaneously extracted from b, and the written information is erased. This is shown in FIG.

The following will describe a case where a nonvolatile semiconductor memory device having a memory cell array of a conventional virtual ground configuration having the above configuration and operating is operated according to the present invention. Problems will arise. The problem will be described with reference to FIG.

If a conventional nonvolatile semiconductor memory device having a memory cell array having a virtual ground configuration is operated according to the present invention, a problem occurs when the write operation according to the present invention is performed. It will be. FIG.
, To write information into, for example, floating gate 305a by performing a write operation according to the present invention, a selected control gate 307 is selected.
For example, a voltage of about −8 V is applied. At this time, a voltage of about 5 V is applied to the selected bit line, in this case, the high concentration impurity region 302b functioning as a bit line. Then, unselected bit lines, in this case, the high concentration impurity regions 302a, 302c, 3
02d is kept at the ground potential.

As a result, as shown by arrows in FIG. 159, electrons are extracted from floating gate 305a and, at the same time, floating gate 305a
Electrons are also extracted from the floating gate 305b adjacent to. It is the high concentration impurity region 3
02b partially overlaps the floating gate 305a, and the other end of the floating gate 3b
This is because it is formed so as to partially overlap with 05b.

As described above, the high concentration impurity region 302b
And floating gate 305a and floating gate 305b are formed in a positional relationship such that they partially overlap each other.
Due to the N phenomenon, each floating gate 305
Electrons are extracted from a and 305b. That is, information has been written to both floating gates 305a and 305b. As a result, there arises a problem that a malfunction of the nonvolatile semiconductor memory device is caused.

The nonvolatile semiconductor memory device according to the present embodiment has been devised to solve the above-described problems. Hereinafter, the structure and operation of the nonvolatile semiconductor memory device according to this embodiment will be described with reference to FIGS.

Referring to FIG. 120, in the nonvolatile semiconductor memory device having the memory cell array of the virtual ground configuration in this embodiment, one end of high concentration impurity regions 302a, 302b, 302c, and 302d functioning as bit lines. Is located below the floating gate 305 and the other end is adjacent to the floating gate 30.
5 is formed so as not to be located below. The concentration of the high-concentration impurity regions 302a, 302b, 302c, 302d is preferably 1020 / cm3 or more.

More specifically, referring to FIG. 120, one end of high-concentration impurity region 302b is located below floating gate 305a. Floating gate 305b adjacent to floating gate 305a and impurity region 302b Are offset so that they do not overlap. For other structures, FIG. 156 (b)
This is almost the same as the conventional structure shown in FIG.

As described above, by forming the end portion of high-concentration impurity region 302b so as not to overlap with adjacent floating gate 305b, for example, when a write operation according to the present invention is performed on floating gate 305a, the adjacent region is formed. It is possible to avoid a situation in which electrons are extracted from the floating gate 305b. This makes it possible to write information more reliably.

Next, referring to FIGS. 121 to 125, FIG.
A method for manufacturing the nonvolatile semiconductor memory device having the structure shown in FIG. First, Figure 1
21 (a) and (b), p-type semiconductor substrate 3
01 insulating film 3 having a thickness of about 100 ° on the main surface
04 is formed. Then, on this insulating film 304, CV
Using a method D or the like, the first
A polycrystalline silicon layer 305c is deposited.

A resist 308 having a desired film thickness is applied on the first polycrystalline silicon 305c. This resist 308 is patterned into a predetermined shape. Using the patterned resist 308 as a mask, the first polycrystalline silicon layer 305 is etched.
Pattern c.

Next, referring to FIG. 122 (a), after patterning the first polycrystalline silicon layer 305c,
Using the resist 308 as a mask, an n-type impurity such as arsenic (As) is ion-implanted into the main surface of the p-type semiconductor substrate 301. At this time, the implantation angle of the impurity is inclined by a predetermined angle θ. Thus, the high-concentration impurity region 302 is formed on the main surface of the p-type semiconductor substrate 301 by the shadowing effect of the resist 308 such that the end thereof partially overlaps only one of the adjacent floating gates.
a to 302d can be formed.

[0564] The value of the inclination angle θ is preferably about 7 °. In this manner, arsenic (As) is ion-implanted at an angle to the vertical direction by an angle of θ, so that one of the adjacent first polysilicon layers 305 c patterned according to the resist 308 is formed. High-concentration impurity regions 302a to 302d overlapping with the first polycrystalline silicon layer 305c but offset from the other first polycrystalline silicon layer 305c are formed. FIG. 122 (b) shows this state as viewed in plan.

Next, referring to FIG.
After removing 8, an oxide film 309 is formed using a CVD method or the like so as to cover first polycrystalline silicon layer 305c. Then, the oxide film 309 is etched back to form the oxide film 309 on the first polysilicon layer 305.
Embed between c.

Next, referring to FIG. 124, an insulating film 306 is formed on oxide film 309 and first polycrystalline silicon layer 305c by using a CVD method or the like. A second polycrystalline silicon layer 307a having a predetermined thickness is deposited on insulating film 306 by using a CVD method or the like. Then, FIG.
25 (a), the second polycrystalline silicon layer 3
07a is coated with a resist 310, and the resist 31
0 is patterned into a predetermined shape. In this case,
Referring to FIG. 125 (b), high concentration impurity region 302a
The resist 310 is patterned in a direction substantially orthogonal to 302d. Resist 3 patterned in this way
By etching using 10 as a mask, as shown in FIG. 125 (a), control gate 307, floating gates 305a, 305
b, 305 and an insulating film 306 are formed. After that, the resist 310 is removed. Through the above steps, FIG.
Is completed.

Next, another embodiment of the seventeenth embodiment shown in FIG. 120 will be described with reference to FIG.
In the nonvolatile semiconductor memory device shown in FIG. 120, only high-concentration impurity regions 302a to 302d are formed. However, in the present embodiment, the n-type high-concentration impurity regions 302a to 302d involved in the writing operation are formed by using the same method as in the seventeenth embodiment, and furthermore, the n-type low-concentration impurity regions are further formed. 303 are formed. By providing the low-concentration impurity regions 303 in this manner, the operation characteristics of the nonvolatile semiconductor memory device can be improved. The low-concentration impurity region 303 is formed by ion-implanting an n-type impurity such as arsenic (As) into the main surface of the semiconductor substrate 301 at the same implantation angle as in the conventional example.

As an example of implantation conditions, arsenic (As) is implanted in an amount of 10 11 / cm 2 or more for forming the low concentration impurity region 303. Thereby, the concentration of the low-concentration impurity region 303 to be formed has a concentration of 10 16 / cm 3 or more. At this time, when forming the high concentration impurity regions 302a to 302d, arsenic (A
The injection amount of s) is preferably 10 15 / cm 2 or more. Thereby, the high-concentration impurity regions 302a to 302d
Is 1020 / cm3 or more.

Next, the present invention will be summarized with reference to FIG. FIG. 127 is a schematic diagram showing an essential configuration of the nonvolatile semiconductor memory device according to the present invention. Referring to FIG. 127, impurity regions 402a and 402b are formed on the main surface of semiconductor substrate 401 at intervals. Channel region 40 between impurity regions 402a and 402b
9, an insulating film 403 is formed.
A floating gate 404 is formed on the substrate 03. The floating gate 404 serves as an electron storage unit. An insulating film 405 is formed on the floating gate 404.
The word line 406 is formed via the. Word line 406
On top of this, an interlayer insulating film 407 is formed.
A bit line 408 is formed on 07. Bit line 40
8 is electrically connected to the impurity region 402a via a contact hole 410 provided in the interlayer insulating film 407.

In the nonvolatile semiconductor memory device having the above configuration, a characteristic operation according to the present invention is performed. First, in the characteristic operation of the nonvolatile semiconductor memory device according to the present invention, the initial state is an erased state. That is, the state in which electrons are accumulated in the floating gate 404 is the erased state (initial state). As a method of accumulating electrons in the floating gate 404,
First, the bit line 408 is held in a floating state, and a voltage of, for example, about −10 V is applied to the semiconductor substrate 401. At this time, a voltage of about 10 V is applied to the word line 406. As a result, the FN over the entire surface of the channel region 409
The phenomenon (channel FN) makes it possible to inject electrons into the floating gate 404. At this time, the threshold voltage Vth of the memory transistor in the erased state
(E) shows the voltage V applied to the word line 406 at the time of reading.
The value is higher than Read.

[0571] After the erased state is set as described above, information is written by extracting electrons from a predetermined memory transistor. When writing,
A voltage of about 5 V is applied to the bit line 408. At this time, the semiconductor substrate 401 is kept at the ground potential. And
A voltage of about −10 V is applied to the word line 406. As a result, electrons are extracted from the floating gate 404. At this time, the extraction of electrons is performed by the FN phenomenon at the overlapping portion between the floating gate 404 and the impurity region 402a. As a result, the threshold voltage V
th (p) has a value smaller than the voltage VRead applied to the word line 406 at the time of reading.

As described above, in the operation of the nonvolatile semiconductor memory device according to the present invention, the state where electrons are injected into the memory transistor is in the erased state, and the predetermined memory transistor among all the memory transistors is in the erased state. The information is written by extracting electrons from the. In each of the above embodiments, the case where the present invention is applied to the nonvolatile semiconductor memory device has been described. However, the present invention is also applicable to semiconductor storage devices other than nonvolatile semiconductor storage devices.

[0573]

According to the first aspect, the electric field in the channel direction of the drain or in the substrate direction can be reduced. According to the second aspect, a high electric field can be generated in the source channel direction or the substrate direction. According to the third aspect, the electric field in the channel direction or the substrate direction of the drain can be weakened, and a high electric field can be generated in the channel direction or the substrate direction of the source.

[Brief description of the drawings]

FIG. 1 is a diagram showing a relationship between program and erase operations and threshold voltages in first to eleventh embodiments in comparison with a conventional example.

FIG. 2 is a diagram showing an erased state and a programmed state in the first to eleventh embodiments in comparison with a conventional example.

FIG. 3 is a diagram showing threshold voltages at the time of batch erasing in the first to eleventh embodiments.

FIG. 4 is a diagram showing a change in threshold voltage due to a batch erase operation in the first to eleventh embodiments.

FIG. 5 is a block diagram showing the overall configuration of the flash memory according to the first embodiment.

FIG. 6 is a diagram showing conditions for applying a voltage to a memory cell during programming and erasing in the first embodiment.

FIG. 7 is a diagram showing voltage application conditions during a batch erase operation, a program operation, and a read operation in the first embodiment.

FIG. 8 is a flowchart for explaining a rewriting operation in the first embodiment.

FIG. 9 is a diagram showing conditions for applying a voltage to a memory cell during programming and erasing in the second embodiment.

FIG. 10 is a diagram showing voltage application conditions during a batch erase operation, a program operation, and a read operation in the second embodiment.

FIG. 11 is a block diagram showing an overall configuration of a flash memory according to a third embodiment.

FIG. 12 is a block diagram illustrating a configuration of an X decoder included in the flash memory of FIG. 11;

FIG. 13 is a diagram showing conditions for applying a voltage to a memory cell at the time of programming and erasing in the third embodiment.

FIG. 14 is a diagram showing voltage application conditions during a batch erase operation, a program operation, and a read operation in the third embodiment.

FIG. 15 is a diagram showing voltage application conditions during a page erase operation, a program operation, and a read operation in the fourth embodiment.

FIG. 16 is a flowchart for explaining a rewriting operation in the fourth embodiment.

FIG. 17 is a diagram illustrating voltage application conditions during a page batch erase operation, a program operation, and a read operation in the fifth embodiment.

FIG. 18 is a block diagram showing an overall configuration of a flash memory according to a sixth embodiment.

19 is a circuit diagram showing a detailed configuration of a memory array included in the flash memory of FIG. 18 and a portion related thereto.

FIG. 20 is a diagram showing conditions for applying a voltage to a memory cell during programming and erasing in the sixth embodiment.

FIG. 21 is a diagram showing voltage application conditions during a collective sector erase operation, a program operation, and a read operation in the sixth embodiment.

FIG. 22 is a flowchart illustrating a program operation and a verify operation in the sixth embodiment.

FIG. 23 is a sectional view showing a structure of a memory cell used in a flash memory according to a sixth embodiment.

FIG. 24 is a structural diagram of two adjacent memory cells in the sixth embodiment.

FIG. 25 is a layout diagram of a memory cell array in a sixth embodiment.

FIG. 26 is a circuit diagram showing a voltage applied in the memory cell array of the embodiment of FIG.

FIG. 27 is a circuit diagram showing an equivalent circuit of a high voltage generation circuit.

FIG. 28 is a sectional view showing a partial structure of a high-voltage generating circuit used in a flash memory according to a sixth embodiment;

FIG. 29 is a cross-sectional view for explaining that a parasitic transistor exists in the structure shown in FIG. 28;

30 is an equivalent circuit diagram of a circuit constituted by the parasitic transistors shown in FIG.

FIG. 31 is a sectional view showing another structure of the high voltage generation circuit used in the flash memory according to the sixth embodiment.

FIG. 32 is a circuit diagram showing an equivalent circuit of a negative voltage generation circuit.

FIG. 33 is a sectional view showing a partial structure of a negative voltage generating circuit used in a flash memory according to a sixth embodiment;

FIG. 34 is a circuit diagram showing a detailed configuration of a memory array included in a flash memory according to a seventh embodiment and portions related thereto.

FIG. 35 is a diagram showing a change in voltage of a main bit line during programming in the seventh embodiment.

FIG. 36 is a block diagram showing an overall configuration of a flash memory according to an eighth embodiment.

FIG. 37 is a circuit diagram showing a detailed configuration of a memory array included in the flash memory of FIG. 36 and parts related thereto.

FIG. 38 is a diagram for explaining a state of a memory cell at the time of erasing when there is no gate bird's beak.

FIG. 39 is a diagram showing conditions for applying a voltage to a memory cell of a selected sector and a memory cell of a non-selected sector at the time of erasing when there is no gate bird's beak.

FIG. 40 is a diagram showing a voltage application condition at the time of a collective sector erase operation when there is no gate bird's beak.

FIG. 41 is a circuit diagram showing a configuration of a source decoder used when there is no gate bird's beak.

FIG. 42 is a diagram showing voltages of respective parts of the source decoder of FIG. 41.

FIG. 43 is a diagram illustrating a state of a memory cell at the time of erasing when there is a gate bird's beak.

FIG. 44 is a diagram showing conditions for applying a voltage to a memory cell of a selected sector and a memory cell of a non-selected sector at the time of erasing when there is a gate bird's beak.

FIG. 45 is a diagram showing voltage application conditions during a collective sector erase operation when there is a gate bird's beak.

FIG. 46 is a circuit diagram showing a configuration of a source decoder used when there is a gate bird's beak.

FIG. 47 is a diagram showing voltages of respective parts of the source decoder of FIG. 46;

FIG. 48 is a diagram showing conditions for applying voltages to a memory cell of a selected sector and a memory cell of a non-selected sector during erasing when the well potential is low.

FIG. 49 is a diagram showing voltage application conditions during a collective sector erase operation when a well potential is low.

FIG. 50 is a circuit diagram showing a configuration of a source decoder used when a well potential is low.

FIG. 51 is a diagram showing voltages of respective parts of the source decoder of FIG. 50;

FIG. 52 is a block diagram showing an overall configuration of a flash memory according to a ninth embodiment.

FIG. 53 is a circuit diagram showing a detailed configuration of a memory array included in the flash memory of FIG. 52 and a portion related thereto.

FIG. 54 is a diagram showing voltage application conditions during a collective sector erase operation in the ninth embodiment.

FIG. 55 is a circuit diagram showing a configuration of a select gate decoder and a source switch included in the flash memory of FIG. 52;

FIG. 56 is a diagram showing voltages of respective parts of the select gate decoder and the source switch of FIG. 55;

FIG. 57 is a flowchart for explaining a program operation in the flash memory according to the tenth embodiment;

FIG. 58 is a flowchart for explaining a program operation in the flash memory according to the eleventh embodiment;

FIG. 59 is a block diagram showing an overall configuration of a flash memory according to a twelfth embodiment.

FIG. 60 is a circuit diagram of the memory cell array and its peripheral circuits shown in FIG. 59.

FIG. 61 is a layout diagram on a semiconductor substrate showing a connection mode between the word lines shown in FIG. 60 and the output lines of the local decoder.

FIG. 62 is a cross-sectional structural diagram showing separation between two memory cells 1491 and 1492 shown in FIG. 60;

FIG. 63 is a sectional view showing a structure in which separation between two memory cells 1491 and 1492 shown in FIG. 60 is performed by a field shield transistor.

FIG. 64 is a circuit diagram of a word line voltage control circuit and a predecoder used in the twelfth embodiment.

FIG. 65 is a cross-sectional view of a part of a memory transistor part of a thirteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 66A is a cross-sectional view of a part of a memory transistor section of a nonvolatile semiconductor memory device according to a fourteenth embodiment of the present invention, and FIG. 66B is an equivalent circuit diagram thereof.

FIG. 67 is a sectional view showing a memory transistor according to a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 68 is a plan view up to a state where a control gate having the structure shown in FIG. 66A is formed.

FIG. 69 is a plan view up to a state where a sub-bit line having the structure shown in FIG. 66A is formed.

FIG. 70 is a plan view up to a state where a main bit line having the structure shown in FIG. 66A is formed.

FIG. 71 is a plan view up to a state where aluminum wiring having the structure shown in FIG. 66A is formed.

FIG. 72 is a block diagram showing a first example of the entire configuration of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 73 is a block diagram showing a second example of the entire configuration of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 74 is a block diagram showing a third example of the overall configuration of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 75 is a block diagram showing a fourth example of the entire configuration of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 76 is a block diagram showing a fifth example of the entire configuration of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 77 is a diagram illustrating a first example of a method of manufacturing a memory transistor unit according to a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
It is sectional drawing which shows a process.

FIG. 78 shows a second method of manufacturing the memory transistor section of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
It is sectional drawing which shows a process.

FIG. 79 shows a third method of manufacturing the memory transistor section of the nonvolatile semiconductor memory device according to the fourteenth embodiment of the present invention;
It is sectional drawing which shows a process.

FIG. 80 is a fourth view of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
It is sectional drawing which shows a process.

FIG. 81 is a fifth view of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
It is sectional drawing which shows a process.

FIG. 82 is a sixth view of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
It is sectional drawing which shows a process.

FIG. 83 is a seventh view of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
It is sectional drawing which shows a process.

FIG. 84 is an eighth view of the manufacturing method of the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
It is sectional drawing which shows a process.

FIG. 85 is a ninth embodiment of a method for manufacturing a memory transistor section of a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
It is sectional drawing which shows a process.

FIG. 86 shows a first step of a method for manufacturing a memory transistor section of a nonvolatile semiconductor memory device according to a fourteenth embodiment of the present invention.
It is sectional drawing which shows 0 process.

FIG. 87 shows a first step of the method for manufacturing the memory transistor section of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
It is sectional drawing which shows one process.

FIG. 88 illustrates a first step of the method for manufacturing the memory transistor portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.
It is sectional drawing which shows two processes.

FIG. 89 is a first step in a method for manufacturing a memory transistor section according to a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
It is sectional drawing which shows three processes.

FIG. 90 is a diagram illustrating a first example of a method of manufacturing a memory transistor unit according to a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
It is sectional drawing which shows 4 processes.

FIG. 91 is a diagram illustrating a first example of a method of manufacturing a memory transistor unit according to a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
It is sectional drawing which shows 5 processes.

FIG. 92 is a diagram illustrating a first example of a method of manufacturing a memory transistor unit according to a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
It is sectional drawing which shows 6 processes.

FIG. 93 is a diagram illustrating a first example of a method of manufacturing a memory transistor unit according to a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
It is sectional drawing which shows 7 processes.

FIG. 94 is a diagram illustrating a first example of a method for manufacturing a memory transistor section of a nonvolatile semiconductor memory device according to a fourteenth embodiment of the present invention;
It is sectional drawing which shows 8 processes.

FIG. 95 is a first step in a method for manufacturing a memory transistor section of a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;
It is sectional drawing which shows 9 processes.

FIG. 96 is a cross-sectional view showing a first step of the method for manufacturing the select gate contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 97 is a cross sectional view showing a second step of the method for manufacturing the select gate contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 98 is a cross sectional view showing a third step of the method for manufacturing the select gate contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 99 is a cross sectional view showing a fourth step of the method for manufacturing the select gate contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 100 is a sectional view showing a fifth step of the method for manufacturing the select gate contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 101 is a plan view of a source line contact portion in a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 102 is a cross sectional view showing a first step of a method for manufacturing a source line contact portion in a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 103 is a cross sectional view showing a second step of the method for manufacturing the source line contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 104 is a sectional view showing a third step of the method of manufacturing the source line contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 105 is a sectional view showing a fourth step of the method of manufacturing the source line contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 106 is a sectional view showing a fifth step of the method of manufacturing the source line contact portion in the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 107 is a sectional view of a memory transistor part of a fifteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 108 is a cross-sectional view of a part of the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 109 is a view showing a cross section corresponding to a cross section viewed along line FF in FIG. 69;

FIG. 110 is a sectional view showing a tenth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 111 is a sectional view showing an eleventh step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 112 is a sectional view showing a twelfth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 113 is a sectional view showing a thirteenth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 114 is a sectional view showing a fourteenth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 115 is a cross-sectional view showing a fifteenth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 116 is a cross-sectional view showing a sixteenth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 117 is a sectional view showing a seventeenth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 118 is a sectional view showing an eighteenth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 119 is a sectional view showing a nineteenth step of the method for manufacturing the memory transistor portion of the sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 120 is a partial cross section showing a seventeenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 121 (a) is a partial cross-sectional view showing a first step of the method for manufacturing the memory transistor portion of the seventeenth embodiment of the nonvolatile semiconductor memory device according to the present invention. (B) is a plan view in this case.

FIG. 122 (a) is a partial cross-sectional view showing a second step of the method for manufacturing the memory transistor portion in the seventeenth embodiment of the nonvolatile semiconductor memory device according to the present invention; (B) is a plan view in this case.

FIG. 123 is a partial cross sectional view showing a third step of the method for manufacturing the memory transistor portion of the seventeenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 124 is a partial cross sectional view showing a fourth step of the method for manufacturing the memory transistor portion of the seventeenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 125 (a) is a partial cross-sectional view showing a fifth step of the method for manufacturing the memory transistor portion in the seventeenth embodiment of the nonvolatile semiconductor memory device according to the present invention. (B) is a plan view in this case.

FIG. 126 is a partial sectional view showing another mode of the seventeenth embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 127 is a schematic diagram for explaining a characteristic operation of the nonvolatile semiconductor memory device according to the present invention.

FIG. 128 is a cross-sectional view showing a structure of a stack gate type memory cell used in a conventional flash memory.

FIG. 129 is a diagram showing a relationship between program and erase operations and a threshold voltage in a conventional flash memory.

FIG. 130 is a diagram showing conditions for applying a voltage to a memory cell during programming and erasing in a conventional flash memory.

FIG. 131 is a block diagram showing the overall configuration of a conventional flash memory.

FIG. 132 shows X included in the flash memory of FIG. 131.
FIG. 3 is a block diagram illustrating a configuration of a decoder.

FIG. 133 is a diagram showing voltage application conditions during a program operation in a conventional flash memory.

FIG. 134 is a flowchart for describing a pre-erase write operation in a conventional flash memory.

FIG. 135 is a flowchart for explaining a batch erasing operation in a conventional flash memory.

FIG. 136 is a diagram showing voltage application conditions during a batch erase operation in a conventional flash memory.

FIG. 137 is a diagram showing voltage application conditions during a read operation in a conventional flash memory.

FIG. 138 is a diagram showing voltages of respective lines in a conventional flash memory during a program operation, an erase operation, and a read operation.

FIG. 139 is a diagram showing a threshold voltage when a batch erase operation is performed without performing a pre-erase write operation in a conventional flash memory.

FIG. 140 is a diagram showing a threshold voltage when a batch erase operation is performed after performing a pre-erase write operation in a conventional flash memory.

FIG. 141 is a flowchart for describing a rewriting operation in a conventional flash memory.

FIG. 142 is a diagram showing a change in threshold voltage when a batch erasing operation is performed in a conventional flash memory.

FIG. 143 is a cross-sectional view showing a structure of a memory cell including a selection transistor.

FIG. 144 is a diagram for explaining disturbance at the time of sector division.

FIG. 145 is a layout diagram of a memory cell array of a conventional flash memory having main bit lines and sub-bit lines.

FIG. 146 is a structural diagram of a memory cell of a conventional flash memory.

FIG. 147 is a circuit diagram showing a voltage applied in a memory cell array of a conventional flash memory.

FIG. 148 is a block diagram showing a general configuration of a flash memory.

FIG. 149 is an equivalent circuit diagram showing a schematic configuration of a NOR type memory cell matrix.

FIG. 150 is a cross-sectional structure diagram of a NOR-type memory transistor;

FIG. 151 is a schematic plan view showing a NOR type planar arrangement.

FIG. 152 is a partial sectional view taken along line AA of FIG. 151.

FIG. 153 is an equivalent circuit diagram of a part of a memory cell matrix of the NAND flash memory.

FIG. 154 is a cross-sectional view of a part of the memory cell matrix of the NAND flash memory.

FIG. 155 is a sectional structural view of a memory transistor of a NAND flash memory.

FIG. 156 (a) is a plan view showing a schematic configuration of a conventional nonvolatile semiconductor memory device having a memory cell array having a virtual ground configuration. (B) is B in (a)
It is sectional drawing seen along the -B line.

FIG. 157 is a view illustrating a conventional write operation of the nonvolatile semiconductor memory device shown in FIG. 156.

FIG. 158 is a view illustrating a conventional erase operation of the nonvolatile semiconductor memory device shown in FIG. 156.

FIG. 159 is a diagram for describing a problem when the conventional nonvolatile semiconductor memory device shown in FIG. 156 is operated according to the present invention.

[Explanation of symbols]

Reference Signs List 80 semiconductor substrate 81 n-well region 82 p-well region 83a, b source / drain region 84a, b source region 85a, b drain region 86 select gate transistor 87a, b, c, d memory transistor 88 control gate 89 floating gate 90 sub-bit Line 91a, b Branch line 92 Main bit line 93 MOS transistor 1001 P- type semiconductor substrate 1002 Drain 1003 Source 1004 Insulating film 1005 Floating gate 1006 Control gate 1008 P-well 1010, 10a Memory array 1020 Address buffer 1030 X decoder 1040 Y decoder 1050 Y gate 1060 Sense amplifier 1070 Data input / output buffer 1080 Write circuit 1090 Vpp / Vcc off Circuit 100 Verify voltage generation circuit 1110 Source control circuit 1120 Control signal buffer 1130 Control circuit 1140 Negative voltage control circuit 1210,1220 High voltage generation circuit 1230,1240 Negative voltage generation circuit 1250 Well potential generation circuit 1260 Select gate decoder 1270 Source decoder 1281, 1282 Source switch BL1, BL2, BL3 Bit line WL0, WL1, WL2, WL3 Word line M11, M12, M13, M21, M22, M23, M
31, M32, M33 Memory cell SL Source line SE1, SE2 Sector MB0, MB1 Main bit line SB01, SB02, SB11, SB12 Sub bit line SL1, SL2 Source line SGL1, SGL2 Select gate line Note that the same reference numerals in each drawing are the same. Or indicate a substantial part.

[Procedure amendment]

[Submission date] June 6, 2001 (2001.6.6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0573

[Correction method] Change

[Correction contents]

[0573]

According to the first aspect, the electric field in the channel direction of the drain or in the substrate direction can be reduced. According to the second aspect, a high electric field can be generated in the source channel direction or the substrate direction. According to the third aspect, the electric field in the channel direction or the substrate direction of the drain can be weakened, and a high electric field can be generated in the channel direction or the substrate direction of the source. According to the fourth invention
Then, FN is applied from the semiconductor substrate to the floating gate.
Since electrons are injected by tunneling, the source and
Rain is made of a first conductive type high-concentration impurity region and a low-concentration impurity.
The structure can reduce the electric field in the region. According to the fifth invention
Transfer the floating gate electron to the well and drain
In order to increase the degree of structural freedom for the source
Can be. According to the sixth invention, the memory cell and the M
An IS transistor is surrounded by a first conductivity type well.
Since it is formed in a conductive well, the memory cell and
And the MIS transistor are directly connected to the potential from the semiconductor substrate.
Can be unaffected. According to the seventh invention, the
Since the width of the source is smaller than the width of the drain,
Smaller than a memory cell array with the same width
A molycell array can be realized. According to the eighth invention, the
Since a source wiring layer is used, an isolation insulating film is formed.
The problem of the source withstand voltage in the portion can be eliminated.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme court ゛ (Reference) H01L 29/792 (31) Priority claim number Japanese Patent Application No. 4-238546 (32) Priority date September, 1994 7th (199.2.9.7) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 4-344807 (32) Priority date December 24, 1992 (1992.12. 24) (33) Priority claiming country Japan (JP) Application for Article 30 (1) of the Patent Act is filed Jan. 1, 1993 Published in Nikkei BP, "Nikkei Microdevices January 1993" issued by Nikkei BP. (72) Inventor Yoshikazu Miyawaki 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric LSI Research Institute, Inc. (72) Inventor Takeshi 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation S-I Laboratory ( 72) Inventor Tomoshi Futani 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric LSI Research Institute, Inc. (72) Inventor Yuichi Kunori 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation (72) Inventor Natsuo Mika 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric L-S Laboratory Inc. (72) Inventor Hiroshi Onoda 4-chome, Mizuhara, Itami-shi, Hyogo No. 1 Mitsubishi Electric LSI Research Institute (72) Inventor Makoto Oi 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric LSI Research Institute (72) Inventor Atsushi Fukumoto Itami Hyogo Prefecture 4-1-1, Mizuhara-shi, Ichiba F-term (reference) 5B025 AA03 AB01 AC01 AD04 AD08 AE05 AE06 AE08 5F083 EP02 EP23 EP33 EP77 ER09 ER15 ER22 ER30 JA04 JA36 KA06 KA12 LA06 MA06 MA20 PR36F39F BA01 BB05 BC02 BC11 BD36 BE02 BE05 BE 07

Claims (3)

[Claims] A first conductive type impurity region formed on the main surface of the semiconductor substrate at a predetermined interval; and a high-concentration impurity region, the other first conductive type impurity region. A drain having a low-concentration impurity region formed so as to cover the high-concentration impurity region; a floating gate formed through an insulating film formed on the semiconductor substrate between the source and the drain; A nonvolatile semiconductor memory device comprising: a memory cell including a control gate formed via an insulating film on a floating gate; a word line connected to the control gate; and a bit line connected to the drain. 2. A semiconductor device comprising: a first conductive type impurity region formed as a drain on a main surface of a semiconductor substrate at a predetermined interval; a second conductive type impurity region; An impurity region of a second conductivity type different from the first conductivity type formed so as to cover; a floating gate formed via an insulating film formed on the semiconductor substrate between the source and the drain; A nonvolatile semiconductor memory device comprising: a memory cell including a floating gate formed via an insulating film on the floating gate; a word line connected to the control gate; and a bit line connected to the drain. 3. The nonvolatile semiconductor memory device according to claim 1, further comprising an impurity region of a second conductivity type different from the first conductivity type formed so as to cover the source.