JP3576858B2 - Clock transfer method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock transfer method, and more particularly to a clock transfer method for preventing instability immediately after power-on or the like.
[0002]
[Prior art]
In a digital device such as a dual-port memory, a clock as an operation reference is essential. A clock and frame transfer circuit used in an elastic store used in a transmission device or the like is disclosed in, for example, Japanese Patent Application Laid-Open No. 9-74401.
[0003]
FIG. 3 shows a conventional clock switching method using a VCO (voltage controlled oscillator). This clock transfer method includes a memory 10, a comparison unit 11, a VCO 12, and a read pulse generation unit 13. The memory 10 is a dual-port type memory, which writes input data into the memory by a write input pulse and outputs data written to the memory 10 by a read pulse as a data output from an output port. A write input pulse is input to the comparison unit 11 and the VCO 12. The VCO 12 reads out the output pulse based on this and inputs it to the pulse generation unit 13 together with the frame pulse. The read pulse generator 13 is input to the memory 10 as the read pulse described above, and is also input to the comparator 11. The comparison unit 11 compares the write input pulse with the read pulse, and outputs a comparison output to the read pulse generation unit 13.
[0004]
Next, the operation of the clock transfer method shown in FIG. 3 will be described. The read pulse of the memory 10 is generated by the read pulse generator 13 using a clock signal output from the VCO 12 that operates simultaneously with turning on the power and a frame pulse signal synchronized with the data input to the memory 10. The read pulse generation unit 13 generates a read pulse at n / 2 position with respect to the cycle n of the write input pulse. By reading out the data written in the memory 10 with the readout pulse, a clock change is realized.
[0005]
The read pulse from the read pulse generation unit 13 can be replaced at any position as long as the write pulse and the pulse do not overlap with each other. By initial setting to / 2, protection was provided so that the transfer could be performed even if the pulse was shifted forward and backward. Further, the comparison unit 11 compares the write and read pulse positions, and when the pulses overlap, the comparison unit 11 outputs a reset signal to the read pulse generation unit 13. This resets the read pulse generator 13 and resets the read pulse.
[0006]
[Problems to be solved by the invention]
In the above-described related art, the read pulse does not become the initial setting immediately after the power is turned on or when the power is unstable (for example, when noise occurs) and the write pulse is unstable. Therefore, it is not known where the read pulse is located relative to the write pulse, and in the worst case, there is a risk that data cannot be read. Further, even if the read pulse is stabilized from an unstable state, it is not clear where the pulse is located, so that there is a problem that the front-rear protection is biased to one side.
[0007]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock switching method capable of reading data with a stable read pulse having sufficient protection at all times by controlling the read pulse.
[0008]
Another object of the present invention is to provide a clock switching method that can control a read pulse before a data error occurs and can avoid the occurrence of a data error.
[0009]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the clock switching method according to the present invention employs the following characteristic configuration.
[0010]
(1) In a clock transfer method including a VCO that receives a write input pulse to a memory and generates an output clock and a read pulse generator that generates a read pulse,
A shift unit that shifts the write input pulse for a predetermined time; an instability determining unit for a generated pulse of the read pulse generating unit; and a comparing unit that compares the write shift pulse and a generated pulse from the read pulse generator. A read pulse control unit is provided,
A clock switching method in which the write shift pulse of the shift unit is used as a read pulse of the memory during the unstable period.
[0011]
(2) The clock transfer method according to (1), further including a delay unit for delaying the write input pulse and the output pulse of the read pulse control unit.
[0012]
(3) The clock switching method according to (1), wherein the read pulse control unit has a protection unit that checks the number of matches in the comparison unit.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a preferred embodiment of a clock switching method according to the present invention will be described in detail with reference to FIGS.
[0016]
FIG. 1 is a block diagram of a preferred embodiment of a clock re-switching method according to the present invention, and FIG. 2 is a timing chart for explaining its operation. Note that the same reference numerals are used for components or blocks corresponding to those in the related art.
[0017]
First, with reference to FIG. 1, the configuration of the clock switching system according to the present invention will be described. In this clock transfer method, in addition to the dual-port memory 10, the VCO 12, and the read pulse generator 13, a delay unit 15 on the write side of the memory 10 and a delay unit 16 and a read pulse controller 20 on the read side of the memory 10 are used. It is characterized by having been provided. The read pulse control unit 20 includes a shift unit 21, a comparison unit 22, a protection unit 23, a determination unit 24, and a selector 25.
[0018]
A write input pulse is input to the shift unit 21, and an output thereof is input to the selector 25 and the comparison unit 22. The comparison unit 22 compares the output of the shift unit 21 with the output of the read pulse generation unit 13, and the comparison result is input to the determination unit 24 together with the output from the protection unit 23. The output signal from the protection unit 23 is input to the selector 25 together with the output from the shift unit 21, and one of them is selected and input to the delay unit 16 by the output from the determination unit 24.
[0019]
Note that the output pulse of the VCO 12 and the frame pulse synchronized with the data input are input to the read pulse generation unit 13 in the same manner as in the related art.
[0020]
1 will be described below with reference to the timing chart of FIG. 2A illustrates a write input pulse input to the delay unit 15, the VCO 12, and the shift unit 21. FIG. (B) is a write pulse delayed by the delay unit 15 and input to the memory 10. (C) is a write shift pulse shifted by the shift unit 21. (D) is a VCO output clock input from the VCO 12 to the read pulse generation unit 13. (E) is a generated pulse output from the read pulse generating unit 13. (F) is a control unit output pulse output from the read pulse control unit 20. (G) is a read pulse delayed by the delay unit 16 and input to the memory 10. (H) is a comparison signal output from the comparison unit 22.
[0021]
First, an operation until a read pulse (see FIG. 2 (g)) is generated will be described by taking power supply on (ON) as an example. When the power is turned on, the VCO 12 generates an output clock (see (d) of FIG. 2). Based on this, a generation pulse (see (e) of FIG. 2) having a cycle set by the read pulse generation unit 13 is generated. However, since it takes time to output a stable output clock, the VCO 12 outputs an unstable output clock immediately after power-on. As a result, the generated pulse (e) from the read pulse generating unit 13 is not stable in synchronization and becomes an unstable pulse as shown. Therefore, it is difficult to read data from the memory 10.
[0022]
Therefore, until the generated pulse (e) becomes stable, the write shift pulse (c) obtained by shifting the write input pulse (a) to the position and cycle set by the read pulse generator 13 by the shift unit 21 is read pulse. The selector 25 selects the control section output pulse (f) from the control section 20. It should be noted that the write shift pulse (c) is a stable pulse synchronized with the data input, so that the memory 10 cannot read data.
[0023]
Next, whether or not the generated pulse (e) is stable is determined by comparing the write shift pulse (c) with the generated pulse (e) in the comparing unit 22. Further, in order to avoid accidental coincidence between the write shift pulse (c) and the generated pulse (e), the protection unit 23 confirms the coincidence n times (n = 1 to ∞) continuously, and the judgment unit 24 When the conditions of the comparison unit 22 and the protection unit 23 match, it is determined that the generated pulse (e) is stable. When the stability of the output clock (d) of the VCO 12 is confirmed, the determination unit 24 outputs a switching signal to the selector 25, and outputs the determination pulse from the protection unit 23 to the delay unit 16 as a control unit output pulse (f). I do.
[0024]
However, in this state, it is necessary to wait for the determination by the determination unit 24, for example, when the normally operating read pulse suddenly becomes unstable. Therefore, occurrence of a data error triggers read pulse control. As a countermeasure, delays 15 and 16 are provided to delay writing and reading to and from the memory 10 in advance, and to control a reading pulse before a data error occurs (reading is impossible), thereby avoiding a data error. .
[0025]
The preferred embodiment of the clock transfer method according to the present invention has been described above. However, it should be understood that the present invention should not be limited to only such specific examples, and that various modifications can be made without departing from the spirit of the present invention.
[0026]
【The invention's effect】
As can be understood from the above description, according to the clock transfer method of the present invention, by controlling the read pulse, it is possible to always read data from the memory with a stable read pulse having sufficient protection in front and rear. is there. In addition, since the read pulse is controlled before a data error occurs, a data error can be avoided.
[Brief description of the drawings]
FIG. 1 is a block diagram of a preferred embodiment of a clock transfer method according to the present invention.
FIG. 2 is an operation timing chart of the clock transfer method of FIG. 1;
FIG. 3 is a block diagram of a conventional clock switching method.
[Explanation of symbols]
10 Memory 12 VCO
13 Read pulse generator 15, 16 Delay unit 20 Read pulse controller 21 Shift unit 22 Comparison unit 23 Protection unit 24 Judgment unit 25 Selector

Claims (3)

In a clock transfer method having a VCO that receives a write input pulse to a memory and generates an output clock and a read pulse generation unit that generates a read pulse,
A shift unit that shifts the write input pulse for a predetermined time; an instability determining unit for a generated pulse of the read pulse generating unit; and a comparing unit that compares the write shift pulse and a generated pulse from the read pulse generator. A read pulse control unit is provided,
A clock switching method, wherein a write shift pulse of the shift unit is used as a read pulse of the memory during the unstable period. The clock switching method according to claim 1, further comprising a delay unit that delays the write input pulse and the output pulse of the read pulse control unit . The clock switching system according to claim 1, wherein the read pulse control unit includes a protection unit that checks the number of matches in the comparison unit .

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