JPH0366239A - Slip control circuit for elastic storage - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to a slip control circuit in an elastic store that changes the operating clock of data.

The purpose is to reliably prevent the collision by changing the read timing to an appropriate position when a collision occurs between the write timing and the read timing.

The elastic stored memory includes an elastic stored memory, a write timing generation circuit, and a read timing generation circuit, and reads a read signal synchronized with a second clock frequency from the elastic stored memory in which input data synchronized with the first clock frequency is written. In the elastic store that reads and outputs data written by the elastic store, a collision detection circuit detects a collision between write timing and read timing in the elastic store memory, and a predetermined pulse is generated in response to a collision detection signal from the collision detection circuit. The device includes a mask signal generation circuit that generates a mask signal of a certain width, and a gate circuit that uses the mask signal to mask the supply of an operation clock to the read timing generation circuit when a collision is detected.

[Industrial Application F] The present invention is based on elastic stored memory (hereinafter referred to as ES).
The present invention relates to an elastic store that uses a memory (referred to as a memory) to change the operating clock of input data, and particularly relates to a slip control circuit that prevents slip phenomena such as reading data twice or destroying data from occurring.

Slip phenomena, such as reading input data twice or missing data, occur when the write timing and read timing collide in the ES memory. This occurs when frequency synchronization is lost between the two.

As one method for avoiding this slip, for example, an elastic store circuit having a parallel configuration having two ES memories is known. In the elastic 31 to 31, when a conflict occurs between the write timing and the read timing, it is necessary to reliably perform slip control to avoid slip by changing the read timing.

[Prior Art] An example of the configuration of a conventional elastic store is shown in FIG. In FIG. 5, ■, 2 is an ES memory, 3 is a write timing generation circuit, 4 is a read timing generation circuit,
5 is a prohibited area signal generation circuit, and 6 is a phase comparator.

The write timing generation circuit 3 includes a flip-flop 31
．． It is composed of gates 32 and 33, into which a write reset signal WR is input, and based on this write reset signal WR, a write reset signal W for the ES memory 1.2 is generated.
RI, WR2 and write inhibit signal WI 1. Generates WI2. These signals are generated in such a way that while the write data WD is being written to one ES memory, data writing to the other ES memory is prohibited, so that the write data WD is not stored in ESI and ES2. are written alternately.

The read timing generation circuit 4 has the same configuration as the write timing generation circuit 3, and includes flip-flops 41 .
Includes gates 42.43. This read timing generation circuit 4 splits the read reset signal RR into two and inputs one as the select clock SC to the clock terminal C of the flip-flop 41, so that the output terminal Q,
Read inhibit signals R whose phases are opposite to each other from Q
II, RI2, and these read inhibit signals R11, R
By alternately opening the gates 42.43 using I2, the read reset signal RR is alternately output from the gate 42.43, and the read reset signal RRI,
It is configured to be supplied as RR2.

Here, the frequency fl of the write clock WC on the write side and the frequency f2 of the read clock RC on the read side are frequencies that are out of phase (cannot be guaranteed), but are synchronized on average. That is, when looking at the frequency f2 from the frequency fl, it has a jitter component.

The prohibited area signal generation circuit 5 is a circuit that generates a prohibited area signal IE having a predetermined pulse width that is phase-synchronized with the write reset signal WR2 to the ES memory 2. This prohibited area signal I
E is for changing the generation timing of the read reset signal RR2 when the read reset signal RR2 enters this signal region.

The phase comparator 6 is a circuit that compares the phases of the prohibited area signal IE and the read reset signal R'R2 and generates a collision detection signal COL if the phases of the two match (that is, a collision between the write timing and the read timing occurs). This collision detection signal C0L is input to the reset terminal R of the flip-flop 41.

The operation of this conventional elastic store will be explained below with reference to the drawings. Here, FIG. 6 is a time chart of signals of various parts during normal operation of the elastic store shown in FIG. 5, and FIG. 7 is a time chart when a collision occurs.

In the elastic store shown in FIG. 5, two E
The clocks are switched using the S memories 1 and 2.

That is, on the write side, write reset signals WRI and WR2 are alternately output from write reset signal WR.
and write inhibit signals Wll and WI2 having mutually opposite phases are generated and supplied to the ES memory 1.2, respectively. E
S memory 1.2 has its address reset by write reset signals WRI and WR2, and write inhibit signal WII.
, W2 are alternately set to a write-inhibited state. As a result, the write data WD is sequentially written, for example, in 8-bit units, such as ES memory 1 → ES memory 2 → ES memory 1, while switching between the ES memories 1 and 2 alternately.

The operation on the read side is also similar, and the ES memory l and ES
The read data RD is sequentially read out while switching the memory 2.

For example, if the timings of the write reset signal WR2 and the read reset signal RR2 collide in the ES memory 2, write and read accesses to the same ES memory will be performed in the same manner, so that Data may be read twice or lost, resulting in data destruction.

To avoid this collision, if a collision occurs between write and read reset signals WR2 and RR2,
By generating the read reset signal twice in succession, the timings of both signals WR2 and RR2 are shifted. This is detected by the phase comparator 6 as the write reset signal W.
The prohibited area signal IE, which is phase-synchronized with R2, and the read reset signal RR2 are phase-compared, and when the two phases match, a collision detection signal COL is sent to the reset terminal R of the flip-flop 41 of the read timing generation circuit 4, and this flip-flop This is done by resetting step 41.

[Problem to be Solved by the Invention 1] The conflict avoidance operation between the write and read timings in the conventional elastic store described above is 9.For example, in FIG. 6, when the read reset signal RR2 approaches the prohibited area signal IE from the left side of the drawing, is performed normally.

However, as shown in FIG. 7, when the read reset signal RR2 approaches the inhibition signal IE from the right side of the drawing, collision avoidance does not operate normally.

That is, in this case, even if the collision detection signal COL is reset inputted to the flip-flop 41, the polarity inversion timing of the read inhibit signals RII and RI2 does not change, and therefore the output timing of the read reset signals RR1 and RR2 also does not change. As a result, even though the timing of the readout reset signal RR2 should be changed so that it is output at the position indicated by the dotted line in FIG. 7 after a collision occurs, it still remains at the same timing as before. This continues to occur, and the collision state continues, resulting in data destruction and normal clock transfer.

Therefore, an object of the present invention is to provide a slip control circuit that can reliably avoid the collision by reliably changing the read timing to an appropriate position when a collision occurs between write and read timings.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

The elastic store slip control circuit according to the present invention includes an elastic stored memory 21, a write timing generation circuit 22, and a read 0 timing generation circuit 23, and input data synchronized with a first clock frequency is written. Collision detection detects a collision between write timing and read timing in the elastic stored memory, in which data written in the elastic stored memory is read and output using a read signal synchronized with a second clock frequency. circuit 24, and a mask signal generation circuit 25 that generates a mask signal of a predetermined pulse width in response to the collision detection signal from the collision detection circuit 24.

A gate circuit 26 is provided for masking the supply of an operating clock to the read timing generation circuit 23 using a mask signal when a collision is detected.

[Operation] When a collision occurs between write timing and read timing in the elastic stored memory 21, this collision state is detected by the collision detection circuit 24, and masked by the mask signal generation circuit 25 by the collision detection signal outputted thereby. A signal is generated. This mask signal closes the gate circuit 26 and temporarily cuts off the supply of the select clock to the read timing generation circuit 23, thereby changing the generation timing of the read timing signal output from the read timing generation circuit 23 to the elastic stored memory 21. is changed and the collision condition is avoided.

【Example] The present invention will be described in detail below with reference to nine drawings.

FIG. 2 shows a slip control circuit for an elastic store as an embodiment of the present invention.

In FIG. 2, ES memories 1, 2 . Write timing generation circuit 3. Read timing generation circuit 4. The prohibited area signal generating circuit 51 and the phase comparator 6 have the same structure as that described above as the prior art with reference to FIG.

The difference from the conventional elastic store is that the select clock SC input to the read timing generation circuit 4 delays the read reset signal RR by a predetermined time via the delay circuit 10. 9 to the clock terminal C of the flip-flop 41 of the read timing generation circuit 4. Here, the delay circuits 10 and 11 are composed of shift registers. Further, the collision detection signal COL from the 9-phase comparator 6 is inputted to the clock terminal CK of the flip-flop 6 via the inverter 7, and the output Q of this flip-flop 8 is inputted to the gate 9 as the clock mask signal CM. , the opening and closing of the gate 9 can be controlled. In addition, the reset of the flip-flop 8 is as follows.
This is executed by inputting the output signal QH of the delay circuit 11 to the reset terminal R as the clock mask clear signal C'MC.

The operation of the embodiment circuit will be explained below with reference to the drawings. FIG. 3 is a time chart of the signals of each part during normal operation in the circuit of the embodiment, and FIG. 4 is a time chart of the signals of each part when a collision occurs.

During normal operation, the read reset signal RR is delayed for a predetermined time by the delay circuit 10.11, and then input as the select clock SC to the flip-flop 41 of the read timing generation circuit 4 via the gate 9.
As a result, the read inhibit signals RII, R, I2 from the output terminals Q, Q of the flip-flop 41 are inverted and output.

Then, the gates 42 and 43 are opened alternately by the read inhibit signals R11 and RI2, and the read reset signal RR
sends reset signals RRI and R to ES memories 1 and 2, respectively.
Supplied as R2.

Next, what happens when a collision occurs will be explained. It is now assumed that the write timing and the read timing in the ES memory 2 are the same, and a timing conflict has occurred. This collision is detected by the phase comparator 6 and a collision detection signal COL is generated. This collision detection signal COL is input to the clock terminal GK of the flip-flop 8 via the inverter 7, so that the flip-flop 8 receives the collision detection signal Co
13 4 By detecting the falling edge of L, the signal is output from the output terminal.
Generates a clock mask signal CM of H” level (fourth
(See figure ■). This clock mask signal CM closes the gate 9 to mask the select clock SC (see FIG. 4), and the supply of the select clock SC to the read timing generating circuit 4 is cut off.

As a result, the polarity of the read inhibit signals RII and RI2, which are the outputs Q and Q of the flip-flop 41, is not inverted, and therefore, the read reset signal RR inputted to the ninth order is read out and reset to the ES memory 2 via the gate 43 again. It is input as signal RR2 (see ◎ in Figure 4). That is,
The read reset signal RR2 is input to the ES memory 2 twice in succession, and the timing of generation of the read reset signal RR2 changes with respect to the write reset signal WR2.

After this, the flip-flop 8 receives the read reset signal R
It is cleared by the clock mask clear signal CMC generated by shifting R with the shift register 11 (the fourth
(See Figure ■), and from then on, normal operation will occur.

Various modifications are possible in implementing the invention. For example, in the above embodiment, 2 ports h are used as ES memory.
Although a parallel configuration of two RAMs is used, the present invention is not limited to this.

The ES memory may be configured with one 2-point RAM.

[Effects of the Invention] According to the present invention, when the write timing and the epsilon output timing collide, the read timing can be reliably changed to an appropriate position, thereby ensuring that data destruction due to slips does not occur. can be prevented.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a block diagram showing a slip control circuit of an Elaste 56 IC store as an embodiment of the present invention. FIG. 3 is a time chart of signals of various parts during normal operation in the circuit of the embodiment. FIG. 4 is a time chart of signals of various parts when a collision occurs in the circuit of the embodiment. FIG. 5 is a block diagram showing a conventional example of a slip control circuit for an elastic store. FIG. 6 is a time chart of signals of various parts during normal operation in a conventional circuit; FIG. 7 is a time chart of signals of various parts when a collision occurs in a conventional circuit. In fig. 1.2 ES memory 3 Write timing generation circuit 4 Read timing generation circuit 5 Prohibited area signal generation circuit 6 Phase comparator 7 Inverter 8.31.41 ---Flip-flop9.32.33
, 42.43... Gate 10.11... Shift register WR, WRl, WR2... Write reset signal WII
, WI2...Write inhibit signal RR, RRI, RR2...Read reset signal RII
, RI2-... Read inhibit signal SC... Select clock CM... Clock mask 0 bow CMC... Clock mask clear signal 7 8 tr ) Unexamined Japanese Patent Publication No. 3 66239 (9) Time chart of the 4-leg example circuit (when the eaves were broken) 331-

Claims (1)

[Claims] An error storage system comprising an elastic stored memory (21), a write timing generation circuit (22), and a read timing generation circuit (23), in which input data synchronized with a first clock frequency is written. In an elastic store that reads and outputs written data from a stick stored memory using a read signal synchronized with a second clock frequency, a collision detection circuit detects a collision between write timing and read timing in the elastic stored memory ( 24), a mask signal generation circuit (25) that generates a mask signal of a predetermined pulse width in response to a collision detection signal from the collision detection circuit (24), and a mask signal generation circuit (25) that generates a mask signal of a predetermined pulse width in response to a collision detection signal from the collision detection circuit (24); A slip control circuit for an elastic store, comprising a gate circuit (26) that masks the supply of an operating clock using the mask signal.