JPH0332086B2 - - Google Patents

Description

TECHNICAL FIELD The present invention relates to a clock control circuit in a digital control device, and more particularly to clock stop detection and clock switching control.

Prior Art In recent years, significant advances in semiconductor integrated circuits have been made, particularly as the capacity of memory integrated circuits has increased, resulting in smaller memories and lower unit costs per bit.As a result, large-scale external storage devices called electronic disks have become popular. started to be used. This is a memory device using a semiconductor integrated circuit and operates at high speed, and data transfer between the memory device and the input/output device is most appropriately performed in a clock-synchronous manner. In order to transfer data in a clock-synchronous manner, it is necessary to receive a clock from the input/output device and operate based on that clock. However, if the external storage device is designed to operate only with the clock supplied from the input/output device, when the input/output device clock stops, the operating clock of the external storage device will stop, causing the storage The refresh operation of the element becomes impossible, resulting in an inexpensive dynamic
There is a problem that RAM cannot be adopted. Conventionally, when the clock of an input/output device stops, a clock stop signal is sent from the input/output device to the external storage device, and when the external storage device receives the above signal, it switches to its own internal clock and performs a refresh operation. We are making it possible for this to continue. However, if the clock supply is stopped without notification by a clock stop signal due to a failure in the clock system of the input/output device, the refresh operation will stop and the stored information will be lost. As mentioned above, in the conventional clock switching method in which clock switching is performed using an external switching control signal (see Japanese Patent Publication No. 54-26343, Clock Switching Control Method, etc.), information can be lost due to failure of the switching control signal, etc. There is a risk that

OBJECT OF THE INVENTION The object of the invention is to solve the above-mentioned conventional drawbacks and
A clock that monitors the clock itself supplied from an input/output device, automatically detects when the clock has stopped, and can switch to its own built-in clock when the externally supplied clock stops. The purpose is to provide a control circuit.

Structure of the Invention The clock control circuit of the present invention includes a first delay circuit that delays a first clock, and a first flip-flop that holds and outputs the first clock using the output of the first delay circuit. , a second delay circuit that further delays the output of the first delay circuit, a second flip-flop that holds and outputs the first clock using the output of the second delay circuit; The output of the flip-flop and the first
an exclusive OR circuit that inputs the output of the flip-flop, a third delay circuit that delays a second clock that is input independently of the first clock, and an exclusive OR circuit that inverts the output of the exclusive logic circuit. a first synchronized flip-flop that holds and outputs the signal in synchronization with the output of the third delay circuit;
a gate opened by the output of the synchronized flip-flop to allow the second clock to pass; and a gate opened by the inverted output of the first synchronized flip-flop to allow the output of the exclusive OR circuit to pass. , a second synchronized flip-flop that holds and outputs the output of the gate in synchronization with a delayed signal of the first clock; an output of the second synchronized flip-flop and an inverted output of the first synchronized flip-flop; and a gate that is closed when both are "1" to allow the first clock to pass through, and when the first clock stops, the clock is switched to the second clock for output. do.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. That is, the first delay circuit 10 delays the first clock C ₁ inputted through the buffer 21, and the output of the first delay circuit 10 holds and outputs the first clock C ₁ . a first flip-flop 4 and the first delay circuit 10
a second delay circuit 11 that further delays the output of
, a second flip-flop 5 that holds and outputs the first clock _C1 by the output of the second delay circuit 11, and an output of the second flip-flop 5 and an output of the first flip-flop 4. , a third delay circuit 13 that delays the second clock C2 inputted via the buffer ₂₂ independently of the first clock, and flip-flops 8 and 9. a first synchronized flip-flop which is continuously connected and holds and outputs a signal obtained by inverting the output of the exclusive OR circuit 14 by an inverter 20 in synchronization with the output of the third delay circuit 13; a gate 18 opened by the output of the first synchronizing flip-flop to allow said second clock _C2 to pass;
Flip-flops 6 and 7 are continuously connected to a gate 15 which is opened by the inverted output of the synchronized flip-flop and passes the output of the exclusive OR circuit 14; a second synchronized flip-flop that holds and outputs the output of the gate 15 in synchronization with a signal obtained by delaying the first clock _C1 ; a gate 16 that outputs "1" when both outputs are "1"; and a gate 16 that is opened when the output of the gate 16 is "1" and outputs the first clock;
It is composed of a gate 17 that allows the clock C1 to pass through, and an OR circuit 19 _that allows the first clock C1 outputted from the gate ₁₇ or the second clock _C2 outputted from the gate 18 to pass through.

If the period of the first clock C ₁ is P ₁ and its high level time width (“1” period) is w ₁ , then
The delay time τ ₁ of the first delay circuit 10 is set to w ₁ +nP ₁ <τ ₁ <(n+1)P ₁ , and the delay time τ _{2 of the second delay circuit 11 is set to w 1 +nP 1 <τ 1 <(n+1)P 1} .
is set to satisfy (n+1)P ₁ <τ ₁ +τ ₁ <(n+1)P ₁ +w ₁ .

The delay time τ ₃ of the third delay circuit 13 is determined by w ₂ +nP ₂ <τ ₃ <(n+1), where the period of the second clock C ₂ is P ₂ and the time width of its high level is w ₂ . Set to satisfy P ₂ .

The delay time τ ₄ of the delay circuit 12 is set to w ₁ +nP ₁ <τ ₄ <(n+1)P ₁ . For simplicity, if n=0, then w ₁ <τ ₁ <P ₁ P ₁ <τ ₁ +τ ₂ <P ₁ +w ₁ w ₂ <τ ₃ <P ₂ w ₁ <τ ₄ <P ₁ . The fourth delay circuit 12 may be omitted, and the timing pulses may be supplied to the flip-flops 6 and 7 by the output of the first delay circuit 10.

In this embodiment, as described below, when the first clock _C1 stops, the gate 18 can be opened to output the second clock _C2 .

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2. FIG. 2 is a time chart showing signals of various parts in this embodiment. Now, the first clock C ₁ is set at time t ₁ as shown in FIG. 2A.
It is assumed that the _second clock _C2 is an independent clock that is input at almost the same period as the first clock _C1 , as shown in FIG.

When the first clock _C1 is input normally, as shown in FIG. Since the level is high as shown in Figure D, exclusive OR circuit 1
The output x of No. 4 is at a high level (E in the same figure). on the other hand,
Since the outputs of flip-flops 8 and 9 are both low level and the inverted output of flip-flop 9 is high level, the output of gate 15 is high level, and the output c of flip-flop 6 and the output d of flip-flop 7 are both high level. level (see F and G in the same figure). Therefore, gate 16
The output of becomes "1", gate 17 is opened,
Gate 18 is closed. That is, the second clock C ₂ is blocked by the gate 18, and the first clock C ₁ passes through the gate 17 and the OR circuit 19 to the clock signal 3.
It is output as .

Next, when the first clock C ₁ stops at time t ₁ , when the last clock is delayed by τ ₁ + τ ₂ and input to the clock input of the second flip-flop 5, the first clock C ₁ is 0", the output b of the second flip-flop 5 is inverted from "1" to "0" as shown in FIG. Therefore, the output x of the exclusive OR circuit 14 also changes from “1” to “0”.
(E in the same figure).

When the output x of the exclusive OR circuit 14 becomes "0", the output of the inverter 20 becomes "1", and the flip-flop 8 takes in the output of the inverter 20 by the output of the third delay circuit 13 and operates the flip-flop 8. The output e of the flip-flop 8 becomes "1", and then the output f of the flip-flop 9 becomes "1" (H,
(see I). The output f of flip-flop 9 is “1”
Then, the gate 18 is opened and the second clock _C2 is outputted as the clock signal 3 through the gate 18 and the OR circuit 19, as shown in FIG. On the other hand, the output of gate 15 is "0", but
Since the first clock _C1 does not appear at the output of the delay circuit 12, the flip-flops 6 and 7 continue to hold the previously held "1" (FIGS. F and G in the figure). However, since gate 16 is closed by the inverted output of flip-flop 9, gate 17 is closed. In addition, flip-flop 9
The point at which the output f becomes “1” is the second clock
Since _C2 is in the low level period, the clock pulse of the second clock _C2 (referring to the high level period) will be output from the beginning of the next clock pulse, and will be wider than usual. A narrow pulse is never output. Note that at this point, the first clock C ₁ has already stopped, so the second clock C ₂ is output at a certain interval after the first clock C 1 stops as the clock signal ₃ . Therefore, the clock signal 3 is not disturbed. Further, since the gate 17 is closed as described above, even if the first clock _C1 starts operating again at the above-mentioned switching point, it will not be output immediately, so the clock signal 3 will not be disturbed.

The operation of the first clock _C1 upon recovery is as follows. Now, when the first clock _C1 recovers at time _t2 , a trigger pulse is output from the delay circuit 12 with a delay of _τ4 , the flip-flop 6 takes in the output "0" of the gate 15, and the output of the flip-flop 6 is c changes from “1” to “0”, and then the output d of flip-flop 7 changes from “1” to “0”.
(Figure F and G). On the other hand, a trigger pulse is output from the second delay circuit 11 with a delay of τ ₁ +τ ₂ , and the output b of the second flip-flop 5 becomes “1”.
(D in the same figure), and the output x of the exclusive OR circuit 14 also becomes "1" (E in the same figure). As a result, the output of the inverter 20 becomes "0", the output e of the flip-flop 8 is inverted to "0" at the time of the output of the third delay circuit 13, and then the output e of the flip-flop 8 is inverted to "0".
The output f of is also inverted to "0" (H and I in the figure). When the output f of the flip-flop 9 becomes "0", the gate 18 closes and the second clock _C2 is blocked (J in the figure).

On the other hand, the inverted output of flip-flop 9 is “1”
Therefore, the output of the gate 15 also becomes "1". Thereafter, the flip-flop 6 takes in the output of the gate 15 by the output of the delay circuit 12, and the output c of the flip-flop 6 becomes "1", and then the output d of the flip-flop 7 also becomes "1" (F,
G). As a result, the output of the gate 16 becomes "1".
Then, gate 17 is opened and the first clock is opened.
_C1 is output as clock signal 3 through gate 17 and OR circuit 19 (J in the same figure). Since the time when the gate 17 opens is during the period when the first clock _C1 is at a low level, a narrow pulse is not output at the time of switching. As mentioned above, after the second clock _C2 is blocked by the gate 18, the first clock _C1 passes through the gate 17 after a certain period of time, so that the clock signal 3 is not disturbed and is The clock period is not shortened even temporarily.

In the above, the first clock _C1 stops at “0”,
We have explained the case where it starts operating again after that, but if the first clock _C1 stops at "1",
During the stop, the output a of the first flip-flop 4 becomes "1" and the output b of the second flip-flop 5 remains "1", so that the output x of the exclusive OR circuit 14 becomes "0". After that, the operation can be performed in the same manner as described above.

This embodiment does not require external switching control to switch the clock, so when the clock stops due to a failure of an external device, the clock stops itself and is reliably switched to another clock. It has the effect of being able to

Note that in the above, the settings of the delay times τ ₁ to τ ₄ , etc. are set to n=0.
However, if n is any integer, the same clock control as above is possible. However, the larger n is, the longer the time required from when the clock stops to when the clock is switched. Further, the delay time of the first delay circuit 10 is set as (n+1)P ₁ <τ ₁ <(n+1)P ₁ +w ₂ , and the delay time of the second delay circuit 11 is set as w ₁ +(n+1)P ₁ Even if it is set so that <τ ₁ +τ ₂ <(n+2)P ₁ , the relationship between the first and second flip-flops 4 and 5 is simply reversed, so it is clear that the operation will be the same as described above. It is.

If this circuit is applied to a large-scale external storage device, while the first clock supplied from the input/output device is stopped, the external storage device can continue the refresh operation using the built-in second clock. It is possible.

Effects of the Invention As described above, in the present invention, since the clock stop itself is detected and the clock is switched to another clock when the clock stops, there is no need for external clock switching control. This has the advantage that when the clock stops, it is possible to reliably switch to another clock.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a time chart showing various signals of the above embodiment. In the figure, 3: clock signal, 4: first flip-flop, 5: second flip-flop,
6 to 9: flip-flop, 10: first delay circuit, 11: second delay circuit, 12: fourth delay circuit, 13: third delay circuit, 14: exclusive OR circuit, 15 to 18: Gate, 19: OR circuit, 2
0: inverter, 21, 22: buffer.

Claims (1)

[Claims] 1: a first delay circuit that delays a first clock; a first flip-flop that holds and outputs the first clock using the output of the first delay circuit; a second delay circuit that further delays the clock; a second flip-flop that holds and outputs the first clock using the output of the second delay circuit; a third delay circuit that delays a second clock that is input independently of the first clock; and an exclusive OR circuit that inverts the output of the exclusive OR circuit. a first synchronization flip-flop that holds and outputs a signal in synchronization with the output of the third delay circuit; a gate that is opened by the output of the first synchronization flip-flop and allows the second clock to pass through; a gate that is opened by the inverted output of the first synchronized flip-flop and allows the output of the exclusive OR circuit to pass; and a gate that holds and outputs the output of the gate in synchronization with the delayed signal of the first clock. a second synchronized flip-flop;
A gate that is opened when the output of the second synchronized flip-flop and the inverted output of the first synchronized flip-flop are both "1" and allows the first clock to pass through. Clock control circuit.