JP3564946B2 - Flip chip mounting structure - Google Patents

Flip chip mounting structure Download PDF

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Publication number
JP3564946B2
JP3564946B2 JP15120297A JP15120297A JP3564946B2 JP 3564946 B2 JP3564946 B2 JP 3564946B2 JP 15120297 A JP15120297 A JP 15120297A JP 15120297 A JP15120297 A JP 15120297A JP 3564946 B2 JP3564946 B2 JP 3564946B2
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flip chip
chip mounting
warpage
mounting structure
ceramic multilayer
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JPH10340928A (en
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撤男 中野
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、フリップチップがセラミック多層基板上に実装されたフリップチップの実装構造に関する。
【０００２】
【従来の技術】
従来、フリップチップをはんだバンプを用いて基板上に実装し、その後、フリップチップと基板間に、はんだの熱疲労寿命を確保するため、補強用樹脂を注入するものが提案されている（特開平８−８３００号公報参照）。
このようなフリップチップの実装工程の一例を図２に示す。まず、図２（ａ）に示すように、セラミック多層基板１上の導体ランド２に、はんだペースト３を印刷する。次に、図２（ｂ）に示すように、バンプ電極５およびはんだバンプ６を有するフリップチップ４をセラミック多層基板１上にマウントする。この後、図２（ｃ）に示すように、リフロー処理を行ってはんだを溶融させ、導体ランド２とバンプ電極５とをはんだ７にて接続固定する。そして、洗浄を行った後、図２（ｄ）に示すように、フリップチップ４の側面１辺よりディスペンサを用いて補強用樹脂８を注入し、この後、補強用樹脂８を加熱硬化させる。
【０００３】
このようなフリップチップの実装構造において、補強用樹脂８の注入を良好に行うためには、セラミック多層基板１とフリップチップ４の間の注入口間隔を所定値以上に確保する必要がある。
従来、基板とフリップチップ間の間隔を所定値以上に確保する場合、フリップチップと基板間に間隔規定物を設けるもの（特開平４−８４４４８号公報、特開平４−６２９４５号公報参照）、フリップチップ実装時に外部からの力でフリップチップを押し上げてバンプを形成するもの（特開昭６２−１３９３８６号公報参照）、はんだバンプを高融点はんだと低融点はんだにて構成するもの（特開昭５９−５８８４３号公報参照）、あるいはフリップチップのバンプ電極の高さを高くするもの（特開平７−２１１７２２号公報参照）がある。
【０００４】
【発明が解決しようとする課題】
しかしながら、フリップチップと基板間に間隔規定物を設けるものは、間隔規定物を余分に必要とするとともに補強用樹脂との接合性に問題が生じる可能性があり、フリップチップ実装時に外部からの力でフリップチップを押し上げてバンプを形成するものは、そのための工程の追加および治具が必要になり、はんだバンプを高融点はんだと低融点はんだにて構成したり、フリップチップのバンプ電極の高さにするものは、はんだ材料、電極構成に特別の細工が必要となる。
【０００５】
本発明は上記問題に鑑みたもので、上記した従来のものとは異なる新規な構造にて、注入口間隔を確保することを目的とする。
【０００６】
【課題を解決するための手段】
本発明者は、フリップチップのバンプ電極の微細化、バンプ電極数の増加を図るため、バンプ電極のピッチ（バンプピッチ）が３００μｍでチップサイズが１０ｍｍ□（１０ｍｍ×１０ｍｍ）のフリップチップをセラミック多層基板に実装することを試みたところ、フリップチップを実装する領域（以下、フリップチップ実装部という）に局部的な反りが発生することを見い出した。
【０００７】
本発明者は、この局所的な反りについて検討を行った。セラミック多層基板を形成する場合、図３（ａ）に示すように、グリーンシート１０に、導体を充填したスルーホール１１を形成するとともに引出し配線１２を形成し、各グリーンシート１０を積層した後、焼成を行うが、焼成初期の段階では、図３（ｂ）に示すように、２層目の引出し配線１２が図中の矢印のように収縮しはじめ、引出し配線１２のない部分のグリーンシート１０が押し出され反りが発生する。また、焼成の最終段階では、図３（ｃ）に示すように、グリーンシート１０が収縮しはじめるが、このときには引出し配線１２はすでに固くなりはじめているので、フリップチップ実装部には図に示すような大きな凸状のドーム型の反り１ａが発生する。
【０００８】
このような反り１ａが形成された場合、補強用樹脂がフリップチップの中央部に入りにくくなるため、何らかの方法で注入口間隔を大きくする必要がある。
本発明者は、さらに、反り１ａについて鋭意検討をした結果、２層目の引出し配線１２の配線密度を調節することにより、反り１ａの高さを調節できることを見い出した。すなわち、図４に示すように、導体ランド２をフリップチップ実装部１３の外周に形成し、その引き出し配線１２を、それぞれの導体ランド２から外方に形成した場合、導体ランド２で囲まれた領域の内側には、引き出し配線１２が形成されていないため、セラミック多層基板１の焼成時に、フリップチップ実装部１３において大きな収縮が生じ、反り１ａの高さを大きくすることができる。なお、導体ランド２としては、上述したフリップチップの場合、フリップチップ実装部１３の外周に１００程度形成することができる。
【０００９】
図５に、上述した場合のフリップチップ実装部１３の反り１ａを、３次元レーザ変位計を用いて測定した結果を示す。フリップチップ実装部１３の中央部で４０μｍ程度の反りが発生していることが分かる。
なお、反り１ａを大きくするためには、２層目の引出し配線１２のみならず、３層目以下の引出し配線においても導体ランド２で囲まれた領域の内側に形成しないようにするのが好ましい。
【００１０】
本発明者は、上述した検討を基に、補強用樹脂の注入に妨げとなっていた反り１ａを、逆に、注入口間隔を規定する間隔規定物として利用することを着想し、本発明を想到するに至った。
すなわち、本発明の特徴とするところは、請求項１に記載したように、セラミック多層基板（１）におけるフリップチップ実装部（１３）に形成される反り（１ａ）を、補強用樹脂（８）の注入口の間隔を規定する高さにしたことを特徴としている。
【００１１】
従って、従来のもののように余分な間隔規定物を設けることなく、所望の注入口間隔を確保して、補強用樹脂を良好に注入することができる。
この場合、請求項２に記載したように、反り（１ａ）は、フリップチップ（４）の下面と当接する高さになっているのが好ましい。
また、具体的には、請求項３に記載したように、バンプ電極（５）のピッチが３００μｍ以下の場合に、反り（１ａ）を４０μｍ以上の高さにすれば、補強用樹脂の注入を良好に行うことができる。
【００１２】
【発明の実施の形態】
以下、本発明を図に示す実施形態について説明する。
図１に、フリップチップ実装部１３において、フリップチップ４をセラミック多層基板１にマウントし、リフロー処理を行った後、補強用樹脂８を注入する工程を示す。
【００１３】
図１（ａ）の工程においては、フリップチップ４をセラミック多層基板１にマウントする。セラミック多層基板１には、図３、図４で示したように、導体が充填されたスルーホール１１および引出し配線１２により内部配線が形成されており、セラミック多層基板１上には導体ランド２が形成されている。フリップチップ４は、１０ｍｍ□サイズのもので、その下面外周部には３００μｍのピッチで等間隔に複数のバンプ電極５が形成されている。また、バンプ電極５には、はんだバンプ６が形成されている。
【００１４】
また、セラミック多層基板１には、高さ約４０μｍの反り１ａが形成されている。ここで、バンプ電極５、はんだバンプ６、導体ランド２、はんだペースト３のそれぞれの厚さの合計は、４０μｍより大きく設定されており、このため、フリップチップ４をセラミック多層基板１にマウントしたとき、フリップチップ４と反り１ａの間には、図に示すように隙間が生じている。
【００１５】
次に、図１（ｂ）の工程において、リフロー処理を行う。このリフロー処理によって、はんだ３、６を溶融・硬化させ、バンプ電極５と導体ランド２とを、はんだ７により接続固定する。この場合、はんだ３、６の溶融によって、フリップチップ４がセラミック多層基板１側に下がり、フリップチップ４の下面と反り１ａの上部とが当接する。従って、フリップチップ４とセラミック多層基板１間の注入口間隔ｈが、反り１ａの高さである約４０μｍになる。
【００１６】
そして、洗浄を行った後、図１（ｃ）に示すように、フリップチップ４とセラミック多層基板１の間に、ガラスフィラー入りの補強用樹脂８を注入する。
この場合、注入口間隔ｈが約４０μｍ以上であれば、補強用樹脂８を良好に注入できることが確認できているので、反り１ａにより注入口間隔ｈを約４０μｍに規定することによって、従来のもののように余分な間隔規定物を設けることなく、所望の注入口間隔ｈを確保して、補強用樹脂８を良好に注入することができる。
【００１７】
このようにして、補強用樹脂８が注入されたフリップチップの実装構造が得られる。
なお、上述した実施形態において、反り１ａの高さは、バンプ電極５と導体ランド２の高さの和より大きければ、注入口間隔ｈを所望の値に確保することができる。この場合、反り１ａは、フリップチップ４の下面と反り１ａの上部とが当接する高さになるのが好ましいが、反り１ａによって注入口間隔ｈを規定することができれば、必ずしもフリップチップ４の下面と反り１ａの上部とが当接していなくてもよい。
【００１８】
また、フリップチップ４において、バンプピッチが小さくなるほどバンプ電極５が微細化し注入口間隔ｈが小さくなるので、バンプピッチが３００μｍより小さい場合でも、注入口間隔ｈが４０μｍより大きくなるように、反り１ａの高さを設定すれば、補強用樹脂８を良好に注入することができる。
また、バンプ電極５と導体ランド２を電気的に接続固定する場合、はんだバンプ６、はんだペースト３を用いて行うものを示したが、それ以外の接続材料を用いて行うようにしてもよい。例えば、はんだバンプ６、はんだペースト３に代わりに導電性接着剤として銀ペーストを用いることができる。
【図面の簡単な説明】
【図１】本発明の一実施形態における、フリップチップ実装部の実装工程を示す図である。
【図２】フリップチップの全体の実装工程を示す図である。
【図３】セラミック積層基板１の焼成時に局部的な反りが発生することを説明するための図である。
【図４】導体ランド２と引き出し配線１２の平面的な形成状態を示す図である。
【図５】３次元レーザ変位計を用いてフリップチップ実装部における反りの状態を測定した結果を示す図である。
【符号の説明】
１…セラミック多層基板、１ａ…反り、２…導体ランド、
４…フリップチップ、５…バンプ電極、７…はんだ、８…補強用樹脂、
１３…フリップチップ実装部。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a flip chip mounting structure in which a flip chip is mounted on a ceramic multilayer substrate.
[0002]
[Prior art]
Conventionally, a method has been proposed in which a flip chip is mounted on a substrate using solder bumps, and then a reinforcing resin is injected between the flip chip and the substrate in order to secure the thermal fatigue life of the solder (Japanese Patent Application Laid-Open No. HEI 9-163568). 8-8300).
FIG. 2 shows an example of such a flip chip mounting process. First, as shown in FIG. 2A, the solder paste 3 is printed on the conductor lands 2 on the ceramic multilayer substrate 1. Next, as shown in FIG. 2B, the flip chip 4 having the bump electrodes 5 and the solder bumps 6 is mounted on the ceramic multilayer substrate 1. Thereafter, as shown in FIG. 2C, a reflow process is performed to melt the solder, and the conductor land 2 and the bump electrode 5 are connected and fixed by the solder 7. Then, after the cleaning, as shown in FIG. 2D, the reinforcing resin 8 is injected from one side of the flip chip 4 using a dispenser, and then the reinforcing resin 8 is cured by heating.
[0003]
In such a flip-chip mounting structure, in order to inject the reinforcing resin 8 satisfactorily, it is necessary to secure a gap between the injection ports between the ceramic multilayer substrate 1 and the flip chip 4 to a predetermined value or more.
Conventionally, when a gap between a substrate and a flip chip is secured to a predetermined value or more, a gap regulating member is provided between the flip chip and the substrate (see JP-A-4-84448 and JP-A-4-62945). A method in which a flip chip is pushed up by an external force during chip mounting to form a bump (see Japanese Patent Application Laid-Open No. Sho 62-139386), and a method in which a solder bump is composed of a high melting point solder and a low melting point solder (Japanese Patent Application Laid-Open No. 59-1984). Japanese Unexamined Patent Application Publication No. 7-211722), or a method in which the height of a flip chip bump electrode is increased (see Japanese Patent Application Laid-Open No. 7-211722).
[0004]
[Problems to be solved by the invention]
However, a device having a spacing member between the flip chip and the substrate requires an extra spacing member and may have a problem in bonding with the reinforcing resin. In the case of forming a bump by pushing up a flip chip, additional steps and jigs are required for this, and solder bumps may be composed of high melting point solder and low melting point solder, or the height of flip chip bump electrodes Requires special work for the solder material and the electrode configuration.
[0005]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to secure an injection port interval with a novel structure different from the above-described conventional one.
[0006]
[Means for Solving the Problems]
In order to miniaturize the bump electrode of the flip chip and increase the number of bump electrodes, the present inventor used a flip chip having a bump electrode pitch (bump pitch) of 300 μm and a chip size of 10 mm □ (10 mm × 10 mm) as a ceramic multilayer. An attempt was made to mount it on a substrate, and found that local warpage occurred in a region where a flip chip was mounted (hereinafter, referred to as a flip chip mounting portion).
[0007]
The inventor has studied this local warpage. In the case of forming a ceramic multilayer substrate, as shown in FIG. 3A, a through hole 11 filled with a conductor is formed in a green sheet 10 and a lead wiring 12 is formed. In the initial stage of firing, as shown in FIG. 3B, the second-layer lead wiring 12 starts to shrink as indicated by the arrow in the figure, and the green sheet 10 in a portion where there is no lead wiring 12 is provided. Are extruded and warpage occurs. Also, at the final stage of firing, as shown in FIG. 3C, the green sheet 10 starts to shrink, but at this time, the extraction wiring 12 has already begun to harden. A large convex dome-shaped warpage 1a occurs.
[0008]
When such a warp 1a is formed, it becomes difficult for the reinforcing resin to enter the central portion of the flip chip, and it is necessary to increase the gap between the injection ports by some method.
The inventor has further studied the warpage 1a and found that the height of the warpage 1a can be adjusted by adjusting the wiring density of the second-layer lead wiring 12. That is, as shown in FIG. 4, when the conductor lands 2 are formed on the outer periphery of the flip chip mounting portion 13 and the lead-out wirings 12 are formed outward from the respective conductor lands 2, they are surrounded by the conductor lands 2. Since the lead-out wiring 12 is not formed inside the region, a large shrinkage occurs in the flip chip mounting portion 13 when the ceramic multilayer substrate 1 is fired, and the height of the warpage 1a can be increased. In the case of the flip chip described above, about 100 conductor lands can be formed on the outer periphery of the flip chip mounting portion 13.
[0009]
FIG. 5 shows a result of measuring the warpage 1a of the flip chip mounting portion 13 in the case described above using a three-dimensional laser displacement meter. It can be seen that warpage of about 40 μm has occurred at the center of the flip chip mounting part 13.
In order to increase the warpage 1a, it is preferable that not only the second-layer lead wiring 12 but also the third-layer and lower lead wiring are not formed inside the region surrounded by the conductor land 2. .
[0010]
The present inventor has conceived of using the warpage 1a, which has hindered the injection of the reinforcing resin, on the contrary, as an interval regulating member for defining an injection port interval, based on the above-described study, and has developed the present invention. I came to imagination.
That is, the feature of the present invention is that, as described in claim 1, the warpage (1a) formed in the flip chip mounting portion (13) of the ceramic multilayer substrate (1) is reduced by the reinforcing resin (8). The height is defined to define the interval between the injection ports.
[0011]
Accordingly, a desired injection port interval can be ensured and a reinforcing resin can be injected well without providing an extra interval defining material unlike the conventional one.
In this case, as described in claim 2, it is preferable that the warp (1a) has a height which is in contact with the lower surface of the flip chip (4).
Further, specifically, when the pitch of the bump electrodes (5) is 300 μm or less and the warpage (1a) is set to a height of 40 μm or more, the injection of the reinforcing resin is performed. Can be performed well.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention shown in the drawings will be described.
FIG. 1 shows a process in which the flip chip 4 is mounted on the ceramic multilayer substrate 1 in the flip chip mounting section 13, a reflow process is performed, and the reinforcing resin 8 is injected.
[0013]
In the step of FIG. 1A, the flip chip 4 is mounted on the ceramic multilayer substrate 1. As shown in FIGS. 3 and 4, the ceramic multi-layer substrate 1 has an internal wiring formed by a through hole 11 filled with a conductor and a lead-out wiring 12, and a conductor land 2 is formed on the ceramic multi-layer substrate 1. Is formed. The flip chip 4 has a size of 10 mm square, and a plurality of bump electrodes 5 are formed at equal intervals at a pitch of 300 μm on the outer peripheral portion of the lower surface. Further, a solder bump 6 is formed on the bump electrode 5.
[0014]
The ceramic multilayer substrate 1 has a warp 1a having a height of about 40 μm. Here, the sum of the respective thicknesses of the bump electrode 5, the solder bump 6, the conductor land 2, and the solder paste 3 is set to be larger than 40 μm. Therefore, when the flip chip 4 is mounted on the ceramic multilayer substrate 1, A gap is formed between the flip chip 4 and the warp 1a as shown in FIG.
[0015]
Next, a reflow process is performed in the step of FIG. By this reflow treatment, the solders 3 and 6 are melted and hardened, and the bump electrodes 5 and the conductor lands 2 are connected and fixed by the solders 7. In this case, the melting of the solders 3 and 6 causes the flip chip 4 to move down to the ceramic multilayer substrate 1 side, so that the lower surface of the flip chip 4 and the upper part of the warpage 1a come into contact. Therefore, the distance h between the injection ports between the flip chip 4 and the ceramic multilayer substrate 1 is about 40 μm, which is the height of the warpage 1a.
[0016]
After cleaning, a reinforcing resin 8 containing a glass filler is injected between the flip chip 4 and the ceramic multilayer substrate 1 as shown in FIG.
In this case, it has been confirmed that the reinforcing resin 8 can be satisfactorily injected when the inlet gap h is about 40 μm or more. As described above, the reinforcing resin 8 can be satisfactorily injected by securing a desired injection port interval h without providing an extra interval regulating member.
[0017]
In this way, a flip chip mounting structure into which the reinforcing resin 8 has been injected is obtained.
In the above-described embodiment, if the height of the warpage 1a is larger than the sum of the heights of the bump electrode 5 and the conductor land 2, the injection port interval h can be secured to a desired value. In this case, it is preferable that the warp 1a has a height at which the lower surface of the flip chip 4 and the upper portion of the warp 1a come into contact with each other. And the upper part of the warp 1a may not be in contact.
[0018]
Also, in the flip chip 4, the smaller the bump pitch, the finer the bump electrode 5 and the smaller the gap h between the inlets. Is set, the reinforcing resin 8 can be injected well.
In the case where the bump electrodes 5 and the conductor lands 2 are electrically connected and fixed, the solder bumps 6 and the solder paste 3 are used, but the connection may be performed using other connection materials. For example, a silver paste can be used as a conductive adhesive instead of the solder bumps 6 and the solder paste 3.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a mounting process of a flip-chip mounting unit according to an embodiment of the present invention.
FIG. 2 is a view showing an entire mounting process of the flip chip.
FIG. 3 is a diagram for explaining that local warpage occurs when the ceramic laminated substrate 1 is fired.
FIG. 4 is a diagram showing a planar formation state of a conductor land 2 and a lead wiring 12;
FIG. 5 is a diagram showing a result of measuring a state of warpage in a flip chip mounting portion using a three-dimensional laser displacement meter.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Ceramic multilayer board, 1a ... Warpage, 2 ... Conductor land,
4: Flip chip, 5: Bump electrode, 7: Solder, 8: Reinforcing resin,
13 ... Flip chip mounting part.

Claims (3)

フリップチップ（４）に形成された複数のバンプ電極（５）とセラミック多層基板（１）上に形成された複数の導体ランド（２）とをそれぞれ電気的な接続部（７）により固定し、前記フリップチップ（４）と前記セラミック多層基板（１）の間に補強用樹脂（８）を注入してなるフリップチップの実装構造において、
前記セラミック多層基板（１）上で前記フリップチップ（４）が実装される領域（１３）に、反り（１ａ）が形成されており、この反り（１ａ）は、前記補強用樹脂（８）の注入口の間隔を規定する高さになっていることを特徴とするフリップチップの実装構造。A plurality of bump electrodes (5) formed on the flip chip (4) and a plurality of conductor lands (2) formed on the ceramic multilayer substrate (1) are fixed by electric connection parts (7), respectively. In a flip chip mounting structure in which a reinforcing resin (8) is injected between the flip chip (4) and the ceramic multilayer substrate (1),
A warp (1a) is formed in an area (13) where the flip chip (4) is mounted on the ceramic multilayer substrate (1), and the warp (1a) is formed by the reinforcing resin (8). A flip-chip mounting structure characterized in that the height of the flip-chip is defined to define an interval between inlets. 前記反り（１ａ）は、前記フリップチップ（４）の下面と当接する高さになっていることを特徴とする請求項１に記載のフリップチップの実装構造。The flip chip mounting structure according to claim 1, wherein the warp (1a) has a height at which it contacts the lower surface of the flip chip (4). 前記バンプ電極（５）のピッチは３００μｍ以下であって、前記反り（１ａ）は、４０μｍ以上の高さになっていることを特徴とする請求項１又は２に記載のフリップチップの実装構造。The flip chip mounting structure according to claim 1, wherein a pitch of the bump electrodes is less than or equal to 300 μm, and the height of the warpage is greater than or equal to 40 μm.
JP15120297A 1997-06-09 1997-06-09 Flip chip mounting structure Expired - Fee Related JP3564946B2 (en)

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KR100636364B1 (en) 2005-04-15 2006-10-19 한국과학기술원 Bonding method for solder-pad in flip-chip package
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