JP3564111B2 - Erroneous output prevention device and vortex flowmeter provided with the device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a device for preventing erroneous output in a vortex flowmeter and a vortex flowmeter provided with the device.
[0002]
[Prior art]
Generally, a vortex flowmeter obtains a flow signal pulse by triggering a Karman vortex signal from a detection sensor with a trigger circuit. However, in the compressible fluid flow rate measuring mechanism, even when the shut-off valve provided on the downstream side or the upstream side of the flow meter is closed to stop the flow, the flow is stopped in the pipeline closed by the compressible fluid such as gas. The fluid compresses and expands, causing movement of the fluid.The flow detector detects the movement of the fluid, and the signal transmitter connected to the flow detector transmits a signal, as if the flow was measured. There is a disadvantage of becoming. In addition to the noise signal due to the fluid oscillation (pulsation), noise signals such as pipe vibration and electrical noise are large when the flow is stopped, regardless of the compressibility of the fluid, and the noise signal exceeds the trigger level. Even in the case of a pulse, it may be pulsed as a flow signal, and normal measurement may be disturbed. At this time, if an alarm device for the vortex flowmeter has been installed, an alarm will sound.
[0003]
These inconveniences are remarkably observed in a flow meter that has a wide flow rate range, such as a vortex flow meter, and that integrates and detects a flow rate according to the flow velocity of a fluid. In a conventional flow measuring device, a normal filter is disposed between a flow detecting unit in a pipeline and a signal unit (trigger) for generating a pulse signal in order to increase an S / N ratio (signal conditioner). However, since the filter is selected to cover the flow rate range, the above disadvantages are not solved. Such a phenomenon is not a problem when the shut-off valve is opened and the compressible fluid is continuously flowed and the flow rate is measured, but in fact, the shut-off valve is often closed most of the day. Therefore, the compressible fluid counts the pulsation in the pipeline as a flow rate. Although it is possible to suppress these noise triggers to some extent by increasing the trigger level, there is a problem that the flow rate range that can be measured is also reduced by increasing the trigger level.
[0004]
As a result of observing the state of counting by pulsation, the present applicant has generated a signal that enters the counting range in a very short time, and for example, when averaging a period of about 10 seconds, the frequency falls below the lower limit frequency of the filter. By paying attention, an erroneous counting preventing device for preventing erroneous counting due to the fluctuation of the fluid was proposed in Japanese Utility Model Publication No. 53-14199. The erroneous counting prevention device in the flow meter according to the present invention stores a signal between a signal transmission unit connected to a flow detection unit in a pipeline and transmitting a pulse signal and a counting mechanism that counts the signal and counts the flow rate. If the accumulation counter does not reach the set value within the set time of the timer by arranging the counter and the timer, the pulse signal is generated due to oscillation as apparent from the above, so that this erroneous pulse signal is cut off. The counter is not sent to the counting mechanism, and the counting mechanism does not start the accumulation depending on the oscillation of the fluid, thereby preventing erroneous measurement. In other words, this publication describes a digital filter that focuses on the fact that the cycle of erroneous output pulses due to noise or the like is generally irregular. Before the external output, input the pulse to the memory function, store a certain set pulse, and if the cycle of the input pulse is longer than a certain set cycle, reset the pulse in the memory. It has a function to prevent the output of irregular pulses.
[0005]
The digital filter circuit used in the vortex flowmeter, such as the erroneous counting prevention device described above, is a circuit for cutting and preventing a sensor from being mistriggered due to mechanical or electrical disturbance. Unless a certain number or more of the flow pulses having a period or more are detected continuously, the pulse is not transmitted to the subsequent circuit. That is, this digital filter circuit does not output a signal that does not continuously enter for a certain period or more as a noise signal, and is indispensable to a vortex flowmeter that is easily affected by disturbance.
[0006]
FIG. 5 is a block diagram showing a configuration of an erroneous output prevention device and a vortex flowmeter using the device according to the related art.
The vortex flowmeter according to the prior art described here includes a flow tube (measurement tube) 11 of the vortex flowmeter through which the fluid to be measured flows, and a vortex that is disposed inside the flow tube 11 so as to face the flow and generates Karman vortices. A vortex signal detector for detecting a Karman vortex signal generated by the vortex generator 12; and a converter for converting a signal detected by the vortex signal detector to output a pulse. By measuring, the flow rate or the flow velocity of the fluid to be measured is measured. In order to prevent erroneous output due to noise signals such as vibration, fluid pulsation, and electrical noise, an erroneous output prevention device (also referred to as an erroneous counting prevention device) 40 is provided in the converter. In the vortex signal detector, a vortex signal detection sensor 13 is disposed downstream of the vortex generator 12 and on the side surface of the vortex generator 12 or the inner wall of the flow tube 11. The vortex signal detection sensor 13 detects the vortex of the Karman vortex street generated by the vortex generator 12. By processing the Karman vortex signal from the vortex signal detection sensor 13 at a later stage, the flow rate or flow velocity is measured.
[0007]
The erroneous output preventing device 40 includes, as its configuration, a piezo-electric element, a strain, and the like, which detect a pressure change due to flow (naturally includes noise) as a stress change of the detection element as the vortex signal detection sensor 13. It is a device corresponding to one using a sensor such as a gauge. Other examples of the vortex signal detection sensor 13 include a sensor having a shuttle piston, a capacity sensor, or the like as a detection element, and any of the detection elements detects a pressure change and outputs (normally amplified by an amplifier 14 or the like). The configuration corresponds to a physical change of the detection element. Therefore, if the measurement is performed after pausing the measurement or stopping the flow, the measurement is started from the position at the time of the pause or stop.
[0008]
The Karman vortex signal from the vortex signal detection sensor 13 is output to a converter. The converter is a device that amplifies, shapes, converts a vortex signal obtained by the vortex signal detection sensor 13 into a pulse signal, and outputs it as an output signal. In the converter exemplified in FIG. 5, a bridge (not shown) connected to the vortex signal detection sensor 13 generates an alternating voltage of one cycle every time a pair of vortices is generated, and the voltage is amplified and transmitted by an amplifier (amplifier) 14. It is like that. Note that this bridge is required for a thermistor, but not required for a piezoelectric element. The alternating voltage signal amplified by the amplifier 14 is filtered and shaped by the filter circuit 15 to increase the S / N ratio and input to the erroneous output prevention device 40. It can also be said that a signal conditioner is formed by the filter circuit 15, the trigger circuit 16, and the erroneous output prevention device 40. Further, as will be described later, a pulse signal is generated by the erroneous output prevention device 40, its output is obtained, and the flow rate (or flow velocity) is calculated by the flow rate calculation circuit 17, so that the erroneous output prevention device 40 functions as a digital filter. I can say that.
[0009]
In the trigger circuit 16, when the output level from the eddy signal detection sensor 13 exceeds a predetermined trigger level, the signal (which may be a signal passed through the amplifier 14 and the filter circuit 15 as shown in the figure) is pulsed and input. Outputs a sine wave as a square wave.
[0010]
6 is a diagram showing an example of a signal starting from a low level in each stage of the erroneous output prevention device of FIG. 5. FIG. 6A shows an input signal b to the erroneous output prevention device, and FIG. 6C shows an input signal v to the logic IC, FIG. 6C shows an output signal w of the logic IC, FIG. 6D shows an input signal x to the integration circuit, and FIG. 6E shows an output signal of the integration circuit. FIG. 3 is a diagram showing y and an input signal z to the counter circuit. With reference to FIG. 6, a description will be given of a case where the measurement is started in a state where the phase of the detection element is at the low level.
[0011]
The example of FIG. 6A shows a case where the frequency of the pulse signal b output from the trigger circuit 16 and input to the erroneous output prevention device 40 gradually increases as time passes. The state often appears as a transient phenomenon when the measurement is restarted after the flow is stopped (stopped at the low state). In this example, the reference voltage of the erroneous output prevention device 40 is 3 V, and the voltage level of the trigger signal (often called a TRG signal) b output from the trigger circuit 16 is 0.2 (Low) to 2.4 (High). V, the bias voltage of the differential waveform is set to 1.3 V, and the comparator voltage in the comparator 45, which will be described later, depends on the output level from the comparator 45. The comparator voltage depends on the measurement from the Low level and the measurement from the High level. Shall be changed. A part of the pulse signal b is input to the differentiating circuit 41 and is differentiated there to become a signal v having a differentiated waveform. It should be noted that the signal v is actually a signal obtained by applying a bias voltage using a diode or the like and raising the signal. The signal v is input to the NAND logic IC 42, and the NAND of the signal v and the reference voltage (3V) is obtained as a pulse signal w. The signal w is a square wave having a voltage of 0 V at a portion corresponding to the rising portion of the TRG signal b and having a voltage of 3 V after a certain time determined by the time constant of the differentiating circuit 41. The signal w is a one-shot multi with a small width to facilitate the integration circuit 44. This square wave signal w is differentiated by a differentiating circuit 43 to obtain a pulse signal x having a differentiated waveform. Here, since the differential waveform is determined by the time constant of the differentiating circuit 43, the level difference x in the signal x is obtained. ₁ And level difference x ₂ Is determined by the frequency around the signal x, and the lower the frequency (the longer the period), the more time it takes to fall to a low level, so x ₁ <X ₂ It becomes. The pulse signal x is integrated by an integrating circuit 44 to obtain an integrated signal y, which is input to a comparator 45. The comparator voltage and the level of the input pulse signal y are compared by the comparator 45. A signal z having a square wave in which a portion exceeding the comparison voltage is set to 0V and a portion below the comparison voltage is set to 3V is obtained. As a result, the comparator 45 only falls below the compare voltage in a portion where a waveform having a certain period or more exists in the TRG signal b, and outputs a clear signal (CLR). This CLR signal is input to the counter circuit 31 and is used as a signal for resetting the count in the counter circuit 31. In the case of a signal other than the CLR signal, the counter circuit 31 remains active.
[0012]
The counter circuit 31 counts the pulse signal b output from the trigger circuit 16 by a clock input (CK) and accumulates the counted value. This count value is a value that is CLR by the output signal z from the comparator 45, and the TRG signal b having a certain period or more is excluded by the CLR signal. On the other hand, the count value is a value for determining whether or not the pulse signal b input from the trigger circuit 16 is accumulated by a predetermined value before being eliminated. The counter circuit 31 outputs a low value when the count value is not the predetermined value, and outputs a high value when the count value is the predetermined value.
[0013]
The pulse output means is a means capable of cutting off a noise signal to a counting mechanism such as the flow rate calculation circuit 17. As a result, only the pulse output from the pulse output means is used to determine the flow rate or the flow velocity of the fluid to be measured. It is possible to prevent erroneous counting of the counting mechanism by using it for the calculation. As the pulse output means, a means for opening the gate for the TRG signal b from the trigger circuit 16 with the output signal from the counter circuit 31 and outputting the TRG signal b to the flow rate calculation circuit 17 only when the count value is Full. Can be An example will be described below with reference to FIG.
[0014]
The NAND gate 33 is configured to invert the signal input from the counter circuit 31 and output the inverted signal regardless of whether the count value is Full based on the output of the counter circuit 31 or not. The NAND gate 32 is connected to the NAND gate 33 and the trigger circuit 16, and is configured to close the gate for the output from the trigger circuit 16 when the count value is Full by the output from the NAND gate 33. As a result, when the count value is full, the clock input (CK) of the counter circuit 31 stops, so that the counter circuit 31 keeps counting unless the CLR signal is input, that is, unless the TRG signal b becomes equal to or less than a certain period. Holds the state of the numerical value full. The NAND gate 34 is connected to the counter circuit 31 and the trigger circuit 16, and closes the gate for the output from the trigger circuit 16 when the count value is not Full, and opens the gate for the output from the trigger circuit 16 when the count value is Full. It is configured. With the above configuration, when the count value in the counter circuit 31 is less than the predetermined value, the output pulse from the trigger circuit 16 is not output (cut off). In this example, the output of the NAND gate 34 is always High when the count value is not Full, and the count in the subsequent flow rate calculation circuit 17 is disabled. On the other hand, when the count value in the counter circuit 31 has reached the predetermined value, the output pulse from the trigger circuit 16 can be output (inverted).
[0015]
[Problems to be solved by the invention]
The erroneous output prevention device as described above uses a differentiating circuit and inputs the output to a logic IC, so that the current consumption is large. Accordingly, the current consumption of a converter or eddy flow meter using such a device is increased. Becomes larger. In fact, it has been found that the converter in the conventional vortex flow meter consumes a large amount of current, and a considerable part of the current is occupied by the digital filter circuit.
[0016]
Further, in the above-mentioned conventional vortex flowmeter, the differentiating circuit 41, the logic IC 42, the differentiating circuit 43, and the integrating circuit 44 are F / V circuits, and output a voltage proportional to the frequency. The value may be compared with a comparator voltage to reset the counter of the counter circuit 31, but the current consumption is further increased as compared with the vortex flowmeter described above.
[0017]
In any case, the conventional digital filter circuit is composed of a combination of a differentiating circuit and a logic IC, and a combination of a one-shot IC and a V / F circuit by an integrating circuit. This has been a major obstacle in designing battery-powered converters. That is, the specification of the battery life had to be shortened.
[0018]
SUMMARY OF THE INVENTION The present invention has been made in view of the above situation, and has a simple component configuration and low current consumption, and can prevent erroneous counting (erroneous output) due to noise, and can prevent erroneous output in a vortex flowmeter. It is an object of the present invention to provide a device and a vortex flowmeter provided with the device.
[0019]
[Means for Solving the Problems]
A first technical means detects a vortex generated by a vortex generator provided in a flow tube in which a fluid to be measured flows in a flow tube so as to face the flow by a vortex signal detection sensor that detects a pressure change as a change in a detection element. An erroneous output prevention device in a vortex flowmeter for measuring a flow rate or a flow velocity of a fluid to be measured by measuring a signal detected by the vortex signal detection sensor, wherein a signal output from the vortex signal detection sensor is a predetermined value. A trigger circuit that outputs a pulse when the trigger level is exceeded, an integration circuit that integrates the pulse output from the trigger circuit, a signal integrated by the integration circuit as an input signal, and a voltage of the input signal. Two comparators that compare predetermined upper and lower limit voltages to form pulses and output the same, a counter circuit that counts pulses output from the trigger circuit, and the two comparators A logic IC for inputting both output pulses to perform a logical operation and outputting a signal relating to resetting of the count value in the counter circuit, and a trigger circuit when the count value in the counter circuit is less than a predetermined value. Pulse output means for outputting an output pulse from the trigger circuit when the count value in the counter circuit has reached the predetermined value without outputting an output pulse from the vortex flow meter. The calculation of the flow rate or the flow velocity of the fluid to be measured is performed using the pulse output from the pulse output means.
[0020]
A second technical means is provided with the erroneous output prevention device according to the first technical means.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram showing a configuration of an erroneous output prevention device according to an embodiment of the present invention and a vortex flowmeter using the device.
The vortex flowmeter according to the present embodiment includes a flow tube (measurement tube) 11 of a vortex flowmeter through which a fluid to be measured flows, and a vortex generator that is disposed in the flow tube 11 so as to face a flow and generates a Karman vortex. 12, a vortex signal detector for detecting a Karman vortex signal generated by the vortex generator 12, and a converter for converting a signal detected by the vortex signal detector and outputting a pulse, and measuring the pulse. Thus, the flow rate or flow velocity of the fluid to be measured is measured. In order to prevent erroneous output due to noise signals such as vibration, fluid pulsation, and electrical noise, an erroneous output prevention device (also referred to as an erroneous counting prevention device) 20 is provided in the converter. In the vortex signal detector, a vortex signal detection sensor 13 is disposed downstream of the vortex generator 12 and on the side surface of the vortex generator 12 or the inner wall of the flow tube 11. The vortex signal detection sensor 13 detects the vortex of the Karman vortex street generated by the vortex generator 12. By processing the Karman vortex signal from the vortex signal detection sensor 13 at a later stage, the flow rate or flow velocity is measured. Further, the vortex flowmeter may be a flowmeter in which all of the measurement fluid passes through the measurement tube of the flowmeter, or a small-diameter small-diameter flowtube suitable for measuring a flow rate in a large-diameter flowtube. An insertion type vortex flowmeter may be used in which a vortex flowmeter is inserted and the total flow rate is obtained from the partial flow velocity. Further, the shape of the vortex generator may be a triangular prism or any other shape as long as the flow is separated on both sides of the vortex generator and a Karman vortex is generated alternately.
[0022]
The erroneous output prevention device 20 according to the present embodiment has a configuration in which a change in pressure due to a flow (which naturally includes noise) is used as a change in stress of the detection element as the vortex signal detection sensor 13. It is a device corresponding to a device that uses a sensor such as a piezoelectric element or a strain gauge for detection. The piezoelectric element detects an alternating pressure difference caused by the vortex generator 12 as a change in electric charge. The piezoelectric element is incorporated in a cantilever-shaped vibrating tube in the vortex generator 12 and used as a sensor. In this case, pressure guide holes for guiding an alternating differential pressure to the sensor are provided at both ends of the vortex generator 12. Note that there is a mode in which the pressure guiding hole is not provided. As the Karman vortex is generated, the pressure of the vortex generator 12 changes alternately, and this alternating differential pressure gives an alternating lift to the sensor, and the stress is detected as a change in the charge of the piezoelectric element. I have. This sensor may be provided separately from the vortex generator 12, or may have a structure in which the piezoelectric element is directly built in the vortex generator 12 supported only at one end. The sensor using the strain gauge detects an alternating pressure difference accompanying the vortex generator 12 as a resistance change of the strain gauge, and incorporates a pair of strain gauges in the vortex generator 12 having only one end supported. Used as a sensor. A strain gauge that receives a strain stress due to an alternating lift of the vortex generator 12 accompanying the generation of the Karman vortex is configured as two sides of a bridge, and can detect a resistance change of the strain gauge as a voltage change. Other examples of the vortex signal detection sensor 13 include a sensor having a shuttle piston, a capacity sensor, or the like as a detection element, and any of the detection elements detects a pressure change and outputs (normally amplified by an amplifier 14 or the like). The configuration corresponds to a physical change of the detection element. Therefore, if measurement is performed after pausing the measurement or stopping the flow, the change at the time of pausing or stopping (High “H” or Low “L”) The measurement is started from.
[0023]
The Karman vortex signal from the vortex signal detection sensor 13 is output to a converter. The converter is a device that amplifies, shapes, converts a vortex signal obtained by the vortex signal detection sensor 13 into a pulse signal, and outputs it as an output signal. In the converter illustrated in FIG. 1, a bridge (not shown) connected to the vortex signal detection sensor 13 generates an alternating voltage of one cycle every time a pair of vortices is generated, and the voltage is amplified and transmitted by an amplifier (amplifier) 14. It is like that. Note that this bridge is required for a thermistor, but not required for a piezoelectric element. The alternating voltage signal amplified by the amplifier 14 is filtered and shaped by the filter circuit 15 to increase the S / N ratio and input to the erroneous output prevention device 20. It can also be said that a signal conditioner is formed by the filter circuit 15, the trigger circuit 16, and the erroneous output prevention device 20. As will be described later, a pulse signal is generated by the erroneous output prevention device 20, the output is obtained, and the flow rate (or flow velocity) is calculated by the flow rate calculation circuit 17, so that the erroneous output prevention device 20 functions as a digital filter. I can say that.
[0024]
In the trigger circuit 16, when the output level from the eddy signal detection sensor 13 exceeds a predetermined trigger level, the signal (which may be a signal passed through the amplifier 14 and the filter circuit 15 as shown in the figure) is pulsed and input. Outputs a sine wave as a square wave. The trigger level in the trigger circuit 16 needs to be set to a magnitude that can sufficiently trigger the Karman vortex signal at the minimum flow rate to be measured. This setting may be fixed and cannot be changed. It is preferable that this size can be set according to the use of the meter. The output level of the Karman vortex can be predicted to some extent from the characteristics of the Karman vortex, the characteristics of the detection sensor 13, and the like. Although the trigger circuit 16 is not shown in FIG. 1 as being not included in the erroneous output prevention device 20 for the sake of comparison with the prior art (FIG. 5), the erroneous output prevention device 20 according to the present invention is of course. Alternatively, it is a component to be included in a converter or a vortex flow meter provided with the device 20.
[0025]
FIG. 2 is a diagram showing an example of a signal starting from a low level in each stage of the erroneous output prevention device of FIG. 1. FIG. 2A shows an input signal b to the erroneous output prevention device, and FIG. 2C shows an input signal c to the comparison circuit and an output signal d from one comparator, and FIG. 2C shows an input signal f to the counter circuit. FIG. 3 is a diagram showing an example of a signal starting from a high level in each stage of the erroneous output prevention device of FIG. 1. FIG. 3A shows an input signal b 'to the erroneous output prevention device. 3B is a diagram showing an input signal c 'to the comparison circuit and an output signal d' from one comparator, and FIG. 3C is a diagram showing an input signal f 'to the counter circuit. FIG. 3 is a diagram showing a case where measurement is started in a state where the phase of the above-described detection element is at a high level, and an example in which the waveform of the input signal b 'is obtained by inverting the signal b of FIG. Cite. Here, based on FIG. 2, a case where the measurement is started in a state where the change is a low level in the above-described detection element will be described, but the concept is the same for a high level.
[0026]
The example of FIG. 2A shows a case where the frequency of the pulse signal b output from the trigger circuit 16 and input to the erroneous output prevention device 20 gradually increases with time. The state often appears as a transient phenomenon when the measurement is restarted after the flow is stopped (stopped at the low state). In this example, the reference voltage of the erroneous output prevention device 20 is 3 V, and the voltage level of the trigger signal (often called a TRG signal) output from the trigger circuit 16 is 0.2 (Low) /2.4 (High) V. And a comparator voltage V at a comparator 25 described later. ₁ , Comparator voltage V at comparator 26 ₂ Are 2.0 V and 0.3 V, respectively.
[0027]
A part of the pulse signal b is input to the integration circuit 21 and integrated there, and becomes a signal c. The integration circuit 21 is a circuit that integrates the pulse output from the trigger circuit 16. Here, the resistance value R is used as the integration circuit 21. ₁ Resistance 22 and capacitance C ₁ The example shown in FIG. The signal c is input to a comparison circuit 24 including a comparator 25 and a comparator 26. In this example, the input to the comparison circuit 24 is a signal obtained by integrating the TRG signal b, so that the oscillation oscillates at about 1.4 V, and the amplitude decreases as the frequency increases (to approach 1.4 V). Go). The two comparators 25 and 26 receive the signal integrated by the integration circuit 21 as an input signal, compare the signal level (voltage) of the input signal with predetermined upper and lower limits, and output a pulse. is there.
[0028]
In the comparator 25, the signal c is a comparator voltage (upper limit voltage) V determined by the resistor 27. ₁ Is compared with V ₁ The higher part is output as a pulse (square wave) synchronized with the input signal c. As a result, the output of the comparator 25 becomes like a signal d. On the other hand, in the comparator 26, the signal c is a comparator voltage (lower limit voltage) V determined by the resistor 28. ₂ Is compared with V ₂ The portion other than the lower portion is output as a pulse synchronized with the input signal c. In the example of FIG. ₂ , And the output signal e of the comparator 26 has the reference voltage (3 V) at all positions (not shown). By inputting the output signals d and e from the comparator 25 and the comparator 26 to the logic IC 30, an input signal f to the counter circuit 31 is obtained. As a result, when the frequency of the output signal f from the logic IC 30 increases and the minimum value of the input waveform exceeds +0.3 V, the output of the comparator 26 always becomes “H”, and the frequency further increases and the maximum value of the input waveform increases. When the value falls below +2.0, the output of the comparator 25 always becomes "H". Only when both the outputs of the comparator 25 and the comparator 26 become “H”, the CLR of the counter circuit 31 is released and the CK pulse is captured. Further, in the example of FIG. 2, the cut frequency is determined by the comparator 25 because the comparator 26 becomes “H” first. The CLR signal is input to the counter circuit 31 and is used as a signal for resetting the count in the counter circuit 31. When the CLR signal is not input, the counter circuit 31 remains active. That is, the counter of the counter circuit 31 becomes valid at a frequency larger than a certain value (CLR is not applied). The state in which the transmission of the TRG signal b is stopped is either 0.2 V (Low) or 2.4 V (High). However, when the transmission is stopped at 0.2 V, the comparator 26 operates at 2.4 V. , The output of the comparator 25 becomes "L". As a result, when the TRG signal b is stopped, the output signal f of the logic IC 30 always supplies the CLR signal to the counter circuit 31.
[0029]
Regarding the description with reference to FIG. 2 and FIG. 3, when the TRG signal stops at either “H” or “L”, at the time of stop, either the comparator 25 or the comparator 26 always becomes “L”. CLR is always applied to 31. In addition, even if the TRG signal is restarted at either “H” or “L”, if the signal has a certain period or more, either the comparator 25 or the comparator 26 always becomes “L”. Is always applied with CLR, and a signal having a certain period or more can be excluded. As described above, when the frequency is slow and the input waveform oscillates at an amplitude of 0.3 V or less and 2.0 V or more, the output of the comparator 25 or the comparator 26 becomes a pulse shape synchronized with the input and is constant. If the frequency is lower than the value of, CLR is applied to the counter circuit 31.
[0030]
The outputs from the comparator 25 and the comparator 26 are input to the NAND logic IC 30. The NAND is taken between the respective inputs and output as a pulse signal. As can be understood by referring to the example of FIG. 2, the logic IC 30 determines whether the signal c from the trigger circuit 16 is equal to or longer than a certain period, whether the measurement is started at a low level or the measurement is started at a high level. The CLR signal will be output. Here, depending on the configuration of the comparators 25 and 26, the logic IC 30 may be an IC functioning as an AND gate. In any case, the logic IC 30 only needs to be able to input both output pulses from the two comparators 25 and 26, perform a logic operation, and output a signal related to the reset of the count value in the counter circuit 31. The counter circuit 31 is reset by an output (CLR signal) from the logic IC 30.
[0031]
The counter circuit 31 counts the pulse signal b (or b '; the same applies hereinafter) output from the trigger circuit 16 via the logic IC 32 and accumulates the counted value. This count value is a value that is CLR based on the output signal f from the logic IC 30, and the TRG signal b having a certain period or more is excluded by the CLR signal. On the other hand, the count value is a value for determining whether or not the pulse signal b input from the trigger circuit 16 is accumulated by a predetermined value before being eliminated. The counter circuit 31 outputs a low value when the count value is not the predetermined value, and outputs a high value when the count value is the predetermined value.
[0032]
The pulse output means is a means capable of cutting off a noise signal to a counting mechanism such as the flow rate calculation circuit 17. As a result, only the pulse output from the pulse output means in the vortex flow meter is output from the fluid to be measured. By using the calculation for the flow rate or the flow velocity, it is possible to prevent erroneous counting of the counting mechanism. The pulse output means does not output the output pulse from the trigger circuit 16 when the count value in the counter circuit 31 is less than a predetermined value (Full value) (cuts off), and only when the count value is Full, Means for opening the gate for the TRG signal b from the trigger circuit 16 with the output signal from the counter circuit 31 and outputting the TRG signal b to the flow rate calculation circuit 17 or the counter circuit 31 if the frequency division is not performed by the counter circuit 31 Means for outputting the output of the above to the flow rate calculation circuit 17 as it is. An example of the former case will be described below with reference to FIG.
[0033]
The NAND gate 33 is configured to invert the signal input from the counter circuit 31 and output the inverted signal regardless of whether the count value is Full based on the output of the counter circuit 31 or not. The NAND gate 32 is connected to the NAND gate 33 and the trigger circuit 16, and is configured to close the gate for the output from the trigger circuit 16 when the count value is Full by the output from the NAND gate 33. The NAND gate 34 is connected to the counter circuit 31 and the trigger circuit 16, and closes the gate for the output from the trigger circuit 16 when the count value is not Full, and opens the gate for the output from the trigger circuit 16 when the count value is Full. It is configured. With the above configuration, when the count value in the counter circuit 31 is less than the predetermined value, the output pulse from the trigger circuit 16 is not output (cut off). In this example, the output of the NAND gate 34 is always High when the count value is not Full, and the count in the flow rate calculation circuit 17 at the subsequent stage is disabled. On the other hand, when the count value in the counter circuit 31 reaches the predetermined value, the output pulse from the trigger circuit 16 can be output (inverted).
[0034]
The above-described counter circuit 31 and pulse output means function as a kind of memory. In other words, all the pulses triggered at the trigger level by the trigger circuit 16 are input to the memory before being output to the flow rate calculation circuit 17 for calculating the flow rate or the flow velocity. In this memory, a certain number of memory pulses (the above-mentioned predetermined value) is set, and the pulse is not output to the outside until the set number of pulses is stored, and is output to the outside after the memory is saturated. That is, when the memory is saturated, the input pulse is output as it is.
[0035]
FIG. 4 is a diagram illustrating a cut frequency in the erroneous output prevention device described with reference to FIGS. 1 and 2.
The cut frequency in this embodiment is calculated based on the following equation (1).
Vc = V (1-e ＾ (-t / (R ₁ ・ C ₁ )))… (1)
Here, since the minimum value of the TRG waveform is 0.2 V, 0.2 V is used as the reference voltage.
The time t required for the input of the comparator 25 to reach the comparator voltage (2.0−0.2 = 1.8 V) is represented by Vc = 1.8 and V = 2.2 in the above equation (1). = -R ₁ ・ C ₁ ・ Log _e 0.18 ≒ 1.71 · R ₁ ・ C ₁ (Sec). Therefore, the cut frequency fc is given by the following equation (2).
fc = 1 / (2t) = 1 / (3.42 · R ₁ ・ C ₁ …… (2)
FIG. 4 is a graph of the above equation (2). Where C ₁ = 0.1 μF.
[0036]
Next, as a result of measuring the current consumption (battery life) of the erroneous output prevention device described with reference to FIGS. A significant reduction was confirmed with the filter.
[0037]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to suppress power consumption and to extend battery life significantly.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an erroneous output prevention device according to an embodiment of the present invention and a vortex flowmeter using the device.
FIG. 2 is a diagram illustrating an example of a signal starting from a low level in each stage of the erroneous output prevention device in FIG. 1;
FIG. 3 is a diagram illustrating an example of a signal starting from a High level in each stage of the erroneous output prevention device in FIG. 1;
FIG. 4 is a diagram showing a cut frequency in the erroneous output prevention device described with reference to FIGS. 1 and 2;
FIG. 5 is a block diagram showing a configuration of an erroneous output prevention device and a vortex flowmeter using the device according to the related art.
6 is a diagram illustrating an example of a signal starting from a low level in each stage of the erroneous output prevention device in FIG. 5;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Flow tube, 12 ... Eddy generator, 13 ... Eddy signal detection sensor, 14 ... Amplifier, 15 ... Filter circuit, 16 ... Trigger circuit, 17 ... Flow rate operation circuit, 20 ... False output prevention circuit, 21 ... Integration circuit, 22, 27, 28 resistors, 23 capacitors, 24 comparators, 25, 26 comparators, 30 logic ICs, 31 counter circuits, 32, 33, 34 NAND gates.

Claims (2)

A vortex generated by a vortex generator provided opposite to the flow in the flow pipe through which the fluid to be measured flows is detected by a vortex signal detection sensor that detects a pressure change as a change in a detection element. An erroneous output prevention device in a vortex flowmeter that measures a flow rate or a flow velocity of a fluid to be measured by measuring a detected signal, wherein a signal output from the vortex signal detection sensor exceeds a predetermined trigger level. A trigger circuit for outputting a pulse, an integration circuit for integrating the pulse output from the trigger circuit, a signal integrated by the integration circuit as an input signal, and a voltage of the input signal and predetermined upper and lower limits. Two comparators for comparing the voltage with a pulse and outputting the pulse, a counter circuit for counting the pulses output from the trigger circuit, and both output pulses from the two comparators A logic IC that inputs and performs a logical operation and outputs a signal related to reset of a count value in the counter circuit, and outputs an output pulse from the trigger circuit when the count value in the counter circuit is less than a predetermined value. Pulse output means for outputting an output pulse from the trigger circuit when the count value in the counter circuit has reached the predetermined value, and the vortex flowmeter is output by the pulse output means. A device for preventing erroneous output in a vortex flowmeter, wherein the calculation of the flow rate or the flow velocity of a fluid to be measured is performed by using a measured pulse. A vortex flowmeter comprising the erroneous output prevention device according to claim 1.

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