JP3563235B2 - Data interpolation circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention provides a device that repeatedly writes data to a memory and then reads and processes a fixed unit of data written to the memory, and sets in advance data of a word where no data was written at the time of writing the data. The present invention relates to a data interpolation circuit that interpolates and outputs a predetermined predetermined value.
[0002]
[Prior art]
For example, in a device that repeatedly writes data in a memory for the purpose of format conversion and the like, and then reads and processes a certain unit of data written in the memory repeatedly, when data is written, a read operation is performed. It is assumed that, out of the data of a certain unit to be read, only data which is not a predetermined value set in advance by the device is written, and at the time of reading data, the data of a certain unit which is read by the read operation is sequentially read.
[0003]
Here, data that is written at the time of writing data and that is not a predetermined value preset by the device is referred to as valid data, and is a predetermined value preset by the device, and is not written at the time of data writing. The data will be referred to as invalid data.
[0004]
In such a device, since invalid data is not written to the memory, words of the memory to which valid data has not been written out of the fixed unit of data read out in the read operation are written before writing this data. Valid data remains written. Therefore, it is necessary to read out a predetermined value preset in the device as data of a word of a memory in which valid data has not been written so that no trouble occurs in data processing.
[0005]
For example, in an encoding apparatus that employs a JPEG (Joint Photographic Experts Group) algorithm, which is an international standard encoding method for color still images, in decoding of encoded compressed data, for example, as shown in FIG. After Huffman decoding the data, temporarily storing the data sequence obtained in the zigzag scan order in the memory, reading the data from the memory in the block scan order, and performing inverse DCT (discrete cosine) transform, the decoded image data is obtained. Get.
[0006]
Here, the memory converts the data obtained in the zigzag scan order into the block scan order. For writing and reading data to and from the memory, for example, two memories for storing one block of image data are provided, one is used for writing data, and the other is used for reading data. By alternately exchanging the memory used for the reading and the reading, the processing can be continuously performed.
[0007]
However, in Huffman decoding, valid data corresponding to non-zero effective coefficients can be obtained, but invalid data corresponding to consecutive zero coefficients after the last valid coefficient cannot be obtained. . Therefore, only valid data is written to the memory, but at the time of reading data, it is not possible to distinguish whether or not the data read from the memory is valid data. '0' is written to the memory word.
[0008]
Here, when the speed of reading data from the memory is sufficiently slower than the speed of writing data to the memory, for example, writing '0' to all words of the memory before writing valid data is performed. There is no particular problem if valid data is written after initialization, but if data writing and data reading have the same operation rate, data writing will be continued until data writing is completed. There has been a problem that a weight is required for reading.
[0009]
Further, for example, when writing valid data to the memory, if “0” is written to the word of the memory where the valid data is not written, the word of the memory where the valid data is not written changes every time data is written. As a result, there is a problem in that reading data requires a weight. Further, there is also a problem that control is considerably complicated in order to write "0" in a word of a memory in which valid data has not been written.
[0010]
[Problems to be solved by the invention]
An object of the present invention is to interpolate data of a word in a memory in which valid data is not written, with a simple circuit configuration, without giving a weight to reading data from the memory, in view of the problems based on the conventional technology. It is another object of the present invention to provide a data interpolation circuit which can perform data processing efficiently.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a flag indicating whether data has been written to each word of the memory, in one-to-one correspondence with each word of the memory having a predetermined number of words. Holding means, when data is written to a word in the memory, means for setting a flag corresponding to the word in which the data has been written, and when the data is read from the word in the memory, If the flag corresponding to the read word is set, the output of the memory is output. If the flag corresponding to the word from which the data is read is not set, a preset value is output. Means, and when data is read from a word in the memory, means for resetting a flag corresponding to the word from which the data was read. There is provided a data interpolation circuit according to claim.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a data interpolation circuit of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.
[0013]
FIG. 1 is a conceptual diagram of an embodiment of a data interpolation circuit according to the present invention.
The data interpolation circuit 10 in the illustrated example includes a memory 12 having a predetermined number of words having a predetermined bit width, a flip-flop 14 holding an address ADDR_IN, a flip-flop 16 holding valid data DATA_IN, and a one-to-one correspondence with each word of the memory 12. , A flag register 18 for holding a flag indicating whether or not valid data has been written to each word, and an AND gate 20.
[0014]
Here, the memory 12 is a semiconductor memory capable of writing and reading data to and from a word specified by an address. For example, a conventionally known SRAM or DRAM can be used. Further, although not shown, for example, two or more memories 12 are provided, and one is used for writing the next data, and the other is used for reading the previous data. Can be used alternately.
[0015]
The flip-flop 14 holds an address ADDR_IN that specifies a word address of the memory 12, and an output signal of the flip-flop 14 is input to an address input terminal of the memory 12 and a flag register 18.
The flip-flop 16 holds valid data DATA_IN written to the memory 12, and an output signal of the flip-flop 16 is input to a data input terminal of the memory 12.
[0016]
As described above, the flag register 18 holds a one-bit flag corresponding to each word of the memory 12 on a one-to-one basis. Each flag is valid for a word of the memory 12 specified by the address ADDR_IN. When data is written, a flag corresponding to the word of the memory 12 in which valid data is written is set, and when data is read from the word of the memory 12, the flag corresponds to the word of the memory 12 from which the data is read. Flag is reset.
[0017]
Each flag is initialized, for example, when the power is turned on. Thereafter, as described above, when valid data is written to a word in the memory 12, a flag corresponding to this word is set, and when data is read from a word in the memory 12, a flag corresponding to this word is set. Reset.
As a result, all the flags are always initialized when the reading of the data from the word in the memory 12 is completed.
[0018]
The circuit configuration of the flag register 18 is not particularly limited, but means for holding a 1-bit flag provided in one-to-one correspondence with each word of the memory 12, such as a register, for example, an address decoder Means for setting and resetting a flag based on an address ADDR_IN and a data write signal and a read signal (not shown), for example, means for selectively outputting each flag such as a multiplexer, etc. .
[0019]
Each flag is set to either "1" or "0" which is set in advance when set. That is, the flag may be set to '1' or '0'. Conversely, when the flag is reset, it is set to '0' or '1', which is the opposite of when it was set. In this embodiment, each flag is reset at initialization to be all "0", set to "1" when set, and set to "0" when reset. .
[0020]
The AND gate 20 gates the data read from the memory 12 by a 1-bit flag from the flag register 18 corresponding to the word from which the data has been read, and outputs this as output data DATA_OUT.
[0021]
That is, when data is read from a word in the memory 12 and the flag from the flag register 18 corresponding to the word from which the data is read is set to “1”, the data is read from the memory 12. The data is output as output data DATA_OUT as it is, whereas if the flag from the flag register 18 corresponding to the word from which the data has been read is reset to '0', '0' is output as DATAA_OUT. Is output.
[0022]
In this embodiment, the AND gate 20 is used. However, the present invention is not limited to this. When data is read from a word in the memory 12, a flag corresponding to the word from which the data is read is used. If the flag from the register 18 is set, the data read from the memory 12 is output as it is. If the flag is not set, a predetermined value set as the output data DATA_OUT is output. Is also good.
[0023]
For example, a multiplexer may be used in place of the AND gate 20, and data read from the memory 12 and a predetermined value may be selectively output according to the state of the flag from the flag register 18. Alternatively, an AND gate or an OR gate may be used in place of the AND gate 20 in accordance with the state of the flag from the flag register 18 and the inverted signal thereof, so that a preset predetermined value is output. You may do it.
[0024]
Next, the operation of the data interpolation circuit 10 shown in FIG. 1 will be described by taking as an example a case where format conversion is performed between writing and reading of data.
[0025]
FIG. 2 is a conceptual diagram of one embodiment showing the order of writing data to the memory and reading data from the memory.
As shown in the figure, here, when writing data to the memory 12, only valid data is written in the order of write addresses 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9. In reading data from the memory 12, all data are read in the order of the read addresses 0, 2, 4, 6, 8, 1, 3, 5, 7, and 9.
[0026]
FIG. 3 is a conceptual diagram of one embodiment showing a flow of the operation of the data interpolation circuit of the present invention.
As shown in FIG. 3, in the data interpolation circuit 10 of the present invention, first, each flag is initialized. For example, all the flags are reset and initialized to '0' by a power-on reset when the power is turned on or by giving a system reset to the data interpolation circuit 10.
[0027]
The word of the memory 12 where data is written and read is specified by the address ADDR_IN. After the address ADDR_IN is held in the flip-flop 14, it is input to the address input terminal of the memory 12 and the flag register 18. The data DATA_IN to be written to the word of the memory 12 specified by the address ADDR_IN is stored in the flip-flop 16 and then input to the data input terminal of the memory 12.
[0028]
In this case, as shown in FIG. 3, for example, the write data (valid data) '2' is written to the word at the write address 0, and the write addresses 1 and 3 are similarly written. , 4, 7, 9 write data '3', '8', '1', '3', '5' are sequentially written, respectively, and the other write addresses 2, 5, 6, 8 are written. No valid data is written.
[0029]
At this time, in the flag register 18, when valid data is written in the word of the memory 12 specified by the address ADDR_IN, a flag corresponding to this word (address) is set at the same time. That is, here, as shown in FIG. 3, the flags corresponding to the respective addresses (words) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 of the memory 12 are 1, 1,0,1,1,0,0,1,0,1.
[0030]
The word of the memory 12 from which data is read is also specified by the address ADDR_IN as in the case of writing data. Read data from a word in the memory 12 specified by the address ADDR_IN is output from a data output terminal of the memory 12, and a flag corresponding to this word is output from the flag register 18. These are both input to the AND gate 20, and the output data DATA_OUT is output from the AND gate 20.
[0031]
Here, when data is read from the word in the memory 12 specified by the address ADDR_IN and the flag output from the flag register 18 corresponding to this word is “1”, the AND gate 20 outputs: The data read from this word is output as output data DATA_OUT. On the other hand, if the flag corresponding to this word is '0', '0' is output regardless of the data read from this word. .
[0032]
That is, since “1” is output from the flag register 18 as a flag corresponding to the read address 0, read data “2” from the word at the read address 0 of the memory 12 is output from the AND gate 20 as output data DATA_OUT. Is output. Since “0” is output as the flag corresponding to the read address 2, “0” is output from the AND gate 20 regardless of the read data from the word at the read address 2 in the memory 12.
[0033]
Similarly, when the data of the word corresponding to the read addresses 4, 6, 8, 1, 3, 5, 7, and 9 of the memory 12 is read, the read data from the word of the address 4 is output from the AND gate 20. '1', '0', '0', read data '3' from address 1, read data '8', '0' from address 3, read data '3' from address 7, read data from address 9 Read data '5' is sequentially output as output data DATA_OUT.
[0034]
At this time, in the flag register 18, when data is read from the word of the memory 12 specified by the address ADDR_IN, the flag corresponding to this word is reset at the same time. That is, here, as shown in FIG. 3, all flags are set to '0'. As a result, when the data reading is completed, all the flags of the flag register 18 are reset and initialized, so that the data writing and reading can be repeated thereafter.
[0035]
The data interpolation circuit of the present invention is basically as described above.
[0036]
Note that the present invention is not limited to the case of format conversion, such as the case of JPEG decoding described in the description of the related art. In an apparatus that repeatedly reads and processes data, it is necessary to interpolate and output data of words for which valid data has not been written at the time of writing data with a predetermined value at the time of reading data. Applicable to all cases.
[0037]
In the above embodiment, the flag is read from the flag register 18 at the same time as the data is read from the memory 12, but the present invention is not limited to this. For example, after reading the flag from the flag register 18 first, When the flag is “0”, data is not read from the memory 12 and a preset value is output. When the flag is “1”, data is read from the memory 12. Good.
[0038]
As described above, the data interpolation circuit of the present invention has been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and changes may be made without departing from the gist of the present invention. is there.
[0039]
【The invention's effect】
As described in detail above, the data interpolation circuit of the present invention determines whether data has been written to each word of the memory in one-to-one correspondence with each word of the memory having the predetermined number of words. A flag indicating that when data is written to a word in memory, a flag corresponding to the word in which the data is written is set, and when data is read from a word in memory, this data is read. If the flag corresponding to the word is set, the memory output is output.If the flag is not set, the preset value is output, and then the flag corresponding to the word from which this data is read is reset. It is something to keep.
According to the data interpolation circuit of the present invention, without writing a predetermined value for initialization, it is possible to interpolate the data of the word of the memory in which the valid data is not written. Without writing, data can be written and read to and from the memory at the same operation rate to perform data processing efficiently. Further, according to the data interpolation circuit of the present invention, by referring to the flag, it is determined whether or not the read data from the memory is valid data, and the data of the word of the memory where the valid data is not written is interpolated. Therefore, when writing data to the memory, it is not necessary to determine the word of the memory where the valid data has not been written, and to write a predetermined value to the word of the memory, thereby eliminating the need for a complicated control circuit. There are benefits too.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram of one embodiment of a data interpolation circuit of the present invention.
FIG. 2 is a conceptual diagram of an embodiment showing an order of writing data to a memory and reading data from the memory.
FIG. 3 is a conceptual diagram of one embodiment showing a flow of operation of the data interpolation circuit of the present invention.
FIG. 4 is a conceptual diagram illustrating an example of a decoding procedure in JPEG.
[Explanation of symbols]
Reference Signs List 10 Data interpolation circuit 12 Memory 14, 16 Flip-flop 18 Flag register 20 AND gate

Claims (1)

Means for holding a flag indicating whether data has been written to each word of the memory in one-to-one correspondence with each word of the memory having a predetermined number of words; Means for setting, when written, a flag corresponding to the word in which the data was written; and for reading data from the word in the memory, a flag corresponding to the word from which the data was read is set. Means for outputting the output of the memory if the flag has been set, and outputting a predetermined value which is set in advance if the flag corresponding to the word from which the data has been read has not been set; and reading data from the word of the memory. Means for resetting a flag corresponding to the word from which the data has been read when the data has been read.

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