JP3563032B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same. In particular, the present invention relates to a field effect transistor using titanium oxide as a gate insulating film and a method for manufacturing the same.
[0002]
[Prior art]
In the field-effect transistor generation in which the gate length is 0.1 μm or less, the performance that the gate insulating film is driven at 1.5 nm or less in terms of SiO ₂ is required. If SiO ₂ is used for the gate insulating film as in the related art, there is a problem that a leak current mainly consisting of a tunnel current increases because the thickness is 1.5 nm or less. This leakage current is so high that even a logic circuit that requires high speed even with relatively high power consumption cannot be ignored, and it is an issue to prevent the leakage current and reduce the power consumption.
[0003]
Therefore, a high dielectric material having a relative dielectric constant larger than that of SiO ₂ is used as the gate insulating film, and a tunnel current is prevented by increasing the physical gate thickness while maintaining the driving performance, thereby reducing power consumption. The research and development of the technology to be performed is actively performed.
[0004]
Materials examined as high dielectric materials include metal oxides such as TiO ₂ , Ta ₂ O ₅ , ZrO ₂ , HfO ₂ , and La ₂ O ₃ . Among these metal oxides, TiO ₂ (titanium oxide) has the highest relative dielectric constant. Titanium oxide has a track record of being commonly used in LSIs as a dielectric material for capacitors such as DRAMs, and research and development using titanium oxide as a gate insulating film of a field effect transistor have been actively conducted.
[0005]
However, titanium oxide has high reactivity with silicon, and in the process of depositing titanium oxide on a silicon substrate, an interface reaction layer mainly composed of SiO ₂ is formed at an interface between the titanium oxide film and the silicon substrate of 2 nm or more. Problem.
[0006]
Since the interface reaction layer mainly composed of SiO ₂ has a relative dielectric constant as low as that of SiO ₂ , the insulating film in which the titanium oxide film and the interface reaction layer are laminated has almost the same electric capacitance value as the interface reaction layer. Is determined by the capacitance value of In addition, since the thickness of the interface layer mainly composed of SiO ₂ is inevitably 2 nm or more, a required thickness of 1.5 nm or less in terms of SiO ₂ cannot be achieved as a gate insulating film. There is also.
[0007]
In order to prevent the formation of the interface reaction layer, it has been attempted to form a thin film containing nitrogen such as SiON or SiN on a silicon substrate in advance and form a titanium oxide film on the thin film containing nitrogen. Have been. However, in this method, although the interface reaction layer mainly composed of SiO ₂ can be suppressed, the interface characteristics between the gate insulating film and the silicon substrate greatly differ depending on the properties of the nitrogen-containing thin film. For example, electric characteristics may be degraded by nitrogen existing near the interface between the gate insulating film and the silicon substrate. Specifically, a large number of defects, such as excess charge typified by fixed charges due to nitrogen atoms and interface levels, occur at the interface, deteriorating the device characteristics.
[0008]
[Problems to be solved by the invention]
As described above, in the method of forming titanium oxide directly on a silicon substrate, the interface reaction layer mainly composed of SiO ₂ is formed to a thickness of 2 nm or more by reacting silicon and titanium oxide. In addition, there is a problem that the capacitance of the insulating film is reduced to a level that cannot be practically used.
[0009]
Attempts have been made to suppress this interfacial reaction layer by using a thin film containing nitrogen as a buffer layer. However, the deterioration of the interfacial properties due to nitrogen has been remarkable, but has not yet reached practical use.
[0010]
The present invention has been made to solve the above problems, and realizes a high-quality interface characteristic, realizes a high insulating film capacity having a performance of 1.5 nm or less in terms of SiO ₂ , and suppresses a tunnel current. It is an object of the present invention to provide a semiconductor device that achieves both.
[0011]
Another object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming such a gate insulating film on a silicon substrate.
[0012]
[Means for Solving the Problems]
To achieve the above object, the present invention provides a silicon substrate,
A buffer layer made of an oxide containing titanium and silicon formed on the silicon substrate,
A gate insulating film made of titanium oxide formed on the buffer layer,
A gate electrode formed on the gate insulating film;
A channel region formed under the gate insulating film in the silicon substrate;
A source region and a drain region formed apart from each other in the silicon substrate and provided so as to locate the channel region therebetween;
The semiconductor device, wherein the buffer layer has a thickness of 0.5 nm or more and 2 nm or less and an atomic concentration of titanium of 1% or more and 8% or less.
[0013]
Further, an SiO ₂ layer having a thickness of 1 nm or less may be formed between the buffer layer and the silicon substrate.
[0014]
The buffer layer may contain some nitrogen.
[0015]
Further, the present invention, the step of peeling the oxide film formed on the silicon substrate surface,
By sputtering with a target of titanium oxide and an oxygen flow rate of 0 sccm or more and 1.2 sccm or less, an oxide containing titanium and silicon is formed on the silicon substrate, and a film thickness of 0.5 nm or more and 2 nm or less, Forming a buffer layer having an atomic concentration of titanium of 1% or more and 8% or less;
Forming a gate insulating film made of titanium oxide on the buffer layer by sputtering with a target of titanium oxide and an oxygen flow rate of 10 sccm or more. And a method for producing the same.
[0016]
In the present invention, a buffer layer composed of titanium atoms, silicon atoms, and oxygen atoms is previously formed on a silicon substrate before forming a titanium oxide in order to suppress an interface reaction layer mainly composed of SiO ₂ . In order to maintain the quality of the interface with the silicon substrate at a high quality without significantly deteriorating the value of the insulating film capacitance, the ratio of the constituent materials of the buffer layer and the thickness thereof were studied in various ways. In the following, it has been found that the above object can be achieved by setting the constituent element to an oxide containing titanium and silicon, and setting the atomic concentration of titanium to 1% or more and 8% or less.
[0017]
The buffer layer at this time may have a thickness of at least 0.5 nm. In addition, the atomic concentration indicates the ratio of the atoms constituting the film to the total number of atoms existing in the film.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0019]
First, prior to describing an embodiment of the present invention, a titanium oxide film was formed directly on a silicon substrate in order to find out the problems of the prior art.
[0020]
FIG. 1 shows a conceptual diagram when a titanium oxide film is formed on a silicon substrate by a conventional CVD (chemical vapor deposition) method.
[0021]
First, as shown in FIG. 1A, a silicon substrate 1 from which a natural oxide film has been removed in advance is prepared. Then, a titanium source gas 2 such as an organic metal gas containing titanium and an oxygen gas 3 are supplied onto the silicon substrate 1 on the surface of the silicon substrate 1.
[0022]
Then, as shown in FIG. 1B, in this film forming method by CVD, an interface reaction layer 4 mainly composed of SiO ₂ is formed at the interface between the silicon substrate 1 and the titanium oxide film 5 to a thickness of about 2 nm. I will.
[0023]
FIG. 2 shows a conceptual diagram when a titanium oxide film is formed on a silicon substrate by a conventional sputtering method using titanium as a target.
[0024]
In this method, first, as shown in FIG. 2A, a silicon substrate 1 from which a natural oxide film has been removed in advance is prepared. The surface of the silicon substrate 1 is irradiated with the excited argon 7 on the titanium target 6 to supply Ti—O and Ti in an oxygen atmosphere 8.
[0025]
Then, as shown in FIG. 2B, even in this film forming method by sputtering, an interface reaction layer 4 containing SiO ₂ as a main component is formed on the interface between the silicon substrate 1 and the titanium oxide film 5 to a thickness of about 2 nm. I found out.
[0026]
What is common to these conventional film forming methods is that the silicon surface is exposed to a large amount of oxygen at the initial stage when the titanium oxide is formed on the silicon substrate 1. This means that a larger amount of oxygen is supplied to the surface of the chemically active silicon substrate 1 than titanium, and the interface reaction layer 4 mainly composed of SiO ₂ having a low dielectric constant has a thickness of 2 nm or more. It causes filming. Conventionally, there has been a tendency for the supply amount of oxygen gas to be excessive during film formation in order to enhance the bulk characteristics of titanium oxide. This is because oxygen atoms are generally easily released from titanium oxide, and the composition ratio does not become stoichiometric unless the supply of oxygen gas is excessive.
[0027]
However, the interfacial reaction layer formed at this time has a thickness of at least 2 nm and further contains SiO ₂ as a main component, so that the relative dielectric constant is as low as about 4 and the insulating film capacity is reduced.
[0028]
From the above considerations, the present inventors first form a buffer layer made of a titanium oxide film on a silicon substrate using a titanium oxide film as a target, with the supply amount of oxygen gas being reduced or not supplied at all. Then, a gate insulating film made of titanium oxide is formed on the buffer layer again by sputtering in an atmosphere in which oxygen gas is sufficiently supplied, using titanium oxide as a target. By doing so, it has been found that formation of an interface reaction layer mainly composed of SiO ₂ can be prevented.
[0029]
FIG. 3 is a conceptual diagram illustrating a method for forming a gate insulating film made of a titanium oxide film according to the present invention.
[0030]
First, as shown in FIG. 3A, a silicon substrate 1 from which a natural oxide film has been removed in advance is prepared. On the surface of this silicon substrate 1, a target 9 made of titanium oxide is irradiated with activated argon 7 and sputtered. By doing so, Ti—O or Ti is supplied onto the silicon substrate 1. At this time, the supply amount of oxygen is reduced as much as possible or not supplied at all. However, since the target is titanium oxide, oxygen 8 evaporates from the titanium oxide and is supplied to the surface of the silicon substrate 1.
[0031]
Thus, as shown in FIG. 3B, a buffer layer 10 made of an oxide containing titanium and silicon is formed on the silicon substrate 1. In this reaction, the formation of titanium oxide and the oxidation of the surface of the silicon substrate 1 proceed simultaneously, and titanium, silicon, and oxygen are mixed in the buffer layer 10.
[0032]
Next, as shown in FIG. 3C, the oxygen gas 8 is sufficiently supplied, the titanium oxide target 9 is irradiated with the excited argon 7, and Ti—O and Ti are supplied onto the buffer layer 10. In this reaction, since the oxygen gas 8 is sufficiently supplied, the titanium atoms and the oxygen atoms are close to stoichiometry and can form a titanium oxide having excellent electric characteristics. FIG. 3D is a diagram in which the gate insulating film 11 made of titanium oxide is formed on the buffer layer 10 by this.
[0033]
As described above, the process for forming the buffer layer is a two-stage process in which the supply of oxygen is reduced to zero or zero, and the process for forming the gate insulating film is performed under a condition of sufficient oxygen supply. A buffer layer made of an excellent titanium oxide and an oxide containing titanium and silicon having a high relative dielectric constant can be realized.
[0034]
FIG. 4 is a diagram showing a composition analysis result of the buffer layer.
[0035]
As shown in FIG. 4, it can be seen that the buffer layer contains titanium atoms, silicon atoms, and oxygen atoms. As described above, by containing titanium, the buffer layer has a higher dielectric constant than SiO ₂ .
[0036]
Next, FIG. 5 shows a graph in which the vertical axis indicates the relative dielectric constant of the buffer layer and the horizontal axis indicates the atomic concentration of titanium in the buffer layer.
[0037]
As it can be seen from FIG. 5, the dielectric constant of the TiSi _x O _y film when the atomic concentration of titanium in TiSi _x O _y film is high increases. However, if the content of titanium atoms is too high, there is a problem that titanium separates into TiO ₂ and SiO ₂ , which causes crystallization of titanium oxide and an accompanying increase in leakage current. There is also a problem that the relative dielectric constant is reduced due to phase separation of SiO ₂ . It was found that this phase separation between TiO ₂ and SiO ₂ became apparent around the point where the atomic concentration of titanium exceeded 8%. Therefore, in the present invention, the atomic concentration of titanium in the buffer layer made of an oxide containing titanium and silicon is specified to be 8% or less.
[0038]
Also, as can be seen from FIG. 5, when the atomic concentration of titanium is too low, the relative dielectric constant decreases, and when the atomic concentration of titanium is lower than 1%, the relative dielectric constant becomes lower than 5. This means that the thickness of the buffer layer thickness, for example 2 nm, becomes equivalent SiO ₂ thickness 1.6 nm, is equivalent SiO ₂ thickness is spec 0.1μm generation can not meet the 1.5 nm. Therefore, in the present invention, the atomic concentration of titanium is specified to be 1% or more. At this time, the thickness of the buffer layer must be 2 nm or less. In the method of the present invention, since the buffer layer is formed by the sputtering method, the thickness can be easily controlled. In experiments conducted by the present inventors, it is possible to reduce the thickness of the buffer layer to 1.5 nm or less. The thickness of the buffer layer may be such that an SiO ₂ interface layer is not generated during the next titanium oxide film formation, and may be 0.5 nm or more. However, if it is SiO ₂ of 0.1 nm or less, even if it is formed as an interface layer, there is no problem even if the SiO ₂ equivalent film thickness is sufficiently thin.
[0039]
The buffer layer consisting of TiSi _x O _y From these considerations, it is preferred atomic concentration of titanium atoms is 4% or less than 2%. The buffer layer according to the present invention is preferably microscopically a mixture of TiO ₂ and SiO ₂ . In the buffer layer, silicon has an atomic concentration of 20% or more and 40% or less, and more preferably 25% or more and 35% or less. The atomic concentration of oxygen is preferably 65% or more and 70% or less in order to achieve both the interface characteristics between the silicon substrate and the buffer layer and the improvement of the insulating film capacity.
[0040]
In addition, for example, about 1 × 10 ²⁰ / cm ³ or less of nitrogen atoms may be mixed in the buffer layer.
[0041]
In the present invention, suppressing the oxygen flow rate at the beginning of the titanium oxide film formation when forming the buffer layer also has the effect of reducing the thickness of the buffer layer to 2 nm or less. Specifically, the buffer layer can be thinned to 1.5 nm or less by completely eliminating oxygen.
[0042]
In the present invention, the supply amount of oxygen at the time of forming the buffer layer is set to 0 sccm or more and 2 sccm or less so that the ratio of Ti to O is sufficiently lower than that of stoichiometry (TiO ₂ ). Here, the thickness of the buffer layer, the atomic concentration of titanium atoms, and the relative dielectric constant are greatly affected by the amount of supplied oxygen. In order to increase the relative dielectric constant and increase the insulating film capacity of the buffer layer, it is preferable to completely remove oxygen. On the other hand, when the atomic concentration of titanium increases, a slight leak current flows. Therefore, in order to give priority to a low leak current, it is preferable to flow a slight amount of oxygen.
[0043]
After forming the buffer layer on the silicon substrate by the method as described in detail above, it is preferable to use a method of sputtering while supplying a large amount of oxygen, which is optimal for improving the bulk characteristics of titanium oxide. May be formed.
[0044]
FIG. 6 shows a buffer layer made of TiSi _x O _y on a silicon substrate and a titanium oxide film formed on the buffer layer.
[0045]
As shown in FIG. 6, if the atomic concentration of titanium in the buffer layer is 2% or more and 8% or less, preferably 4% or less, and the film thickness is 2 nm or less, ideal interface characteristics can be obtained.
[0046]
FIG. 8 is a cross-sectional view of a field-effect transistor in which a gate insulating film is formed using the above-described method of the present invention.
[0047]
As shown in FIG. 7, this field-effect transistor includes a silicon substrate 1, a buffer layer 4 formed on the silicon substrate 1, a gate insulating film 5 made of polysilicon or the like formed on the buffer layer 4, And a gate electrode 12 formed on the gate insulating film.
[0048]
The buffer layer 4 is made of an oxide containing titanium and silicon, and is formed so that the atomic concentration of titanium is 1% or more and 8% or less and the film thickness is 2 nm or less. Gate insulating film 5 is composed of a titanium oxide film.
[0049]
A gate side wall 15 made of silicon oxide or silicon nitride is formed on the side wall of the stacked structure of the buffer layer 4 / gate insulating film 5 / gate electrode 12. At a position below the gate insulating film 5 in the silicon substrate 1, a channel region is formed. A deep diffusion region 13 and a shallow diffusion region 14 in which impurities are diffused at a high concentration are formed at positions sandwiching the channel region, and constitute a source region / drain region. Reference numeral 17 denotes an element isolation region. Reference numeral 18 denotes a salicide formed on the deep diffusion region 13, and reference numeral 19 denotes a salicide formed on the gate electrode 12.
[0050]
Next, a method of manufacturing the field-effect transistor shown in FIG. 7 will be described with reference to FIG.
[0051]
First, as shown in FIG. 8A, an element isolation region 17 made of silicon oxide or the like is formed at a predetermined position on the silicon substrate 1 by a normal process. Next, the natural oxide film on the silicon substrate 1 is peeled off by dilute HF solution treatment, and the silicon surface is terminated with hydrogen. This step is extremely important to prevent an extra oxide film from being formed on the Si surface.
[0052]
Next, as shown in FIG. 8B, a buffer layer 17 composed of titanium atoms, silicon atoms, and oxygen atoms is formed on the silicon substrate 1. In this step, the sputtering method described with reference to FIGS.
[0053]
Specifically, TiO ₂ was used as a target, and the target was irradiated with argon excited by RF sputtering to deposit. The gas flow conditions at this time were such that the Ar gas was 20 sccm, and the buffer layer was formed under different conditions in the range of oxygen flow from 0 sccm to 1.2 sccm. By this step, a buffer layer having a thickness of 1.3 nm (under the condition of oxygen at 0 sccm) to 1.8 nm (under the condition of oxygen at 1.2 sccm) was formed. As a matter of course, TiOx (x <2) is deposited on the element isolation region 17.
[0054]
Next, as shown in FIG. 8C, a titanium oxide film 7 having a high dielectric constant is deposited on the entire surface. In this step, the sputtering method described with reference to FIGS.
[0055]
Specifically, TiO ₂ was used as a target, and the target was irradiated with argon excited by RF sputtering to deposit. The gas flow conditions at this time were 10 sccm for Ar gas and 10 sccm for oxygen gas. This is a condition for depositing a titanium oxide having a composition ratio close to stoichiometry and having extremely excellent electric characteristics. At this time, the thickness of the titanium oxide 4 is preferably 1 nm or more in consideration of a leak current.
[0056]
These sputtering steps were performed continuously in the same apparatus, with only the gas flow conditions changed. By doing so, the buffer layer 4 and the gate insulating film 7 can be formed in a strictly controlled gas atmosphere without breaking the vacuum. This is very important in improving the characteristics of the insulating film by eliminating contamination (carbon, oxygen, nitrogen, etc.) on the insulating film.
[0057]
Next, as shown in FIG. 8D, a gate electrode material such as TiN or polysilicon is deposited by a normal process, and processed by etching to form a gate electrode 12. Next, using the gate electrode 12 as a mask, a shallow diffusion region 14 is formed by ion-implanting impurities. Next, silicon oxide or silicon nitride is entirely deposited and anisotropically etched to form gate sidewalls 5 on the side surfaces of buffer layer 4 / gate insulating film 5 / gate electrode 12. Next, a deep diffusion region 13 is formed by ion-implanting impurities using the gate electrode 12 and the gate side wall 15 as a mask. The acceleration voltage of the impurity at this time may be higher than that of the shallow diffusion region 14. These impurity implantations are simultaneously performed in the gate electrode 12. Next, heat treatment for activating the impurity ions implanted into the shallow diffusion region 14, the deep diffusion region 13, and the gate electrode 12 is performed.
[0058]
This heat treatment temperature varies slightly depending on the material used for the gate electrode 12, and typically requires a heat treatment of about 900 ° C. to 1050 ° C. FIG. 9 is a cross-sectional view of a laminated structure of the silicon substrate 1 / TiSiO buffer layer 4 / titanium oxide gate insulating film 5 and gate electrode 12 when heat treatment is performed under these conditions. FIG. 9A shows the state before the heat treatment, and FIG. 9B shows the state after the heat treatment.
[0059]
The titanium oxide film 5 keeps flatness, and the thickness of the Ti—Si—O buffer layer 4 hardly changes between (a) before the heat treatment and (b) after the heat treatment. That is, there is no problem of aggregation in the titanium oxide film 5, and the problem of capacity reduction due to the regrowth of the buffer layer 4 can be almost ignored.
[0060]
As described above, the laminated insulating film structure of the present invention has heat resistance enough to cope with the conventional CMOS process.
[0061]
Next, by depositing Co and performing a heat treatment, the salicide 18 is formed on the deep diffusion region 13 and the salicide 19 is formed on the gate electrode 12 as shown in FIG.
[0062]
FIG. 10 is a diagram showing the electrical characteristics of the gate voltage and the source / drain current of the field effect transistor (a) and the field effect transistor using silicon oxide as the gate insulating film thus formed.
[0063]
The characteristic (a) of the field effect transistor of the present invention is that the S factor (the amount of change in the gate voltage with respect to a single digit change in the drain current), which is an index of the interface characteristics, is such that This is almost the same as the characteristic (b) of FIG.
[0064]
【The invention's effect】
As described above in detail, according to the present invention, a semiconductor which realizes high-quality interface characteristics, realizes a high insulating film capacity having a performance of 1.5 nm or less in terms of SiO ₂ , and suppresses a tunnel current. An apparatus can be provided.
[0065]
Further, the present invention can provide a method for manufacturing a semiconductor device capable of forming such a gate insulating film on a silicon substrate.
[Brief description of the drawings]
FIG. 1 is a view showing a step of depositing a titanium oxide film on a silicon substrate by CVD.
FIG. 2 is a view showing a step of depositing a titanium oxide film on a silicon substrate by reactive sputtering.
FIG. 3 is a view showing a step of depositing a buffer layer and a titanium oxide film on a silicon substrate in this order by a method according to the present invention.
FIG. 4 is a view showing an elemental analysis result of a buffer layer deposited by a method according to the present invention.
FIG. 5 is a diagram showing experimental results showing the relationship between the relative dielectric constant of a buffer film deposited by the method according to the present invention and the atomic concentration of Ti atoms.
FIG. 6 is a cross-sectional view of a silicon substrate / TiSiO buffer layer / titanium oxide film deposited by a method according to the present invention.
FIG. 7 is a sectional view of a field-effect transistor according to the present invention.
FIG. 8 is a diagram for explaining a manufacturing process of the field-effect transistor according to the present invention, and FIGS. 8A, 8B, 8C, and 8D are cross-sectional views in each process.
9 is a cross-sectional view before and after heat treatment of a laminated structure of the silicon substrate / buffer layer / titanium oxide film gate insulating film / gate electrode of the present invention, FIG. 9 (a) before heat treatment, and FIG. 9 (b) The latter one.
FIG. 10 is a voltage-current characteristic diagram of a field-effect transistor according to the present invention and a field-effect transistor using silicon oxide for a gate insulating film.
[Explanation of symbols]
1 ... silicon substrate 2 ... titanium material 3 ... oxygen source 4 ... of SiO ₂ as a main interface reaction layer 5: titanium oxide film 6 ... titanium target 7 ... Argon 8 ... Oxygen 9 ... Titanium oxide target 10 ... Buffer layer 11 ... Titanium oxide film 12 ... Gate electrode 13 ... Deep diffusion region 14 ... Shallow diffusion region 15 ... Gate sidewall 16: TiO ₂
17 element isolation region 18 salicide 19 salicide

Claims (3)

A silicon substrate,
A buffer layer made of an oxide containing titanium and silicon formed on the silicon substrate,
A gate insulating film made of titanium oxide formed on the buffer layer,
A gate electrode formed on the gate insulating film;
A channel region formed under the gate insulating film in the silicon substrate;
A source region and a drain region formed apart from each other in the silicon substrate and provided so as to locate the channel region therebetween;
The semiconductor device, wherein the buffer layer has a thickness of 0.5 nm or more and 2 nm or less and an atomic concentration of titanium of 1% or more and 8% or less. _2. The semiconductor device according to claim 1, wherein an SiO ₂ layer having a thickness of 1 nm or less is formed between said buffer layer and said silicon substrate. Removing the oxide film formed on the silicon substrate surface,
By sputtering with a titanium oxide target under an oxidation flow rate of 0 sccm or more and 1.2 sccm or less, an oxide containing titanium and silicon is formed on the silicon substrate, and a film thickness of 0.5 nm or more and 2 nm or less, Forming a buffer layer having an atomic concentration of titanium of 1% or more and 8% or less;
Forming a gate insulating film made of titanium oxide on the buffer layer by sputtering with a target of titanium oxide and an oxygen flow rate of 10 sccm or more. Manufacturing method.

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